Merge branch 'feat/psram_support_d2wd_single_clk_u4wdh_v5.1' into 'release/v5.1'

spiram: Add support for U4WDH, and fixed D0WD/D2WD cannot share CLK pins (v5.1)

See merge request espressif/esp-idf!25171

components/esp_psram/esp32/Kconfig.spiram

@@ -300,6 +300,9 @@ menu "SPI RAM config"
                 The PSRAM CLOCK IO can be any unused GPIO, user can config it based on hardware design. If user use
                 1.8V flash and 1.8V psram, this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17.
 
+                If configured to the same pin as Flash, PSRAM shouldn't be rev0. Contact Espressif for more
+                information.
+
         config D0WD_PSRAM_CS_IO
             int "PSRAM CS IO number"
             depends on SPIRAM
@@ -321,6 +324,9 @@ menu "SPI RAM config"
                 User can config it based on hardware design. For ESP32-D2WD chip, the psram can only be 1.8V psram,
                 so this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17.
 
+                If configured to the same pin (GPIO6) as Flash, PSRAM shouldn't be rev0. Contact Espressif for more
+                information.
+
         config D2WD_PSRAM_CS_IO
             int "PSRAM CS IO number"
             depends on SPIRAM
@@ -331,7 +337,7 @@ menu "SPI RAM config"
                 so this value can only be one of 6, 7, 8, 9, 10, 11, 16, 17.
     endmenu
 
-    menu "PSRAM clock and cs IO for ESP32-PICO"
+    menu "PSRAM clock and cs IO for ESP32-PICO-D4"
 
         config PICO_PSRAM_CS_IO
             int "PSRAM CS IO number"

components/esp_psram/esp32/esp_psram_impl_quad.c

@@ -846,14 +846,16 @@ esp_err_t IRAM_ATTR esp_psram_impl_enable(psram_vaddr_mode_t vaddrmode)   //psra
     } else if (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4 && ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 300)) {
         ESP_EARLY_LOGE(TAG, "This chip is ESP32-PICO-V3. It does not support PSRAM (disable it in Kconfig)");
         abort();
-    } else if ((pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD2) || (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4)) {
+    } else if ((pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4) || (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32U4WDH)) {
-        ESP_EARLY_LOGI(TAG, "This chip is ESP32-PICO");
+        ESP_EARLY_LOGI(TAG, "This chip is %s",
+                        (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4)? "ESP32-PICO": "ESP32-U4WDH");
+        // We have better alternatives, though it's possible to use U4WDH together with PSRAM.
+        // U4WDH shares the same pin config with PICO for historical reasons.
         rtc_vddsdio_config_t cfg = rtc_vddsdio_get_config();
         if (cfg.tieh != RTC_VDDSDIO_TIEH_3_3V) {
             ESP_EARLY_LOGE(TAG, "VDDSDIO is not 3.3V");
             return ESP_FAIL;
         }
-        s_clk_mode = PSRAM_CLK_MODE_NORM;
         psram_io.psram_clk_io = PICO_PSRAM_CLK_IO;
         psram_io.psram_cs_io  = PICO_PSRAM_CS_IO;
     } else if (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOV302) {
@@ -863,7 +865,6 @@ esp_err_t IRAM_ATTR esp_psram_impl_enable(psram_vaddr_mode_t vaddrmode)   //psra
             ESP_EARLY_LOGE(TAG, "VDDSDIO is not 3.3V");
             return ESP_FAIL;
         }
-        s_clk_mode = PSRAM_CLK_MODE_NORM;
         psram_io.psram_clk_io = PICO_V3_02_PSRAM_CLK_IO;
         psram_io.psram_cs_io  = PICO_V3_02_PSRAM_CS_IO;
     } else if ((pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32D0WDQ6) || (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32D0WDQ5)){
@@ -877,7 +878,6 @@ esp_err_t IRAM_ATTR esp_psram_impl_enable(psram_vaddr_mode_t vaddrmode)   //psra
             ESP_EARLY_LOGE(TAG, "VDDSDIO is not 3.3V");
             return ESP_FAIL;
         }
-        s_clk_mode = PSRAM_CLK_MODE_NORM;
         psram_io.psram_clk_io = D0WDR2_V3_PSRAM_CLK_IO;
         psram_io.psram_cs_io  = D0WDR2_V3_PSRAM_CS_IO;
     } else {
@@ -910,6 +910,12 @@ esp_err_t IRAM_ATTR esp_psram_impl_enable(psram_vaddr_mode_t vaddrmode)   //psra
         psram_io.psram_spiwp_sd3_io = bootloader_flash_get_wp_pin();
     }
 
+    if (psram_io.flash_clk_io == psram_io.psram_clk_io) {
+        s_clk_mode = PSRAM_CLK_MODE_NORM;
+    } else {
+        s_clk_mode = PSRAM_CLK_MODE_DCLK;
+    }
+
     assert(mode < PSRAM_CACHE_MAX && "we don't support any other mode for now.");
     s_psram_mode = mode;
 
@@ -964,7 +970,10 @@ esp_err_t IRAM_ATTR esp_psram_impl_enable(psram_vaddr_mode_t vaddrmode)   //psra
     }
 
     if (psram_is_32mbit_ver0()) {
-        s_clk_mode = PSRAM_CLK_MODE_DCLK;
+        if (s_clk_mode != PSRAM_CLK_MODE_DCLK) {
+            ESP_EARLY_LOGE(TAG, "PSRAM rev0 can't share CLK with Flash");
+            abort();
+        }
         if (mode == PSRAM_CACHE_F80M_S80M) {
 #ifdef CONFIG_SPIRAM_OCCUPY_NO_HOST
             ESP_EARLY_LOGE(TAG, "This version of PSRAM needs to claim an extra SPI peripheral at 80MHz. Please either: choose lower frequency by SPIRAM_SPEED_, or select one SPI peripheral it by SPIRAM_OCCUPY_*SPI_HOST in the menuconfig.");