From cccaa68467d8a309a99fb0b4489f0cdff33e7a93 Mon Sep 17 00:00:00 2001 From: Ivan Grokhotkov Date: Mon, 3 Sep 2018 18:10:46 +0800 Subject: [PATCH 1/3] bootloader: fix IROM and DROM swapped in log messages --- components/bootloader_support/src/bootloader_utility.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/components/bootloader_support/src/bootloader_utility.c b/components/bootloader_support/src/bootloader_utility.c index 644496c5b5..c0dbf04afc 100644 --- a/components/bootloader_support/src/bootloader_utility.c +++ b/components/bootloader_support/src/bootloader_utility.c @@ -389,7 +389,7 @@ static void unpack_load_app(const esp_image_metadata_t* data) // Find DROM & IROM addresses, to configure cache mappings for (int i = 0; i < data->image.segment_count; i++) { const esp_image_segment_header_t *header = &data->segments[i]; - if (header->load_addr >= SOC_IROM_LOW && header->load_addr < SOC_IROM_HIGH) { + if (header->load_addr >= SOC_DROM_LOW && header->load_addr < SOC_DROM_HIGH) { if (drom_addr != 0) { ESP_LOGE(TAG, MAP_ERR_MSG, "DROM"); } else { @@ -399,7 +399,7 @@ static void unpack_load_app(const esp_image_metadata_t* data) drom_load_addr = header->load_addr; drom_size = header->data_len; } - if (header->load_addr >= SOC_DROM_LOW && header->load_addr < SOC_DROM_HIGH) { + if (header->load_addr >= SOC_IROM_LOW && header->load_addr < SOC_IROM_HIGH) { if (irom_addr != 0) { ESP_LOGE(TAG, MAP_ERR_MSG, "IROM"); } else { From b1ee25afde07a3a6b5d9e1cd51a8316ac67bde64 Mon Sep 17 00:00:00 2001 From: Ivan Grokhotkov Date: Mon, 3 Sep 2018 18:15:20 +0800 Subject: [PATCH 2/3] bootloader: account for load address when mapping cache pages Bootloader used to calculate the number of cache pages assuming that load address was aligned, while in reality load address for DROM and IROM was offset by 0x20 bytes from the start of 64kB page. This caused the bootloader to map one less page if the size of the image was 0x4..0x1c less than a multiple of 64kB. Reported in https://esp32.com/viewtopic.php?f=13&t=6952. --- .../include_bootloader/bootloader_flash.h | 17 ++++++++ .../bootloader_support/src/bootloader_flash.c | 7 ++- .../src/bootloader_utility.c | 43 +++++++++++++------ 3 files changed, 49 insertions(+), 18 deletions(-) diff --git a/components/bootloader_support/include_bootloader/bootloader_flash.h b/components/bootloader_support/include_bootloader/bootloader_flash.h index 85a4827819..ce867d7573 100644 --- a/components/bootloader_support/include_bootloader/bootloader_flash.h +++ b/components/bootloader_support/include_bootloader/bootloader_flash.h @@ -111,4 +111,21 @@ esp_err_t bootloader_flash_erase_sector(size_t sector); */ esp_err_t bootloader_flash_erase_range(uint32_t start_addr, uint32_t size); +/* Cache MMU block size */ +#define MMU_BLOCK_SIZE 0x00010000 + +/* Cache MMU address mask (MMU tables ignore bits which are zero) */ +#define MMU_FLASH_MASK (~(MMU_BLOCK_SIZE - 1)) + +/** + * @brief Calculate the number of cache pages to map + * @param size size of data to map + * @param vaddr virtual address where data will be mapped + * @return number of cache MMU pages required to do the mapping + */ +static inline uint32_t bootloader_cache_pages_to_map(uint32_t size, uint32_t vaddr) +{ + return (size + (vaddr - (vaddr & MMU_FLASH_MASK)) + MMU_BLOCK_SIZE - 1) / MMU_BLOCK_SIZE; +} + #endif diff --git a/components/bootloader_support/src/bootloader_flash.c b/components/bootloader_support/src/bootloader_flash.c index 735c213270..dbdf84ee2b 100644 --- a/components/bootloader_support/src/bootloader_flash.c +++ b/components/bootloader_support/src/bootloader_flash.c @@ -91,8 +91,6 @@ static const char *TAG = "bootloader_flash"; */ #define MMU_BLOCK0_VADDR 0x3f400000 #define MMU_BLOCK50_VADDR 0x3f720000 -#define MMU_FLASH_MASK 0xffff0000 -#define MMU_BLOCK_SIZE 0x00010000 static bool mapped; @@ -112,10 +110,11 @@ const void *bootloader_mmap(uint32_t src_addr, uint32_t size) } uint32_t src_addr_aligned = src_addr & MMU_FLASH_MASK; - uint32_t count = (size + (src_addr - src_addr_aligned) + 0xffff) / MMU_BLOCK_SIZE; + uint32_t count = bootloader_cache_pages_to_map(size, src_addr); Cache_Read_Disable(0); Cache_Flush(0); - ESP_LOGD(TAG, "mmu set paddr=%08x count=%d", src_addr_aligned, count ); + ESP_LOGD(TAG, "mmu set paddr=%08x count=%d size=%x src_addr=%x src_addr_aligned=%x", + src_addr & MMU_FLASH_MASK, count, size, src_addr, src_addr_aligned ); int e = cache_flash_mmu_set(0, 0, MMU_BLOCK0_VADDR, src_addr_aligned, 64, count); if (e != 0) { ESP_LOGE(TAG, "cache_flash_mmu_set failed: %d\n", e); diff --git a/components/bootloader_support/src/bootloader_utility.c b/components/bootloader_support/src/bootloader_utility.c index c0dbf04afc..80550b11c5 100644 --- a/components/bootloader_support/src/bootloader_utility.c +++ b/components/bootloader_support/src/bootloader_utility.c @@ -430,6 +430,7 @@ static void set_cache_and_start_app( uint32_t irom_size, uint32_t entry_addr) { + int rc; ESP_LOGD(TAG, "configure drom and irom and start"); Cache_Read_Disable( 0 ); Cache_Flush( 0 ); @@ -441,20 +442,34 @@ static void set_cache_and_start_app( DPORT_PRO_FLASH_MMU_TABLE[i] = DPORT_FLASH_MMU_TABLE_INVALID_VAL; } - uint32_t drom_page_count = (drom_size + 64*1024 - 1) / (64*1024); // round up to 64k - ESP_LOGV(TAG, "d mmu set paddr=%08x vaddr=%08x size=%d n=%d", drom_addr & 0xffff0000, drom_load_addr & 0xffff0000, drom_size, drom_page_count ); - int rc = cache_flash_mmu_set( 0, 0, drom_load_addr & 0xffff0000, drom_addr & 0xffff0000, 64, drom_page_count ); - ESP_LOGV(TAG, "rc=%d", rc ); - rc = cache_flash_mmu_set( 1, 0, drom_load_addr & 0xffff0000, drom_addr & 0xffff0000, 64, drom_page_count ); - ESP_LOGV(TAG, "rc=%d", rc ); - uint32_t irom_page_count = (irom_size + 64*1024 - 1) / (64*1024); // round up to 64k - ESP_LOGV(TAG, "i mmu set paddr=%08x vaddr=%08x size=%d n=%d", irom_addr & 0xffff0000, irom_load_addr & 0xffff0000, irom_size, irom_page_count ); - rc = cache_flash_mmu_set( 0, 0, irom_load_addr & 0xffff0000, irom_addr & 0xffff0000, 64, irom_page_count ); - ESP_LOGV(TAG, "rc=%d", rc ); - rc = cache_flash_mmu_set( 1, 0, irom_load_addr & 0xffff0000, irom_addr & 0xffff0000, 64, irom_page_count ); - ESP_LOGV(TAG, "rc=%d", rc ); - DPORT_REG_CLR_BIT( DPORT_PRO_CACHE_CTRL1_REG, (DPORT_PRO_CACHE_MASK_IRAM0) | (DPORT_PRO_CACHE_MASK_IRAM1 & 0) | (DPORT_PRO_CACHE_MASK_IROM0 & 0) | DPORT_PRO_CACHE_MASK_DROM0 | DPORT_PRO_CACHE_MASK_DRAM1 ); - DPORT_REG_CLR_BIT( DPORT_APP_CACHE_CTRL1_REG, (DPORT_APP_CACHE_MASK_IRAM0) | (DPORT_APP_CACHE_MASK_IRAM1 & 0) | (DPORT_APP_CACHE_MASK_IROM0 & 0) | DPORT_APP_CACHE_MASK_DROM0 | DPORT_APP_CACHE_MASK_DRAM1 ); + uint32_t drom_load_addr_aligned = drom_load_addr & MMU_FLASH_MASK; + uint32_t drom_page_count = bootloader_cache_pages_to_map(drom_size, drom_load_addr); + ESP_LOGV(TAG, "d mmu set paddr=%08x vaddr=%08x size=%d n=%d", + drom_addr & MMU_FLASH_MASK, drom_load_addr_aligned, drom_size, drom_page_count); + rc = cache_flash_mmu_set(0, 0, drom_load_addr_aligned, drom_addr & MMU_FLASH_MASK, 64, drom_page_count); + ESP_LOGV(TAG, "rc=%d", rc); + rc = cache_flash_mmu_set(1, 0, drom_load_addr_aligned, drom_addr & MMU_FLASH_MASK, 64, drom_page_count); + ESP_LOGV(TAG, "rc=%d", rc); + + uint32_t irom_load_addr_aligned = irom_load_addr & MMU_FLASH_MASK; + uint32_t irom_page_count = bootloader_cache_pages_to_map(irom_size, irom_load_addr); + ESP_LOGV(TAG, "i mmu set paddr=%08x vaddr=%08x size=%d n=%d", + irom_addr & MMU_FLASH_MASK, irom_load_addr_aligned, irom_size, irom_page_count); + rc = cache_flash_mmu_set(0, 0, irom_load_addr_aligned, irom_addr & MMU_FLASH_MASK, 64, irom_page_count); + ESP_LOGV(TAG, "rc=%d", rc); + rc = cache_flash_mmu_set(1, 0, irom_load_addr_aligned, irom_addr & MMU_FLASH_MASK, 64, irom_page_count); + ESP_LOGV(TAG, "rc=%d", rc); + + DPORT_REG_CLR_BIT( DPORT_PRO_CACHE_CTRL1_REG, + (DPORT_PRO_CACHE_MASK_IRAM0) | (DPORT_PRO_CACHE_MASK_IRAM1 & 0) | + (DPORT_PRO_CACHE_MASK_IROM0 & 0) | DPORT_PRO_CACHE_MASK_DROM0 | + DPORT_PRO_CACHE_MASK_DRAM1 ); + + DPORT_REG_CLR_BIT( DPORT_APP_CACHE_CTRL1_REG, + (DPORT_APP_CACHE_MASK_IRAM0) | (DPORT_APP_CACHE_MASK_IRAM1 & 0) | + (DPORT_APP_CACHE_MASK_IROM0 & 0) | DPORT_APP_CACHE_MASK_DROM0 | + DPORT_APP_CACHE_MASK_DRAM1 ); + Cache_Read_Enable( 0 ); // Application will need to do Cache_Flush(1) and Cache_Read_Enable(1) From c4c1af114e42852e93768b4146424bcbf64ad3ca Mon Sep 17 00:00:00 2001 From: Angus Gratton Date: Tue, 8 Jan 2019 23:11:41 -0800 Subject: [PATCH 3/3] Update esptool.py to v2.6 --- components/esptool_py/esptool | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/components/esptool_py/esptool b/components/esptool_py/esptool index 9fbe1eec65..9ad444a6e0 160000 --- a/components/esptool_py/esptool +++ b/components/esptool_py/esptool @@ -1 +1 @@ -Subproject commit 9fbe1eec656dc69942f5163cc6cc79c33d5aad64 +Subproject commit 9ad444a6e06e58833d5e6044c1d5f3eb3dd56023