From cd7fab3bdcf4c4954daebdf5f5530986c59925ff Mon Sep 17 00:00:00 2001 From: Tomas Rezucha Date: Wed, 22 Jan 2025 13:19:22 +0100 Subject: [PATCH] refactor(usb): Include supported PHYs information in SoC --- components/soc/esp32p4/usb_dwc_periph.c | 2 ++ components/soc/esp32s2/usb_dwc_periph.c | 1 + components/soc/esp32s3/usb_dwc_periph.c | 1 + components/soc/include/soc/usb_dwc_periph.h | 11 +++++++++++ 4 files changed, 15 insertions(+) diff --git a/components/soc/esp32p4/usb_dwc_periph.c b/components/soc/esp32p4/usb_dwc_periph.c index a392f53cf0..ede82c5ed8 100644 --- a/components/soc/esp32p4/usb_dwc_periph.c +++ b/components/soc/esp32p4/usb_dwc_periph.c @@ -42,6 +42,7 @@ const usb_dwc_info_t usb_dwc_info = { .fsls_signals = NULL, .otg_signals = NULL, .internal_phy_io = NULL, // HS PHY is not mapped to any GPIO + .supported_phys = USB_PHY_INST_UTMI_0, .irq = ETS_USB_OTG_INTR_SOURCE, .irq_2nd_cpu = ETS_USB_OTG_ENDP_MULTI_PROC_INTR_SOURCE, }, @@ -50,6 +51,7 @@ const usb_dwc_info_t usb_dwc_info = { .fsls_signals = NULL, .otg_signals = &dwc_fs_otg_signals, .internal_phy_io = &internal_phy_io, + .supported_phys = USB_PHY_INST_FSLS_INTERN_0, .irq = ETS_USB_OTG11_CH0_INTR_SOURCE, .irq_2nd_cpu = -1, }, diff --git a/components/soc/esp32s2/usb_dwc_periph.c b/components/soc/esp32s2/usb_dwc_periph.c index 75bbf9957a..1d77e297fa 100644 --- a/components/soc/esp32s2/usb_dwc_periph.c +++ b/components/soc/esp32s2/usb_dwc_periph.c @@ -52,6 +52,7 @@ const usb_dwc_info_t usb_dwc_info = { .fsls_signals = &fsls_signals, .otg_signals = &otg_signals, .internal_phy_io = &internal_phy_io, + .supported_phys = USB_PHY_INST_FSLS_INTERN_0, .irq = ETS_USB_INTR_SOURCE, .irq_2nd_cpu = -1, }, diff --git a/components/soc/esp32s3/usb_dwc_periph.c b/components/soc/esp32s3/usb_dwc_periph.c index 75bbf9957a..1d77e297fa 100644 --- a/components/soc/esp32s3/usb_dwc_periph.c +++ b/components/soc/esp32s3/usb_dwc_periph.c @@ -52,6 +52,7 @@ const usb_dwc_info_t usb_dwc_info = { .fsls_signals = &fsls_signals, .otg_signals = &otg_signals, .internal_phy_io = &internal_phy_io, + .supported_phys = USB_PHY_INST_FSLS_INTERN_0, .irq = ETS_USB_INTR_SOURCE, .irq_2nd_cpu = -1, }, diff --git a/components/soc/include/soc/usb_dwc_periph.h b/components/soc/include/soc/usb_dwc_periph.h index 8da20218f4..185a6bdb37 100644 --- a/components/soc/include/soc/usb_dwc_periph.h +++ b/components/soc/include/soc/usb_dwc_periph.h @@ -16,6 +16,16 @@ extern "C" { /* ---------------------------------- Types --------------------------------- */ +/** + * @brief USB PHY Instance Type + */ +typedef enum { + USB_PHY_INST_FSLS_INTERN_0 = (1 << 0), + USB_PHY_INST_FSLS_INTERN_1 = (1 << 1), + USB_PHY_INST_UTMI_0 = (1 << 2), + USB_PHY_INST_EXTERN = (1 << 3), +} usb_phy_inst_t; + /** * @brief USB PHY FSLS Serial Interface Signals * @@ -83,6 +93,7 @@ typedef struct { const usb_fsls_serial_signal_conn_t * const fsls_signals; // Must be set if external PHY is supported by controller const usb_otg_signal_conn_t * const otg_signals; const usb_internal_phy_io_t * const internal_phy_io; // Must be set for internal FSLS PHY(s) + const usb_phy_inst_t supported_phys; // Bitmap of supported PHYs by this controller const int irq; const int irq_2nd_cpu; // The USB-DWC can provide 2nd interrupt so each CPU can have its own interrupt line. Set to -1 if not supported } controllers [SOC_USB_OTG_PERIPH_NUM];