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rtc_clk: fix esp32 unreachable code in rtc_clk_xtal_freq_estimate

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songruo
2022-04-11 00:52:30 +08:00
parent 60bb5c913d
commit cd83f4f307
1 changed files with 20 additions and 13 deletions
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33
components/esp_hw_support/port/esp32/rtc_clk_init.c
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@@ -135,6 +135,7 @@ static rtc_xtal_freq_t rtc_clk_xtal_freq_estimate(void)
#if CONFIG_IDF_ENV_FPGA #if CONFIG_IDF_ENV_FPGA
return RTC_XTAL_FREQ_40M; return RTC_XTAL_FREQ_40M;
#endif // CONFIG_IDF_ENV_FPGA #endif // CONFIG_IDF_ENV_FPGA
rtc_xtal_freq_t xtal_freq;
/* Enable 8M/256 clock if needed */ /* Enable 8M/256 clock if needed */
const bool clk_8m_enabled = rtc_clk_8m_enabled(); const bool clk_8m_enabled = rtc_clk_8m_enabled();
const bool clk_8md256_enabled = rtc_clk_8md256_enabled(); const bool clk_8md256_enabled = rtc_clk_8md256_enabled();
@@ -151,20 +152,26 @@ static rtc_xtal_freq_t rtc_clk_xtal_freq_estimate(void)
/* Guess the XTAL type. For now, only 40 and 26MHz are supported. /* Guess the XTAL type. For now, only 40 and 26MHz are supported.
*/ */
switch (freq_mhz) { switch (freq_mhz) {
case 21 ... 31: case 21 ... 31:
return RTC_XTAL_FREQ_26M; xtal_freq = RTC_XTAL_FREQ_26M;
case 32 ... 33: break;
ESP_HW_LOGW(TAG, "Potentially bogus XTAL frequency: %d MHz, guessing 26 MHz", freq_mhz); case 32 ... 33:
return RTC_XTAL_FREQ_26M; ESP_HW_LOGW(TAG, "Potentially bogus XTAL frequency: %d MHz, guessing 26 MHz", freq_mhz);
case 34 ... 35: xtal_freq = RTC_XTAL_FREQ_26M;
ESP_HW_LOGW(TAG, "Potentially bogus XTAL frequency: %d MHz, guessing 40 MHz", freq_mhz); break;
return RTC_XTAL_FREQ_40M; case 34 ... 35:
case 36 ... 45: ESP_HW_LOGW(TAG, "Potentially bogus XTAL frequency: %d MHz, guessing 40 MHz", freq_mhz);
return RTC_XTAL_FREQ_40M; xtal_freq = RTC_XTAL_FREQ_40M;
default: break;
ESP_HW_LOGW(TAG, "Bogus XTAL frequency: %d MHz", freq_mhz); case 36 ... 45:
return RTC_XTAL_FREQ_AUTO; xtal_freq = RTC_XTAL_FREQ_40M;
break;
default:
ESP_HW_LOGW(TAG, "Bogus XTAL frequency: %d MHz", freq_mhz);
xtal_freq = RTC_XTAL_FREQ_AUTO;
break;
} }
/* Restore 8M and 8md256 clocks to original state */ /* Restore 8M and 8md256 clocks to original state */
rtc_clk_8m_enable(clk_8m_enabled, clk_8md256_enabled); rtc_clk_8m_enable(clk_8m_enabled, clk_8md256_enabled);
return xtal_freq;
} }