diff --git a/components/bootloader_support/src/esp32h4/bootloader_esp32h4.c b/components/bootloader_support/src/esp32h4/bootloader_esp32h4.c
index 2dc5c6b66c..bfdb0547f1 100644
--- a/components/bootloader_support/src/esp32h4/bootloader_esp32h4.c
+++ b/components/bootloader_support/src/esp32h4/bootloader_esp32h4.c
@@ -28,8 +28,8 @@
 #include "bootloader_flash_config.h"
 #include "bootloader_mem.h"
 #include "esp_private/regi2c_ctrl.h"
-#include "soc/regi2c_lp_bias.h"
-#include "soc/regi2c_bias.h"
+// #include "soc/regi2c_lp_bias.h"
+// #include "soc/regi2c_bias.h"
 #include "soc/hp_system_reg.h"
 #include "bootloader_console.h"
 #include "bootloader_flash_priv.h"
@@ -110,12 +110,12 @@ void spi_flash_extra_dummy_set(uint8_t spi_num, uint8_t extra_dummy)
  */
 static inline void bootloader_hardware_init(void)
 {
+    // TODO: IDF-12285 RF disable?
 
-    // TODO: [ESP32H4] IDF-12315
-    ESP_EARLY_LOGE(TAG, "Analog i2c mst clk enable skipped!\n");
     /* Enable analog i2c master clock */
-    // SET_PERI_REG_MASK(MODEM_LPCON_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_EN);
-    // SET_PERI_REG_MASK(MODEM_LPCON_I2C_MST_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_SEL_160M);
+    _regi2c_ctrl_ll_master_enable_clock(true); // keep ana i2c mst clock always enabled in bootloader
+    regi2c_ctrl_ll_master_force_enable_clock(true); // TODO: IDF-12285 Remove this?
+    regi2c_ctrl_ll_master_configure_clock();
 }
 
 static inline void bootloader_ana_reset_config(void)
diff --git a/components/esp_rom/CMakeLists.txt b/components/esp_rom/CMakeLists.txt
index e8d5d862c7..c75e227101 100644
--- a/components/esp_rom/CMakeLists.txt
+++ b/components/esp_rom/CMakeLists.txt
@@ -27,7 +27,7 @@ else()
 
     # Override regi2c implementation in ROM
     if(CONFIG_ESP_ROM_HAS_REGI2C_BUG OR CONFIG_ESP_ROM_WITHOUT_REGI2C)
-        if(target STREQUAL "esp32c6" OR target STREQUAL "esp32c5" OR target STREQUAL "esp32h4")
+        if(target STREQUAL "esp32c6" OR target STREQUAL "esp32c5")
             list(APPEND sources "patches/esp_rom_hp_regi2c_${target}.c")
         else()
             list(APPEND sources "patches/esp_rom_regi2c_${target}.c")
diff --git a/components/esp_rom/patches/esp_rom_hp_regi2c_esp32h4.c b/components/esp_rom/patches/esp_rom_hp_regi2c_esp32h4.c
deleted file mode 100644
index 2db1531b3c..0000000000
--- a/components/esp_rom/patches/esp_rom_hp_regi2c_esp32h4.c
+++ /dev/null
@@ -1,189 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-#include "esp_rom_sys.h"
-#include "esp_attr.h"
-#include "soc/i2c_ana_mst_reg.h"
-
-// TODO: [ESP32H4] IDF-12315 inherit from verify code, need check
-
-/**
- * BB    - 0x67 - BIT0
- * TXRF  - 0x6B - BIT1
- * SDM   - 0x63 - BIT2
- * PLL   - 0x62 - BIT3
- * BIAS  - 0x6A - BIT4
- * BBPLL - 0x66 - BIT5
- * ULP   - 0x61 - BIT6
- * SAR   - 0x69 - BIT7
- * PMU   - 0x6d - BIT8
-*/
-
-#define REGI2C_BIAS_MST_SEL    (BIT(8))
-#define REGI2C_BBPLL_MST_SEL   (BIT(9))
-#define REGI2C_ULP_CAL_MST_SEL (BIT(10))
-#define REGI2C_SAR_I2C_MST_SEL (BIT(11))
-#define REGI2C_DIG_REG_MST_SEL (BIT(12))
-
-#define REGI2C_BIAS_RD_MASK     (~BIT(6)    & I2C_ANA_MST_ANA_CONF1_M)
-#define REGI2C_BBPLL_RD_MASK    (~BIT(7)    & I2C_ANA_MST_ANA_CONF1_M)
-#define REGI2C_ULP_CAL_RD_MASK  (~BIT(8)    & I2C_ANA_MST_ANA_CONF1_M)
-#define REGI2C_SAR_I2C_RD_MASK  (~BIT(9)    & I2C_ANA_MST_ANA_CONF1_M)
-#define REGI2C_DIG_REG_RD_MASK  (~BIT(10)   & I2C_ANA_MST_ANA_CONF1_M)
-
-#define I2C_ANA_MST_I2C_CTRL_REG(n) (I2C_ANA_MST_I2C0_CTRL_REG + n*4) // 0: I2C_ANA_MST_I2C0_CTRL_REG; 1: I2C_ANA_MST_I2C1_CTRL_REG
-
-#define REGI2C_RTC_BUSY           (BIT(25))
-#define REGI2C_RTC_BUSY_M         (BIT(25))
-#define REGI2C_RTC_BUSY_V         0x1
-#define REGI2C_RTC_BUSY_S         25
-
-#define REGI2C_RTC_WR_CNTL        (BIT(24))
-#define REGI2C_RTC_WR_CNTL_M      (BIT(24))
-#define REGI2C_RTC_WR_CNTL_V      0x1
-#define REGI2C_RTC_WR_CNTL_S      24
-
-#define REGI2C_RTC_DATA           0x000000FF
-#define REGI2C_RTC_DATA_M         ((I2C_RTC_DATA_V)<<(I2C_RTC_DATA_S))
-#define REGI2C_RTC_DATA_V         0xFF
-#define REGI2C_RTC_DATA_S         16
-
-#define REGI2C_RTC_ADDR           0x000000FF
-#define REGI2C_RTC_ADDR_M         ((I2C_RTC_ADDR_V)<<(I2C_RTC_ADDR_S))
-#define REGI2C_RTC_ADDR_V         0xFF
-#define REGI2C_RTC_ADDR_S         8
-
-#define REGI2C_RTC_SLAVE_ID       0x000000FF
-#define REGI2C_RTC_SLAVE_ID_M     ((I2C_RTC_SLAVE_ID_V)<<(I2C_RTC_SLAVE_ID_S))
-#define REGI2C_RTC_SLAVE_ID_V     0xFF
-#define REGI2C_RTC_SLAVE_ID_S     0
-
-/* SLAVE */
-
-#define REGI2C_BBPLL              (0x66)
-#define REGI2C_BBPLL_HOSTID       0
-
-#define REGI2C_BIAS               (0x6a)
-#define REGI2C_BIAS_HOSTID        0
-
-#define REGI2C_DIG_REG            (0x6d)
-#define REGI2C_DIG_REG_HOSTID     0
-
-#define REGI2C_ULP_CAL            (0x61)
-#define REGI2C_ULP_CAL_HOSTID     0
-
-#define REGI2C_SAR_I2C            (0x69)
-#define REGI2C_SAR_I2C_HOSTID     0
-
-/* SLAVE END */
-
-uint8_t esp_rom_regi2c_read(uint8_t block, uint8_t host_id, uint8_t reg_add) __attribute__((alias("regi2c_read_impl")));
-uint8_t esp_rom_regi2c_read_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb) __attribute__((alias("regi2c_read_mask_impl")));
-void esp_rom_regi2c_write(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data) __attribute__((alias("regi2c_write_impl")));
-void esp_rom_regi2c_write_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data) __attribute__((alias("regi2c_write_mask_impl")));
-
-// static IRAM_ATTR uint8_t regi2c_enable_block(uint8_t block)
-// {
-//     uint32_t i2c_sel = 0;
-
-//     /* Before config I2C register, enable corresponding slave. */
-//     switch (block) {
-//     case REGI2C_BBPLL  :
-//         i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_BBPLL_MST_SEL);
-//         REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, REGI2C_BBPLL_RD_MASK);
-//         break;
-//     case REGI2C_BIAS   :
-//         i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_BIAS_MST_SEL);
-//         REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, REGI2C_BIAS_RD_MASK);
-//         break;
-//     case REGI2C_DIG_REG:
-//         i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_DIG_REG_MST_SEL);
-//         REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, REGI2C_DIG_REG_RD_MASK);
-//         break;
-//     case REGI2C_ULP_CAL:
-//         i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_ULP_CAL_MST_SEL);
-//         REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, REGI2C_ULP_CAL_RD_MASK);
-//         break;
-//     case REGI2C_SAR_I2C:
-//         i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_SAR_I2C_MST_SEL);
-//         REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, REGI2C_SAR_I2C_RD_MASK);
-//         break;
-//     }
-
-//     return (uint8_t)(i2c_sel ? 0: 1);
-// }
-
-uint8_t IRAM_ATTR regi2c_read_impl(uint8_t block, uint8_t host_id, uint8_t reg_add)
-{
-    // (void)host_id;
-    // uint8_t i2c_sel = regi2c_enable_block(block);
-
-    // while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); // wait i2c idle
-    // uint32_t temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S)
-    //                 | (reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S;
-    // REG_WRITE(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), temp);
-    // while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY));
-    // uint8_t ret = REG_GET_FIELD(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_DATA);
-
-    // return ret;
-    return -1;
-}
-
-uint8_t IRAM_ATTR regi2c_read_mask_impl(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb)
-{
-    // assert(msb - lsb < 8);
-    // uint8_t i2c_sel = regi2c_enable_block(block);
-
-    // (void)host_id;
-    // while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); // wait i2c idle
-    // uint32_t temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S)
-    //                 | (reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S;
-    // REG_WRITE(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), temp);
-    // while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY));
-    // uint32_t data = REG_GET_FIELD(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_DATA);
-    // uint8_t ret = (uint8_t)((data >> lsb) & (~(0xFFFFFFFF << (msb - lsb + 1))));
-
-    // return ret;
-    return -1;
-}
-
-void IRAM_ATTR regi2c_write_impl(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data)
-{
-    // (void)host_id;
-    // uint8_t i2c_sel = regi2c_enable_block(block);
-
-    // while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); // wait i2c idle
-    // uint32_t temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S)
-    //                 | ((reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S)
-    //                 | ((0x1 & REGI2C_RTC_WR_CNTL_V) << REGI2C_RTC_WR_CNTL_S) // 0: READ I2C register; 1: Write I2C register;
-    //                 | (((uint32_t)data & REGI2C_RTC_DATA_V) << REGI2C_RTC_DATA_S);
-    // REG_WRITE(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), temp);
-    // while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY));
-
-}
-
-void IRAM_ATTR regi2c_write_mask_impl(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data)
-{
-    // (void)host_id;
-    // assert(msb - lsb < 8);
-    // uint8_t i2c_sel = regi2c_enable_block(block);
-
-    // while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY));
-    // /*Read the i2c bus register*/
-    // uint32_t temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S)
-    //                 | (reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S;
-    // REG_WRITE(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), temp);
-    // while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY));
-    // temp = REG_GET_FIELD(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_DATA);
-    // /*Write the i2c bus register*/
-    // temp &= ((~(0xFFFFFFFF << lsb)) | (0xFFFFFFFF << (msb + 1)));
-    // temp = (((uint32_t)data & (~(0xFFFFFFFF << (msb - lsb + 1)))) << lsb) | temp;
-    // temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S)
-    //         | ((reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S)
-    //         | ((0x1 & REGI2C_RTC_WR_CNTL_V) << REGI2C_RTC_WR_CNTL_S)
-    //         | ((temp & REGI2C_RTC_DATA_V) << REGI2C_RTC_DATA_S);
-    // REG_WRITE(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), temp);
-    // while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY));
-}
diff --git a/components/esp_rom/patches/esp_rom_regi2c_esp32h4.c b/components/esp_rom/patches/esp_rom_regi2c_esp32h4.c
new file mode 100644
index 0000000000..ebc179de4f
--- /dev/null
+++ b/components/esp_rom/patches/esp_rom_regi2c_esp32h4.c
@@ -0,0 +1,127 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include "esp_rom_sys.h"
+#include "esp_attr.h"
+#include "soc/i2c_ana_mst_reg.h"
+#include "hal/regi2c_ctrl_ll.h"
+
+/* SLAVE */
+#define REGI2C_BBPLL       (0x66)
+#define REGI2C_BBTOP       (0x67)
+#define REGI2C_DCDC        (0x6d)
+#define REGI2C_PERIF       (0x69)
+#define REGI2C_PLL         (0x62)
+#define REGI2C_SDM         (0x63)
+#define REGI2C_ULP         (0x61)
+/* SLAVE END */
+
+uint8_t esp_rom_regi2c_read(uint8_t block, uint8_t host_id, uint8_t reg_add) __attribute__((alias("regi2c_read_impl")));
+uint8_t esp_rom_regi2c_read_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb) __attribute__((alias("regi2c_read_mask_impl")));
+void esp_rom_regi2c_write(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data) __attribute__((alias("regi2c_write_impl")));
+void esp_rom_regi2c_write_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data) __attribute__((alias("regi2c_write_mask_impl")));
+
+static IRAM_ATTR uint8_t regi2c_enable_block(uint8_t block)
+{
+    uint32_t i2c_sel = 0;
+    assert(regi2c_ctrl_ll_master_is_clock_enabled());
+
+    /* Before config I2C register, enable corresponding slave. */
+    switch (block) {
+        case REGI2C_BBPLL:
+            i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_CONF2_BBPLL_SEL);
+            REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, ~REGI2C_CONF1_BBPLL_SEL & I2C_ANA_MST_ANA_CONF1_M);
+            break;
+        case REGI2C_BBTOP:
+            i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_CONF2_BBTOP_SEL);
+            REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, ~REGI2C_CONF1_BBTOP_SEL & I2C_ANA_MST_ANA_CONF1_M);
+            break;
+        case REGI2C_DCDC:
+            i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_CONF2_DCDC_SEL);
+            REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, ~REGI2C_CONF1_DCDC_SEL  & I2C_ANA_MST_ANA_CONF1_M);
+            break;
+        case REGI2C_PERIF:
+            i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_CONF2_PERIF_SEL);
+            REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, ~REGI2C_CONF1_PERIF_SEL & I2C_ANA_MST_ANA_CONF1_M);
+            break;
+        case REGI2C_PLL:
+            i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_CONF2_PLL_SEL);
+            REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, ~REGI2C_CONF1_PLL_SEL   & I2C_ANA_MST_ANA_CONF1_M);
+            break;
+        case REGI2C_SDM:
+            i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_CONF2_SDM_SEL);
+            REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, ~REGI2C_CONF1_SDM_SEL   & I2C_ANA_MST_ANA_CONF1_M);
+            break;
+        case REGI2C_ULP:
+            i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, REGI2C_CONF2_ULP_SEL);
+            REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, ~REGI2C_CONF1_ULP_SEL   & I2C_ANA_MST_ANA_CONF1_M);
+            break;
+    }
+    return (uint8_t)(i2c_sel ? 0 : 1);
+}
+
+uint8_t IRAM_ATTR regi2c_read_impl(uint8_t block, uint8_t host_id, uint8_t reg_add)
+{
+    (void)host_id;
+    uint8_t i2c_sel = regi2c_enable_block(block);
+    while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); // wait i2c idle
+    uint32_t temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S)
+                    | (reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S;
+    REG_WRITE(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), temp);
+    while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY));
+    uint8_t ret = REG_GET_FIELD(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_DATA);
+    return ret;
+}
+
+uint8_t IRAM_ATTR regi2c_read_mask_impl(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb)
+{
+    assert(msb - lsb < 8);
+    uint8_t i2c_sel = regi2c_enable_block(block);
+    (void)host_id;
+    while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); // wait i2c idle
+    uint32_t temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S)
+                    | (reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S;
+    REG_WRITE(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), temp);
+    while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY));
+    uint32_t data = REG_GET_FIELD(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_DATA);
+    uint8_t ret = (uint8_t)((data >> lsb) & (~(0xFFFFFFFF << (msb - lsb + 1))));
+    return ret;
+}
+
+void IRAM_ATTR regi2c_write_impl(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data)
+{
+    (void)host_id;
+    uint8_t i2c_sel = regi2c_enable_block(block);
+    while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); // wait i2c idle
+    uint32_t temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S)
+                    | ((reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S)
+                    | ((0x1 & REGI2C_RTC_WR_CNTL_V) << REGI2C_RTC_WR_CNTL_S) // 0: READ I2C register; 1: Write I2C register;
+                    | (((uint32_t)data & REGI2C_RTC_DATA_V) << REGI2C_RTC_DATA_S);
+    REG_WRITE(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), temp);
+    while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY));
+}
+
+void IRAM_ATTR regi2c_write_mask_impl(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data)
+{
+    (void)host_id;
+    assert(msb - lsb < 8);
+    uint8_t i2c_sel = regi2c_enable_block(block);
+    while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY));
+    /*Read the i2c bus register*/
+    uint32_t temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S)
+                    | (reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S;
+    REG_WRITE(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), temp);
+    while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY));
+    temp = REG_GET_FIELD(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_DATA);
+    /*Write the i2c bus register*/
+    temp &= ((~(0xFFFFFFFF << lsb)) | (0xFFFFFFFF << (msb + 1)));
+    temp = (((uint32_t)data & (~(0xFFFFFFFF << (msb - lsb + 1)))) << lsb) | temp;
+    temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S)
+            | ((reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S)
+            | ((0x1 & REGI2C_RTC_WR_CNTL_V) << REGI2C_RTC_WR_CNTL_S)
+            | ((temp & REGI2C_RTC_DATA_V) << REGI2C_RTC_DATA_S);
+    REG_WRITE(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), temp);
+    while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY));
+}
diff --git a/components/hal/esp32h4/include/hal/clk_tree_ll.h b/components/hal/esp32h4/include/hal/clk_tree_ll.h
index b69dc768b7..c7d378cf94 100644
--- a/components/hal/esp32h4/include/hal/clk_tree_ll.h
+++ b/components/hal/esp32h4/include/hal/clk_tree_ll.h
@@ -295,37 +295,37 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_set_freq_mhz(uint
  */
 static inline __attribute__((always_inline)) void clk_ll_bbpll_set_config(uint32_t pll_freq_mhz, uint32_t xtal_freq_mhz)
 {
-    HAL_ASSERT(pll_freq_mhz == CLK_LL_PLL_96M_FREQ_MHZ);
-    uint8_t div_ref;
-    uint8_t div7_0;
-    uint8_t dr1;
-    uint8_t dr3;
-    uint8_t dchgp;
-    uint8_t dcur;
-    uint8_t dbias;
+    // HAL_ASSERT(pll_freq_mhz == CLK_LL_PLL_96M_FREQ_MHZ);
+    // uint8_t div_ref;
+    // uint8_t div7_0;
+    // uint8_t dr1;
+    // uint8_t dr3;
+    // uint8_t dchgp;
+    // uint8_t dcur;
+    // uint8_t dbias;
 
-    /* Configure 480M PLL */
-    switch (xtal_freq_mhz) {
-    case SOC_XTAL_FREQ_32M:
-    default:
-        div_ref = 0;
-        div7_0 = 8;
-        dr1 = 0;
-        dr3 = 0;
-        dchgp = 5;
-        dcur = 3;
-        dbias = 2;
-        break;
-    }
-    uint8_t i2c_bbpll_lref  = (dchgp << I2C_BBPLL_OC_DCHGP_LSB) | (div_ref);
-    uint8_t i2c_bbpll_div_7_0 = div7_0;
-    uint8_t i2c_bbpll_dcur = (1 << I2C_BBPLL_OC_DLREF_SEL_LSB ) | (3 << I2C_BBPLL_OC_DHREF_SEL_LSB) | dcur;
-    REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_OC_REF_DIV, i2c_bbpll_lref);
-    REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_OC_DIV_7_0, i2c_bbpll_div_7_0);
-    REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_DR1, dr1);
-    REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_DR3, dr3);
-    REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_OC_DCUR, i2c_bbpll_dcur);
-    REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_VCO_DBIAS, dbias);
+    // /* Configure 480M PLL */
+    // switch (xtal_freq_mhz) {
+    // case SOC_XTAL_FREQ_32M:
+    // default:
+    //     div_ref = 0;
+    //     div7_0 = 8;
+    //     dr1 = 0;
+    //     dr3 = 0;
+    //     dchgp = 5;
+    //     dcur = 3;
+    //     dbias = 2;
+    //     break;
+    // }
+    // uint8_t i2c_bbpll_lref  = (dchgp << I2C_BBPLL_OC_DCHGP_LSB) | (div_ref);
+    // uint8_t i2c_bbpll_div_7_0 = div7_0;
+    // uint8_t i2c_bbpll_dcur = (1 << I2C_BBPLL_OC_DLREF_SEL_LSB ) | (3 << I2C_BBPLL_OC_DHREF_SEL_LSB) | dcur;
+    // REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_OC_REF_DIV, i2c_bbpll_lref);
+    // REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_OC_DIV_7_0, i2c_bbpll_div_7_0);
+    // REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_DR1, dr1);
+    // REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_DR3, dr3);
+    // REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_OC_DCUR, i2c_bbpll_dcur);
+    // REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_VCO_DBIAS, dbias);
 }
 
 /**
diff --git a/components/hal/esp32h4/include/hal/regi2c_ctrl_ll.h b/components/hal/esp32h4/include/hal/regi2c_ctrl_ll.h
index bcf642a630..ee3c7c94bc 100644
--- a/components/hal/esp32h4/include/hal/regi2c_ctrl_ll.h
+++ b/components/hal/esp32h4/include/hal/regi2c_ctrl_ll.h
@@ -9,21 +9,72 @@
 #include <stdbool.h>
 #include <stdint.h>
 #include "soc/soc.h"
-#include "soc/regi2c_defs.h"
-
-//TODO: [ESP32H4] IDF-12315 inherited from verification branch, need check
+#include "soc/i2c_ana_mst_reg.h"
+#include "soc/pmu_reg.h"
+#include "modem/modem_lpcon_struct.h"
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
+#define ANA_I2C_MST_CLK_HAS_ROOT_GATING 1   /*!< Any regi2c operation needs enable the analog i2c master clock first */
+
+/**
+ * @brief Enable analog I2C master clock
+ */
+static inline __attribute__((always_inline)) void _regi2c_ctrl_ll_master_enable_clock(bool en)
+{
+    MODEM_LPCON.clk_conf.clk_i2c_mst_en = en;
+}
+
+/// use a macro to wrap the function, force the caller to use it in a critical section
+/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance
+#define regi2c_ctrl_ll_master_enable_clock(...) (void)__DECLARE_RCC_RC_ATOMIC_ENV; _regi2c_ctrl_ll_master_enable_clock(__VA_ARGS__)
+
+/**
+ * @brief Check whether analog I2C master clock is enabled
+ */
+static inline __attribute__((always_inline)) bool regi2c_ctrl_ll_master_is_clock_enabled(void)
+{
+    return MODEM_LPCON.clk_conf.clk_i2c_mst_en;
+}
+
+/**
+ * @brief Reset analog I2C master
+ */
+static inline __attribute__((always_inline)) void _regi2c_ctrl_ll_master_reset(void)
+{
+    MODEM_LPCON.rst_conf.rst_i2c_mst = 1;
+    MODEM_LPCON.rst_conf.rst_i2c_mst = 0;
+}
+
+/// use a macro to wrap the function, force the caller to use it in a critical section
+/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance
+#define regi2c_ctrl_ll_master_reset(...) (void)__DECLARE_RCC_RC_ATOMIC_ENV; _regi2c_ctrl_ll_master_reset(__VA_ARGS__)
+
+/**
+ * @brief Force enable analog I2C master clock
+ */
+static inline __attribute__((always_inline)) void regi2c_ctrl_ll_master_force_enable_clock(bool en)
+{
+    MODEM_LPCON.clk_conf_force_on.clk_i2c_mst_fo = en;
+}
+
+/**
+ * @brief Configure analog I2C master clock
+ */
+static inline __attribute__((always_inline)) void regi2c_ctrl_ll_master_configure_clock(void)
+{
+    // Nothing to configure
+}
+
 /**
  * @brief Start BBPLL self-calibration
  */
 static inline __attribute__((always_inline)) void regi2c_ctrl_ll_bbpll_calibration_start(void)
 {
-    REG_CLR_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH);
-    REG_SET_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW);
+    REG_CLR_BIT(I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH);
+    REG_SET_BIT(I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW);
 }
 
 /**
@@ -31,8 +82,8 @@ static inline __attribute__((always_inline)) void regi2c_ctrl_ll_bbpll_calibrati
  */
 static inline __attribute__((always_inline)) void regi2c_ctrl_ll_bbpll_calibration_stop(void)
 {
-    REG_CLR_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW);
-    REG_SET_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH);
+    REG_CLR_BIT(I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW);
+    REG_SET_BIT(I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH);
 }
 
 /**
@@ -42,7 +93,7 @@ static inline __attribute__((always_inline)) void regi2c_ctrl_ll_bbpll_calibrati
  */
 static inline __attribute__((always_inline)) bool regi2c_ctrl_ll_bbpll_calibration_is_done(void)
 {
-    return REG_GET_BIT(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_CAL_DONE);
+    return REG_GET_BIT(I2C_ANA_MST_ANA_CONF0_REG, I2C_MST_BBPLL_CAL_DONE);
 }
 
 /**
@@ -50,8 +101,7 @@ static inline __attribute__((always_inline)) bool regi2c_ctrl_ll_bbpll_calibrati
  */
 static inline void regi2c_ctrl_ll_i2c_sar_periph_enable(void)
 {
-    // TODO: [ESP32H4] IDF-12368 IDF-12370
-    abort();
+    SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_PERIF_I2C);
 }
 
 /**
@@ -59,8 +109,7 @@ static inline void regi2c_ctrl_ll_i2c_sar_periph_enable(void)
  */
 static inline void regi2c_ctrl_ll_i2c_sar_periph_disable(void)
 {
-    // TODO: [ESP32H4] IDF-12368 IDF-12370
-    abort();
+    CLEAR_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_PERIF_I2C);
 }
 
 #ifdef __cplusplus
diff --git a/components/soc/esp32h4/include/modem/reg_base.h b/components/soc/esp32h4/include/modem/reg_base.h
index e9ff67dc0b..c3452b3c51 100644
--- a/components/soc/esp32h4/include/modem/reg_base.h
+++ b/components/soc/esp32h4/include/modem/reg_base.h
@@ -5,5 +5,8 @@
  */
 
 #pragma once
+#define DR_REG_MODEM_BASE         0x600C0000
+#define DR_REG_MODEM_PWR_BASE     0x600CD000
+
 #define DR_REG_MODEM_SYSCON_BASE  0x600C9C00
-#define DR_REG_MODEM_LPCON_BASE   0x600CF000
+#define DR_REG_MODEM_LPCON_BASE   0x600CF000 // (DR_REG_MODEM_PWR_BASE + 0x2000)
diff --git a/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in b/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in
index 3ddec58754..1bf3e90773 100644
--- a/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in
+++ b/components/soc/esp32h4/include/soc/Kconfig.soc_caps.in
@@ -47,6 +47,10 @@ config SOC_PAU_SUPPORTED
     bool
     default y
 
+config SOC_REG_I2C_SUPPORTED
+    bool
+    default y
+
 config SOC_WDT_SUPPORTED
     bool
     default y
diff --git a/components/soc/esp32h4/include/soc/i2c_ana_mst_reg.h b/components/soc/esp32h4/include/soc/i2c_ana_mst_reg.h
index 6c67a5ab3d..4b714a02bd 100644
--- a/components/soc/esp32h4/include/soc/i2c_ana_mst_reg.h
+++ b/components/soc/esp32h4/include/soc/i2c_ana_mst_reg.h
@@ -13,103 +13,128 @@
 extern "C" {
 #endif
 
-//TODO: [ESP32H4] IDF-12315 inherit from verify code, need check
-
 #define I2C_ANA_MST_I2C0_CTRL_REG          (DR_REG_I2C_ANA_MST_BASE + 0x0)
-/* I2C_MST_I2C0_BUSY : RO ;bitpos:[25] ;default: 1'h0 ; */
+/* I2C_ANA_MST_I2C0_BUSY : RO ;bitpos:[25] ;default: 1'h0 ; */
 /*description: .*/
 #define I2C_ANA_MST_I2C0_BUSY    (BIT(25))
 #define I2C_ANA_MST_I2C0_BUSY_M  (BIT(25))
 #define I2C_ANA_MST_I2C0_BUSY_V  0x1
 #define I2C_ANA_MST_I2C0_BUSY_S  25
-/* I2C_MST_I2C0_CTRL : R/W ;bitpos:[24:0] ;default: 25'h0 ; */
+/* I2C_ANA_MST_I2C0_CTRL : R/W ;bitpos:[24:0] ;default: 25'h0 ; */
 /*description: .*/
 #define I2C_ANA_MST_I2C0_CTRL    0x01FFFFFF
-#define I2C_ANA_MST_I2C0_CTRL_M  ((I2C_MST_I2C0_CTRL_V)<<(I2C_MST_I2C0_CTRL_S))
+#define I2C_ANA_MST_I2C0_CTRL_M  ((I2C_ANA_MST_I2C0_CTRL_V)<<(I2C_ANA_MST_I2C0_CTRL_S))
 #define I2C_ANA_MST_I2C0_CTRL_V  0x1FFFFFF
 #define I2C_ANA_MST_I2C0_CTRL_S  0
 
 #define I2C_ANA_MST_I2C1_CTRL_REG          (DR_REG_I2C_ANA_MST_BASE + 0x4)
-/* I2C_MST_I2C1_BUSY : RO ;bitpos:[25] ;default: 1'h0 ; */
+/* I2C_ANA_MST_I2C1_BUSY : RO ;bitpos:[25] ;default: 1'h0 ; */
 /*description: .*/
 #define I2C_ANA_MST_I2C1_BUSY    (BIT(25))
 #define I2C_ANA_MST_I2C1_BUSY_M  (BIT(25))
 #define I2C_ANA_MST_I2C1_BUSY_V  0x1
 #define I2C_ANA_MST_I2C1_BUSY_S  25
-/* I2C_MST_I2C1_CTRL : R/W ;bitpos:[24:0] ;default: 25'h0 ; */
+/* I2C_ANA_MST_I2C1_CTRL : R/W ;bitpos:[24:0] ;default: 25'h0 ; */
 /*description: .*/
 #define I2C_ANA_MST_I2C1_CTRL    0x01FFFFFF
-#define I2C_ANA_MST_I2C1_CTRL_M  ((I2C_MST_I2C1_CTRL_V)<<(I2C_MST_I2C1_CTRL_S))
+#define I2C_ANA_MST_I2C1_CTRL_M  ((I2C_ANA_MST_I2C1_CTRL_V)<<(I2C_ANA_MST_I2C1_CTRL_S))
 #define I2C_ANA_MST_I2C1_CTRL_V  0x1FFFFFF
 #define I2C_ANA_MST_I2C1_CTRL_S  0
 
+#define I2C_ANA_MST_I2C_CTRL_REG(n) (I2C_ANA_MST_I2C0_CTRL_REG + n * 4) // 0: I2C_ANA_MST_I2C0_CTRL_REG; 1: I2C_ANA_MST_I2C1_CTRL_REG
+
+#define REGI2C_RTC_BUSY           (BIT(25))
+#define REGI2C_RTC_BUSY_M         (BIT(25))
+#define REGI2C_RTC_BUSY_V         0x1
+#define REGI2C_RTC_BUSY_S         25
+
+#define REGI2C_RTC_WR_CNTL        (BIT(24))
+#define REGI2C_RTC_WR_CNTL_M      (BIT(24))
+#define REGI2C_RTC_WR_CNTL_V      0x1
+#define REGI2C_RTC_WR_CNTL_S      24
+
+#define REGI2C_RTC_DATA           0x000000FF
+#define REGI2C_RTC_DATA_M         ((I2C_RTC_DATA_V)<<(I2C_RTC_DATA_S))
+#define REGI2C_RTC_DATA_V         0xFF
+#define REGI2C_RTC_DATA_S         16
+
+#define REGI2C_RTC_ADDR           0x000000FF
+#define REGI2C_RTC_ADDR_M         ((I2C_RTC_ADDR_V)<<(I2C_RTC_ADDR_S))
+#define REGI2C_RTC_ADDR_V         0xFF
+#define REGI2C_RTC_ADDR_S         8
+
+#define REGI2C_RTC_SLAVE_ID       0x000000FF
+#define REGI2C_RTC_SLAVE_ID_M     ((I2C_RTC_SLAVE_ID_V)<<(I2C_RTC_SLAVE_ID_S))
+#define REGI2C_RTC_SLAVE_ID_V     0xFF
+#define REGI2C_RTC_SLAVE_ID_S     0
+
 #define I2C_ANA_MST_I2C0_CONF_REG          (DR_REG_I2C_ANA_MST_BASE + 0x8)
-/* I2C_MST_I2C0_STATUS : RO ;bitpos:[31:24] ;default: 8'h0 ; */
+/* I2C_ANA_MST_I2C0_STATUS : RO ;bitpos:[31:24] ;default: 8'h0 ; */
 /*description: .*/
 #define I2C_ANA_MST_I2C0_STATUS    0x000000FF
-#define I2C_ANA_MST_I2C0_STATUS_M  ((I2C_MST_I2C0_STATUS_V)<<(I2C_MST_I2C0_STATUS_S))
+#define I2C_ANA_MST_I2C0_STATUS_M  ((I2C_ANA_MST_I2C0_STATUS_V)<<(I2C_ANA_MST_I2C0_STATUS_S))
 #define I2C_ANA_MST_I2C0_STATUS_V  0xFF
 #define I2C_ANA_MST_I2C0_STATUS_S  24
-/* I2C_MST_I2C0_CONF : R/W ;bitpos:[23:0] ;default: 24'h0 ; */
+/* I2C_ANA_MST_I2C0_CONF : R/W ;bitpos:[23:0] ;default: 24'h0 ; */
 /*description: .*/
 #define I2C_ANA_MST_I2C0_CONF    0x00FFFFFF
-#define I2C_ANA_MST_I2C0_CONF_M  ((I2C_MST_I2C0_CONF_V)<<(I2C_MST_I2C0_CONF_S))
+#define I2C_ANA_MST_I2C0_CONF_M  ((I2C_ANA_MST_I2C0_CONF_V)<<(I2C_ANA_MST_I2C0_CONF_S))
 #define I2C_ANA_MST_I2C0_CONF_V  0xFFFFFF
 #define I2C_ANA_MST_I2C0_CONF_S  0
 
 #define I2C_ANA_MST_I2C1_CONF_REG          (DR_REG_I2C_ANA_MST_BASE + 0xC)
-/* I2C_MST_I2C1_STATUS : RO ;bitpos:[31:24] ;default: 8'h0 ; */
+/* I2C_ANA_MST_I2C1_STATUS : RO ;bitpos:[31:24] ;default: 8'h0 ; */
 /*description: .*/
 #define I2C_ANA_MST_I2C1_STATUS    0x000000FF
-#define I2C_ANA_MST_I2C1_STATUS_M  ((I2C_MST_I2C1_STATUS_V)<<(I2C_MST_I2C1_STATUS_S))
+#define I2C_ANA_MST_I2C1_STATUS_M  ((I2C_ANA_MST_I2C1_STATUS_V)<<(I2C_ANA_MST_I2C1_STATUS_S))
 #define I2C_ANA_MST_I2C1_STATUS_V  0xFF
 #define I2C_ANA_MST_I2C1_STATUS_S  24
-/* I2C_MST_I2C1_CONF : R/W ;bitpos:[23:0] ;default: 24'h0 ; */
+/* I2C_ANA_MST_I2C1_CONF : R/W ;bitpos:[23:0] ;default: 24'h0 ; */
 /*description: .*/
 #define I2C_ANA_MST_I2C1_CONF    0x00FFFFFF
-#define I2C_ANA_MST_I2C1_CONF_M  ((I2C_MST_I2C1_CONF_V)<<(I2C_MST_I2C1_CONF_S))
+#define I2C_ANA_MST_I2C1_CONF_M  ((I2C_ANA_MST_I2C1_CONF_V)<<(I2C_ANA_MST_I2C1_CONF_S))
 #define I2C_ANA_MST_I2C1_CONF_V  0xFFFFFF
 #define I2C_ANA_MST_I2C1_CONF_S  0
 
 #define I2C_ANA_MST_I2C_BURST_CONF_REG          (DR_REG_I2C_ANA_MST_BASE + 0x10)
-/* I2C_MST_BURST_CTRL : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/* I2C_ANA_MST_I2C_MST_BURST_CTRL : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
 /*description: .*/
-#define I2C_ANA_MST_BURST_CTRL    0xFFFFFFFF
-#define I2C_ANA_MST_BURST_CTRL_M  ((I2C_MST_BURST_CTRL_V)<<(I2C_MST_BURST_CTRL_S))
-#define I2C_ANA_MST_BURST_CTRL_V  0xFFFFFFFF
-#define I2C_ANA_MST_BURST_CTRL_S  0
+#define I2C_ANA_MST_I2C_MST_BURST_CTRL    0xFFFFFFFF
+#define I2C_ANA_MST_I2C_MST_BURST_CTRL_M  ((I2C_ANA_MST_I2C_MST_BURST_CTRL_V)<<(I2C_ANA_MST_I2C_MST_BURST_CTRL_S))
+#define I2C_ANA_MST_I2C_MST_BURST_CTRL_V  0xFFFFFFFF
+#define I2C_ANA_MST_I2C_MST_BURST_CTRL_S  0
 
 #define I2C_ANA_MST_I2C_BURST_STATUS_REG          (DR_REG_I2C_ANA_MST_BASE + 0x14)
-/* I2C_MST_BURST_TIMEOUT_CNT : R/W ;bitpos:[31:20] ;default: 12'h400 ; */
+/* I2C_ANA_MST_I2C_MST_BURST_TIMEOUT_CNT : R/W ;bitpos:[31:20] ;default: 12'h400 ; */
 /*description: .*/
-#define I2C_ANA_MST_BURST_TIMEOUT_CNT    0x00000FFF
-#define I2C_ANA_MST_BURST_TIMEOUT_CNT_M  ((I2C_MST_BURST_TIMEOUT_CNT_V)<<(I2C_MST_BURST_TIMEOUT_CNT_S))
-#define I2C_ANA_MST_BURST_TIMEOUT_CNT_V  0xFFF
-#define I2C_ANA_MST_BURST_TIMEOUT_CNT_S  20
-/* I2C_MST1_BURST_ERR_FLAG : RO ;bitpos:[2] ;default: 1'b0 ; */
+#define I2C_ANA_MST_I2C_MST_BURST_TIMEOUT_CNT    0x00000FFF
+#define I2C_ANA_MST_I2C_MST_BURST_TIMEOUT_CNT_M  ((I2C_ANA_MST_I2C_MST_BURST_TIMEOUT_CNT_V)<<(I2C_ANA_MST_I2C_MST_BURST_TIMEOUT_CNT_S))
+#define I2C_ANA_MST_I2C_MST_BURST_TIMEOUT_CNT_V  0xFFF
+#define I2C_ANA_MST_I2C_MST_BURST_TIMEOUT_CNT_S  20
+/* I2C_ANA_MST_I2C_MST1_BURST_ERR_FLAG : RO ;bitpos:[2] ;default: 1'b0 ; */
 /*description: .*/
-#define I2C_ANA_MST1_BURST_ERR_FLAG    (BIT(2))
-#define I2C_ANA_MST1_BURST_ERR_FLAG_M  (BIT(2))
-#define I2C_ANA_MST1_BURST_ERR_FLAG_V  0x1
-#define I2C_ANA_MST1_BURST_ERR_FLAG_S  2
-/* I2C_MST0_BURST_ERR_FLAG : RO ;bitpos:[1] ;default: 1'b0 ; */
+#define I2C_ANA_MST_I2C_MST1_BURST_ERR_FLAG    (BIT(2))
+#define I2C_ANA_MST_I2C_MST1_BURST_ERR_FLAG_M  (BIT(2))
+#define I2C_ANA_MST_I2C_MST1_BURST_ERR_FLAG_V  0x1
+#define I2C_ANA_MST_I2C_MST1_BURST_ERR_FLAG_S  2
+/* I2C_ANA_MST_I2C_MST0_BURST_ERR_FLAG : RO ;bitpos:[1] ;default: 1'b0 ; */
 /*description: .*/
-#define I2C_ANA_MST0_BURST_ERR_FLAG    (BIT(1))
-#define I2C_ANA_MST0_BURST_ERR_FLAG_M  (BIT(1))
-#define I2C_ANA_MST0_BURST_ERR_FLAG_V  0x1
-#define I2C_ANA_MST0_BURST_ERR_FLAG_S  1
-/* I2C_MST_BURST_DONE : RO ;bitpos:[0] ;default: 1'b0 ; */
+#define I2C_ANA_MST_I2C_MST0_BURST_ERR_FLAG    (BIT(1))
+#define I2C_ANA_MST_I2C_MST0_BURST_ERR_FLAG_M  (BIT(1))
+#define I2C_ANA_MST_I2C_MST0_BURST_ERR_FLAG_V  0x1
+#define I2C_ANA_MST_I2C_MST0_BURST_ERR_FLAG_S  1
+/* I2C_ANA_MST_I2C_MST_BURST_DONE : RO ;bitpos:[0] ;default: 1'b0 ; */
 /*description: .*/
-#define I2C_ANA_MST_BURST_DONE    (BIT(0))
-#define I2C_ANA_MST_BURST_DONE_M  (BIT(0))
-#define I2C_ANA_MST_BURST_DONE_V  0x1
-#define I2C_ANA_MST_BURST_DONE_S  0
+#define I2C_ANA_MST_I2C_MST_BURST_DONE    (BIT(0))
+#define I2C_ANA_MST_I2C_MST_BURST_DONE_M  (BIT(0))
+#define I2C_ANA_MST_I2C_MST_BURST_DONE_V  0x1
+#define I2C_ANA_MST_I2C_MST_BURST_DONE_S  0
 
 #define I2C_ANA_MST_ANA_CONF0_REG          (DR_REG_I2C_ANA_MST_BASE + 0x18)
-/* I2C_ANA_MST_STATUS0 : RO ;bitpos:[31:24] ;default: 8'h0 ; */
+/* I2C_ANA_MST_ANA_STATUS0 : RO ;bitpos:[31:24] ;default: 8'h0 ; */
 /*description: .*/
 #define I2C_ANA_MST_ANA_STATUS0    0x000000FF
-#define I2C_ANA_MST_ANA_STATUS0_M  ((I2C_ANA_MST_STATUS0_V)<<(I2C_ANA_MST_STATUS0_S))
+#define I2C_ANA_MST_ANA_STATUS0_M  ((I2C_ANA_MST_ANA_STATUS0_V)<<(I2C_ANA_MST_ANA_STATUS0_S))
 #define I2C_ANA_MST_ANA_STATUS0_V  0xFF
 #define I2C_ANA_MST_ANA_STATUS0_S  24
 /* I2C_ANA_MST_ANA_CONF0 : R/W ;bitpos:[23:0] ;default: 24'h00_e408 ; */
@@ -118,26 +143,51 @@ extern "C" {
 #define I2C_ANA_MST_ANA_CONF0_M  ((I2C_ANA_MST_ANA_CONF0_V)<<(I2C_ANA_MST_ANA_CONF0_S))
 #define I2C_ANA_MST_ANA_CONF0_V  0xFFFFFF
 #define I2C_ANA_MST_ANA_CONF0_S  0
+/* specifically */
+#define I2C_MST_BBPLL_STOP_FORCE_HIGH  (BIT(2))
+#define I2C_MST_BBPLL_STOP_FORCE_LOW   (BIT(3))
+#define I2C_MST_BBPLL_CAL_DONE         (BIT(24))
 
 #define I2C_ANA_MST_ANA_CONF1_REG          (DR_REG_I2C_ANA_MST_BASE + 0x1C)
-/* I2C_ANA_MST_STATUS1 : RO ;bitpos:[31:24] ;default: 8'h0 ; */
+/* I2C_ANA_MST_ANA_STATUS1 : RO ;bitpos:[31:24] ;default: 8'h0 ; */
 /*description: .*/
 #define I2C_ANA_MST_ANA_STATUS1    0x000000FF
-#define I2C_ANA_MST_ANA_STATUS1_M  ((I2C_ANA_MST_STATUS1_V)<<(I2C_ANA_MST_STATUS1_S))
+#define I2C_ANA_MST_ANA_STATUS1_M  ((I2C_ANA_MST_ANA_STATUS1_V)<<(I2C_ANA_MST_ANA_STATUS1_S))
 #define I2C_ANA_MST_ANA_STATUS1_V  0xFF
 #define I2C_ANA_MST_ANA_STATUS1_S  24
-/* I2C_MST_AANA_NA_CONF1 : R/W ;bitpos:[23:0] ;default: 24'h00_002d ; */
+/* I2C_ANA_MST_ANA_CONF1 : R/W ;bitpos:[23:0] ;default: 24'h00_002d ; */
 /*description: .*/
 #define I2C_ANA_MST_ANA_CONF1    0x00FFFFFF
 #define I2C_ANA_MST_ANA_CONF1_M  ((I2C_ANA_MST_ANA_CONF1_V)<<(I2C_ANA_MST_ANA_CONF1_S))
 #define I2C_ANA_MST_ANA_CONF1_V  0xFFFFFF
 #define I2C_ANA_MST_ANA_CONF1_S  0
+/*      bit0  : test_i2c
+        bit1  : ana_dig_ch0
+        bit2  : BB_TOP_I2C
+        bit3  : TXTOP_I2C
+        bit4  : SDM_I2C
+        bit5  : PLL_I2C
+        bit6  : BIAS_I2C
+        bit7  : BB_PLL_I2C
+        bit8  : ULP_I2C
+        bit9  : PERIF_I2C
+        bit10 : DCDC_I2C
+*/
+#define REGI2C_CONF1_BBTOP_SEL   (BIT(2))
+#define REGI2C_CONF1_TXTOP_SEL   (BIT(3))
+#define REGI2C_CONF1_SDM_SEL     (BIT(4))
+#define REGI2C_CONF1_PLL_SEL     (BIT(5))
+#define REGI2C_CONF1_BIAS_SEL    (BIT(6))
+#define REGI2C_CONF1_BBPLL_SEL   (BIT(7))
+#define REGI2C_CONF1_ULP_SEL     (BIT(8))
+#define REGI2C_CONF1_PERIF_SEL   (BIT(9))
+#define REGI2C_CONF1_DCDC_SEL    (BIT(10))
 
 #define I2C_ANA_MST_ANA_CONF2_REG          (DR_REG_I2C_ANA_MST_BASE + 0x20)
-/* I2C_ANA_MST_STATUS2 : RO ;bitpos:[31:24] ;default: 8'h0 ; */
+/* I2C_ANA_MST_ANA_STATUS2 : RO ;bitpos:[31:24] ;default: 8'h0 ; */
 /*description: .*/
 #define I2C_ANA_MST_ANA_STATUS2    0x000000FF
-#define I2C_ANA_MST_ANA_STATUS2_M  ((I2C_ANA_MST_STATUS2_V)<<(I2C_ANA_MST_STATUS2_S))
+#define I2C_ANA_MST_ANA_STATUS2_M  ((I2C_ANA_MST_ANA_STATUS2_V)<<(I2C_ANA_MST_ANA_STATUS2_S))
 #define I2C_ANA_MST_ANA_STATUS2_V  0xFF
 #define I2C_ANA_MST_ANA_STATUS2_S  24
 /* I2C_ANA_MST_ANA_CONF2 : R/W ;bitpos:[23:0] ;default: 24'h00_0004 ; */
@@ -146,74 +196,121 @@ extern "C" {
 #define I2C_ANA_MST_ANA_CONF2_M  ((I2C_ANA_MST_ANA_CONF2_V)<<(I2C_ANA_MST_ANA_CONF2_S))
 #define I2C_ANA_MST_ANA_CONF2_V  0xFFFFFF
 #define I2C_ANA_MST_ANA_CONF2_S  0
+/*      bit4  : BB_TOP_I2C
+        bit5  : TXTOP_I2C
+        bit6  : SDM_I2C
+        bit7  : PLL_I2C
+        bit8  : BIAS_I2C
+        bit9  : BB_PLL_I2C
+        bit10 : ULP_I2C
+        bit11 : PERIF_I2C
+        bit12 : DCDC_I2C
+*/
+#define REGI2C_CONF2_BBTOP_SEL   (BIT(4))
+#define REGI2C_CONF2_TXTOP_SEL   (BIT(5))
+#define REGI2C_CONF2_SDM_SEL     (BIT(6))
+#define REGI2C_CONF2_PLL_SEL     (BIT(7))
+#define REGI2C_CONF2_BIAS_SEL    (BIT(8))
+#define REGI2C_CONF2_BBPLL_SEL   (BIT(9))
+#define REGI2C_CONF2_ULP_SEL     (BIT(10))
+#define REGI2C_CONF2_PERIF_SEL   (BIT(11))
+#define REGI2C_CONF2_DCDC_SEL    (BIT(12))
 
 #define I2C_ANA_MST_I2C0_CTRL1_REG          (DR_REG_I2C_ANA_MST_BASE + 0x24)
-/* I2C_MST_I2C0_SDA_SIDE_GUARD : R/W ;bitpos:[10:6] ;default: 5'h1 ; */
+/* I2C_ANA_MST_I2C0_SDA_SIDE_GUARD : R/W ;bitpos:[10:6] ;default: 5'h1 ; */
 /*description: .*/
 #define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD    0x0000001F
-#define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_M  ((I2C_MST_I2C0_SDA_SIDE_GUARD_V)<<(I2C_MST_I2C0_SDA_SIDE_GUARD_S))
+#define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_M  ((I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_V)<<(I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_S))
 #define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_V  0x1F
 #define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_S  6
-/* I2C_MST_I2C0_SCL_PULSE_DUR : R/W ;bitpos:[5:0] ;default: 6'h2 ; */
+/* I2C_ANA_MST_I2C0_SCL_PULSE_DUR : R/W ;bitpos:[5:0] ;default: 6'h2 ; */
 /*description: .*/
 #define I2C_ANA_MST_I2C0_SCL_PULSE_DUR    0x0000003F
-#define I2C_ANA_MST_I2C0_SCL_PULSE_DUR_M  ((I2C_MST_I2C0_SCL_PULSE_DUR_V)<<(I2C_MST_I2C0_SCL_PULSE_DUR_S))
+#define I2C_ANA_MST_I2C0_SCL_PULSE_DUR_M  ((I2C_ANA_MST_I2C0_SCL_PULSE_DUR_V)<<(I2C_ANA_MST_I2C0_SCL_PULSE_DUR_S))
 #define I2C_ANA_MST_I2C0_SCL_PULSE_DUR_V  0x3F
 #define I2C_ANA_MST_I2C0_SCL_PULSE_DUR_S  0
 
 #define I2C_ANA_MST_I2C1_CTRL1_REG          (DR_REG_I2C_ANA_MST_BASE + 0x28)
-/* I2C_MST_I2C1_SDA_SIDE_GUARD : R/W ;bitpos:[10:6] ;default: 5'h1 ; */
+/* I2C_ANA_MST_I2C1_SDA_SIDE_GUARD : R/W ;bitpos:[10:6] ;default: 5'h1 ; */
 /*description: .*/
 #define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD    0x0000001F
-#define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_M  ((I2C_MST_I2C1_SDA_SIDE_GUARD_V)<<(I2C_MST_I2C1_SDA_SIDE_GUARD_S))
+#define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_M  ((I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_V)<<(I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_S))
 #define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_V  0x1F
 #define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_S  6
-/* I2C_MST_I2C1_SCL_PULSE_DUR : R/W ;bitpos:[5:0] ;default: 6'h2 ; */
+/* I2C_ANA_MST_I2C1_SCL_PULSE_DUR : R/W ;bitpos:[5:0] ;default: 6'h2 ; */
 /*description: .*/
 #define I2C_ANA_MST_I2C1_SCL_PULSE_DUR    0x0000003F
-#define I2C_ANA_MST_I2C1_SCL_PULSE_DUR_M  ((I2C_MST_I2C1_SCL_PULSE_DUR_V)<<(I2C_MST_I2C1_SCL_PULSE_DUR_S))
+#define I2C_ANA_MST_I2C1_SCL_PULSE_DUR_M  ((I2C_ANA_MST_I2C1_SCL_PULSE_DUR_V)<<(I2C_ANA_MST_I2C1_SCL_PULSE_DUR_S))
 #define I2C_ANA_MST_I2C1_SCL_PULSE_DUR_V  0x3F
 #define I2C_ANA_MST_I2C1_SCL_PULSE_DUR_S  0
 
 #define I2C_ANA_MST_HW_I2C_CTRL_REG          (DR_REG_I2C_ANA_MST_BASE + 0x2C)
-/* I2C_MST_ARBITER_DIS : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/* I2C_ANA_MST_ARBITER_DIS : R/W ;bitpos:[11] ;default: 1'h0 ; */
 /*description: .*/
 #define I2C_ANA_MST_ARBITER_DIS    (BIT(11))
 #define I2C_ANA_MST_ARBITER_DIS_M  (BIT(11))
 #define I2C_ANA_MST_ARBITER_DIS_V  0x1
 #define I2C_ANA_MST_ARBITER_DIS_S  11
-/* I2C_MST_HW_I2C_SDA_SIDE_GUARD : R/W ;bitpos:[10:6] ;default: 5'h1 ; */
+/* I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD : R/W ;bitpos:[10:6] ;default: 5'h1 ; */
 /*description: .*/
 #define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD    0x0000001F
-#define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_M  ((I2C_MST_HW_I2C_SDA_SIDE_GUARD_V)<<(I2C_MST_HW_I2C_SDA_SIDE_GUARD_S))
+#define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_M  ((I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_V)<<(I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_S))
 #define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_V  0x1F
 #define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_S  6
-/* I2C_MST_HW_I2C_SCL_PULSE_DUR : R/W ;bitpos:[5:0] ;default: 6'h2 ; */
+/* I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR : R/W ;bitpos:[5:0] ;default: 6'h2 ; */
 /*description: .*/
 #define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR    0x0000003F
-#define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_M  ((I2C_MST_HW_I2C_SCL_PULSE_DUR_V)<<(I2C_MST_HW_I2C_SCL_PULSE_DUR_S))
+#define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_M  ((I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_V)<<(I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_S))
 #define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_V  0x3F
 #define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_S  0
 
-#define I2C_ANA_MST_NOUSE_REG          (DR_REG_I2C_ANA_MST_BASE + 0x30)
-/* I2C_MST_NOUSE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+#define I2C_ANA_MST_I2C_MST_NOUSE_REG          (DR_REG_I2C_ANA_MST_BASE + 0x30)
+/* I2C_ANA_MST_I2C_MST_NOUSE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
 /*description: .*/
-#define I2C_ANA_MST_NOUSE    0xFFFFFFFF
-#define I2C_ANA_MST_NOUSE_M  ((I2C_MST_NOUSE_V)<<(I2C_MST_NOUSE_S))
-#define I2C_ANA_MST_NOUSE_V  0xFFFFFFFF
-#define I2C_ANA_MST_NOUSE_S  0
+#define I2C_ANA_MST_I2C_MST_NOUSE    0xFFFFFFFF
+#define I2C_ANA_MST_I2C_MST_NOUSE_M  ((I2C_ANA_MST_I2C_MST_NOUSE_V)<<(I2C_ANA_MST_I2C_MST_NOUSE_S))
+#define I2C_ANA_MST_I2C_MST_NOUSE_V  0xFFFFFFFF
+#define I2C_ANA_MST_I2C_MST_NOUSE_S  0
 
-#define I2C_ANA_MST_DATE_REG          (DR_REG_I2C_ANA_MST_BASE + 0x34)
-/* I2C_MST_CLK_EN : R/W ;bitpos:[28] ;default: 1'h0 ; */
+#define I2C_ANA_MST_EXT_I2C_MASK_REG        (DR_REG_I2C_ANA_MST_BASE + 0x34)
+/* I2C_ANA_MST_EXT_I2C_SDA_O_MASK : R/W ;bitpos:[31:16] ;default: 16'h0 ; */
+/*description: .*/
+#define I2C_ANA_MST_EXT_I2C_SDA_O_MASK    0x0000FFFF
+#define I2C_ANA_MST_EXT_I2C_SDA_O_MASK_M  ((I2C_ANA_MST_EXT_I2C_SDA_O_MASK_V)<<(I2C_ANA_MST_EXT_I2C_SDA_O_MASK_S))
+#define I2C_ANA_MST_EXT_I2C_SDA_O_MASK_V  0x0000FFFF
+#define I2C_ANA_MST_EXT_I2C_SDA_O_MASK_S  16
+/* I2C_ANA_MST_EXT_I2C_SDA_I_MASK : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: .*/
+#define I2C_ANA_MST_EXT_I2C_SDA_I_MASK    0x0000FFFF
+#define I2C_ANA_MST_EXT_I2C_SDA_I_MASK_M  ((I2C_ANA_MST_EXT_I2C_SDA_I_MASK_V)<<(I2C_ANA_MST_EXT_I2C_SDA_I_MASK_S))
+#define I2C_ANA_MST_EXT_I2C_SDA_I_MASK_V  0x0000FFFF
+#define I2C_ANA_MST_EXT_I2C_SDA_I_MASK_S  16
+
+#define I2C_ANA_MST_I2C_MASK_REG (DR_REG_I2C_ANA_MST_BASE + 0x38)
+/* I2C_ANA_MST_I2C_SDA_O_MASK : R/W ;bitpos:[31:16] ;default: 16'h0 ; */
+/*description: .*/
+#define I2C_ANA_MST_I2C_SDA_O_MASK    0x0000FFFF
+#define I2C_ANA_MST_I2C_SDA_O_MASK_M  ((I2C_ANA_MST_I2C_SDA_O_MASK_V)<<(I2C_ANA_MST_I2C_SDA_O_MASK_S))
+#define I2C_ANA_MST_I2C_SDA_O_MASK_V  0x0000FFFF
+#define I2C_ANA_MST_I2C_SDA_O_MASK_S  16
+/* I2C_ANA_MST_I2C_SDA_I_MASK : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: .*/
+#define I2C_ANA_MST_I2C_SDA_I_MASK    0x0000FFFF
+#define I2C_ANA_MST_I2C_SDA_I_MASK_M  ((I2C_ANA_MST_I2C_SDA_I_MASK_V)<<(I2C_ANA_MST_I2C_SDA_I_MASK_S))
+#define I2C_ANA_MST_I2C_SDA_I_MASK_V  0x0000FFFF
+#define I2C_ANA_MST_I2C_SDA_I_MASK_S  16
+
+#define I2C_ANA_MST_DATE_REG          (DR_REG_I2C_ANA_MST_BASE + 0x3C)
+/* I2C_ANA_MST_CLK_EN : R/W ;bitpos:[28] ;default: 1'h0 ; */
 /*description: .*/
 #define I2C_ANA_MST_CLK_EN    (BIT(28))
 #define I2C_ANA_MST_CLK_EN_M  (BIT(28))
 #define I2C_ANA_MST_CLK_EN_V  0x1
 #define I2C_ANA_MST_CLK_EN_S  28
-/* I2C_MST_DATE : R/W ;bitpos:[27:0] ;default: 28'h2201300 ; */
+/* I2C_ANA_MST_DATE : R/W ;bitpos:[27:0] ;default: 28'h2411290 ; */
 /*description: .*/
 #define I2C_ANA_MST_DATE    0x0FFFFFFF
-#define I2C_ANA_MST_DATE_M  ((I2C_MST_DATE_V)<<(I2C_MST_DATE_S))
+#define I2C_ANA_MST_DATE_M  ((I2C_ANA_MST_DATE_V)<<(I2C_ANA_MST_DATE_S))
 #define I2C_ANA_MST_DATE_V  0xFFFFFFF
 #define I2C_ANA_MST_DATE_S  0
 
diff --git a/components/soc/esp32h4/include/soc/reg_base.h b/components/soc/esp32h4/include/soc/reg_base.h
index d5ca03b414..7a0786329b 100644
--- a/components/soc/esp32h4/include/soc/reg_base.h
+++ b/components/soc/esp32h4/include/soc/reg_base.h
@@ -75,6 +75,6 @@
 #define DR_REG_LP_WDT_BASE                        0x600B5400
 #define DR_REG_TOUCH_SENS_BASE                    0x600B5800
 #define DR_REG_TOUCH_AON_BASE                     0x600B5C00
+#define DR_REG_I2C_ANA_MST_BASE                   0x600CF800 // (DR_REG_MODEM_PWR_BASE + 0x2800)
 
-#define DR_REG_I2C_ANA_MST_BASE                   0x600AF800    // TODO: [ESP32H4] IDF-12315 inherit from verify code, need check
 #define DR_REG_CLINT_M_BASE                       0x20000000    // TODO: [ESP32H4] IDF-12303 inherit from verify code, need check
diff --git a/components/soc/esp32h4/include/soc/regi2c_bbpll.h b/components/soc/esp32h4/include/soc/regi2c_bbpll.h
index 4b54a491b4..4ff7047c4a 100644
--- a/components/soc/esp32h4/include/soc/regi2c_bbpll.h
+++ b/components/soc/esp32h4/include/soc/regi2c_bbpll.h
@@ -50,71 +50,19 @@
 #define I2C_BBPLL_OC_REF_DIV_MSB    3
 #define I2C_BBPLL_OC_REF_DIV_LSB    0
 
-#define I2C_BBPLL_OC_DCHGP        2
-#define I2C_BBPLL_OC_DCHGP_MSB    6
-#define I2C_BBPLL_OC_DCHGP_LSB    4
-
-#define I2C_BBPLL_OC_ENB_FCAL        2
-#define I2C_BBPLL_OC_ENB_FCAL_MSB    7
-#define I2C_BBPLL_OC_ENB_FCAL_LSB    7
-
-#define I2C_BBPLL_OC_DIV_7_0        3
-#define I2C_BBPLL_OC_DIV_7_0_MSB    7
-#define I2C_BBPLL_OC_DIV_7_0_LSB    0
-
-#define I2C_BBPLL_RSTB_DIV_ADC        4
-#define I2C_BBPLL_RSTB_DIV_ADC_MSB    0
-#define I2C_BBPLL_RSTB_DIV_ADC_LSB    0
-
-#define I2C_BBPLL_MODE_HF        4
-#define I2C_BBPLL_MODE_HF_MSB    1
-#define I2C_BBPLL_MODE_HF_LSB    1
-
-#define I2C_BBPLL_DIV_ADC        4
-#define I2C_BBPLL_DIV_ADC_MSB    3
-#define I2C_BBPLL_DIV_ADC_LSB    2
-
-#define I2C_BBPLL_DIV_DAC        4
-#define I2C_BBPLL_DIV_DAC_MSB    4
-#define I2C_BBPLL_DIV_DAC_LSB    4
-
-#define I2C_BBPLL_DIV_CPU        4
-#define I2C_BBPLL_DIV_CPU_MSB    5
-#define I2C_BBPLL_DIV_CPU_LSB    5
-
-#define I2C_BBPLL_OC_ENB_VCON        4
-#define I2C_BBPLL_OC_ENB_VCON_MSB    6
-#define I2C_BBPLL_OC_ENB_VCON_LSB    6
+#define I2C_BBPLL_OC_DIV        3
+#define I2C_BBPLL_OC_DIV_MSB    5
+#define I2C_BBPLL_OC_DIV_LSB    0
 
 #define I2C_BBPLL_OC_TSCHGP        4
-#define I2C_BBPLL_OC_TSCHGP_MSB    7
-#define I2C_BBPLL_OC_TSCHGP_LSB    7
+#define I2C_BBPLL_OC_TSCHGP_MSB    6
+#define I2C_BBPLL_OC_TSCHGP_LSB    6
 
-#define I2C_BBPLL_OC_DR1        5
-#define I2C_BBPLL_OC_DR1_MSB    2
-#define I2C_BBPLL_OC_DR1_LSB    0
-
-#define I2C_BBPLL_OC_DR3        5
-#define I2C_BBPLL_OC_DR3_MSB    6
-#define I2C_BBPLL_OC_DR3_LSB    4
-
-#define I2C_BBPLL_EN_USB        5
-#define I2C_BBPLL_EN_USB_MSB    7
-#define I2C_BBPLL_EN_USB_LSB    7
-
-#define I2C_BBPLL_OC_DCUR        6
-#define I2C_BBPLL_OC_DCUR_MSB    2
-#define I2C_BBPLL_OC_DCUR_LSB    0
-
-#define I2C_BBPLL_INC_CUR        6
-#define I2C_BBPLL_INC_CUR_MSB    3
-#define I2C_BBPLL_INC_CUR_LSB    3
-
-#define I2C_BBPLL_OC_DHREF_SEL        6
+#define I2C_BBPLL_OC_DHREF_SEL        5
 #define I2C_BBPLL_OC_DHREF_SEL_MSB    5
 #define I2C_BBPLL_OC_DHREF_SEL_LSB    4
 
-#define I2C_BBPLL_OC_DLREF_SEL        6
+#define I2C_BBPLL_OC_DLREF_SEL        5
 #define I2C_BBPLL_OC_DLREF_SEL_MSB    7
 #define I2C_BBPLL_OC_DLREF_SEL_LSB    6
 
@@ -138,38 +86,10 @@
 #define I2C_BBPLL_OR_LOCK_MSB    7
 #define I2C_BBPLL_OR_LOCK_LSB    7
 
-#define I2C_BBPLL_OC_VCO_DBIAS        9
-#define I2C_BBPLL_OC_VCO_DBIAS_MSB    1
-#define I2C_BBPLL_OC_VCO_DBIAS_LSB    0
-
-#define I2C_BBPLL_BBADC_DELAY2        9
-#define I2C_BBPLL_BBADC_DELAY2_MSB    3
-#define I2C_BBPLL_BBADC_DELAY2_LSB    2
-
-#define I2C_BBPLL_BBADC_DVDD        9
-#define I2C_BBPLL_BBADC_DVDD_MSB    5
-#define I2C_BBPLL_BBADC_DVDD_LSB    4
-
-#define I2C_BBPLL_BBADC_DREF        9
-#define I2C_BBPLL_BBADC_DREF_MSB    7
-#define I2C_BBPLL_BBADC_DREF_LSB    6
-
-#define I2C_BBPLL_BBADC_DCUR        10
-#define I2C_BBPLL_BBADC_DCUR_MSB    1
-#define I2C_BBPLL_BBADC_DCUR_LSB    0
-
-#define I2C_BBPLL_BBADC_INPUT_SHORT        10
-#define I2C_BBPLL_BBADC_INPUT_SHORT_MSB    2
-#define I2C_BBPLL_BBADC_INPUT_SHORT_LSB    2
-
 #define I2C_BBPLL_ENT_PLL        10
-#define I2C_BBPLL_ENT_PLL_MSB    3
-#define I2C_BBPLL_ENT_PLL_LSB    3
+#define I2C_BBPLL_ENT_PLL_MSB    2
+#define I2C_BBPLL_ENT_PLL_LSB    2
 
 #define I2C_BBPLL_DTEST        10
-#define I2C_BBPLL_DTEST_MSB    5
-#define I2C_BBPLL_DTEST_LSB    4
-
-#define I2C_BBPLL_ENT_ADC        10
-#define I2C_BBPLL_ENT_ADC_MSB    7
-#define I2C_BBPLL_ENT_ADC_LSB    6
+#define I2C_BBPLL_DTEST_MSB    1
+#define I2C_BBPLL_DTEST_LSB    0
diff --git a/components/soc/esp32h4/include/soc/regi2c_bbtop.h b/components/soc/esp32h4/include/soc/regi2c_bbtop.h
new file mode 100644
index 0000000000..346f3e0d2e
--- /dev/null
+++ b/components/soc/esp32h4/include/soc/regi2c_bbtop.h
@@ -0,0 +1,10 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#define I2C_BBTOP            0x67
+#define I2C_BBTOP_HOSTID     0
diff --git a/components/soc/esp32h4/include/soc/regi2c_bias.h b/components/soc/esp32h4/include/soc/regi2c_bias.h
deleted file mode 100644
index 8e696e3818..0000000000
--- a/components/soc/esp32h4/include/soc/regi2c_bias.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#pragma once
-
-/**
- * @file regi2c_bias.h
- * @brief Register definitions for bias
- *
- * This file lists register fields of BIAS. These definitions are used via macros defined in regi2c_ctrl.h, by
- * bootloader_hardware_init function in bootloader_esp32c6.c.
- */
-
-#define I2C_BIAS            0X6A
-#define I2C_BIAS_HOSTID     0
-
-#define I2C_BIAS_DREG_1P1_PVT 1
-#define I2C_BIAS_DREG_1P1_PVT_MSB 3
-#define I2C_BIAS_DREG_1P1_PVT_LSB 0
diff --git a/components/soc/esp32h4/include/soc/regi2c_brownout.h b/components/soc/esp32h4/include/soc/regi2c_brownout.h
deleted file mode 100644
index c4e24993c6..0000000000
--- a/components/soc/esp32h4/include/soc/regi2c_brownout.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#pragma once
-
-/**
- * @file regi2c_brownout.h
- * @brief Register definitions for brownout detector
- *
- * This file lists register fields of the brownout detector, located on an internal configuration
- * bus. These definitions are used via macros defined in regi2c_ctrl.h.
- */
-
-#define I2C_BOD            0x61
-#define I2C_BOD_HOSTID     0
-
-#define I2C_BOD_THRESHOLD           0x5
-#define I2C_BOD_THRESHOLD_MSB       2
-#define I2C_BOD_THRESHOLD_LSB       0
diff --git a/components/soc/esp32h4/include/soc/regi2c_dcdc.h b/components/soc/esp32h4/include/soc/regi2c_dcdc.h
new file mode 100644
index 0000000000..361f9c867e
--- /dev/null
+++ b/components/soc/esp32h4/include/soc/regi2c_dcdc.h
@@ -0,0 +1,32 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+/**
+ * @file regi2c_dcdc.h
+ * @brief Register definitions for digital to get rtc voltage & digital voltage
+ *        by setting rtc_dbias_Wak & dig_dbias_wak or by analog self-calibration.
+ */
+
+#define I2C_DCDC    0x6D
+#define I2C_DCDC_HOSTID 0
+
+#define I2C_DCDC_CCM_DREG0               7
+#define I2C_DCDC_CCM_DREG0_MSB           4
+#define I2C_DCDC_CCM_DREG0_LSB           0
+
+#define I2C_DCDC_CCM_PCUR_LIMIT0        7
+#define I2C_DCDC_CCM_PCUR_LIMIT0_MSB    7
+#define I2C_DCDC_CCM_PCUR_LIMIT0_LSB    5
+
+#define I2C_DCDC_VCM_DREG0              10
+#define I2C_DCDC_VCM_DREG0_MSB          4
+#define I2C_DCDC_VCM_DREG0_LSB          0
+
+#define I2C_DCDC_VCM_PCUR_LIMIT0        10
+#define I2C_DCDC_VCM_PCUR_LIMIT0_MSB    7
+#define I2C_DCDC_VCM_PCUR_LIMIT0_LSB    5
diff --git a/components/soc/esp32h4/include/soc/regi2c_defs.h b/components/soc/esp32h4/include/soc/regi2c_defs.h
deleted file mode 100644
index fab4b60504..0000000000
--- a/components/soc/esp32h4/include/soc/regi2c_defs.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#pragma once
-
-#include "esp_bit_defs.h"
-
-/* Analog function control register */
-#define I2C_MST_ANA_CONF0_REG          0x600AF818
-#define I2C_MST_BBPLL_STOP_FORCE_HIGH  (BIT(2))
-#define I2C_MST_BBPLL_STOP_FORCE_LOW   (BIT(3))
-#define I2C_MST_BBPLL_CAL_DONE         (BIT(24))
diff --git a/components/soc/esp32h4/include/soc/regi2c_dig_reg.h b/components/soc/esp32h4/include/soc/regi2c_dig_reg.h
deleted file mode 100644
index 9404325185..0000000000
--- a/components/soc/esp32h4/include/soc/regi2c_dig_reg.h
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#pragma once
-
-/**
- * @file regi2c_dig_reg.h
- * @brief Register definitions for digital to get rtc voltage & digital voltage
- *        by setting rtc_dbias_Wak & dig_dbias_wak or by analog self-calibration.
- */
-
-#define I2C_DIG_REG 0x6D
-#define I2C_DIG_REG_HOSTID 0
-
-#define I2C_DIG_REG_EXT_RTC_DREG    4
-#define I2C_DIG_REG_EXT_RTC_DREG_MSB    4
-#define I2C_DIG_REG_EXT_RTC_DREG_LSB    0
-
-#define I2C_DIG_REG_ENX_RTC_DREG    4
-#define I2C_DIG_REG_ENX_RTC_DREG_MSB    7
-#define I2C_DIG_REG_ENX_RTC_DREG_LSB    7
-
-#define I2C_DIG_REG_EXT_RTC_DREG_SLEEP    5
-#define I2C_DIG_REG_EXT_RTC_DREG_SLEEP_MSB    4
-#define I2C_DIG_REG_EXT_RTC_DREG_SLEEP_LSB    0
-
-#define I2C_DIG_REG_ENIF_RTC_DREG    5
-#define I2C_DIG_REG_ENIF_RTC_DREG_MSB    7
-#define I2C_DIG_REG_ENIF_RTC_DREG_LSB    7
-
-#define I2C_DIG_REG_EXT_DIG_DREG    6
-#define I2C_DIG_REG_EXT_DIG_DREG_MSB    4
-#define I2C_DIG_REG_EXT_DIG_DREG_LSB    0
-
-#define I2C_DIG_REG_ENX_DIG_DREG    6
-#define I2C_DIG_REG_ENX_DIG_DREG_MSB    7
-#define I2C_DIG_REG_ENX_DIG_DREG_LSB    7
-
-#define I2C_DIG_REG_EXT_DIG_DREG_SLEEP    7
-#define I2C_DIG_REG_EXT_DIG_DREG_SLEEP_MSB    4
-#define I2C_DIG_REG_EXT_DIG_DREG_SLEEP_LSB    0
-
-#define I2C_DIG_REG_ENIF_DIG_DREG    7
-#define I2C_DIG_REG_ENIF_DIG_DREG_MSB    7
-#define I2C_DIG_REG_ENIF_DIG_DREG_LSB    7
-
-#define I2C_DIG_REG_OR_EN_CONT_CAL 9
-#define I2C_DIG_REG_OR_EN_CONT_CAL_MSB 7
-#define I2C_DIG_REG_OR_EN_CONT_CAL_LSB 7
-
-#define I2C_DIG_REG_XPD_RTC_REG 13
-#define I2C_DIG_REG_XPD_RTC_REG_MSB 2
-#define I2C_DIG_REG_XPD_RTC_REG_LSB 2
-
-#define I2C_DIG_REG_XPD_DIG_REG 13
-#define I2C_DIG_REG_XPD_DIG_REG_MSB 3
-#define I2C_DIG_REG_XPD_DIG_REG_LSB 3
-
-#define I2C_DIG_REG_SCK_DCAP    14
-#define I2C_DIG_REG_SCK_DCAP_MSB    7
-#define I2C_DIG_REG_SCK_DCAP_LSB    0
diff --git a/components/soc/esp32h4/include/soc/regi2c_pll.h b/components/soc/esp32h4/include/soc/regi2c_pll.h
new file mode 100644
index 0000000000..db7e48fcc0
--- /dev/null
+++ b/components/soc/esp32h4/include/soc/regi2c_pll.h
@@ -0,0 +1,18 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#define I2C_PLL            0x62
+#define I2C_PLL_HOSTID     0
+
+#define I2C_PLL_DTEST 6
+#define I2C_PLL_DTEST_MSB 1
+#define I2C_PLL_DTEST_LSB 0
+
+#define I2C_PLL_EN_TEST_PLL 6
+#define I2C_PLL_EN_TEST_PLL_MSB 2
+#define I2C_PLL_EN_TEST_PLL_LSB 2
diff --git a/components/soc/esp32h4/include/soc/regi2c_saradc.h b/components/soc/esp32h4/include/soc/regi2c_saradc.h
index e69de29bb2..94034a11ce 100644
--- a/components/soc/esp32h4/include/soc/regi2c_saradc.h
+++ b/components/soc/esp32h4/include/soc/regi2c_saradc.h
@@ -0,0 +1,42 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#define I2C_SARADC            0x69
+#define I2C_SARADC_HOSTID     0
+
+#define I2C_SARADC_SAR1_INIT_CODE_LSB 0
+#define I2C_SARADC_SAR1_INIT_CODE_LSB_MSB 7
+#define I2C_SARADC_SAR1_INIT_CODE_LSB_LSB 0
+
+#define I2C_SARADC_SAR1_INIT_CODE_MSB 1
+#define I2C_SARADC_SAR1_INIT_CODE_MSB_MSB 3
+#define I2C_SARADC_SAR1_INIT_CODE_MSB_LSB 0
+
+#define I2C_SARADC_SAR2_INIT_CODE_LSB 3
+#define I2C_SARADC_SAR2_INIT_CODE_LSB_MSB 7
+#define I2C_SARADC_SAR2_INIT_CODE_LSB_LSB 0
+
+#define I2C_SARADC_SAR2_INIT_CODE_MSB 4
+#define I2C_SARADC_SAR2_INIT_CODE_MSB_MSB 3
+#define I2C_SARADC_SAR2_INIT_CODE_MSB_LSB 0
+
+#define I2C_SARADC_DTEST 7
+#define I2C_SARADC_DTEST_MSB 1
+#define I2C_SARADC_DTEST_LSB 0
+
+#define I2C_SARADC_ENT_SAR 7
+#define I2C_SARADC_ENT_SAR_MSB 3
+#define I2C_SARADC_ENT_SAR_LSB 2
+
+#define I2C_SARADC_EN_TOUT_SAR1_BUS 7
+#define I2C_SARADC_EN_TOUT_SAR1_BUS_MSB 5
+#define I2C_SARADC_EN_TOUT_SAR1_BUS_LSB 5
+
+#define I2C_SARADC_EN_TOUT_SAR2_BUS 7
+#define I2C_SARADC_EN_TOUT_SAR2_BUS_MSB 6
+#define I2C_SARADC_EN_TOUT_SAR2_BUS_LSB 6
diff --git a/components/soc/esp32h4/include/soc/regi2c_sdm.h b/components/soc/esp32h4/include/soc/regi2c_sdm.h
new file mode 100644
index 0000000000..f3ebf8d02a
--- /dev/null
+++ b/components/soc/esp32h4/include/soc/regi2c_sdm.h
@@ -0,0 +1,10 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#define I2C_SDM            0x63
+#define I2C_SDM_HOSTID     0
diff --git a/components/soc/esp32h4/include/soc/regi2c_lp_bias.h b/components/soc/esp32h4/include/soc/regi2c_ulp.h
similarity index 84%
rename from components/soc/esp32h4/include/soc/regi2c_lp_bias.h
rename to components/soc/esp32h4/include/soc/regi2c_ulp.h
index 1fba92cf86..2747c8207a 100644
--- a/components/soc/esp32h4/include/soc/regi2c_lp_bias.h
+++ b/components/soc/esp32h4/include/soc/regi2c_ulp.h
@@ -7,7 +7,7 @@
 #pragma once
 
 /**
- * @file regi2c_lp_bias.h
+ * @file regi2c_ulp.h
  * @brief Register definitions for analog to calibrate o_code for getting a more precise voltage.
  *
  * This file lists register fields of low power dbais, located on an internal configuration
@@ -30,10 +30,6 @@
 #define I2C_ULP_IR_FORCE_XPD_IPH_MSB 4
 #define I2C_ULP_IR_FORCE_XPD_IPH_LSB 4
 
-#define I2C_ULP_IR_DISABLE_WATCHDOG_CK 0
-#define I2C_ULP_IR_DISABLE_WATCHDOG_CK_MSB 6
-#define I2C_ULP_IR_DISABLE_WATCHDOG_CK_LSB 6
-
 #define I2C_ULP_O_DONE_FLAG 3
 #define I2C_ULP_O_DONE_FLAG_MSB 0
 #define I2C_ULP_O_DONE_FLAG_LSB 0
@@ -47,8 +43,8 @@
 #define I2C_ULP_OCODE_LSB 0
 
 #define I2C_ULP_IR_FORCE_CODE 5
-#define I2C_ULP_IR_FORCE_CODE_MSB 6
-#define I2C_ULP_IR_FORCE_CODE_LSB 6
+#define I2C_ULP_IR_FORCE_CODE_MSB 3
+#define I2C_ULP_IR_FORCE_CODE_LSB 3
 
 #define I2C_ULP_EXT_CODE 6
 #define I2C_ULP_EXT_CODE_MSB 7
diff --git a/components/soc/esp32h4/include/soc/soc_caps.h b/components/soc/esp32h4/include/soc/soc_caps.h
index 7cdd816143..7bd33f63c7 100644
--- a/components/soc/esp32h4/include/soc/soc_caps.h
+++ b/components/soc/esp32h4/include/soc/soc_caps.h
@@ -75,6 +75,7 @@
 // #define SOC_LP_PERIPHERALS_SUPPORTED    1
 // #define SOC_LP_I2C_SUPPORTED            1    // TODO: [ESP32H4] IDF-12449
 // #define SOC_ULP_LP_UART_SUPPORTED       1    // TODO: [ESP32H4] IDF-12445 IDF-12451
+#define SOC_REG_I2C_SUPPORTED           1
 // #define SOC_CLK_TREE_SUPPORTED          1    // TODO: [ESP32H4] IDF-12285
 // #define SOC_ASSIST_DEBUG_SUPPORTED      1    // TODO: [ESP32H4] IDF-12310
 #define SOC_WDT_SUPPORTED               1