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feat(usb/device): Add USB device support to ESP32-P4 v3

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This commit is contained in:
Tomas Rezucha
2025-09-17 10:00:26 +02:00
parent 1711ed88aa
commit ce590e4bae
2 changed files with 16 additions and 140 deletions
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17
components/esp_hw_support/usb_phy/usb_phy.c
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@@ -145,7 +145,22 @@ esp_err_t usb_phy_otg_set_mode(usb_phy_handle_t handle, usb_otg_mode_t mode)
// USB-DWC2.0 <-> UTMI PHY
// USB-DWC1.1 <-> FSLS PHY
if (handle->target == USB_PHY_TARGET_UTMI) {
return ESP_OK; // No need to configure anything for UTMI PHY
// ESP32-P4 v3 changed connection between USB-OTG peripheral and UTMI PHY.
// On v3 the 15k pulldown resistors on D+/D- are no longer controlled by USB-OTG,
// but must be controlled directly by this software driver.
#if CONFIG_IDF_TARGET_ESP32P4 && !CONFIG_ESP32P4_SELECTS_REV_LESS_V3
#include "soc/lp_system_struct.h"
if (mode == USB_OTG_MODE_HOST) {
// Host must connect 15k pulldown resistors on D+ / D-
LP_SYS.hp_usb_otghs_phy_ctrl.hp_utmiotg_dppulldown = 1;
LP_SYS.hp_usb_otghs_phy_ctrl.hp_utmiotg_dmpulldown = 1;
} else {
// Device must not connect any pulldown resistors on D+ / D-
LP_SYS.hp_usb_otghs_phy_ctrl.hp_utmiotg_dppulldown = 0;
LP_SYS.hp_usb_otghs_phy_ctrl.hp_utmiotg_dmpulldown = 0;
}
#endif // !CONFIG_ESP32P4_SELECTS_REV_LESS_V3
return ESP_OK;
}
const usb_otg_signal_conn_t *otg_sig = usb_dwc_info.controllers[otg11_index].otg_signals;

139
components/soc/esp32p4/register/hw_ver3/soc/usb_wrap_eco5_struct.h
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@@ -1,139 +0,0 @@
/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C" {
#endif
/** Group: USB wrapper registers. */
/** Type of otg_conf register
* USB wrapper configuration registers.
*/
typedef union {
struct {
/** srp_sessend_override : R/W; bitpos: [0]; default: 0;
* This bit is used to enable the software over-ride of srp session end signal. 1'b0:
* the signal is controlled by the chip input, 1'b1: the signal is controlled by the
* software.
*/
uint32_t srp_sessend_override:1;
/** srp_sessend_value : R/W; bitpos: [1]; default: 0;
* Software over-ride value of srp session end signal.
*/
uint32_t srp_sessend_value:1;
/** phy_sel : R/W; bitpos: [2]; default: 0;
* Select internal external PHY. 1'b0: Select internal PHY, 1'b1: Select external PHY.
*/
uint32_t phy_sel:1;
/** dfifo_force_pd : R/W; bitpos: [3]; default: 0;
* Force the dfifo to go into low power mode. The data in dfifo will not lost.
*/
uint32_t dfifo_force_pd:1;
/** dbnce_fltr_bypass : R/W; bitpos: [4]; default: 0;
* Bypass Debounce filters for avalid,bvalid,vbusvalid,session end, id signals
*/
uint32_t dbnce_fltr_bypass:1;
/** exchg_pins_override : R/W; bitpos: [5]; default: 0;
* Enable software controlle USB D+ D- exchange
*/
uint32_t exchg_pins_override:1;
/** exchg_pins : R/W; bitpos: [6]; default: 0;
* USB D+ D- exchange. 1'b0: don't change, 1'b1: exchange D+ D-.
*/
uint32_t exchg_pins:1;
/** vrefh : R/W; bitpos: [8:7]; default: 0;
* Control single-end input high threshold,1.76V to 2V, step 80mV.
*/
uint32_t vrefh:2;
/** vrefl : R/W; bitpos: [10:9]; default: 0;
* Control single-end input low threshold,0.8V to 1.04V, step 80mV.
*/
uint32_t vrefl:2;
/** vref_override : R/W; bitpos: [11]; default: 0;
* Enable software controlle input threshold.
*/
uint32_t vref_override:1;
/** pad_pull_override : R/W; bitpos: [12]; default: 0;
* Enable software controlle USB D+ D- pullup pulldown.
*/
uint32_t pad_pull_override:1;
/** dp_pullup : R/W; bitpos: [13]; default: 0;
* Controlle USB D+ pullup.
*/
uint32_t dp_pullup:1;
/** dp_pulldown : R/W; bitpos: [14]; default: 0;
* Controlle USB D+ pulldown.
*/
uint32_t dp_pulldown:1;
/** dm_pullup : R/W; bitpos: [15]; default: 0;
* Controlle USB D+ pullup.
*/
uint32_t dm_pullup:1;
/** dm_pulldown : R/W; bitpos: [16]; default: 0;
* Controlle USB D+ pulldown.
*/
uint32_t dm_pulldown:1;
/** pullup_value : R/W; bitpos: [17]; default: 0;
* Controlle pullup value. 1'b0: typical value is 2.4K, 1'b1: typical value is 1.2K.
*/
uint32_t pullup_value:1;
/** usb_pad_enable : R/W; bitpos: [18]; default: 0;
* Enable USB pad function.
*/
uint32_t usb_pad_enable:1;
/** ahb_clk_force_on : R/W; bitpos: [19]; default: 0;
* Force ahb clock always on.
*/
uint32_t ahb_clk_force_on:1;
/** phy_clk_force_on : R/W; bitpos: [20]; default: 1;
* Force phy clock always on.
*/
uint32_t phy_clk_force_on:1;
uint32_t reserved_21:1;
/** dfifo_force_pu : R/W; bitpos: [22]; default: 0;
* Disable the dfifo to go into low power mode. The data in dfifo will not lost.
*/
uint32_t dfifo_force_pu:1;
uint32_t reserved_23:8;
/** clk_en : R/W; bitpos: [31]; default: 0;
* Disable auto clock gating of CSR registers.
*/
uint32_t clk_en:1;
};
uint32_t val;
} usb_wrap_otg_conf_reg_t;
/** Type of date register
* Date register.
*/
typedef union {
struct {
/** usb_wrap_date : HRO; bitpos: [31:0]; default: 587400452;
* Date register.
*/
uint32_t usb_wrap_date:32;
};
uint32_t val;
} usb_wrap_date_reg_t;
typedef struct {
volatile usb_wrap_otg_conf_reg_t otg_conf;
uint32_t reserved_004[254];
volatile usb_wrap_date_reg_t date;
} usb_wrap_dev_t;
extern usb_wrap_dev_t USB_WRAP;
#ifndef __cplusplus
_Static_assert(sizeof(usb_wrap_dev_t) == 0x400, "Invalid size of usb_wrap_dev_t structure");
#endif
#ifdef __cplusplus
}
#endif