From ce822125e7ffe87a9139bd2f0f74dc72a68ac724 Mon Sep 17 00:00:00 2001 From: Konstantin Kondrashov Date: Fri, 16 Aug 2024 14:42:08 +0300 Subject: [PATCH] feat(efuse): Updates efuse table for esp32p4 --- components/efuse/esp32p4/esp_efuse_table.c | 492 +++++++++++++++--- components/efuse/esp32p4/esp_efuse_table.csv | 64 ++- .../efuse/esp32p4/include/esp_efuse_table.h | 58 ++- .../soc/esp32p4/include/soc/efuse_reg.h | 65 +-- .../soc/esp32p4/include/soc/efuse_struct.h | 38 +- 5 files changed, 562 insertions(+), 155 deletions(-) diff --git a/components/efuse/esp32p4/esp_efuse_table.c b/components/efuse/esp32p4/esp_efuse_table.c index 74bf9dd257..990c984365 100644 --- a/components/efuse/esp32p4/esp_efuse_table.c +++ b/components/efuse/esp32p4/esp_efuse_table.c @@ -9,7 +9,7 @@ #include #include "esp_efuse_table.h" -// md5_digest_table 2eb36a43d52e9922e08cf545d0e23381 +// md5_digest_table 0d4e1f49db99de4dd9d3eac8d8e6078b // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY. // If you want to change some fields, you need to change esp_efuse_table.csv file // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file. @@ -23,6 +23,98 @@ static const esp_efuse_desc_t WR_DIS_RD_DIS[] = { {EFUSE_BLK0, 0, 1}, // [] wr_dis of RD_DIS, }; +static const esp_efuse_desc_t WR_DIS_KM_RND_SWITCH_CYCLE[] = { + {EFUSE_BLK0, 1, 1}, // [] wr_dis of KM_RND_SWITCH_CYCLE, +}; + +static const esp_efuse_desc_t WR_DIS_KM_DEPLOY_ONLY_ONCE[] = { + {EFUSE_BLK0, 1, 1}, // [] wr_dis of KM_DEPLOY_ONLY_ONCE, +}; + +static const esp_efuse_desc_t WR_DIS_FORCE_USE_KEY_MANAGER_KEY[] = { + {EFUSE_BLK0, 1, 1}, // [] wr_dis of FORCE_USE_KEY_MANAGER_KEY, +}; + +static const esp_efuse_desc_t WR_DIS_FORCE_DISABLE_SW_INIT_KEY[] = { + {EFUSE_BLK0, 1, 1}, // [] wr_dis of FORCE_DISABLE_SW_INIT_KEY, +}; + +static const esp_efuse_desc_t WR_DIS_XTS_KEY_LENGTH_256[] = { + {EFUSE_BLK0, 1, 1}, // [] wr_dis of XTS_KEY_LENGTH_256, +}; + +static const esp_efuse_desc_t WR_DIS_LOCK_KM_KEY[] = { + {EFUSE_BLK0, 1, 1}, // [] wr_dis of LOCK_KM_KEY, +}; + +static const esp_efuse_desc_t WR_DIS_KM_DISABLE_DEPLOY_MODE[] = { + {EFUSE_BLK0, 1, 1}, // [] wr_dis of KM_DISABLE_DEPLOY_MODE, +}; + +static const esp_efuse_desc_t WR_DIS_DIS_USB_JTAG[] = { + {EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_USB_JTAG, +}; + +static const esp_efuse_desc_t WR_DIS_DIS_FORCE_DOWNLOAD[] = { + {EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_FORCE_DOWNLOAD, +}; + +static const esp_efuse_desc_t WR_DIS_SPI_DOWNLOAD_MSPI_DIS[] = { + {EFUSE_BLK0, 2, 1}, // [] wr_dis of SPI_DOWNLOAD_MSPI_DIS, +}; + +static const esp_efuse_desc_t WR_DIS_DIS_TWAI[] = { + {EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_TWAI, +}; + +static const esp_efuse_desc_t WR_DIS_JTAG_SEL_ENABLE[] = { + {EFUSE_BLK0, 2, 1}, // [] wr_dis of JTAG_SEL_ENABLE, +}; + +static const esp_efuse_desc_t WR_DIS_DIS_PAD_JTAG[] = { + {EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_PAD_JTAG, +}; + +static const esp_efuse_desc_t WR_DIS_DIS_DOWNLOAD_MANUAL_ENCRYPT[] = { + {EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_DOWNLOAD_MANUAL_ENCRYPT, +}; + +static const esp_efuse_desc_t WR_DIS_WDT_DELAY_SEL[] = { + {EFUSE_BLK0, 2, 1}, // [] wr_dis of WDT_DELAY_SEL, +}; + +static const esp_efuse_desc_t WR_DIS_HYS_EN_PAD[] = { + {EFUSE_BLK0, 2, 1}, // [] wr_dis of HYS_EN_PAD, +}; + +static const esp_efuse_desc_t WR_DIS_PXA0_TIEH_SEL_0[] = { + {EFUSE_BLK0, 2, 1}, // [] wr_dis of PXA0_TIEH_SEL_0, +}; + +static const esp_efuse_desc_t WR_DIS_PXA0_TIEH_SEL_1[] = { + {EFUSE_BLK0, 2, 1}, // [] wr_dis of PXA0_TIEH_SEL_1, +}; + +static const esp_efuse_desc_t WR_DIS_PXA0_TIEH_SEL_2[] = { + {EFUSE_BLK0, 2, 1}, // [] wr_dis of PXA0_TIEH_SEL_2, +}; + +static const esp_efuse_desc_t WR_DIS_PXA0_TIEH_SEL_3[] = { + {EFUSE_BLK0, 2, 1}, // [] wr_dis of PXA0_TIEH_SEL_3, +}; + +static const esp_efuse_desc_t WR_DIS_DIS_WDT[] = { + {EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_WDT, +}; + +static const esp_efuse_desc_t WR_DIS_DIS_SWD[] = { + {EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_SWD, +}; + +static const esp_efuse_desc_t WR_DIS_HP_PWR_SRC_SEL[] = { + {EFUSE_BLK0, 3, 1}, // [] wr_dis of HP_PWR_SRC_SEL, +}; + static const esp_efuse_desc_t WR_DIS_SPI_BOOT_CRYPT_CNT[] = { {EFUSE_BLK0, 4, 1}, // [] wr_dis of SPI_BOOT_CRYPT_CNT, }; @@ -63,10 +155,86 @@ static const esp_efuse_desc_t WR_DIS_KEY_PURPOSE_5[] = { {EFUSE_BLK0, 13, 1}, // [WR_DIS.KEY5_PURPOSE] wr_dis of KEY_PURPOSE_5, }; +static const esp_efuse_desc_t WR_DIS_SEC_DPA_LEVEL[] = { + {EFUSE_BLK0, 14, 1}, // [] wr_dis of SEC_DPA_LEVEL, +}; + +static const esp_efuse_desc_t WR_DIS_CRYPT_DPA_ENABLE[] = { + {EFUSE_BLK0, 14, 1}, // [] wr_dis of CRYPT_DPA_ENABLE, +}; + static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_EN[] = { {EFUSE_BLK0, 15, 1}, // [] wr_dis of SECURE_BOOT_EN, }; +static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[] = { + {EFUSE_BLK0, 16, 1}, // [] wr_dis of SECURE_BOOT_AGGRESSIVE_REVOKE, +}; + +static const esp_efuse_desc_t WR_DIS_ECDSA_ENABLE_SOFT_K[] = { + {EFUSE_BLK0, 17, 1}, // [] wr_dis of ECDSA_ENABLE_SOFT_K, +}; + +static const esp_efuse_desc_t WR_DIS_FLASH_TYPE[] = { + {EFUSE_BLK0, 18, 1}, // [] wr_dis of FLASH_TYPE, +}; + +static const esp_efuse_desc_t WR_DIS_FLASH_PAGE_SIZE[] = { + {EFUSE_BLK0, 18, 1}, // [] wr_dis of FLASH_PAGE_SIZE, +}; + +static const esp_efuse_desc_t WR_DIS_FLASH_ECC_EN[] = { + {EFUSE_BLK0, 18, 1}, // [] wr_dis of FLASH_ECC_EN, +}; + +static const esp_efuse_desc_t WR_DIS_DIS_USB_OTG_DOWNLOAD_MODE[] = { + {EFUSE_BLK0, 18, 1}, // [] wr_dis of DIS_USB_OTG_DOWNLOAD_MODE, +}; + +static const esp_efuse_desc_t WR_DIS_FLASH_TPUW[] = { + {EFUSE_BLK0, 18, 1}, // [] wr_dis of FLASH_TPUW, +}; + +static const esp_efuse_desc_t WR_DIS_DIS_DOWNLOAD_MODE[] = { + {EFUSE_BLK0, 18, 1}, // [] wr_dis of DIS_DOWNLOAD_MODE, +}; + +static const esp_efuse_desc_t WR_DIS_DIS_DIRECT_BOOT[] = { + {EFUSE_BLK0, 18, 1}, // [] wr_dis of DIS_DIRECT_BOOT, +}; + +static const esp_efuse_desc_t WR_DIS_DIS_USB_SERIAL_JTAG_ROM_PRINT[] = { + {EFUSE_BLK0, 18, 1}, // [] wr_dis of DIS_USB_SERIAL_JTAG_ROM_PRINT, +}; + +static const esp_efuse_desc_t WR_DIS_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[] = { + {EFUSE_BLK0, 18, 1}, // [] wr_dis of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE, +}; + +static const esp_efuse_desc_t WR_DIS_ENABLE_SECURITY_DOWNLOAD[] = { + {EFUSE_BLK0, 18, 1}, // [] wr_dis of ENABLE_SECURITY_DOWNLOAD, +}; + +static const esp_efuse_desc_t WR_DIS_UART_PRINT_CONTROL[] = { + {EFUSE_BLK0, 18, 1}, // [] wr_dis of UART_PRINT_CONTROL, +}; + +static const esp_efuse_desc_t WR_DIS_FORCE_SEND_RESUME[] = { + {EFUSE_BLK0, 18, 1}, // [] wr_dis of FORCE_SEND_RESUME, +}; + +static const esp_efuse_desc_t WR_DIS_SECURE_VERSION[] = { + {EFUSE_BLK0, 18, 1}, // [] wr_dis of SECURE_VERSION, +}; + +static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_DISABLE_FAST_WAKE[] = { + {EFUSE_BLK0, 18, 1}, // [] wr_dis of SECURE_BOOT_DISABLE_FAST_WAKE, +}; + +static const esp_efuse_desc_t WR_DIS_KM_HUK_GEN_STATE[] = { + {EFUSE_BLK0, 19, 1}, // [] wr_dis of KM_HUK_GEN_STATE, +}; + static const esp_efuse_desc_t WR_DIS_BLK1[] = { {EFUSE_BLK0, 20, 1}, // [] wr_dis of BLOCK1, }; @@ -99,24 +267,12 @@ static const esp_efuse_desc_t WR_DIS_BLK_VERSION_MAJOR[] = { {EFUSE_BLK0, 20, 1}, // [] wr_dis of BLK_VERSION_MAJOR, }; -static const esp_efuse_desc_t WR_DIS_FLASH_CAP[] = { - {EFUSE_BLK0, 20, 1}, // [] wr_dis of FLASH_CAP, -}; - -static const esp_efuse_desc_t WR_DIS_FLASH_TEMP[] = { - {EFUSE_BLK0, 20, 1}, // [] wr_dis of FLASH_TEMP, -}; - -static const esp_efuse_desc_t WR_DIS_FLASH_VENDOR[] = { - {EFUSE_BLK0, 20, 1}, // [] wr_dis of FLASH_VENDOR, -}; - static const esp_efuse_desc_t WR_DIS_PSRAM_CAP[] = { {EFUSE_BLK0, 20, 1}, // [] wr_dis of PSRAM_CAP, }; -static const esp_efuse_desc_t WR_DIS_PSRAM_TEMP[] = { - {EFUSE_BLK0, 20, 1}, // [] wr_dis of PSRAM_TEMP, +static const esp_efuse_desc_t WR_DIS_TEMP[] = { + {EFUSE_BLK0, 20, 1}, // [] wr_dis of TEMP, }; static const esp_efuse_desc_t WR_DIS_PSRAM_VENDOR[] = { @@ -171,6 +327,22 @@ static const esp_efuse_desc_t WR_DIS_BLOCK_SYS_DATA2[] = { {EFUSE_BLK0, 29, 1}, // [WR_DIS.SYS_DATA_PART2] wr_dis of BLOCK_SYS_DATA2, }; +static const esp_efuse_desc_t WR_DIS_USB_DEVICE_EXCHG_PINS[] = { + {EFUSE_BLK0, 30, 1}, // [] wr_dis of USB_DEVICE_EXCHG_PINS, +}; + +static const esp_efuse_desc_t WR_DIS_USB_OTG11_EXCHG_PINS[] = { + {EFUSE_BLK0, 30, 1}, // [] wr_dis of USB_OTG11_EXCHG_PINS, +}; + +static const esp_efuse_desc_t WR_DIS_USB_PHY_SEL[] = { + {EFUSE_BLK0, 30, 1}, // [] wr_dis of USB_PHY_SEL, +}; + +static const esp_efuse_desc_t WR_DIS_SOFT_DIS_JTAG[] = { + {EFUSE_BLK0, 31, 1}, // [] wr_dis of SOFT_DIS_JTAG, +}; + static const esp_efuse_desc_t RD_DIS[] = { {EFUSE_BLK0, 32, 7}, // [] Disable reading from BlOCK4-10, }; @@ -476,32 +648,20 @@ static const esp_efuse_desc_t BLK_VERSION_MAJOR[] = { {EFUSE_BLK1, 75, 2}, // [] BLK_VERSION_MAJOR of BLOCK2, }; -static const esp_efuse_desc_t FLASH_CAP[] = { - {EFUSE_BLK1, 77, 3}, // [] Flash capacity, -}; - -static const esp_efuse_desc_t FLASH_TEMP[] = { - {EFUSE_BLK1, 80, 2}, // [] Flash temperature, -}; - -static const esp_efuse_desc_t FLASH_VENDOR[] = { - {EFUSE_BLK1, 82, 3}, // [] Flash vendor, -}; - static const esp_efuse_desc_t PSRAM_CAP[] = { - {EFUSE_BLK1, 85, 2}, // [] PSRAM capacity, + {EFUSE_BLK1, 77, 3}, // [] PSRAM capacity, }; -static const esp_efuse_desc_t PSRAM_TEMP[] = { - {EFUSE_BLK1, 87, 2}, // [] PSRAM temperature, +static const esp_efuse_desc_t TEMP[] = { + {EFUSE_BLK1, 80, 2}, // [] Operating temperature of the ESP chip, }; static const esp_efuse_desc_t PSRAM_VENDOR[] = { - {EFUSE_BLK1, 89, 2}, // [] PSRAM vendor, + {EFUSE_BLK1, 82, 2}, // [] PSRAM vendor, }; static const esp_efuse_desc_t PKG_VERSION[] = { - {EFUSE_BLK1, 91, 3}, // [] Package version, + {EFUSE_BLK1, 84, 3}, // [] Package version, }; static const esp_efuse_desc_t OPTIONAL_UNIQUE_ID[] = { @@ -558,6 +718,121 @@ const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RD_DIS[] = { NULL }; +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KM_RND_SWITCH_CYCLE[] = { + &WR_DIS_KM_RND_SWITCH_CYCLE[0], // [] wr_dis of KM_RND_SWITCH_CYCLE + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KM_DEPLOY_ONLY_ONCE[] = { + &WR_DIS_KM_DEPLOY_ONLY_ONCE[0], // [] wr_dis of KM_DEPLOY_ONLY_ONCE + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FORCE_USE_KEY_MANAGER_KEY[] = { + &WR_DIS_FORCE_USE_KEY_MANAGER_KEY[0], // [] wr_dis of FORCE_USE_KEY_MANAGER_KEY + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FORCE_DISABLE_SW_INIT_KEY[] = { + &WR_DIS_FORCE_DISABLE_SW_INIT_KEY[0], // [] wr_dis of FORCE_DISABLE_SW_INIT_KEY + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_XTS_KEY_LENGTH_256[] = { + &WR_DIS_XTS_KEY_LENGTH_256[0], // [] wr_dis of XTS_KEY_LENGTH_256 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LOCK_KM_KEY[] = { + &WR_DIS_LOCK_KM_KEY[0], // [] wr_dis of LOCK_KM_KEY + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KM_DISABLE_DEPLOY_MODE[] = { + &WR_DIS_KM_DISABLE_DEPLOY_MODE[0], // [] wr_dis of KM_DISABLE_DEPLOY_MODE + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_JTAG[] = { + &WR_DIS_DIS_USB_JTAG[0], // [] wr_dis of DIS_USB_JTAG + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_FORCE_DOWNLOAD[] = { + &WR_DIS_DIS_FORCE_DOWNLOAD[0], // [] wr_dis of DIS_FORCE_DOWNLOAD + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_DOWNLOAD_MSPI_DIS[] = { + &WR_DIS_SPI_DOWNLOAD_MSPI_DIS[0], // [] wr_dis of SPI_DOWNLOAD_MSPI_DIS + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_TWAI[] = { + &WR_DIS_DIS_TWAI[0], // [] wr_dis of DIS_TWAI + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_JTAG_SEL_ENABLE[] = { + &WR_DIS_JTAG_SEL_ENABLE[0], // [] wr_dis of JTAG_SEL_ENABLE + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_PAD_JTAG[] = { + &WR_DIS_DIS_PAD_JTAG[0], // [] wr_dis of DIS_PAD_JTAG + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MANUAL_ENCRYPT[] = { + &WR_DIS_DIS_DOWNLOAD_MANUAL_ENCRYPT[0], // [] wr_dis of DIS_DOWNLOAD_MANUAL_ENCRYPT + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WDT_DELAY_SEL[] = { + &WR_DIS_WDT_DELAY_SEL[0], // [] wr_dis of WDT_DELAY_SEL + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_HYS_EN_PAD[] = { + &WR_DIS_HYS_EN_PAD[0], // [] wr_dis of HYS_EN_PAD + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PXA0_TIEH_SEL_0[] = { + &WR_DIS_PXA0_TIEH_SEL_0[0], // [] wr_dis of PXA0_TIEH_SEL_0 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PXA0_TIEH_SEL_1[] = { + &WR_DIS_PXA0_TIEH_SEL_1[0], // [] wr_dis of PXA0_TIEH_SEL_1 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PXA0_TIEH_SEL_2[] = { + &WR_DIS_PXA0_TIEH_SEL_2[0], // [] wr_dis of PXA0_TIEH_SEL_2 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PXA0_TIEH_SEL_3[] = { + &WR_DIS_PXA0_TIEH_SEL_3[0], // [] wr_dis of PXA0_TIEH_SEL_3 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_WDT[] = { + &WR_DIS_DIS_WDT[0], // [] wr_dis of DIS_WDT + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_SWD[] = { + &WR_DIS_DIS_SWD[0], // [] wr_dis of DIS_SWD + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_HP_PWR_SRC_SEL[] = { + &WR_DIS_HP_PWR_SRC_SEL[0], // [] wr_dis of HP_PWR_SRC_SEL + NULL +}; + const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT[] = { &WR_DIS_SPI_BOOT_CRYPT_CNT[0], // [] wr_dis of SPI_BOOT_CRYPT_CNT NULL @@ -608,11 +883,106 @@ const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_5[] = { NULL }; +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SEC_DPA_LEVEL[] = { + &WR_DIS_SEC_DPA_LEVEL[0], // [] wr_dis of SEC_DPA_LEVEL + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CRYPT_DPA_ENABLE[] = { + &WR_DIS_CRYPT_DPA_ENABLE[0], // [] wr_dis of CRYPT_DPA_ENABLE + NULL +}; + const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_EN[] = { &WR_DIS_SECURE_BOOT_EN[0], // [] wr_dis of SECURE_BOOT_EN NULL }; +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[] = { + &WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[0], // [] wr_dis of SECURE_BOOT_AGGRESSIVE_REVOKE + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ECDSA_ENABLE_SOFT_K[] = { + &WR_DIS_ECDSA_ENABLE_SOFT_K[0], // [] wr_dis of ECDSA_ENABLE_SOFT_K + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TYPE[] = { + &WR_DIS_FLASH_TYPE[0], // [] wr_dis of FLASH_TYPE + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_PAGE_SIZE[] = { + &WR_DIS_FLASH_PAGE_SIZE[0], // [] wr_dis of FLASH_PAGE_SIZE + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_ECC_EN[] = { + &WR_DIS_FLASH_ECC_EN[0], // [] wr_dis of FLASH_ECC_EN + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_OTG_DOWNLOAD_MODE[] = { + &WR_DIS_DIS_USB_OTG_DOWNLOAD_MODE[0], // [] wr_dis of DIS_USB_OTG_DOWNLOAD_MODE + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TPUW[] = { + &WR_DIS_FLASH_TPUW[0], // [] wr_dis of FLASH_TPUW + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MODE[] = { + &WR_DIS_DIS_DOWNLOAD_MODE[0], // [] wr_dis of DIS_DOWNLOAD_MODE + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DIRECT_BOOT[] = { + &WR_DIS_DIS_DIRECT_BOOT[0], // [] wr_dis of DIS_DIRECT_BOOT + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_ROM_PRINT[] = { + &WR_DIS_DIS_USB_SERIAL_JTAG_ROM_PRINT[0], // [] wr_dis of DIS_USB_SERIAL_JTAG_ROM_PRINT + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[] = { + &WR_DIS_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[0], // [] wr_dis of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ENABLE_SECURITY_DOWNLOAD[] = { + &WR_DIS_ENABLE_SECURITY_DOWNLOAD[0], // [] wr_dis of ENABLE_SECURITY_DOWNLOAD + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_UART_PRINT_CONTROL[] = { + &WR_DIS_UART_PRINT_CONTROL[0], // [] wr_dis of UART_PRINT_CONTROL + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FORCE_SEND_RESUME[] = { + &WR_DIS_FORCE_SEND_RESUME[0], // [] wr_dis of FORCE_SEND_RESUME + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_VERSION[] = { + &WR_DIS_SECURE_VERSION[0], // [] wr_dis of SECURE_VERSION + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_DISABLE_FAST_WAKE[] = { + &WR_DIS_SECURE_BOOT_DISABLE_FAST_WAKE[0], // [] wr_dis of SECURE_BOOT_DISABLE_FAST_WAKE + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KM_HUK_GEN_STATE[] = { + &WR_DIS_KM_HUK_GEN_STATE[0], // [] wr_dis of KM_HUK_GEN_STATE + NULL +}; + const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK1[] = { &WR_DIS_BLK1[0], // [] wr_dis of BLOCK1 NULL @@ -653,28 +1023,13 @@ const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MAJOR[] = { NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_CAP[] = { - &WR_DIS_FLASH_CAP[0], // [] wr_dis of FLASH_CAP - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TEMP[] = { - &WR_DIS_FLASH_TEMP[0], // [] wr_dis of FLASH_TEMP - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_VENDOR[] = { - &WR_DIS_FLASH_VENDOR[0], // [] wr_dis of FLASH_VENDOR - NULL -}; - const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PSRAM_CAP[] = { &WR_DIS_PSRAM_CAP[0], // [] wr_dis of PSRAM_CAP NULL }; -const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PSRAM_TEMP[] = { - &WR_DIS_PSRAM_TEMP[0], // [] wr_dis of PSRAM_TEMP +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMP[] = { + &WR_DIS_TEMP[0], // [] wr_dis of TEMP NULL }; @@ -743,6 +1098,26 @@ const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA2[] = { NULL }; +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_DEVICE_EXCHG_PINS[] = { + &WR_DIS_USB_DEVICE_EXCHG_PINS[0], // [] wr_dis of USB_DEVICE_EXCHG_PINS + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_OTG11_EXCHG_PINS[] = { + &WR_DIS_USB_OTG11_EXCHG_PINS[0], // [] wr_dis of USB_OTG11_EXCHG_PINS + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_PHY_SEL[] = { + &WR_DIS_USB_PHY_SEL[0], // [] wr_dis of USB_PHY_SEL + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SOFT_DIS_JTAG[] = { + &WR_DIS_SOFT_DIS_JTAG[0], // [] wr_dis of SOFT_DIS_JTAG + NULL +}; + const esp_efuse_desc_t* ESP_EFUSE_RD_DIS[] = { &RD_DIS[0], // [] Disable reading from BlOCK4-10 NULL @@ -1123,28 +1498,13 @@ const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MAJOR[] = { NULL }; -const esp_efuse_desc_t* ESP_EFUSE_FLASH_CAP[] = { - &FLASH_CAP[0], // [] Flash capacity - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_FLASH_TEMP[] = { - &FLASH_TEMP[0], // [] Flash temperature - NULL -}; - -const esp_efuse_desc_t* ESP_EFUSE_FLASH_VENDOR[] = { - &FLASH_VENDOR[0], // [] Flash vendor - NULL -}; - const esp_efuse_desc_t* ESP_EFUSE_PSRAM_CAP[] = { &PSRAM_CAP[0], // [] PSRAM capacity NULL }; -const esp_efuse_desc_t* ESP_EFUSE_PSRAM_TEMP[] = { - &PSRAM_TEMP[0], // [] PSRAM temperature +const esp_efuse_desc_t* ESP_EFUSE_TEMP[] = { + &TEMP[0], // [] Operating temperature of the ESP chip NULL }; diff --git a/components/efuse/esp32p4/esp_efuse_table.csv b/components/efuse/esp32p4/esp_efuse_table.csv index 18cf111402..7cd373599c 100644 --- a/components/efuse/esp32p4/esp_efuse_table.csv +++ b/components/efuse/esp32p4/esp_efuse_table.csv @@ -9,10 +9,33 @@ # this will generate new source files, next rebuild all the sources. # !!!!!!!!!!! # -# This file was generated by regtools.py based on the efuses.yaml file with the version: 6b72374c237a3473c8832aadee437405 +# This file was generated by regtools.py based on the efuses.yaml file with the version: d4a48929387e281bd05db8cfb3a85f60 WR_DIS, EFUSE_BLK0, 0, 32, [] Disable programming of individual eFuses WR_DIS.RD_DIS, EFUSE_BLK0, 0, 1, [] wr_dis of RD_DIS +WR_DIS.KM_RND_SWITCH_CYCLE, EFUSE_BLK0, 1, 1, [] wr_dis of KM_RND_SWITCH_CYCLE +WR_DIS.KM_DEPLOY_ONLY_ONCE, EFUSE_BLK0, 1, 1, [] wr_dis of KM_DEPLOY_ONLY_ONCE +WR_DIS.FORCE_USE_KEY_MANAGER_KEY, EFUSE_BLK0, 1, 1, [] wr_dis of FORCE_USE_KEY_MANAGER_KEY +WR_DIS.FORCE_DISABLE_SW_INIT_KEY, EFUSE_BLK0, 1, 1, [] wr_dis of FORCE_DISABLE_SW_INIT_KEY +WR_DIS.XTS_KEY_LENGTH_256, EFUSE_BLK0, 1, 1, [] wr_dis of XTS_KEY_LENGTH_256 +WR_DIS.LOCK_KM_KEY, EFUSE_BLK0, 1, 1, [] wr_dis of LOCK_KM_KEY +WR_DIS.KM_DISABLE_DEPLOY_MODE, EFUSE_BLK0, 1, 1, [] wr_dis of KM_DISABLE_DEPLOY_MODE +WR_DIS.DIS_USB_JTAG, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_USB_JTAG +WR_DIS.DIS_FORCE_DOWNLOAD, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_FORCE_DOWNLOAD +WR_DIS.SPI_DOWNLOAD_MSPI_DIS, EFUSE_BLK0, 2, 1, [] wr_dis of SPI_DOWNLOAD_MSPI_DIS +WR_DIS.DIS_TWAI, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_TWAI +WR_DIS.JTAG_SEL_ENABLE, EFUSE_BLK0, 2, 1, [] wr_dis of JTAG_SEL_ENABLE +WR_DIS.DIS_PAD_JTAG, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_PAD_JTAG +WR_DIS.DIS_DOWNLOAD_MANUAL_ENCRYPT, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_DOWNLOAD_MANUAL_ENCRYPT +WR_DIS.WDT_DELAY_SEL, EFUSE_BLK0, 2, 1, [] wr_dis of WDT_DELAY_SEL +WR_DIS.HYS_EN_PAD, EFUSE_BLK0, 2, 1, [] wr_dis of HYS_EN_PAD +WR_DIS.PXA0_TIEH_SEL_0, EFUSE_BLK0, 2, 1, [] wr_dis of PXA0_TIEH_SEL_0 +WR_DIS.PXA0_TIEH_SEL_1, EFUSE_BLK0, 2, 1, [] wr_dis of PXA0_TIEH_SEL_1 +WR_DIS.PXA0_TIEH_SEL_2, EFUSE_BLK0, 2, 1, [] wr_dis of PXA0_TIEH_SEL_2 +WR_DIS.PXA0_TIEH_SEL_3, EFUSE_BLK0, 2, 1, [] wr_dis of PXA0_TIEH_SEL_3 +WR_DIS.DIS_WDT, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_WDT +WR_DIS.DIS_SWD, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_SWD +WR_DIS.HP_PWR_SRC_SEL, EFUSE_BLK0, 3, 1, [] wr_dis of HP_PWR_SRC_SEL WR_DIS.SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 4, 1, [] wr_dis of SPI_BOOT_CRYPT_CNT WR_DIS.SECURE_BOOT_KEY_REVOKE0, EFUSE_BLK0, 5, 1, [] wr_dis of SECURE_BOOT_KEY_REVOKE0 WR_DIS.SECURE_BOOT_KEY_REVOKE1, EFUSE_BLK0, 6, 1, [] wr_dis of SECURE_BOOT_KEY_REVOKE1 @@ -23,7 +46,26 @@ WR_DIS.KEY_PURPOSE_2, EFUSE_BLK0, 10, 1, [WR_DIS.K WR_DIS.KEY_PURPOSE_3, EFUSE_BLK0, 11, 1, [WR_DIS.KEY3_PURPOSE] wr_dis of KEY_PURPOSE_3 WR_DIS.KEY_PURPOSE_4, EFUSE_BLK0, 12, 1, [WR_DIS.KEY4_PURPOSE] wr_dis of KEY_PURPOSE_4 WR_DIS.KEY_PURPOSE_5, EFUSE_BLK0, 13, 1, [WR_DIS.KEY5_PURPOSE] wr_dis of KEY_PURPOSE_5 +WR_DIS.SEC_DPA_LEVEL, EFUSE_BLK0, 14, 1, [] wr_dis of SEC_DPA_LEVEL +WR_DIS.CRYPT_DPA_ENABLE, EFUSE_BLK0, 14, 1, [] wr_dis of CRYPT_DPA_ENABLE WR_DIS.SECURE_BOOT_EN, EFUSE_BLK0, 15, 1, [] wr_dis of SECURE_BOOT_EN +WR_DIS.SECURE_BOOT_AGGRESSIVE_REVOKE, EFUSE_BLK0, 16, 1, [] wr_dis of SECURE_BOOT_AGGRESSIVE_REVOKE +WR_DIS.ECDSA_ENABLE_SOFT_K, EFUSE_BLK0, 17, 1, [] wr_dis of ECDSA_ENABLE_SOFT_K +WR_DIS.FLASH_TYPE, EFUSE_BLK0, 18, 1, [] wr_dis of FLASH_TYPE +WR_DIS.FLASH_PAGE_SIZE, EFUSE_BLK0, 18, 1, [] wr_dis of FLASH_PAGE_SIZE +WR_DIS.FLASH_ECC_EN, EFUSE_BLK0, 18, 1, [] wr_dis of FLASH_ECC_EN +WR_DIS.DIS_USB_OTG_DOWNLOAD_MODE, EFUSE_BLK0, 18, 1, [] wr_dis of DIS_USB_OTG_DOWNLOAD_MODE +WR_DIS.FLASH_TPUW, EFUSE_BLK0, 18, 1, [] wr_dis of FLASH_TPUW +WR_DIS.DIS_DOWNLOAD_MODE, EFUSE_BLK0, 18, 1, [] wr_dis of DIS_DOWNLOAD_MODE +WR_DIS.DIS_DIRECT_BOOT, EFUSE_BLK0, 18, 1, [] wr_dis of DIS_DIRECT_BOOT +WR_DIS.DIS_USB_SERIAL_JTAG_ROM_PRINT, EFUSE_BLK0, 18, 1, [] wr_dis of DIS_USB_SERIAL_JTAG_ROM_PRINT +WR_DIS.DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE, EFUSE_BLK0, 18, 1, [] wr_dis of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE +WR_DIS.ENABLE_SECURITY_DOWNLOAD, EFUSE_BLK0, 18, 1, [] wr_dis of ENABLE_SECURITY_DOWNLOAD +WR_DIS.UART_PRINT_CONTROL, EFUSE_BLK0, 18, 1, [] wr_dis of UART_PRINT_CONTROL +WR_DIS.FORCE_SEND_RESUME, EFUSE_BLK0, 18, 1, [] wr_dis of FORCE_SEND_RESUME +WR_DIS.SECURE_VERSION, EFUSE_BLK0, 18, 1, [] wr_dis of SECURE_VERSION +WR_DIS.SECURE_BOOT_DISABLE_FAST_WAKE, EFUSE_BLK0, 18, 1, [] wr_dis of SECURE_BOOT_DISABLE_FAST_WAKE +WR_DIS.KM_HUK_GEN_STATE, EFUSE_BLK0, 19, 1, [] wr_dis of KM_HUK_GEN_STATE WR_DIS.BLK1, EFUSE_BLK0, 20, 1, [] wr_dis of BLOCK1 WR_DIS.MAC, EFUSE_BLK0, 20, 1, [WR_DIS.MAC_FACTORY] wr_dis of MAC WR_DIS.WAFER_VERSION_MINOR, EFUSE_BLK0, 20, 1, [] wr_dis of WAFER_VERSION_MINOR @@ -32,11 +74,8 @@ WR_DIS.DISABLE_WAFER_VERSION_MAJOR, EFUSE_BLK0, 20, 1, [] wr_dis WR_DIS.DISABLE_BLK_VERSION_MAJOR, EFUSE_BLK0, 20, 1, [] wr_dis of DISABLE_BLK_VERSION_MAJOR WR_DIS.BLK_VERSION_MINOR, EFUSE_BLK0, 20, 1, [] wr_dis of BLK_VERSION_MINOR WR_DIS.BLK_VERSION_MAJOR, EFUSE_BLK0, 20, 1, [] wr_dis of BLK_VERSION_MAJOR -WR_DIS.FLASH_CAP, EFUSE_BLK0, 20, 1, [] wr_dis of FLASH_CAP -WR_DIS.FLASH_TEMP, EFUSE_BLK0, 20, 1, [] wr_dis of FLASH_TEMP -WR_DIS.FLASH_VENDOR, EFUSE_BLK0, 20, 1, [] wr_dis of FLASH_VENDOR WR_DIS.PSRAM_CAP, EFUSE_BLK0, 20, 1, [] wr_dis of PSRAM_CAP -WR_DIS.PSRAM_TEMP, EFUSE_BLK0, 20, 1, [] wr_dis of PSRAM_TEMP +WR_DIS.TEMP, EFUSE_BLK0, 20, 1, [] wr_dis of TEMP WR_DIS.PSRAM_VENDOR, EFUSE_BLK0, 20, 1, [] wr_dis of PSRAM_VENDOR WR_DIS.PKG_VERSION, EFUSE_BLK0, 20, 1, [] wr_dis of PKG_VERSION WR_DIS.SYS_DATA_PART1, EFUSE_BLK0, 21, 1, [] wr_dis of BLOCK2 @@ -50,6 +89,10 @@ WR_DIS.BLOCK_KEY3, EFUSE_BLK0, 26, 1, [WR_DIS.K WR_DIS.BLOCK_KEY4, EFUSE_BLK0, 27, 1, [WR_DIS.KEY4] wr_dis of BLOCK_KEY4 WR_DIS.BLOCK_KEY5, EFUSE_BLK0, 28, 1, [WR_DIS.KEY5] wr_dis of BLOCK_KEY5 WR_DIS.BLOCK_SYS_DATA2, EFUSE_BLK0, 29, 1, [WR_DIS.SYS_DATA_PART2] wr_dis of BLOCK_SYS_DATA2 +WR_DIS.USB_DEVICE_EXCHG_PINS, EFUSE_BLK0, 30, 1, [] wr_dis of USB_DEVICE_EXCHG_PINS +WR_DIS.USB_OTG11_EXCHG_PINS, EFUSE_BLK0, 30, 1, [] wr_dis of USB_OTG11_EXCHG_PINS +WR_DIS.USB_PHY_SEL, EFUSE_BLK0, 30, 1, [] wr_dis of USB_PHY_SEL +WR_DIS.SOFT_DIS_JTAG, EFUSE_BLK0, 31, 1, [] wr_dis of SOFT_DIS_JTAG RD_DIS, EFUSE_BLK0, 32, 7, [] Disable reading from BlOCK4-10 RD_DIS.BLOCK_KEY0, EFUSE_BLK0, 32, 1, [RD_DIS.KEY0] rd_dis of BLOCK_KEY0 RD_DIS.BLOCK_KEY1, EFUSE_BLK0, 33, 1, [RD_DIS.KEY1] rd_dis of BLOCK_KEY1 @@ -130,13 +173,10 @@ DISABLE_WAFER_VERSION_MAJOR, EFUSE_BLK1, 70, 1, [] Disabl DISABLE_BLK_VERSION_MAJOR, EFUSE_BLK1, 71, 1, [] Disables check of blk version major BLK_VERSION_MINOR, EFUSE_BLK1, 72, 3, [] BLK_VERSION_MINOR of BLOCK2 BLK_VERSION_MAJOR, EFUSE_BLK1, 75, 2, [] BLK_VERSION_MAJOR of BLOCK2 -FLASH_CAP, EFUSE_BLK1, 77, 3, [] Flash capacity -FLASH_TEMP, EFUSE_BLK1, 80, 2, [] Flash temperature -FLASH_VENDOR, EFUSE_BLK1, 82, 3, [] Flash vendor -PSRAM_CAP, EFUSE_BLK1, 85, 2, [] PSRAM capacity -PSRAM_TEMP, EFUSE_BLK1, 87, 2, [] PSRAM temperature -PSRAM_VENDOR, EFUSE_BLK1, 89, 2, [] PSRAM vendor -PKG_VERSION, EFUSE_BLK1, 91, 3, [] Package version +PSRAM_CAP, EFUSE_BLK1, 77, 3, [] PSRAM capacity +TEMP, EFUSE_BLK1, 80, 2, [] Operating temperature of the ESP chip +PSRAM_VENDOR, EFUSE_BLK1, 82, 2, [] PSRAM vendor +PKG_VERSION, EFUSE_BLK1, 84, 3, [] Package version OPTIONAL_UNIQUE_ID, EFUSE_BLK2, 0, 128, [] Optional unique 128-bit ID USER_DATA, EFUSE_BLK3, 0, 256, [BLOCK_USR_DATA] User data USER_DATA.MAC_CUSTOM, EFUSE_BLK3, 200, 48, [MAC_CUSTOM CUSTOM_MAC] Custom MAC diff --git a/components/efuse/esp32p4/include/esp_efuse_table.h b/components/efuse/esp32p4/include/esp_efuse_table.h index 9cbeb26359..9e82ad8630 100644 --- a/components/efuse/esp32p4/include/esp_efuse_table.h +++ b/components/efuse/esp32p4/include/esp_efuse_table.h @@ -10,7 +10,7 @@ extern "C" { #include "esp_efuse.h" -// md5_digest_table 2eb36a43d52e9922e08cf545d0e23381 +// md5_digest_table 0d4e1f49db99de4dd9d3eac8d8e6078b // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY. // If you want to change some fields, you need to change esp_efuse_table.csv file // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file. @@ -19,6 +19,29 @@ extern "C" { extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RD_DIS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KM_RND_SWITCH_CYCLE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KM_DEPLOY_ONLY_ONCE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FORCE_USE_KEY_MANAGER_KEY[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FORCE_DISABLE_SW_INIT_KEY[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_XTS_KEY_LENGTH_256[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LOCK_KM_KEY[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KM_DISABLE_DEPLOY_MODE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_JTAG[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_FORCE_DOWNLOAD[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_DOWNLOAD_MSPI_DIS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_TWAI[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_JTAG_SEL_ENABLE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_PAD_JTAG[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MANUAL_ENCRYPT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WDT_DELAY_SEL[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_HYS_EN_PAD[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PXA0_TIEH_SEL_0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PXA0_TIEH_SEL_1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PXA0_TIEH_SEL_2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PXA0_TIEH_SEL_3[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_WDT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_SWD[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_HP_PWR_SRC_SEL[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE0[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE1[]; @@ -35,7 +58,26 @@ extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_4[]; #define ESP_EFUSE_WR_DIS_KEY4_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_4 extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_5[]; #define ESP_EFUSE_WR_DIS_KEY5_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_5 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SEC_DPA_LEVEL[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CRYPT_DPA_ENABLE[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_EN[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ECDSA_ENABLE_SOFT_K[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TYPE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_PAGE_SIZE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_ECC_EN[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_OTG_DOWNLOAD_MODE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TPUW[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MODE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DIRECT_BOOT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_ROM_PRINT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ENABLE_SECURITY_DOWNLOAD[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_UART_PRINT_CONTROL[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FORCE_SEND_RESUME[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_VERSION[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_DISABLE_FAST_WAKE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KM_HUK_GEN_STATE[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK1[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_MAC[]; #define ESP_EFUSE_WR_DIS_MAC_FACTORY ESP_EFUSE_WR_DIS_MAC @@ -45,11 +87,8 @@ extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_WAFER_VERSION_MAJOR[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_BLK_VERSION_MAJOR[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MINOR[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MAJOR[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_CAP[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TEMP[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_VENDOR[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PSRAM_CAP[]; -extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PSRAM_TEMP[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMP[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PSRAM_VENDOR[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PKG_VERSION[]; extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[]; @@ -73,6 +112,10 @@ extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY5[]; #define ESP_EFUSE_WR_DIS_KEY5 ESP_EFUSE_WR_DIS_BLOCK_KEY5 extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA2[]; #define ESP_EFUSE_WR_DIS_SYS_DATA_PART2 ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA2 +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_DEVICE_EXCHG_PINS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_OTG11_EXCHG_PINS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_PHY_SEL[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SOFT_DIS_JTAG[]; extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS[]; extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY0[]; #define ESP_EFUSE_RD_DIS_KEY0 ESP_EFUSE_RD_DIS_BLOCK_KEY0 @@ -162,11 +205,8 @@ extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_WAFER_VERSION_MAJOR[]; extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_BLK_VERSION_MAJOR[]; extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MINOR[]; extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MAJOR[]; -extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_CAP[]; -extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_TEMP[]; -extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_VENDOR[]; extern const esp_efuse_desc_t* ESP_EFUSE_PSRAM_CAP[]; -extern const esp_efuse_desc_t* ESP_EFUSE_PSRAM_TEMP[]; +extern const esp_efuse_desc_t* ESP_EFUSE_TEMP[]; extern const esp_efuse_desc_t* ESP_EFUSE_PSRAM_VENDOR[]; extern const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[]; extern const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[]; diff --git a/components/soc/esp32p4/include/soc/efuse_reg.h b/components/soc/esp32p4/include/soc/efuse_reg.h index 17c2aa5a1a..310bdaa73f 100644 --- a/components/soc/esp32p4/include/soc/efuse_reg.h +++ b/components/soc/esp32p4/include/soc/efuse_reg.h @@ -654,7 +654,7 @@ extern "C" { #define EFUSE_KM_DISABLE_DEPLOY_MODE_V 0x0000000FU #define EFUSE_KM_DISABLE_DEPLOY_MODE_S 8 /** EFUSE_USB_DEVICE_DREFL : RO; bitpos: [13:12]; default: 0; - * Represents the usb device single-end input low threhold, 0.8 V to 1.04 V with step + * Represents the usb device single-end input low threshold, 0.8 V to 1.04 V with step * of 80 mV. */ #define EFUSE_USB_DEVICE_DREFL 0x00000003U @@ -662,7 +662,7 @@ extern "C" { #define EFUSE_USB_DEVICE_DREFL_V 0x00000003U #define EFUSE_USB_DEVICE_DREFL_S 12 /** EFUSE_USB_OTG11_DREFL : RO; bitpos: [15:14]; default: 0; - * Represents the usb otg11 single-end input low threhold, 0.8 V to 1.04 V with step + * Represents the usb otg11 single-end input low threshold, 0.8 V to 1.04 V with step * of 80 mV. */ #define EFUSE_USB_OTG11_DREFL 0x00000003U @@ -789,62 +789,41 @@ extern "C" { #define EFUSE_BLK_VERSION_MAJOR_M (EFUSE_BLK_VERSION_MAJOR_V << EFUSE_BLK_VERSION_MAJOR_S) #define EFUSE_BLK_VERSION_MAJOR_V 0x00000003U #define EFUSE_BLK_VERSION_MAJOR_S 11 -/** EFUSE_FLASH_CAP : R; bitpos: [15:13]; default: 0; - * Flash capacity - */ -#define EFUSE_FLASH_CAP 0x00000007U -#define EFUSE_FLASH_CAP_M (EFUSE_FLASH_CAP_V << EFUSE_FLASH_CAP_S) -#define EFUSE_FLASH_CAP_V 0x00000007U -#define EFUSE_FLASH_CAP_S 13 -/** EFUSE_FLASH_TEMP : R; bitpos: [17:16]; default: 0; - * Flash temperature - */ -#define EFUSE_FLASH_TEMP 0x00000003U -#define EFUSE_FLASH_TEMP_M (EFUSE_FLASH_TEMP_V << EFUSE_FLASH_TEMP_S) -#define EFUSE_FLASH_TEMP_V 0x00000003U -#define EFUSE_FLASH_TEMP_S 16 -/** EFUSE_FLASH_VENDOR : R; bitpos: [20:18]; default: 0; - * Flash vendor - */ -#define EFUSE_FLASH_VENDOR 0x00000007U -#define EFUSE_FLASH_VENDOR_M (EFUSE_FLASH_VENDOR_V << EFUSE_FLASH_VENDOR_S) -#define EFUSE_FLASH_VENDOR_V 0x00000007U -#define EFUSE_FLASH_VENDOR_S 18 -/** EFUSE_PSRAM_CAP : R; bitpos: [22:21]; default: 0; +/** EFUSE_PSRAM_CAP : R; bitpos: [15:13]; default: 0; * PSRAM capacity */ -#define EFUSE_PSRAM_CAP 0x00000003U +#define EFUSE_PSRAM_CAP 0x00000007U #define EFUSE_PSRAM_CAP_M (EFUSE_PSRAM_CAP_V << EFUSE_PSRAM_CAP_S) -#define EFUSE_PSRAM_CAP_V 0x00000003U -#define EFUSE_PSRAM_CAP_S 21 -/** EFUSE_PSRAM_TEMP : R; bitpos: [24:23]; default: 0; - * PSRAM temperature +#define EFUSE_PSRAM_CAP_V 0x00000007U +#define EFUSE_PSRAM_CAP_S 13 +/** EFUSE_TEMP : R; bitpos: [17:16]; default: 0; + * Operating temperature of the ESP chip */ -#define EFUSE_PSRAM_TEMP 0x00000003U -#define EFUSE_PSRAM_TEMP_M (EFUSE_PSRAM_TEMP_V << EFUSE_PSRAM_TEMP_S) -#define EFUSE_PSRAM_TEMP_V 0x00000003U -#define EFUSE_PSRAM_TEMP_S 23 -/** EFUSE_PSRAM_VENDOR : R; bitpos: [26:25]; default: 0; +#define EFUSE_TEMP 0x00000003U +#define EFUSE_TEMP_M (EFUSE_TEMP_V << EFUSE_TEMP_S) +#define EFUSE_TEMP_V 0x00000003U +#define EFUSE_TEMP_S 16 +/** EFUSE_PSRAM_VENDOR : R; bitpos: [19:18]; default: 0; * PSRAM vendor */ #define EFUSE_PSRAM_VENDOR 0x00000003U #define EFUSE_PSRAM_VENDOR_M (EFUSE_PSRAM_VENDOR_V << EFUSE_PSRAM_VENDOR_S) #define EFUSE_PSRAM_VENDOR_V 0x00000003U -#define EFUSE_PSRAM_VENDOR_S 25 -/** EFUSE_PKG_VERSION : R; bitpos: [29:27]; default: 0; +#define EFUSE_PSRAM_VENDOR_S 18 +/** EFUSE_PKG_VERSION : R; bitpos: [22:20]; default: 0; * Package version */ #define EFUSE_PKG_VERSION 0x00000007U #define EFUSE_PKG_VERSION_M (EFUSE_PKG_VERSION_V << EFUSE_PKG_VERSION_S) #define EFUSE_PKG_VERSION_V 0x00000007U -#define EFUSE_PKG_VERSION_S 27 -/** EFUSE_RESERVED_1_94 : R; bitpos: [31:30]; default: 0; +#define EFUSE_PKG_VERSION_S 20 +/** EFUSE_RESERVED_1_87 : R; bitpos: [31:23]; default: 0; * reserved */ -#define EFUSE_RESERVED_1_94 0x00000003U -#define EFUSE_RESERVED_1_94_M (EFUSE_RESERVED_1_94_V << EFUSE_RESERVED_1_94_S) -#define EFUSE_RESERVED_1_94_V 0x00000003U -#define EFUSE_RESERVED_1_94_S 30 +#define EFUSE_RESERVED_1_87 0x000001FFU +#define EFUSE_RESERVED_1_87_M (EFUSE_RESERVED_1_87_V << EFUSE_RESERVED_1_87_S) +#define EFUSE_RESERVED_1_87_V 0x000001FFU +#define EFUSE_RESERVED_1_87_S 23 /** EFUSE_RD_MAC_SYS_3_REG register * BLOCK1 data register $n. @@ -2455,7 +2434,7 @@ extern "C" { #define EFUSE_CLK_EN_S 16 /** EFUSE_CONF_REG register - * eFuse operation mode configuraiton register + * eFuse operation mode configuration register */ #define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x1cc) /** EFUSE_OP_CODE : R/W; bitpos: [15:0]; default: 0; diff --git a/components/soc/esp32p4/include/soc/efuse_struct.h b/components/soc/esp32p4/include/soc/efuse_struct.h index 21a6f9f404..ac74f0f7ec 100644 --- a/components/soc/esp32p4/include/soc/efuse_struct.h +++ b/components/soc/esp32p4/include/soc/efuse_struct.h @@ -495,12 +495,12 @@ typedef union { */ uint32_t km_disable_deploy_mode:4; /** usb_device_drefl : RO; bitpos: [13:12]; default: 0; - * Represents the usb device single-end input low threhold, 0.8 V to 1.04 V with step + * Represents the usb device single-end input low threshold, 0.8 V to 1.04 V with step * of 80 mV. */ uint32_t usb_device_drefl:2; /** usb_otg11_drefl : RO; bitpos: [15:14]; default: 0; - * Represents the usb otg11 single-end input low threhold, 0.8 V to 1.04 V with step + * Represents the usb otg11 single-end input low threshold, 0.8 V to 1.04 V with step * of 80 mV. */ uint32_t usb_otg11_drefl:2; @@ -591,38 +591,26 @@ typedef union { * BLK_VERSION_MAJOR of BLOCK2 */ uint32_t blk_version_major:2; - /** flash_cap : R; bitpos: [15:13]; default: 0; - * Flash capacity - */ - uint32_t flash_cap:3; - /** flash_temp : R; bitpos: [17:16]; default: 0; - * Flash temperature - */ - uint32_t flash_temp:2; - /** flash_vendor : R; bitpos: [20:18]; default: 0; - * Flash vendor - */ - uint32_t flash_vendor:3; - /** psram_cap : R; bitpos: [22:21]; default: 0; + /** psram_cap : R; bitpos: [15:13]; default: 0; * PSRAM capacity */ - uint32_t psram_cap:2; - /** psram_temp : R; bitpos: [24:23]; default: 0; - * PSRAM temperature + uint32_t psram_cap:3; + /** temp : R; bitpos: [17:16]; default: 0; + * Operating temperature of the ESP chip */ - uint32_t psram_temp:2; - /** psram_vendor : R; bitpos: [26:25]; default: 0; + uint32_t temp:2; + /** psram_vendor : R; bitpos: [19:18]; default: 0; * PSRAM vendor */ uint32_t psram_vendor:2; - /** pkg_version : R; bitpos: [29:27]; default: 0; + /** pkg_version : R; bitpos: [22:20]; default: 0; * Package version */ uint32_t pkg_version:3; - /** reserved_1_94 : R; bitpos: [31:30]; default: 0; + /** reserved_1_87 : R; bitpos: [31:23]; default: 0; * reserved */ - uint32_t reserved_1_94:2; + uint32_t reserved_1_87:9; }; uint32_t val; } efuse_rd_mac_sys_2_reg_t; @@ -2068,7 +2056,7 @@ typedef union { } efuse_clk_reg_t; /** Type of conf register - * eFuse operation mode configuraiton register + * eFuse operation mode configuration register */ typedef union { struct { @@ -4292,7 +4280,7 @@ typedef union { } efuse_apb2otp_blk10_w10_reg_t; -/** Group: EFUSE_APB2OTP Function Enable Singal */ +/** Group: EFUSE_APB2OTP Function Enable Signal */ /** Type of apb2otp_en register * eFuse apb2otp enable configuration register. */