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feat(uart): support HP/LP uart on ESP32C5 MP v5.3

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This commit is contained in:
gaoxu
2024-06-12 15:29:16 +08:00
parent 7f0673f634
commit cf123b3626
10 changed files with 96 additions and 44 deletions
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8
components/soc/esp32c5/beta3/include/soc/clk_tree_defs.h
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@@ -19,7 +19,7 @@ extern "C" {
*
* 2) External 40/48MHz Crystal Clock: XTAL
*
* 3) Internal 136kHz RC Oscillator: RC_SLOW (may also referrred as SOSC in TRM or reg. description)
* 3) Internal 136kHz RC Oscillator: RC_SLOW (may also referred as SOSC in TRM or reg. description)
*
* This RC oscillator generates a ~136kHz clock signal output as the RC_SLOW_CLK. The exact frequency of this clock
* can be computed in runtime through calibration.
@@ -250,15 +250,15 @@ typedef enum {
/**
* @brief Array initializer for all supported clock sources of LP_UART
*/
#define SOC_LP_UART_CLKS {SOC_MOD_CLK_RTC_FAST, SOC_MOD_CLK_XTAL_D2}
#define SOC_LP_UART_CLKS {SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_XTAL_D2}
/**
* @brief Type of LP_UART clock source
*/
typedef enum {
LP_UART_SCLK_LP_FAST = SOC_MOD_CLK_RTC_FAST, /*!< LP_UART source clock is LP(RTC)_FAST */
LP_UART_SCLK_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< LP_UART source clock is RC_FAST */
LP_UART_SCLK_XTAL_D2 = SOC_MOD_CLK_XTAL_D2, /*!< LP_UART source clock is XTAL_D2 */
LP_UART_SCLK_DEFAULT = SOC_MOD_CLK_RTC_FAST, /*!< LP_UART source clock default choice is LP(RTC)_FAST */
LP_UART_SCLK_DEFAULT = SOC_MOD_CLK_XTAL_D2, /*!< LP_UART source clock default choice is RC_FAST */
} soc_periph_lp_uart_clk_src_t;
//////////////////////////////////////////////////MCPWM/////////////////////////////////////////////////////////////////

20
components/soc/esp32c5/mp/include/soc/Kconfig.soc_caps.in
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@@ -51,6 +51,10 @@ config SOC_FLASH_ENC_SUPPORTED
bool
default y
config SOC_LP_PERIPHERALS_SUPPORTED
bool
default y
config SOC_SPI_FLASH_SUPPORTED
bool
default y
@@ -383,10 +387,26 @@ config SOC_LP_UART_FIFO_LEN
int
default 16
config SOC_UART_BITRATE_MAX
int
default 5000000
config SOC_UART_SUPPORT_XTAL_CLK
bool
default y
config SOC_UART_SUPPORT_WAKEUP_INT
bool
default y
config SOC_UART_HAS_LP_UART
bool
default y
config SOC_UART_SUPPORT_FSM_TX_WAIT_SEND
bool
default y
config SOC_PM_SUPPORT_MODEM_PD
bool
default y

24
components/soc/esp32c5/mp/include/soc/clk_tree_defs.h
View File

@@ -247,23 +247,39 @@ typedef enum { // TODO: [ESP32C5] IDF-8727 (inherit from C6)
///////////////////////////////////////////////////UART/////////////////////////////////////////////////////////////////
/**
* @brief Array initializer for all supported clock sources of UART
*/
#define SOC_UART_CLKS {SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST}
/**
* @brief Type of UART clock source, reserved for the legacy UART driver
*/
typedef enum { // TODO: [ESP32C5] IDF-8722 (inherit from C6)
typedef enum {
UART_SCLK_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< UART source clock is PLL_F80M */
UART_SCLK_RTC = SOC_MOD_CLK_RC_FAST, /*!< UART source clock is RC_FAST */
UART_SCLK_XTAL = SOC_MOD_CLK_XTAL, /*!< UART source clock is XTAL */
#if SOC_CLK_TREE_SUPPORTED
UART_SCLK_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< UART source clock default choice is PLL_F80M */
#else
UART_SCLK_DEFAULT = SOC_MOD_CLK_XTAL, /*!< UART source clock default choice is XTAL for FPGA environment*/
#endif
} soc_periph_uart_clk_src_legacy_t;
/**
* @brief Array initializer for all supported clock sources of LP_UART
*/
#define SOC_LP_UART_CLKS {SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_XTAL_D2}
/**
* @brief Type of LP_UART clock source
*/
typedef enum { // TODO: [ESP32C5] IDF-8633 (inherit from C6)
LP_UART_SCLK_LP_FAST = SOC_MOD_CLK_RTC_FAST, /*!< LP_UART source clock is LP(RTC)_FAST */
typedef enum {
LP_UART_SCLK_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< LP_UART source clock is RC_FAST */
LP_UART_SCLK_XTAL_D2 = SOC_MOD_CLK_XTAL_D2, /*!< LP_UART source clock is XTAL_D2 */
LP_UART_SCLK_DEFAULT = SOC_MOD_CLK_RTC_FAST, /*!< LP_UART source clock default choice is LP(RTC)_FAST */
//TODO: IDF-10034
LP_UART_SCLK_DEFAULT = SOC_MOD_CLK_XTAL_D2, /*!< LP_UART source clock default choice is XTAL_D2 */
} soc_periph_lp_uart_clk_src_t;
//////////////////////////////////////////////////MCPWM/////////////////////////////////////////////////////////////////

17
components/soc/esp32c5/mp/include/soc/lp_uart_struct.h
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@@ -844,7 +844,22 @@ typedef union {
*/
typedef union {
struct {
uint32_t reserved_0:24;
/** sclk_div_b : R/W; bitpos: [5:0]; default: 0;
* The denominator of the frequency divider factor.
* Only available to LP UART instance
*/
uint32_t sclk_div_b:6;
/** sclk_div_a : R/W; bitpos: [11:6]; default: 0;
* The numerator of the frequency divider factor.
* Only available to LP UART instance
*/
uint32_t sclk_div_a:6;
/** sclk_div_num : R/W; bitpos: [19:12]; default: 1;
* The integral part of the frequency divider factor.
* Only available to LP UART instance
*/
uint32_t sclk_div_num:8;
uint32_t reserved_20:4;
/** tx_sclk_en : R/W; bitpos: [24]; default: 1;
* Configures whether or not to enable LP UART TX clock.\\
* 0: Disable\\

13
components/soc/esp32c5/mp/include/soc/soc_caps.h
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@@ -19,7 +19,7 @@
/*-------------------------- COMMON CAPS ---------------------------------------*/
// #define SOC_ADC_SUPPORTED 1 // TODO: [ESP32C5] IDF-8701
// #define SOC_DEDICATED_GPIO_SUPPORTED 1 // TODO: [ESP32C5] IDF-8725
#define SOC_UART_SUPPORTED 1 // TODO: [ESP32C5] IDF-8722
#define SOC_UART_SUPPORTED 1
#define SOC_GDMA_SUPPORTED 1
#define SOC_AHB_GDMA_SUPPORTED 1
#define SOC_GPTIMER_SUPPORTED 1
@@ -60,7 +60,7 @@
// #define SOC_PAU_SUPPORTED 1 // TODO: [ESP32C5] IDF-8638
// #define SOC_LP_TIMER_SUPPORTED 1 // TODO: [ESP32C5] IDF-8636
// #define SOC_LP_AON_SUPPORTED 1 // TODO: [ESP32C5] IDF-8638
// #define SOC_LP_PERIPHERALS_SUPPORTED 1 // TODO: [ESP32C5] IDF-8695, IDF-8723, IDF-8719
#define SOC_LP_PERIPHERALS_SUPPORTED 1
// #define SOC_LP_I2C_SUPPORTED 1 // TODO: [ESP32C5] IDF-8634
// #define SOC_ULP_LP_UART_SUPPORTED 1 // TODO: [ESP32C5] IDF-8633
// #define SOC_CLK_TREE_SUPPORTED 1 // TODO: [ESP32C5] IDF-8642
@@ -481,14 +481,15 @@
#define SOC_UART_LP_NUM (1U)
#define SOC_UART_FIFO_LEN (128) /*!< The UART hardware FIFO length */
#define SOC_LP_UART_FIFO_LEN (16) /*!< The LP UART hardware FIFO length */
// #define SOC_UART_BITRATE_MAX (5000000) /*!< Max bit rate supported by UART */
#define SOC_UART_BITRATE_MAX (5000000) /*!< Max bit rate supported by UART */
// #define SOC_UART_SUPPORT_PLL_F80M_CLK (1) /*!< Support PLL_F80M as the clock source */
// #define SOC_UART_SUPPORT_RTC_CLK (1) /*!< Support RTC clock as the clock source */
// #define SOC_UART_SUPPORT_RTC_CLK (1) /*!< Support RTC clock as the clock source */ // TODO: [ESP32C5] IDF-8642
#define SOC_UART_SUPPORT_XTAL_CLK (1) /*!< Support XTAL clock as the clock source */
// #define SOC_UART_SUPPORT_WAKEUP_INT (1) /*!< Support UART wakeup interrupt */
#define SOC_UART_SUPPORT_WAKEUP_INT (1) /*!< Support UART wakeup interrupt */
#define SOC_UART_HAS_LP_UART (1) /*!< Support LP UART */
// UART has an extra TX_WAIT_SEND state when the FIFO is not empty and XOFF is enabled
// #define SOC_UART_SUPPORT_FSM_TX_WAIT_SEND (1)
#define SOC_UART_SUPPORT_FSM_TX_WAIT_SEND (1)
/*-------------------------- COEXISTENCE HARDWARE PTI CAPS -------------------------------*/
// #define SOC_COEX_HW_PTI (1)

14
components/soc/esp32c5/mp/include/soc/uart_channel.h
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@@ -8,13 +8,11 @@
#pragma once
// TODO: [ESP32C5] IDF-8722
//UART channels
#define UART_GPIO16_DIRECT_CHANNEL UART_NUM_0
#define UART_NUM_0_TXD_DIRECT_GPIO_NUM 16
#define UART_GPIO17_DIRECT_CHANNEL UART_NUM_0
#define UART_NUM_0_RXD_DIRECT_GPIO_NUM 17
#define UART_GPIO11_DIRECT_CHANNEL UART_NUM_0
#define UART_NUM_0_TXD_DIRECT_GPIO_NUM 11
#define UART_GPIO12_DIRECT_CHANNEL UART_NUM_0
#define UART_NUM_0_RXD_DIRECT_GPIO_NUM 12
#define UART_TXD_GPIO16_DIRECT_CHANNEL UART_GPIO16_DIRECT_CHANNEL
#define UART_RXD_GPIO17_DIRECT_CHANNEL UART_GPIO17_DIRECT_CHANNEL
#define UART_TXD_GPIO11_DIRECT_CHANNEL UART_GPIO11_DIRECT_CHANNEL
#define UART_RXD_GPIO12_DIRECT_CHANNEL UART_GPIO12_DIRECT_CHANNEL

2
components/soc/esp32c5/mp/include/soc/uart_pins.h
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@@ -8,8 +8,6 @@
#include "soc/io_mux_reg.h"
// TODO: [ESP32C5] IDF-8722
/* Specify the number of pins for UART */
#define SOC_UART_PINS_COUNT (4)

20
components/soc/esp32c5/mp/include/soc/uart_struct.h
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@@ -20,8 +20,7 @@ typedef union {
* Represents the data UART $n read from FIFO.\\
* Measurement unit: byte.
*/
uint32_t rxfifo_rd_byte:8;
uint32_t reserved_8:24;
uint32_t rxfifo_rd_byte:32;
};
uint32_t val;
} uart_fifo_reg_t;
@@ -947,7 +946,22 @@ typedef union {
*/
typedef union {
struct {
uint32_t reserved_0:24;
/** sclk_div_b : R/W; bitpos: [5:0]; default: 0;
* The denominator of the frequency divider factor.'
* Only available to LP UART instance
*/
uint32_t sclk_div_b:6;
/** sclk_div_a : R/W; bitpos: [11:6]; default: 0;
* The numerator of the frequency divider factor.
* Only available to LP UART instance
*/
uint32_t sclk_div_a:6;
/** sclk_div_num : R/W; bitpos: [19:12]; default: 1;
* The integral part of the frequency divider factor.
* Only available to LP UART instance
*/
uint32_t sclk_div_num:8;
uint32_t reserved_20:4;
/** tx_sclk_en : R/W; bitpos: [24]; default: 1;
* Configures whether or not to enable UART TX clock.\\
* 0: Disable\\