mirror of
https://github.com/espressif/esp-idf.git
synced 2025-11-02 16:11:41 +01:00
Merge branch 'master' into feature/logging
* master: (45 commits) esp32/lib: update to 1303c92c dhcpserver: Fix crash when switching wifi mode mbedtls: Temporarily disable default hardware crypto SHA & bignum mbedtls hwcrypto sha512: Fix redirection of function names mbedtls upstream tweak: Move mbedtls_sha512_process in sha512.h Format code by using 4 spaces instead modify character conversion error and typo modify i2s_reg.h, rebase to master Only modify headers in soc/ . Pass compiling under esp-idf-tests/merge_soc_tmp/merge_for_soc_headers branch.(only change some names of register and INUM). Rename vender_ie_type_t and vendor_ie_id_t to wifi_vendor_ie_type_t and wifi_vendor_ie_id_t respectively modify arguments for vendor ie APIs by using enum instead esp32: fix typo esp32: fix kconfig define lwip task priority in esp_task.h components: esp32 - fix build error components: lwip - Modify lwip task priority and stack definition method components: esp32 components: esp32 components: esp32/lwip task priority: modify lwip/wifi/event task priority ... # Conflicts: # components/bootloader/src/main/bootloader_start.c # components/bootloader/src/main/flash_encrypt.c # components/bootloader/src/main/secure_boot.c # components/esp32/cpu_start.c
This commit is contained in:
Ivan Grokhotkov
@@ -18,15 +18,11 @@ BOOTLOADER_BIN=$(BOOTLOADER_BUILD_DIR)/bootloader.bin
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$(BOOTLOADER_BIN): $(COMPONENT_PATH)/src/sdkconfig
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$(Q) PROJECT_PATH= \
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LDFLAGS= \
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CFLAGS= \
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BUILD_DIR_BASE=$(BOOTLOADER_BUILD_DIR) \
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$(MAKE) -C $(BOOTLOADER_COMPONENT_PATH)/src MAKEFLAGS= V=$(V) TARGET_BIN_LAYOUT="$(BOOTLOADER_TARGET_BIN_LAYOUT)" $(BOOTLOADER_BIN)
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bootloader-clean:
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$(Q) PROJECT_PATH= \
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LDFLAGS= \
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CFLAGS= \
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BUILD_DIR_BASE=$(BOOTLOADER_BUILD_DIR) \
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$(MAKE) -C $(BOOTLOADER_COMPONENT_PATH)/src app-clean MAKEFLAGS= V=$(V)
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@@ -29,7 +29,7 @@
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#include "soc/io_mux_reg.h"
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#include "soc/efuse_reg.h"
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#include "soc/rtc_cntl_reg.h"
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#include "soc/timers_reg.h"
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#include "soc/timer_group_reg.h"
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#include "sdkconfig.h"
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@@ -73,9 +73,9 @@ void IRAM_ATTR call_start_cpu0()
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Cache_Flush(0);
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Cache_Flush(1);
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mmu_init(0);
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REG_SET_BIT(APP_CACHE_CTRL1_REG, DPORT_APP_CACHE_MMU_IA_CLR);
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REG_SET_BIT(DPORT_APP_CACHE_CTRL1_REG, DPORT_APP_CACHE_MMU_IA_CLR);
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mmu_init(1);
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REG_CLR_BIT(APP_CACHE_CTRL1_REG, DPORT_APP_CACHE_MMU_IA_CLR);
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REG_CLR_BIT(DPORT_APP_CACHE_CTRL1_REG, DPORT_APP_CACHE_MMU_IA_CLR);
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/* (above steps probably unnecessary for most serial bootloader
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usage, all that's absolutely needed is that we unmask DROM0
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cache on the following two lines - normal ROM boot exits with
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@@ -86,8 +86,8 @@ void IRAM_ATTR call_start_cpu0()
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The lines which manipulate DPORT_APP_CACHE_MMU_IA_CLR bit are
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necessary to work around a hardware bug.
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*/
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REG_CLR_BIT(PRO_CACHE_CTRL1_REG, DPORT_PRO_CACHE_MASK_DROM0);
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REG_CLR_BIT(APP_CACHE_CTRL1_REG, DPORT_APP_CACHE_MASK_DROM0);
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REG_CLR_BIT(DPORT_PRO_CACHE_CTRL1_REG, DPORT_PRO_CACHE_MASK_DROM0);
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REG_CLR_BIT(DPORT_APP_CACHE_CTRL1_REG, DPORT_APP_CACHE_MASK_DROM0);
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bootloader_main();
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}
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@@ -258,8 +258,8 @@ void bootloader_main()
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ESP_LOGI(TAG, "compile time " __TIME__ );
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/* close watch dog here */
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REG_CLR_BIT( RTC_WDTCONFIG0, RTC_CNTL_WDT_FLASHBOOT_MOD_EN );
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REG_CLR_BIT( WDTCONFIG0(0), TIMERS_WDT_FLASHBOOT_MOD_EN );
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REG_CLR_BIT( RTC_CNTL_WDTCONFIG0_REG, RTC_CNTL_WDT_FLASHBOOT_MOD_EN );
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REG_CLR_BIT( TIMG_WDTCONFIG0_REG(0), TIMG_WDT_FLASHBOOT_MOD_EN );
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SPIUnlock();
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/*register first sector in drom0 page 0 */
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boot_cache_redirect( 0, 0x5000 );
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@@ -452,8 +452,8 @@ void IRAM_ATTR set_cache_and_start_app(
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ESP_LOGV(TAG, "rc=%d", rc );
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rc = cache_flash_mmu_set( 1, 0, irom_load_addr & 0xffff0000, irom_addr & 0xffff0000, 64, irom_page_count );
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ESP_LOGV(TAG, "rc=%d", rc );
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REG_CLR_BIT( PRO_CACHE_CTRL1_REG, (DPORT_PRO_CACHE_MASK_IRAM0) | (DPORT_PRO_CACHE_MASK_IRAM1 & 0) | (DPORT_PRO_CACHE_MASK_IROM0 & 0) | DPORT_PRO_CACHE_MASK_DROM0 | DPORT_PRO_CACHE_MASK_DRAM1 );
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REG_CLR_BIT( APP_CACHE_CTRL1_REG, (DPORT_APP_CACHE_MASK_IRAM0) | (DPORT_APP_CACHE_MASK_IRAM1 & 0) | (DPORT_APP_CACHE_MASK_IROM0 & 0) | DPORT_APP_CACHE_MASK_DROM0 | DPORT_APP_CACHE_MASK_DRAM1 );
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REG_CLR_BIT( DPORT_PRO_CACHE_CTRL1_REG, (DPORT_PRO_CACHE_MASK_IRAM0) | (DPORT_PRO_CACHE_MASK_IRAM1 & 0) | (DPORT_PRO_CACHE_MASK_IROM0 & 0) | DPORT_PRO_CACHE_MASK_DROM0 | DPORT_PRO_CACHE_MASK_DRAM1 );
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REG_CLR_BIT( DPORT_APP_CACHE_CTRL1_REG, (DPORT_APP_CACHE_MASK_IRAM0) | (DPORT_APP_CACHE_MASK_IRAM1 & 0) | (DPORT_APP_CACHE_MASK_IROM0 & 0) | DPORT_APP_CACHE_MASK_DROM0 | DPORT_APP_CACHE_MASK_DRAM1 );
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Cache_Read_Enable( 0 );
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Cache_Read_Enable( 1 );
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@@ -103,7 +103,7 @@ bool flash_encrypt_write(uint32_t pos, uint32_t len)
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bool flash_encrypt(bootloader_state_t *bs)
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{
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uint32_t bin_len = 0;
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uint32_t flash_crypt_cnt = REG_GET_FIELD(EFUSE_BLK0_RDATA0, EFUSE_FLASH_CRYPT_CNT);
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uint32_t flash_crypt_cnt = REG_GET_FIELD(EFUSE_BLK0_RDATA0_REG, EFUSE_FLASH_CRYPT_CNT);
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uint8_t count = bitcount(flash_crypt_cnt);
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int i = 0;
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ESP_LOGD(TAG, "flash encrypt cnt %x, bitcount %d\n", flash_crypt_cnt, count);
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@@ -176,14 +176,14 @@ bool flash_encrypt(bootloader_state_t *bs)
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ESP_LOGE(TAG, "encrypt ota info error");
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return false;
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}
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REG_SET_FIELD(EFUSE_BLK0_WDATA0, EFUSE_FLASH_CRYPT_CNT, 0x04);
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REG_WRITE(EFUSE_CONF, 0x5A5A); /* efuse_pgm_op_ena, force no rd/wr disable */
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REG_WRITE(EFUSE_CMD, 0x02); /* efuse_pgm_cmd */
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while (REG_READ(EFUSE_CMD)); /* wait for efuse_pagm_cmd=0 */
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ESP_LOGW(TAG, "burn flash_crypt_cnt");
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REG_WRITE(EFUSE_CONF, 0x5AA5); /* efuse_read_op_ena, release force */
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REG_WRITE(EFUSE_CMD, 0x01); /* efuse_read_cmd */
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while (REG_READ(EFUSE_CMD)); /* wait for efuse_read_cmd=0 */
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REG_SET_FIELD(EFUSE_BLK0_WDATA0_REG, EFUSE_FLASH_CRYPT_CNT, 0x04);
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REG_WRITE(EFUSE_CONF_REG, 0x5A5A); /* efuse_pgm_op_ena, force no rd/wr disable */
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REG_WRITE(EFUSE_CMD_REG, 0x02); /* efuse_pgm_cmd */
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while (REG_READ(EFUSE_CMD_REG)); /* wait for efuse_pagm_cmd=0 */
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ESP_LOGW(TAG, "burn flash_crypt_cnt\n");
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REG_WRITE(EFUSE_CONF_REG, 0x5AA5); /* efuse_read_op_ena, release force */
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REG_WRITE(EFUSE_CMD_REG, 0x01); /* efuse_read_cmd */
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while (REG_READ(EFUSE_CMD_REG)); /* wait for efuse_read_cmd=0 */
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return true;
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} else {
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ESP_LOGI(TAG, "flash already encrypted.");
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@@ -96,7 +96,7 @@ bool secure_boot_generate(uint32_t bin_len){
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*/
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bool secure_boot(void){
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uint32_t bin_len = 0;
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if (REG_READ(EFUSE_BLK0_RDATA6) & EFUSE_RD_ABS_DONE_0)
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if (REG_READ(EFUSE_BLK0_RDATA6_REG) & EFUSE_RD_ABS_DONE_0)
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{
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ESP_LOGD(TAG, "already secure boot !");
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return true;
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@@ -113,15 +113,15 @@ bool secure_boot(void){
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}
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}
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REG_SET_BIT(EFUSE_BLK0_WDATA6, EFUSE_RD_ABS_DONE_0);
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REG_WRITE(EFUSE_CONF, 0x5A5A); /* efuse_pgm_op_ena, force no rd/wr disable */
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REG_WRITE(EFUSE_CMD, 0x02); /* efuse_pgm_cmd */
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while (REG_READ(EFUSE_CMD)); /* wait for efuse_pagm_cmd=0 */
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ESP_LOGI(TAG, "burn abstract_done_0");
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REG_WRITE(EFUSE_CONF, 0x5AA5); /* efuse_read_op_ena, release force */
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REG_WRITE(EFUSE_CMD, 0x01); /* efuse_read_cmd */
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while (REG_READ(EFUSE_CMD)); /* wait for efuse_read_cmd=0 */
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ESP_LOGD(TAG, "read EFUSE_BLK0_RDATA6 %x\n", REG_READ(EFUSE_BLK0_RDATA6));
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REG_SET_BIT(EFUSE_BLK0_WDATA6_REG, EFUSE_RD_ABS_DONE_0);
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REG_WRITE(EFUSE_CONF_REG, 0x5A5A); /* efuse_pgm_op_ena, force no rd/wr disable */
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REG_WRITE(EFUSE_CMD_REG, 0x02); /* efuse_pgm_cmd */
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while (REG_READ(EFUSE_CMD_REG)); /* wait for efuse_pagm_cmd=0 */
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ESP_LOGW(TAG, "burn abstract_done_0\n");
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REG_WRITE(EFUSE_CONF_REG, 0x5AA5); /* efuse_read_op_ena, release force */
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REG_WRITE(EFUSE_CMD_REG, 0x01); /* efuse_read_cmd */
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while (REG_READ(EFUSE_CMD_REG)); /* wait for efuse_read_cmd=0 */
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ESP_LOGI(TAG, "read EFUSE_BLK0_RDATA6 %x\n", REG_READ(EFUSE_BLK0_RDATA6_REG));
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return true;
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}
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