espressif/esp-idf
1
0
Fork 1
mirror of https://github.com/espressif/esp-idf.git synced 2025-11-30 22:30:24 +01:00
Code Issues Packages Projects Releases Wiki Activity

refactor(rtc): move soc/rtc.h from soc to esp_hw_support component

Browse Source 
Deprecated rtc_xtal_freq_t, replaced with soc_xtal_freq_t defined in
clk_tree_defs.h in soc component.
This commit is contained in:
Song Ruo Jing
2024-01-03 15:28:29 +08:00
parent e81932d2b2
commit cf93777077
95 changed files with 494 additions and 644 deletions
Download Patch File Download Diff File Expand all files Collapse all files

19
components/hal/esp32c3/include/hal/clk_tree_ll.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -9,7 +9,6 @@
#include <stdint.h>
#include "soc/soc.h"
#include "soc/clk_tree_defs.h"
#include "soc/rtc.h"
#include "soc/system_reg.h"
#include "soc/rtc_cntl_reg.h"
#include "hal/regi2c_ctrl.h"
@@ -32,6 +31,10 @@ extern "C" {
#define CLK_LL_AHB_MAX_FREQ_MHZ CLK_LL_PLL_80M_FREQ_MHZ
/* RC_FAST clock enable/disable wait time */
#define CLK_LL_RC_FAST_WAIT_DEFAULT 20
#define CLK_LL_RC_FAST_ENABLE_WAIT_DEFAULT 5
#define CLK_LL_XTAL32K_CONFIG_DEFAULT() { \
.dac = 3, \
.dres = 3, \
@@ -131,7 +134,7 @@ static inline __attribute__((always_inline)) bool clk_ll_xtal32k_is_enabled(void
static inline __attribute__((always_inline)) void clk_ll_rc_fast_enable(void)
{
CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M);
REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, RTC_CK8M_ENABLE_WAIT_DEFAULT);
REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, CLK_LL_RC_FAST_ENABLE_WAIT_DEFAULT);
}
/**
@@ -140,7 +143,7 @@ static inline __attribute__((always_inline)) void clk_ll_rc_fast_enable(void)
static inline __attribute__((always_inline)) void clk_ll_rc_fast_disable(void)
{
SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M);
REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, RTC_CNTL_CK8M_WAIT_DEFAULT);
REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, CLK_LL_RC_FAST_WAIT_DEFAULT);
}
/**
@@ -311,7 +314,7 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_set_config(uint32
if (pll_freq_mhz == CLK_LL_PLL_480M_FREQ_MHZ) {
/* Configure 480M PLL */
switch (xtal_freq_mhz) {
case RTC_XTAL_FREQ_40M:
case SOC_XTAL_FREQ_40M:
div_ref = 0;
div7_0 = 8;
dr1 = 0;
@@ -320,7 +323,7 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_set_config(uint32
dcur = 3;
dbias = 2;
break;
case RTC_XTAL_FREQ_32M:
case SOC_XTAL_FREQ_32M:
div_ref = 1;
div7_0 = 26;
dr1 = 1;
@@ -343,7 +346,7 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_set_config(uint32
} else {
/* Configure 320M PLL */
switch (xtal_freq_mhz) {
case RTC_XTAL_FREQ_40M:
case SOC_XTAL_FREQ_40M:
div_ref = 0;
div7_0 = 4;
dr1 = 0;
@@ -352,7 +355,7 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_set_config(uint32
dcur = 3;
dbias = 2;
break;
case RTC_XTAL_FREQ_32M:
case SOC_XTAL_FREQ_32M:
div_ref = 1;
div7_0 = 6;
dr1 = 0;