From cf9cb577ce9efa349fb74e0237ad7726c990175d Mon Sep 17 00:00:00 2001
From: Armando <douyiwen@espressif.com>
Date: Mon, 6 Mar 2023 11:00:59 +0800
Subject: [PATCH] esp_psram: return error when fail to detect oct psram

---
 components/esp_hw_support/port/esp32s3/opiram_psram.c | 5 +++++
 components/esp_hw_support/port/esp32s3/spiram_psram.c | 4 ++--
 components/esp_hw_support/port/esp32s3/spiram_psram.h | 5 ++++-
 3 files changed, 11 insertions(+), 3 deletions(-)

diff --git a/components/esp_hw_support/port/esp32s3/opiram_psram.c b/components/esp_hw_support/port/esp32s3/opiram_psram.c
index 0f40a3d7dd..8b4db10daf 100644
--- a/components/esp_hw_support/port/esp32s3/opiram_psram.c
+++ b/components/esp_hw_support/port/esp32s3/opiram_psram.c
@@ -39,6 +39,7 @@
 #define OCT_PSRAM_RD_DUMMY_BITLEN       (2*(10-1))
 #define OCT_PSRAM_WR_DUMMY_BITLEN       (2*(5-1))
 #define OCT_PSRAM_CS1_IO                SPI_CS1_GPIO_NUM
+#define OCT_PSRAM_VENDOR_ID             0xD
 
 #define OCT_PSRAM_CS_SETUP_TIME         3
 #define OCT_PSRAM_CS_HOLD_TIME          3
@@ -255,6 +256,10 @@ esp_err_t psram_enable(psram_cache_mode_t mode, psram_vaddr_mode_t vaddrmode)
     s_init_psram_mode_reg(1, &mode_reg);
     //Print PSRAM info
     s_get_psram_mode_reg(1, &mode_reg);
+    if (mode_reg.mr1.vendor_id != OCT_PSRAM_VENDOR_ID) {
+        ESP_EARLY_LOGE(TAG, "PSRAM ID read error: 0x%08x, PSRAM chip not found or not supported, or wrong PSRAM line mode", mode_reg.mr1.vendor_id);
+        return ESP_ERR_NOT_SUPPORTED;
+    }
     s_print_psram_info(&mode_reg);
     s_psram_size = mode_reg.mr2.density == 0x1 ? PSRAM_SIZE_32MBITS  :
                    mode_reg.mr2.density == 0X3 ? PSRAM_SIZE_64MBITS  :
diff --git a/components/esp_hw_support/port/esp32s3/spiram_psram.c b/components/esp_hw_support/port/esp32s3/spiram_psram.c
index be4900661d..c56c6998e9 100644
--- a/components/esp_hw_support/port/esp32s3/spiram_psram.c
+++ b/components/esp_hw_support/port/esp32s3/spiram_psram.c
@@ -361,8 +361,8 @@ esp_err_t psram_enable(psram_cache_mode_t mode, psram_vaddr_mode_t vaddrmode)
          */
         psram_read_id(SPI1_NUM, &s_psram_id);
         if (!PSRAM_IS_VALID(s_psram_id)) {
-            ESP_EARLY_LOGE(TAG, "PSRAM ID read error: 0x%08x", s_psram_id);
-            return ESP_FAIL;
+            ESP_EARLY_LOGE(TAG, "PSRAM ID read error: 0x%08x, PSRAM chip not found or not supported, or wrong PSRAM line mode", (uint32_t)s_psram_id);
+            return ESP_ERR_NOT_SUPPORTED;
         }
     }
 
diff --git a/components/esp_hw_support/port/esp32s3/spiram_psram.h b/components/esp_hw_support/port/esp32s3/spiram_psram.h
index 06128ccfcc..d51c5dec15 100644
--- a/components/esp_hw_support/port/esp32s3/spiram_psram.h
+++ b/components/esp_hw_support/port/esp32s3/spiram_psram.h
@@ -55,7 +55,10 @@ psram_size_t psram_get_size(void);
  *
  * @param mode       SPI mode to access psram in
  * @param vaddrmode  Mode the psram cache works in.
- * @return ESP_OK on success, ESP_ERR_INVALID_STATE when VSPI peripheral is needed but cannot be claimed.
+ * @return
+ *        - ESP_OK: on success
+ *        - ESP_ERR_NOT_SUPPORTED: PSRAM ID / vendor ID check fail
+ *        - ESP_ERR_INVALID_STATE when VSPI peripheral is needed but cannot be claimed.
  */
 esp_err_t psram_enable(psram_cache_mode_t mode, psram_vaddr_mode_t vaddrmode);