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Merge branch 'bugfix/fix_adc_cali_workround_wrong_range_v5.1' into 'release/v5.1'
fix(regi2c): wrong ADC_CALI_PD_WORKAROUND on c6, h2 (v5.1) See merge request espressif/esp-idf!24747
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@ -1,5 +1,5 @@
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/*
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/*
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* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
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*
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*
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* SPDX-License-Identifier: Apache-2.0
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* SPDX-License-Identifier: Apache-2.0
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*/
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*/
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@ -79,7 +79,7 @@ void IRAM_ATTR regi2c_analog_cali_reg_write(void)
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regi2c_ctrl_write_reg(I2C_SAR_ADC, I2C_SAR_ADC_HOSTID, i, reg_val[i]);
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regi2c_ctrl_write_reg(I2C_SAR_ADC, I2C_SAR_ADC_HOSTID, i, reg_val[i]);
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}
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}
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}
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}
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#endif //#if ADC_CALI_PD_WORKAROUND
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/**
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/**
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* REGI2C_SARADC reference count
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* REGI2C_SARADC reference count
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@ -109,6 +109,3 @@ void regi2c_saradc_disable(void)
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regi2c_exit_critical();
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regi2c_exit_critical();
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}
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}
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#endif //#if ADC_CALI_PD_WORKAROUND
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@ -1,5 +1,5 @@
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/*
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/*
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* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
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*
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*
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* SPDX-License-Identifier: Apache-2.0
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* SPDX-License-Identifier: Apache-2.0
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*/
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*/
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@ -27,11 +27,3 @@
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#define ANA_CONFIG2_M BIT(18)
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#define ANA_CONFIG2_M BIT(18)
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#define ANA_I2C_SAR_FORCE_PU BIT(16)
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#define ANA_I2C_SAR_FORCE_PU BIT(16)
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/**
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* Restore regi2c analog calibration related configuration registers.
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* This is a workaround, and is fixed on later chips
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*/
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#define REGI2C_ANA_CALI_PD_WORKAROUND 1
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#define REGI2C_ANA_CALI_BYTE_NUM 8
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@ -26,10 +26,3 @@
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#define ANA_CONFIG2_M BIT(18)
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#define ANA_CONFIG2_M BIT(18)
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#define ANA_I2C_SAR_FORCE_PU BIT(16)
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#define ANA_I2C_SAR_FORCE_PU BIT(16)
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/**
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* Restore regi2c analog calibration related configuration registers.
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* This is a workaround, and is fixed on later chips
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*/
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#define REGI2C_ANA_CALI_PD_WORKAROUND 1
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#define REGI2C_ANA_CALI_BYTE_NUM 8
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