docs(usb/host): Update maintainer docs for ESP32-P4 (partial, only the common part of the doc)

This commit is contained in:
Roman Leonov
2025-01-13 10:11:31 +01:00
parent 2913869aaa
commit cfaf175cfa
2 changed files with 45 additions and 20 deletions

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@ -37,7 +37,7 @@ The layers of the Host Stack are described in the following table. The layers ar
- ``usb_host.h``, ``usb_host.c`` - ``usb_host.h``, ``usb_host.c``
- The USB Host Library layer is the lowest public API layer of the Host Stack and presents the concept of USB Host Clients. The abstraction of clients allows for multiple class drivers to coexist simultaneously (where each class roughly maps to a single client) and also acts as a mechanism for division of labor (where each client is responsible for its own processing and event handling). - The USB Host Library layer is the lowest public API layer of the Host Stack and presents the concept of USB Host Clients. The abstraction of clients allows for multiple class drivers to coexist simultaneously (where each class roughly maps to a single client) and also acts as a mechanism for division of labor (where each client is responsible for its own processing and event handling).
* - Host Class Drivers * - Host Class Drivers
- See the `ESP-IDF Extra Components repository <https://github.com/espressif/idf-extra-components>`_ or the USB Host examples in ESP-IDF (via :example:`peripherals/usb/host`). - See the `ESP-USB repository <https://github.com/espressif/esp-usb>`_ or the USB Host examples in ESP-IDF (via :example:`peripherals/usb/host`).
- The Host Class Drivers implement the host side of a particular device class (e.g., CDC, MSC, HID). The exposed API is specific to each class driver. - The Host Class Drivers implement the host side of a particular device class (e.g., CDC, MSC, HID). The exposed API is specific to each class driver.
Layer Dependencies Layer Dependencies

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@ -89,26 +89,51 @@ Hardware Configuration
The DWC_OTG IP is configurable. The notable Host related configurations of the {IDF_TARGET_NAME}'s DWC_OTG are listed below: The DWC_OTG IP is configurable. The notable Host related configurations of the {IDF_TARGET_NAME}'s DWC_OTG are listed below:
.. list-table:: {IDF_TARGET_NAME}'s DWC_OTG Configuration .. only:: esp32p4
:widths: 70 30
:header-rows: 1
* - Description .. list-table:: {IDF_TARGET_NAME}'s DWC_OTG Configuration
- Configuration :widths: 70 30
* - Host and Device Mode support with OTG :header-rows: 1
- ``OTG_MODE = 0``
* - Full Speed (FS) and Low Speed (LS) support * - Description
- ``OTG_FSPHY_INTERFACE = 1``, ``OTG_HSPHY_INTERFACE = 0`` - Configuration
* - Internal DMA controller with Scatter/Gather DMA * - Host and Device Mode support with OTG
- ``OTG_ARCHITECTURE = 2``, ``OTG_EN_DESC_DMA = 1`` - ``OTG_MODE = 0``
* - FS Hubs are supported but HS Hub are not (i.e., split transfers not supported) * - High Speed (HS), Full Speed (FS) and Low Speed (LS) support
- ``OTG_SINGLE_POINT = 0`` - ``OTG_FSPHY_INTERFACE = 2``, ``OTG_HSPHY_INTERFACE = 3``
* - 8 Host Mode channels * - Internal DMA controller with Scatter/Gather DMA
- ``OTG_NUM_HOST_CHAN = 8`` - ``OTG_ARCHITECTURE = 2``, ``OTG_EN_DESC_DMA = 1``
* - All transfer types supported, including ISOC and INTR OUT transfers * - Split transfers not supported
- ``OTG_EN_PERIO_HOST = 1`` - ``OTG_SINGLE_POINT = 1``
* - Dynamically sized Data FIFO of 1024 bytes (256 lines) * - 16 Host Mode channels
- ``OTG_DFIFO_DYNAMIC = 1``, ``OTG_DFIFO_DEPTH = 256`` - ``OTG_NUM_HOST_CHAN = 16``
* - All transfer types supported, including ISOC and INTR OUT transfers
- ``OTG_EN_PERIO_HOST = 1``
* - Dynamically sized Data FIFO of 4096 bytes (1024 lines)
- ``OTG_DFIFO_DYNAMIC = 1``, ``OTG_DFIFO_DEPTH = 1024``
* - Only 4 periodic and 4 non-periodic transactions per microframe
- ``OTG_NPERIO_TX_QUEUE_DEPTH = 4``, ``OTG_PERIO_TX_QUEUE_DEPTH = 4``
.. only:: esp32s2 or esp32s3
.. list-table:: {IDF_TARGET_NAME}'s DWC_OTG Configuration
:widths: 70 30
:header-rows: 1
* - Description
- Configuration
* - Host and Device Mode support with OTG
- ``OTG_MODE = 0``
* - Full Speed (FS) and Low Speed (LS) support
- ``OTG_FSPHY_INTERFACE = 1``, ``OTG_HSPHY_INTERFACE = 0``
* - Internal DMA controller with Scatter/Gather DMA
- ``OTG_ARCHITECTURE = 2``, ``OTG_EN_DESC_DMA = 1``
* - 8 Host Mode channels
- ``OTG_NUM_HOST_CHAN = 8``
* - All transfer types supported, including ISOC and INTR OUT transfers
- ``OTG_EN_PERIO_HOST = 1``
* - Dynamically sized Data FIFO of 1024 bytes (256 lines)
- ``OTG_DFIFO_DYNAMIC = 1``, ``OTG_DFIFO_DEPTH = 256``
Scatter/Gather DMA Transfer Scatter/Gather DMA Transfer
--------------------------- ---------------------------