From 254870c3c4e1911428d13f76896e5f3a64af3e7d Mon Sep 17 00:00:00 2001 From: "Michael (XIAO Xufeng)" Date: Sat, 7 May 2022 01:52:55 +0800 Subject: [PATCH 1/7] rtc: fixed 8MD256 can't be used as RTC slow src on ESP32 Sync configuration from other chips Closes: https://github.com/espressif/esp-idf/issues/8007, https://github.com/espressif/esp-idf/pull/8089 --- .../esp_hw_support/port/esp32/rtc_clk.c | 3 +-- .../esp_hw_support/port/esp32c3/rtc_clk.c | 1 - .../esp_hw_support/port/esp32s2/rtc_clk.c | 1 - .../esp_hw_support/port/esp32s3/rtc_clk.c | 1 - components/soc/esp32/include/soc/rtc.h | 3 +++ .../soc/esp32/include/soc/rtc_cntl_reg.h | 19 +++++-------------- .../soc/esp32c3/include/soc/rtc_cntl_reg.h | 1 - 7 files changed, 9 insertions(+), 20 deletions(-) diff --git a/components/esp_hw_support/port/esp32/rtc_clk.c b/components/esp_hw_support/port/esp32/rtc_clk.c index f92c2133d7..3fb09da7c0 100644 --- a/components/esp_hw_support/port/esp32/rtc_clk.c +++ b/components/esp_hw_support/port/esp32/rtc_clk.c @@ -244,8 +244,7 @@ void rtc_clk_8m_enable(bool clk_8m_en, bool d256_en) { if (clk_8m_en) { CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M); - /* no need to wait once enabled by software */ - REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, 1); + REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, RTC_CK8M_ENABLE_WAIT_DEFAULT); if (d256_en) { CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV); } else { diff --git a/components/esp_hw_support/port/esp32c3/rtc_clk.c b/components/esp_hw_support/port/esp32c3/rtc_clk.c index 866d424430..8c35c12c48 100644 --- a/components/esp_hw_support/port/esp32c3/rtc_clk.c +++ b/components/esp_hw_support/port/esp32c3/rtc_clk.c @@ -88,7 +88,6 @@ void rtc_clk_8m_enable(bool clk_8m_en, bool d256_en) { if (clk_8m_en) { CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M); - /* no need to wait once enabled by software */ REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, RTC_CK8M_ENABLE_WAIT_DEFAULT); esp_rom_delay_us(DELAY_8M_ENABLE); } else { diff --git a/components/esp_hw_support/port/esp32s2/rtc_clk.c b/components/esp_hw_support/port/esp32s2/rtc_clk.c index c88dce3da6..5ef8f21750 100644 --- a/components/esp_hw_support/port/esp32s2/rtc_clk.c +++ b/components/esp_hw_support/port/esp32s2/rtc_clk.c @@ -92,7 +92,6 @@ void rtc_clk_8m_enable(bool clk_8m_en, bool d256_en) { if (clk_8m_en) { CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M); - /* no need to wait once enabled by software */ REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, RTC_CK8M_ENABLE_WAIT_DEFAULT); esp_rom_delay_us(DELAY_8M_ENABLE); } else { diff --git a/components/esp_hw_support/port/esp32s3/rtc_clk.c b/components/esp_hw_support/port/esp32s3/rtc_clk.c index f0c10f279c..47091b8498 100644 --- a/components/esp_hw_support/port/esp32s3/rtc_clk.c +++ b/components/esp_hw_support/port/esp32s3/rtc_clk.c @@ -96,7 +96,6 @@ void rtc_clk_8m_enable(bool clk_8m_en, bool d256_en) { if (clk_8m_en) { CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M); - /* no need to wait once enabled by software */ REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, RTC_CK8M_ENABLE_WAIT_DEFAULT); esp_rom_delay_us(DELAY_8M_ENABLE); } else { diff --git a/components/soc/esp32/include/soc/rtc.h b/components/soc/esp32/include/soc/rtc.h index 6f5d8001d4..f163d2b98c 100644 --- a/components/soc/esp32/include/soc/rtc.h +++ b/components/soc/esp32/include/soc/rtc.h @@ -562,6 +562,9 @@ typedef struct rtc_sleep_config_s { #define RTC_CNTL_OTHER_BLOCKS_POWERUP_CYCLES (1) #define RTC_CNTL_OTHER_BLOCKS_WAIT_CYCLES (1) +#define RTC_CNTL_CK8M_WAIT_DEFAULT 20 +#define RTC_CK8M_ENABLE_WAIT_DEFAULT 5 + /** * @brief Prepare the chip to enter sleep mode * diff --git a/components/soc/esp32/include/soc/rtc_cntl_reg.h b/components/soc/esp32/include/soc/rtc_cntl_reg.h index 96a867b31c..7e53e96993 100644 --- a/components/soc/esp32/include/soc/rtc_cntl_reg.h +++ b/components/soc/esp32/include/soc/rtc_cntl_reg.h @@ -1,16 +1,8 @@ -// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at - -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #ifndef _SOC_RTC_CNTL_REG_H_ #define _SOC_RTC_CNTL_REG_H_ @@ -341,7 +333,6 @@ #define RTC_CNTL_CK8M_WAIT_M ((RTC_CNTL_CK8M_WAIT_V)<<(RTC_CNTL_CK8M_WAIT_S)) #define RTC_CNTL_CK8M_WAIT_V 0xFF #define RTC_CNTL_CK8M_WAIT_S 6 -#define RTC_CNTL_CK8M_WAIT_DEFAULT 20 /* RTC_CNTL_CPU_STALL_WAIT : R/W ;bitpos:[5:1] ;default: 5'd1 ; */ /*description: CPU stall wait cycles in fast_clk_rtc*/ #define RTC_CNTL_CPU_STALL_WAIT 0x0000001F diff --git a/components/soc/esp32c3/include/soc/rtc_cntl_reg.h b/components/soc/esp32c3/include/soc/rtc_cntl_reg.h index b25f644832..a8953eeff4 100644 --- a/components/soc/esp32c3/include/soc/rtc_cntl_reg.h +++ b/components/soc/esp32c3/include/soc/rtc_cntl_reg.h @@ -308,7 +308,6 @@ extern "C" { #define RTC_CNTL_CK8M_WAIT_M ((RTC_CNTL_CK8M_WAIT_V)<<(RTC_CNTL_CK8M_WAIT_S)) #define RTC_CNTL_CK8M_WAIT_V 0xFF #define RTC_CNTL_CK8M_WAIT_S 6 -#define RTC_CNTL_CK8M_WAIT_DEFAULT 20 /* RTC_CNTL_CPU_STALL_WAIT : R/W ;bitpos:[5:1] ;default: 5'd1 ; */ /*description: CPU stall wait cycles in fast_clk_rtc*/ #define RTC_CNTL_CPU_STALL_WAIT 0x0000001F From f46bd50884b69c78a8ccf78d273f4156534a5aca Mon Sep 17 00:00:00 2001 From: "Michael (XIAO Xufeng)" Date: Thu, 5 May 2022 03:19:35 +0800 Subject: [PATCH 2/7] pm: putting dbias and pd_cur code into same function --- .../esp_hw_support/port/esp32/rtc_sleep.c | 32 +++++++ .../esp_hw_support/port/esp32c3/rtc_sleep.c | 84 ++++++++++++++----- .../esp_hw_support/port/esp32h2/rtc_sleep.c | 51 ++++++++++- .../esp_hw_support/port/esp32s2/rtc_sleep.c | 76 +++++++++++++---- .../esp_hw_support/port/esp32s3/rtc_sleep.c | 76 +++++++++++++---- components/esp_hw_support/sleep_modes.c | 29 ++++++- components/soc/esp32/include/soc/rtc.h | 49 ++++------- components/soc/esp32c3/include/soc/rtc.h | 57 +++++-------- components/soc/esp32h2/include/soc/rtc.h | 55 +++++------- components/soc/esp32s2/include/soc/rtc.h | 56 +++++-------- components/soc/esp32s3/include/soc/rtc.h | 57 +++++-------- 11 files changed, 391 insertions(+), 231 deletions(-) diff --git a/components/esp_hw_support/port/esp32/rtc_sleep.c b/components/esp_hw_support/port/esp32/rtc_sleep.c index d2efd8b240..b341165c56 100644 --- a/components/esp_hw_support/port/esp32/rtc_sleep.c +++ b/components/esp_hw_support/port/esp32/rtc_sleep.c @@ -84,6 +84,38 @@ static void rtc_sleep_pd(rtc_sleep_pd_config_t cfg) REG_SET_FIELD(FE2_TX_INTERP_CTRL, FE2_TX_INF_FORCE_PU, ~cfg.fe_pd); } +void rtc_sleep_get_default_config(uint32_t sleep_flags, rtc_sleep_config_t *out_config) +{ + *out_config = (rtc_sleep_config_t) { + .lslp_mem_inf_fpu = 0, + .rtc_mem_inf_fpu = 0, + .rtc_mem_inf_follow_cpu = ((sleep_flags) & RTC_SLEEP_PD_RTC_MEM_FOLLOW_CPU) ? 1 : 0, + .rtc_fastmem_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_FAST_MEM) ? 1 : 0, + .rtc_slowmem_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_SLOW_MEM) ? 1 : 0, + .rtc_peri_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_PERIPH) ? 1 : 0, + .wifi_pd_en = 0, + .int_8m_pd_en = ((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? 1 : 0, + .rom_mem_pd_en = 0, + .deep_slp = ((sleep_flags) & RTC_SLEEP_PD_DIG) ? 1 : 0, + .wdt_flashboot_mod_en = 0, + .lslp_meminf_pd = 1, + .vddsdio_pd_en = ((sleep_flags) & RTC_SLEEP_PD_VDDSDIO) ? 1 : 0, + .xtal_fpu = ((sleep_flags) & RTC_SLEEP_PD_XTAL) ? 0 : 1, + }; + + if ((sleep_flags) & RTC_SLEEP_PD_DIG) { + out_config->dig_dbias_wak = RTC_CNTL_DBIAS_1V10; + out_config->dig_dbias_slp = RTC_CNTL_DBIAS_0V90; + out_config->rtc_dbias_wak = RTC_CNTL_DBIAS_1V10; + out_config->rtc_dbias_slp = RTC_CNTL_DBIAS_0V90; + } else { + out_config->dig_dbias_wak = RTC_CNTL_DBIAS_1V10; + out_config->dig_dbias_slp = !((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? RTC_CNTL_DBIAS_1V10 : RTC_CNTL_DBIAS_0V90; + out_config->rtc_dbias_wak = RTC_CNTL_DBIAS_1V10; + out_config->rtc_dbias_slp = !((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? RTC_CNTL_DBIAS_1V10 : RTC_CNTL_DBIAS_0V90; + } +} + void rtc_sleep_init(rtc_sleep_config_t cfg) { // set shortest possible sleep time limit diff --git a/components/esp_hw_support/port/esp32c3/rtc_sleep.c b/components/esp_hw_support/port/esp32c3/rtc_sleep.c index 899091d02b..d9549b0b49 100644 --- a/components/esp_hw_support/port/esp32c3/rtc_sleep.c +++ b/components/esp_hw_support/port/esp32c3/rtc_sleep.c @@ -53,6 +53,61 @@ void rtc_sleep_pu(rtc_sleep_pu_config_t cfg) } } +void rtc_sleep_get_default_config(uint32_t sleep_flags, rtc_sleep_config_t *out_config) +{ + *out_config = (rtc_sleep_config_t) { + .lslp_mem_inf_fpu = 0, + .rtc_mem_inf_follow_cpu = (sleep_flags & RTC_SLEEP_PD_RTC_MEM_FOLLOW_CPU) ? 1 : 0, + .rtc_fastmem_pd_en = (sleep_flags & RTC_SLEEP_PD_RTC_FAST_MEM) ? 1 : 0, + .rtc_slowmem_pd_en = (sleep_flags & RTC_SLEEP_PD_RTC_SLOW_MEM) ? 1 : 0, + .rtc_peri_pd_en = (sleep_flags & RTC_SLEEP_PD_RTC_PERIPH) ? 1 : 0, + .wifi_pd_en = (sleep_flags & RTC_SLEEP_PD_WIFI) ? 1 : 0, + .bt_pd_en = (sleep_flags & RTC_SLEEP_PD_BT) ? 1 : 0, + .cpu_pd_en = (sleep_flags & RTC_SLEEP_PD_CPU) ? 1 : 0, + .int_8m_pd_en = (sleep_flags & RTC_SLEEP_PD_INT_8M) ? 1 : 0, + .dig_peri_pd_en = (sleep_flags & RTC_SLEEP_PD_DIG_PERIPH) ? 1 : 0, + .deep_slp = (sleep_flags & RTC_SLEEP_PD_DIG) ? 1 : 0, + .wdt_flashboot_mod_en = 0, + .vddsdio_pd_en = (sleep_flags & RTC_SLEEP_PD_VDDSDIO) ? 1 : 0, + .xtal_fpu = (sleep_flags & RTC_SLEEP_PD_XTAL) ? 0 : 1, + .deep_slp_reject = 1, + .light_slp_reject = 1 + }; + + if (sleep_flags & RTC_SLEEP_PD_DIG) { + unsigned atten_deep_sleep = RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT; +#if CONFIG_ESP32C3_REV_MIN < 3 + if (esp_efuse_get_chip_ver() < 3) { + atten_deep_sleep = 0; /* workaround for deep sleep issue in high temp on ECO2 and below */ + } +#endif + + out_config->dig_dbias_wak = RTC_CNTL_DBIAS_1V10; + out_config->dig_dbias_slp = RTC_CNTL_DBIAS_SLP; + out_config->rtc_dbias_wak = RTC_CNTL_DBIAS_1V10; + out_config->rtc_dbias_slp = RTC_CNTL_DBIAS_SLP; + + out_config->dbg_atten_monitor = RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT; + out_config->bias_sleep_monitor = RTC_CNTL_BIASSLP_MONITOR_DEFAULT; + out_config->dbg_atten_slp = atten_deep_sleep; + out_config->bias_sleep_slp = RTC_CNTL_BIASSLP_SLEEP_DEFAULT; + out_config->pd_cur_monitor = RTC_CNTL_PD_CUR_MONITOR_DEFAULT; + out_config->pd_cur_slp = RTC_CNTL_PD_CUR_SLEEP_DEFAULT; + } else { + out_config->dig_dbias_wak = RTC_CNTL_DBIAS_1V10; + out_config->dig_dbias_slp = !(sleep_flags & RTC_SLEEP_PD_INT_8M) ? RTC_CNTL_DBIAS_1V10 : RTC_CNTL_DBIAS_SLP; + out_config->rtc_dbias_wak = RTC_CNTL_DBIAS_1V10; + out_config->rtc_dbias_slp = !(sleep_flags & RTC_SLEEP_PD_INT_8M) ? RTC_CNTL_DBIAS_1V10 : RTC_CNTL_DBIAS_SLP; + + out_config->dbg_atten_monitor = RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT; + out_config->bias_sleep_monitor = RTC_CNTL_BIASSLP_MONITOR_DEFAULT; + out_config->dbg_atten_slp = (sleep_flags & RTC_SLEEP_PD_INT_8M) ? RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT : RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_NODROP; + out_config->bias_sleep_slp = !(sleep_flags & RTC_SLEEP_PD_XTAL) ? RTC_CNTL_BIASSLP_SLEEP_ON : RTC_CNTL_BIASSLP_SLEEP_DEFAULT; + out_config->pd_cur_monitor = RTC_CNTL_PD_CUR_MONITOR_DEFAULT; + out_config->pd_cur_slp = !(sleep_flags & RTC_SLEEP_PD_XTAL) ? RTC_CNTL_PD_CUR_SLEEP_ON : RTC_CNTL_PD_CUR_SLEEP_DEFAULT; + } +} + void rtc_sleep_init(rtc_sleep_config_t cfg) { if (cfg.lslp_mem_inf_fpu) { @@ -82,23 +137,19 @@ void rtc_sleep_init(rtc_sleep_config_t cfg) CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_PERI_PD_EN); } - REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN_MONITOR, RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT); - REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_BIAS_SLEEP_MONITOR, RTC_CNTL_BIASSLP_MONITOR_DEFAULT); - REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_BIAS_SLEEP_DEEP_SLP, - (!cfg.deep_slp && cfg.xtal_fpu) ? RTC_CNTL_BIASSLP_SLEEP_ON : RTC_CNTL_BIASSLP_SLEEP_DEFAULT); - REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_PD_CUR_MONITOR, RTC_CNTL_PD_CUR_MONITOR_DEFAULT); - REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_PD_CUR_DEEP_SLP, - (!cfg.deep_slp && cfg.xtal_fpu) ? RTC_CNTL_PD_CUR_SLEEP_ON : RTC_CNTL_PD_CUR_SLEEP_DEFAULT); + REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG_SLEEP, cfg.rtc_dbias_slp); + REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG_SLEEP, cfg.dig_dbias_slp); + + REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN_MONITOR, cfg.dbg_atten_monitor); + REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_BIAS_SLEEP_MONITOR, cfg.bias_sleep_monitor); + REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN_DEEP_SLP, cfg.dbg_atten_slp); + REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_BIAS_SLEEP_DEEP_SLP, cfg.bias_sleep_slp); + REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_PD_CUR_MONITOR, cfg.pd_cur_monitor); + REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_PD_CUR_DEEP_SLP, cfg.pd_cur_slp); + if (cfg.deep_slp) { REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_FORCE_XPD_CK, 0); CLEAR_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU); - unsigned atten_deep_sleep = RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT; - #if CONFIG_ESP32C3_REV_MIN < 3 - if (esp_efuse_get_chip_ver() < 3) { - atten_deep_sleep = 0; /* workaround for deep sleep issue in high temp on ECO2 and below */ - } - #endif - REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN_DEEP_SLP, atten_deep_sleep); SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_PD_EN); CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_CKGEN_I2C_PU | RTC_CNTL_PLL_I2C_PU | @@ -109,8 +160,6 @@ void rtc_sleep_init(rtc_sleep_config_t cfg) REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DG_VDD_DRV_B_SLP, RTC_CNTL_DG_VDD_DRV_B_SLP_DEFAULT); SET_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU); CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_PD_EN); - REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN_DEEP_SLP, - cfg.int_8m_pd_en ? RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT : RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_NODROP); } if (!cfg.int_8m_pd_en) { @@ -125,9 +174,6 @@ void rtc_sleep_init(rtc_sleep_config_t cfg) REG_CLR_BIT(RTC_CNTL_SDIO_CONF_REG, RTC_CNTL_SDIO_FORCE); REG_SET_FIELD(RTC_CNTL_SDIO_CONF_REG, RTC_CNTL_SDIO_PD_EN, cfg.vddsdio_pd_en); - REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG_SLEEP, cfg.rtc_dbias_slp); - REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG_SLEEP, cfg.dig_dbias_slp); - REG_SET_FIELD(RTC_CNTL_SLP_REJECT_CONF_REG, RTC_CNTL_DEEP_SLP_REJECT_EN, cfg.deep_slp_reject); REG_SET_FIELD(RTC_CNTL_SLP_REJECT_CONF_REG, RTC_CNTL_LIGHT_SLP_REJECT_EN, cfg.light_slp_reject); diff --git a/components/esp_hw_support/port/esp32h2/rtc_sleep.c b/components/esp_hw_support/port/esp32h2/rtc_sleep.c index f8f515286d..108e12296f 100644 --- a/components/esp_hw_support/port/esp32h2/rtc_sleep.c +++ b/components/esp_hw_support/port/esp32h2/rtc_sleep.c @@ -154,6 +154,49 @@ void rtc_sleep_pmu_init(void) left_up_trx_fpu(0); } +void rtc_sleep_get_default_config(uint32_t sleep_flags, rtc_sleep_config_t *out_config) +{ + *out_config = (rtc_sleep_config_t) { + .lslp_mem_inf_fpu = 0, + .rtc_mem_inf_follow_cpu = ((sleep_flags) & RTC_SLEEP_PD_RTC_MEM_FOLLOW_CPU) ? 1 : 0, + .rtc_fastmem_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_FAST_MEM) ? 1 : 0, + .rtc_slowmem_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_SLOW_MEM) ? 1 : 0, + .rtc_peri_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_PERIPH) ? 1 : 0, + .dig_ret_pd_en = ((sleep_flags) & RTC_SLEEP_PD_DIG_RET) ? 1 : 0, + .bt_pd_en = ((sleep_flags) & RTC_SLEEP_PD_BT) ? 1 : 0, + .cpu_pd_en = ((sleep_flags) & RTC_SLEEP_PD_CPU) ? 1 : 0, + .int_8m_pd_en = ((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? 1 : 0, + .dig_peri_pd_en = ((sleep_flags) & RTC_SLEEP_PD_DIG_PERIPH) ? 1 : 0, + .deep_slp = ((sleep_flags) & RTC_SLEEP_PD_DIG) ? 1 : 0, + .wdt_flashboot_mod_en = 0, + .vddsdio_pd_en = ((sleep_flags) & RTC_SLEEP_PD_VDDSDIO) ? 1 : 0, + .xtal_fpu = ((sleep_flags) & RTC_SLEEP_PD_XTAL) ? 0 : 1, + .deep_slp_reject = 1, + .light_slp_reject = 1 + }; + + if ((sleep_flags) & RTC_SLEEP_PD_DIG) { + out_config->dig_dbias_wak = RTC_CNTL_DBIAS_1V10; + out_config->dig_dbias_slp = RTC_CNTL_DBIAS_SLP; + out_config->rtc_dbias_wak = RTC_CNTL_DBIAS_1V10; + out_config->rtc_dbias_slp = RTC_CNTL_DBIAS_SLP; + + out_config->bias_sleep_monitor = RTC_CNTL_BIASSLP_MONITOR_DEFAULT; + out_config->bias_sleep_slp = RTC_CNTL_BIASSLP_SLEEP_DEFAULT; + out_config->pd_cur_monitor = RTC_CNTL_PD_CUR_MONITOR_DEFAULT; + out_config->pd_cur_slp = RTC_CNTL_PD_CUR_SLEEP_DEFAULT; + } else { + out_config->dig_dbias_wak = RTC_CNTL_DBIAS_1V10; + out_config->dig_dbias_slp = !((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? RTC_CNTL_DBIAS_1V10 : RTC_CNTL_DBIAS_SLP; + out_config->rtc_dbias_wak = RTC_CNTL_DBIAS_1V10; + out_config->rtc_dbias_slp = !((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? RTC_CNTL_DBIAS_1V10 : RTC_CNTL_DBIAS_SLP; + + out_config->bias_sleep_monitor = RTC_CNTL_BIASSLP_MONITOR_DEFAULT; + out_config->bias_sleep_slp = RTC_CNTL_BIASSLP_SLEEP_DEFAULT; + out_config->pd_cur_monitor = RTC_CNTL_PD_CUR_MONITOR_DEFAULT; + out_config->pd_cur_slp = RTC_CNTL_PD_CUR_SLEEP_DEFAULT; + } +} void rtc_sleep_init(rtc_sleep_config_t cfg) { @@ -182,10 +225,10 @@ void rtc_sleep_init(rtc_sleep_config_t cfg) CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_RET_PD_EN); } - REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_BIAS_SLEEP_MONITOR, RTC_CNTL_BIASSLP_MONITOR_DEFAULT); - REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_BIAS_SLEEP_DEEP_SLP, RTC_CNTL_BIASSLP_SLEEP_DEFAULT); - REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_PD_CUR_MONITOR, RTC_CNTL_PD_CUR_MONITOR_DEFAULT); - REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_PD_CUR_DEEP_SLP, RTC_CNTL_PD_CUR_SLEEP_DEFAULT); + REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_BIAS_SLEEP_MONITOR, cfg.bias_sleep_monitor); + REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_BIAS_SLEEP_DEEP_SLP, cfg.bias_sleep_slp); + REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_PD_CUR_MONITOR, cfg.pd_cur_monitor); + REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_PD_CUR_DEEP_SLP, cfg.pd_cur_slp); // ESP32-H2 TO-DO: IDF-3693 if (cfg.deep_slp) { // REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_FORCE_XPD_CK, 0); diff --git a/components/esp_hw_support/port/esp32s2/rtc_sleep.c b/components/esp_hw_support/port/esp32s2/rtc_sleep.c index 5fc5417eb6..cf587fa38e 100644 --- a/components/esp_hw_support/port/esp32s2/rtc_sleep.c +++ b/components/esp_hw_support/port/esp32s2/rtc_sleep.c @@ -44,6 +44,55 @@ void rtc_sleep_pd(rtc_sleep_pd_config_t cfg) REG_SET_FIELD(FE2_TX_INTERP_CTRL, FE2_TX_INF_FORCE_PU, cfg.fe_fpu); } +void rtc_sleep_get_default_config(uint32_t sleep_flags, rtc_sleep_config_t *out_config) +{ + *out_config = (rtc_sleep_config_t) { + .lslp_mem_inf_fpu = 0, + .rtc_mem_inf_follow_cpu = (sleep_flags & RTC_SLEEP_PD_RTC_MEM_FOLLOW_CPU) ? 1 : 0, + .rtc_fastmem_pd_en = (sleep_flags & RTC_SLEEP_PD_RTC_FAST_MEM) ? 1 : 0, + .rtc_slowmem_pd_en = (sleep_flags & RTC_SLEEP_PD_RTC_SLOW_MEM) ? 1 : 0, + .rtc_peri_pd_en = (sleep_flags & RTC_SLEEP_PD_RTC_PERIPH) ? 1 : 0, + .wifi_pd_en = (sleep_flags & RTC_SLEEP_PD_WIFI) ? 1 : 0, + .int_8m_pd_en = (sleep_flags & RTC_SLEEP_PD_INT_8M) ? 1 : 0, + .deep_slp = (sleep_flags & RTC_SLEEP_PD_DIG) ? 1 : 0, + .wdt_flashboot_mod_en = 0, + .vddsdio_pd_en = (sleep_flags & RTC_SLEEP_PD_VDDSDIO) ? 1 : 0, + .xtal_fpu = (sleep_flags & RTC_SLEEP_PD_XTAL) ? 0 : 1, + .deep_slp_reject = 1, + .light_slp_reject = 1 + }; + + if (sleep_flags & RTC_SLEEP_PD_DIG) { + out_config->dig_dbias_wak = RTC_CNTL_DIG_DBIAS_1V10; + out_config->dig_dbias_slp = RTC_CNTL_DIG_DBIAS_0V90; + out_config->rtc_dbias_wak = RTC_CNTL_DBIAS_1V10; + out_config->rtc_dbias_slp = RTC_CNTL_DBIAS_1V00; + + out_config->dbg_atten_monitor = RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT; + out_config->bias_sleep_monitor = RTC_CNTL_BIASSLP_MONITOR_DEFAULT; + out_config->dbg_atten_slp = RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT; + out_config->bias_sleep_slp = RTC_CNTL_BIASSLP_SLEEP_DEFAULT; + out_config->pd_cur_monitor = RTC_CNTL_PD_CUR_MONITOR_DEFAULT; + out_config->pd_cur_slp = RTC_CNTL_PD_CUR_SLEEP_DEFAULT; + } else { + out_config->dig_dbias_wak = RTC_CNTL_DIG_DBIAS_1V10; + out_config->dig_dbias_slp = !(sleep_flags & RTC_SLEEP_PD_INT_8M) ? RTC_CNTL_DIG_DBIAS_1V10 + : !(sleep_flags & RTC_SLEEP_PD_XTAL) ? RTC_CNTL_DIG_DBIAS_1V10 + : RTC_CNTL_DIG_DBIAS_0V90; + out_config->rtc_dbias_wak = RTC_CNTL_DBIAS_1V10; + out_config->rtc_dbias_slp = !(sleep_flags & RTC_SLEEP_PD_INT_8M) ? RTC_CNTL_DBIAS_1V10 + : !(sleep_flags & RTC_SLEEP_PD_XTAL) ? RTC_CNTL_DBIAS_1V10 + : RTC_CNTL_DBIAS_1V00; + + out_config->dbg_atten_monitor = RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT; + out_config->bias_sleep_monitor = RTC_CNTL_BIASSLP_MONITOR_DEFAULT; + out_config->dbg_atten_slp = (sleep_flags & RTC_SLEEP_PD_INT_8M) ? RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT : RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_NODROP; + out_config->bias_sleep_slp = !(sleep_flags & RTC_SLEEP_PD_XTAL) ? RTC_CNTL_BIASSLP_SLEEP_ON : RTC_CNTL_BIASSLP_SLEEP_DEFAULT; + out_config->pd_cur_monitor = RTC_CNTL_PD_CUR_MONITOR_DEFAULT; + out_config->pd_cur_slp = !(sleep_flags & RTC_SLEEP_PD_XTAL) ? RTC_CNTL_PD_CUR_SLEEP_ON : RTC_CNTL_PD_CUR_SLEEP_DEFAULT; + } +} + void rtc_sleep_init(rtc_sleep_config_t cfg) { if (cfg.lslp_mem_inf_fpu) { @@ -89,16 +138,20 @@ void rtc_sleep_init(rtc_sleep_config_t cfg) CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_PD_EN); } - REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN_MONITOR, RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT); - REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_BIAS_SLEEP_MONITOR, RTC_CNTL_BIASSLP_MONITOR_DEFAULT); - REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_BIAS_SLEEP_DEEP_SLP, - (!cfg.deep_slp && cfg.xtal_fpu) ? RTC_CNTL_BIASSLP_SLEEP_ON : RTC_CNTL_BIASSLP_SLEEP_DEFAULT); - REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_PD_CUR_MONITOR, RTC_CNTL_PD_CUR_MONITOR_DEFAULT); - REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_PD_CUR_DEEP_SLP, - (!cfg.deep_slp && cfg.xtal_fpu) ? RTC_CNTL_PD_CUR_SLEEP_ON : RTC_CNTL_PD_CUR_SLEEP_DEFAULT); + REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DBIAS_SLP, cfg.rtc_dbias_slp); + REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DBIAS_WAK, cfg.rtc_dbias_wak); + REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, cfg.dig_dbias_wak); + REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_SLP, cfg.dig_dbias_slp); + + REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN_MONITOR, cfg.dbg_atten_monitor); + REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_BIAS_SLEEP_MONITOR, cfg.bias_sleep_monitor); + REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_BIAS_SLEEP_DEEP_SLP, cfg.bias_sleep_slp); + REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_PD_CUR_MONITOR, cfg.pd_cur_monitor); + REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_PD_CUR_DEEP_SLP, cfg.pd_cur_slp); + REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN_DEEP_SLP, cfg.dbg_atten_slp); + if (cfg.deep_slp) { CLEAR_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU); - REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN_DEEP_SLP, RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT); SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_PD_EN); CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_CKGEN_I2C_PU | RTC_CNTL_PLL_I2C_PU | @@ -107,8 +160,6 @@ void rtc_sleep_init(rtc_sleep_config_t cfg) } else { SET_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU); CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_PD_EN); - REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN_DEEP_SLP, - cfg.int_8m_pd_en ? RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT : RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_NODROP); } if (!cfg.int_8m_pd_en) { @@ -121,11 +172,6 @@ void rtc_sleep_init(rtc_sleep_config_t cfg) REG_CLR_BIT(RTC_CNTL_SDIO_CONF_REG, RTC_CNTL_SDIO_FORCE); REG_SET_FIELD(RTC_CNTL_SDIO_CONF_REG, RTC_CNTL_SDIO_PD_EN, cfg.vddsdio_pd_en); - REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DBIAS_SLP, cfg.rtc_dbias_slp); - REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DBIAS_WAK, cfg.rtc_dbias_wak); - REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, cfg.dig_dbias_wak); - REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_SLP, cfg.dig_dbias_slp); - REG_SET_FIELD(RTC_CNTL_SLP_REJECT_CONF_REG, RTC_CNTL_DEEP_SLP_REJECT_EN, cfg.deep_slp_reject); REG_SET_FIELD(RTC_CNTL_SLP_REJECT_CONF_REG, RTC_CNTL_LIGHT_SLP_REJECT_EN, cfg.light_slp_reject); /* Set wait cycle for touch or COCPU after deep sleep and light sleep. */ diff --git a/components/esp_hw_support/port/esp32s3/rtc_sleep.c b/components/esp_hw_support/port/esp32s3/rtc_sleep.c index cd7a0baefa..4df230e6d7 100644 --- a/components/esp_hw_support/port/esp32s3/rtc_sleep.c +++ b/components/esp_hw_support/port/esp32s3/rtc_sleep.c @@ -53,6 +53,54 @@ void rtc_sleep_pu(rtc_sleep_pu_config_t cfg) } } +void rtc_sleep_get_default_config(uint32_t sleep_flags, rtc_sleep_config_t *out_config) +{ + *out_config = (rtc_sleep_config_t) { + .lslp_mem_inf_fpu = 0, + .rtc_mem_inf_follow_cpu = (sleep_flags & RTC_SLEEP_PD_RTC_MEM_FOLLOW_CPU) ? 1 : 0, + .rtc_fastmem_pd_en = (sleep_flags & RTC_SLEEP_PD_RTC_FAST_MEM) ? 1 : 0, + .rtc_slowmem_pd_en = (sleep_flags & RTC_SLEEP_PD_RTC_SLOW_MEM) ? 1 : 0, + .rtc_peri_pd_en = (sleep_flags & RTC_SLEEP_PD_RTC_PERIPH) ? 1 : 0, + .wifi_pd_en = (sleep_flags & RTC_SLEEP_PD_WIFI) ? 1 : 0, + .bt_pd_en = (sleep_flags & RTC_SLEEP_PD_BT) ? 1 : 0, + .cpu_pd_en = (sleep_flags & RTC_SLEEP_PD_CPU) ? 1 : 0, + .int_8m_pd_en = (sleep_flags & RTC_SLEEP_PD_INT_8M) ? 1 : 0, + .dig_peri_pd_en = (sleep_flags & RTC_SLEEP_PD_DIG_PERIPH) ? 1 : 0, + .deep_slp = (sleep_flags & RTC_SLEEP_PD_DIG) ? 1 : 0, + .wdt_flashboot_mod_en = 0, + .vddsdio_pd_en = (sleep_flags & RTC_SLEEP_PD_VDDSDIO) ? 1 : 0, + .xtal_fpu = (sleep_flags & RTC_SLEEP_PD_XTAL) ? 0 : 1, + .deep_slp_reject = 1, + .light_slp_reject = 1 + }; + + if (sleep_flags & RTC_SLEEP_PD_DIG) { + out_config->dig_dbias_wak = RTC_CNTL_DBIAS_1V10; + out_config->dig_dbias_slp = RTC_CNTL_DBIAS_SLP; + out_config->rtc_dbias_wak = RTC_CNTL_DBIAS_1V10; + out_config->rtc_dbias_slp = RTC_CNTL_DBIAS_SLP; + + out_config->dbg_atten_monitor = RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT; + out_config->bias_sleep_monitor = RTC_CNTL_BIASSLP_MONITOR_DEFAULT; + out_config->dbg_atten_slp = RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT; + out_config->bias_sleep_slp = RTC_CNTL_BIASSLP_SLEEP_DEFAULT; + out_config->pd_cur_monitor = RTC_CNTL_PD_CUR_MONITOR_DEFAULT; + out_config->pd_cur_slp = RTC_CNTL_PD_CUR_SLEEP_DEFAULT; + } else { + out_config->dig_dbias_wak = RTC_CNTL_DBIAS_1V10; + out_config->dig_dbias_slp = !(sleep_flags & RTC_SLEEP_PD_INT_8M) ? RTC_CNTL_DBIAS_1V10 : RTC_CNTL_DBIAS_SLP; + out_config->rtc_dbias_wak = RTC_CNTL_DBIAS_1V10; + out_config->rtc_dbias_slp = !(sleep_flags & RTC_SLEEP_PD_INT_8M) ? RTC_CNTL_DBIAS_1V10 : RTC_CNTL_DBIAS_SLP; + + out_config->dbg_atten_monitor = RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT; + out_config->bias_sleep_monitor = RTC_CNTL_BIASSLP_MONITOR_DEFAULT; + out_config->dbg_atten_slp = (sleep_flags & RTC_SLEEP_PD_INT_8M) ? RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT : RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_NODROP; + out_config->bias_sleep_slp = !(sleep_flags & RTC_SLEEP_PD_XTAL) ? RTC_CNTL_BIASSLP_SLEEP_ON : RTC_CNTL_BIASSLP_SLEEP_DEFAULT; + out_config->pd_cur_monitor = RTC_CNTL_PD_CUR_MONITOR_DEFAULT; + out_config->pd_cur_slp = !(sleep_flags & RTC_SLEEP_PD_XTAL) ? RTC_CNTL_PD_CUR_SLEEP_ON : RTC_CNTL_PD_CUR_SLEEP_DEFAULT; + } +} + void rtc_sleep_init(rtc_sleep_config_t cfg) { if (cfg.lslp_mem_inf_fpu) { @@ -95,16 +143,21 @@ void rtc_sleep_init(rtc_sleep_config_t cfg) } else { CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_PD_EN); } - REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN_MONITOR, RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT); - REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_BIAS_SLEEP_MONITOR, RTC_CNTL_BIASSLP_MONITOR_DEFAULT); - REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_BIAS_SLEEP_DEEP_SLP, - (!cfg.deep_slp && cfg.xtal_fpu) ? RTC_CNTL_BIASSLP_SLEEP_ON : RTC_CNTL_BIASSLP_SLEEP_DEFAULT); - REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_PD_CUR_MONITOR, RTC_CNTL_PD_CUR_MONITOR_DEFAULT); - REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_PD_CUR_DEEP_SLP, - (!cfg.deep_slp && cfg.xtal_fpu) ? RTC_CNTL_PD_CUR_SLEEP_ON : RTC_CNTL_PD_CUR_SLEEP_DEFAULT); + + REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG_SLEEP, cfg.rtc_dbias_slp); + REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG, cfg.rtc_dbias_wak); + REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG_SLEEP, cfg.dig_dbias_slp); + REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG, cfg.dig_dbias_wak); + + REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN_MONITOR, cfg.dbg_atten_monitor); + REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_BIAS_SLEEP_MONITOR, cfg.bias_sleep_monitor); + REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN_DEEP_SLP, cfg.dbg_atten_slp); + REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_BIAS_SLEEP_DEEP_SLP, cfg.bias_sleep_slp); + REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_PD_CUR_MONITOR, cfg.pd_cur_monitor); + REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_PD_CUR_DEEP_SLP, cfg.pd_cur_slp); + if (cfg.deep_slp) { CLEAR_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU); - REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN_DEEP_SLP, RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT); SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_PD_EN); CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_CKGEN_I2C_PU | RTC_CNTL_PLL_I2C_PU | @@ -114,8 +167,6 @@ void rtc_sleep_init(rtc_sleep_config_t cfg) REG_SET_FIELD(RTC_CNTL_REGULATOR_DRV_CTRL_REG, RTC_CNTL_DG_VDD_DRV_B_SLP, RTC_CNTL_DG_VDD_DRV_B_SLP_DEFAULT); SET_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU); CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_PD_EN); - REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN_DEEP_SLP, - cfg.int_8m_pd_en ? RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT : RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_NODROP); } /* mem pd */ CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_LSLP_MEM_FORCE_PU); @@ -130,11 +181,6 @@ void rtc_sleep_init(rtc_sleep_config_t cfg) REG_CLR_BIT(RTC_CNTL_SDIO_CONF_REG, RTC_CNTL_SDIO_FORCE); REG_SET_FIELD(RTC_CNTL_SDIO_CONF_REG, RTC_CNTL_SDIO_PD_EN, cfg.vddsdio_pd_en); - REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG_SLEEP, cfg.rtc_dbias_slp); - REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG, cfg.rtc_dbias_wak); - REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG_SLEEP, cfg.dig_dbias_slp); - REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG, cfg.dig_dbias_wak); - REG_SET_FIELD(RTC_CNTL_SLP_REJECT_CONF_REG, RTC_CNTL_DEEP_SLP_REJECT_EN, cfg.deep_slp_reject); REG_SET_FIELD(RTC_CNTL_SLP_REJECT_CONF_REG, RTC_CNTL_LIGHT_SLP_REJECT_EN, cfg.light_slp_reject); diff --git a/components/esp_hw_support/sleep_modes.c b/components/esp_hw_support/sleep_modes.c index e3bfbfffaa..b5a8120674 100644 --- a/components/esp_hw_support/sleep_modes.c +++ b/components/esp_hw_support/sleep_modes.c @@ -178,6 +178,10 @@ static bool s_light_sleep_wakeup = false; static portMUX_TYPE spinlock_rtc_deep_sleep = portMUX_INITIALIZER_UNLOCKED; static const char *TAG = "sleep"; +static bool s_adc_tsen_enabled = false; +//in this mode, 2uA is saved, but RTC memory can't use at high temperature, and RTCIO can't be used as INPUT. +static bool s_ultra_low_enabled = false; + static uint32_t get_power_down_flags(void); #if SOC_PM_SUPPORT_EXT_WAKEUP @@ -462,8 +466,21 @@ static uint32_t IRAM_ATTR esp_sleep_start(uint32_t pd_flags) #endif } + //Append some flags in addition to power domains + uint32_t sleep_flags = pd_flags; + if (s_adc_tsen_enabled) { + sleep_flags |= RTC_SLEEP_USE_ADC_TESEN_MONITOR; + } + if (!s_ultra_low_enabled) { + sleep_flags |= RTC_SLEEP_NO_ULTRA_LOW; + } + if (rtc_dig_8m_enabled()) { + sleep_flags |= RTC_SLEEP_DIG_USE_8M; + } + // Enter sleep - rtc_sleep_config_t config = RTC_SLEEP_CONFIG_DEFAULT(pd_flags); + rtc_sleep_config_t config; + rtc_sleep_get_default_config(sleep_flags, &config); rtc_sleep_init(config); // Set state machine time for light sleep @@ -1330,3 +1347,13 @@ void esp_deep_sleep_disable_rom_logging(void) { rtc_suppress_rom_log(); } + +void rtc_sleep_enable_adc_tesn_monitor(bool enable) +{ + s_adc_tsen_enabled = enable; +} + +void rtc_sleep_enable_ultra_low(bool enable) +{ + s_ultra_low_enabled = enable; +} diff --git a/components/soc/esp32/include/soc/rtc.h b/components/soc/esp32/include/soc/rtc.h index f163d2b98c..b336cb2a7d 100644 --- a/components/soc/esp32/include/soc/rtc.h +++ b/components/soc/esp32/include/soc/rtc.h @@ -511,40 +511,6 @@ typedef struct rtc_sleep_config_s { uint32_t xtal_fpu : 1; //!< keep main XTAL powered up in sleep } rtc_sleep_config_t; -/** - * Default initializer for rtc_sleep_config_t - * - * This initializer sets all fields to "reasonable" values (e.g. suggested for - * production use) based on a combination of RTC_SLEEP_PD_x flags. - * - * @param RTC_SLEEP_PD_x flags combined using bitwise OR - */ -#define is_dslp(pd_flags) ((pd_flags) & RTC_SLEEP_PD_DIG) -#define RTC_SLEEP_CONFIG_DEFAULT(sleep_flags) { \ - .lslp_mem_inf_fpu = 0, \ - .rtc_mem_inf_fpu = 0, \ - .rtc_mem_inf_follow_cpu = ((sleep_flags) & RTC_SLEEP_PD_RTC_MEM_FOLLOW_CPU) ? 1 : 0, \ - .rtc_fastmem_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_FAST_MEM) ? 1 : 0, \ - .rtc_slowmem_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_SLOW_MEM) ? 1 : 0, \ - .rtc_peri_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_PERIPH) ? 1 : 0, \ - .wifi_pd_en = 0, \ - .int_8m_pd_en = ((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? 1 : 0, \ - .rom_mem_pd_en = 0, \ - .deep_slp = ((sleep_flags) & RTC_SLEEP_PD_DIG) ? 1 : 0, \ - .wdt_flashboot_mod_en = 0, \ - .dig_dbias_wak = RTC_CNTL_DBIAS_1V10, \ - .dig_dbias_slp = is_dslp(sleep_flags) ? RTC_CNTL_DBIAS_0V90 \ - : !((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? RTC_CNTL_DBIAS_1V10 \ - : RTC_CNTL_DBIAS_0V90, \ - .rtc_dbias_wak = RTC_CNTL_DBIAS_1V10, \ - .rtc_dbias_slp = is_dslp(sleep_flags) ? RTC_CNTL_DBIAS_0V90 \ - : !((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? RTC_CNTL_DBIAS_1V10 \ - : RTC_CNTL_DBIAS_0V90, \ - .lslp_meminf_pd = 1, \ - .vddsdio_pd_en = ((sleep_flags) & RTC_SLEEP_PD_VDDSDIO) ? 1 : 0, \ - .xtal_fpu = ((sleep_flags) & RTC_SLEEP_PD_XTAL) ? 0 : 1 \ -}; - #define RTC_SLEEP_PD_DIG BIT(0) //!< Deep sleep (power down digital domain) #define RTC_SLEEP_PD_RTC_PERIPH BIT(1) //!< Power down RTC peripherals #define RTC_SLEEP_PD_RTC_SLOW_MEM BIT(2) //!< Power down RTC SLOW memory @@ -554,6 +520,21 @@ typedef struct rtc_sleep_config_s { #define RTC_SLEEP_PD_XTAL BIT(6) //!< Power down main XTAL #define RTC_SLEEP_PD_INT_8M BIT(7) //!< Power down Internal 8M oscillator +//These flags are not power domains, but will affect some sleep parameters +#define RTC_SLEEP_DIG_USE_8M BIT(16) +#define RTC_SLEEP_USE_ADC_TESEN_MONITOR BIT(17) +#define RTC_SLEEP_NO_ULTRA_LOW BIT(18) //!< Avoid using ultra low power in deep sleep, in which RTCIO cannot be used as input, and RTCMEM can't work under high temperature + +/** + * Default initializer for rtc_sleep_config_t + * + * This initializer sets all fields to "reasonable" values (e.g. suggested for + * production use) based on a combination of RTC_SLEEP_PD_x flags. + * + * @param RTC_SLEEP_PD_x flags combined using bitwise OR + */ +void rtc_sleep_get_default_config(uint32_t sleep_flags, rtc_sleep_config_t *out_config); + /* Various delays to be programmed into power control state machines */ #define RTC_CNTL_XTL_BUF_WAIT_SLP_US (500) #define RTC_CNTL_PLL_BUF_WAIT_SLP_CYCLES (1) diff --git a/components/soc/esp32c3/include/soc/rtc.h b/components/soc/esp32c3/include/soc/rtc.h index 0eea13ad74..5222da63ad 100644 --- a/components/soc/esp32c3/include/soc/rtc.h +++ b/components/soc/esp32c3/include/soc/rtc.h @@ -647,48 +647,18 @@ typedef struct { uint32_t dig_dbias_slp : 5; //!< set bias for digital domain, in sleep mode uint32_t rtc_dbias_wak : 5; //!< set bias for RTC domain, in active mode uint32_t rtc_dbias_slp : 5; //!< set bias for RTC domain, in sleep mode + uint32_t dbg_atten_monitor : 4; //!< voltage parameter, in monitor mode + uint32_t bias_sleep_monitor : 1; //!< circuit control parameter, in monitor mode + uint32_t dbg_atten_slp : 4; //!< voltage parameter, in sleep mode + uint32_t bias_sleep_slp : 1; //!< circuit control parameter, in sleep mode + uint32_t pd_cur_monitor : 1; //!< circuit control parameter, in monitor mode + uint32_t pd_cur_slp : 1; //!< circuit control parameter, in sleep mode uint32_t vddsdio_pd_en : 1; //!< power down VDDSDIO regulator uint32_t xtal_fpu : 1; //!< keep main XTAL powered up in sleep uint32_t deep_slp_reject : 1; uint32_t light_slp_reject : 1; } rtc_sleep_config_t; -/** - * Default initializer for rtc_sleep_config_t - * - * This initializer sets all fields to "reasonable" values (e.g. suggested for - * production use) based on a combination of RTC_SLEEP_PD_x flags. - * - * @param RTC_SLEEP_PD_x flags combined using bitwise OR - */ -#define is_dslp(pd_flags) ((pd_flags) & RTC_SLEEP_PD_DIG) -#define RTC_SLEEP_CONFIG_DEFAULT(sleep_flags) { \ - .lslp_mem_inf_fpu = 0, \ - .rtc_mem_inf_follow_cpu = ((sleep_flags) & RTC_SLEEP_PD_RTC_MEM_FOLLOW_CPU) ? 1 : 0, \ - .rtc_fastmem_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_FAST_MEM) ? 1 : 0, \ - .rtc_slowmem_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_SLOW_MEM) ? 1 : 0, \ - .rtc_peri_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_PERIPH) ? 1 : 0, \ - .wifi_pd_en = ((sleep_flags) & RTC_SLEEP_PD_WIFI) ? 1 : 0, \ - .bt_pd_en = ((sleep_flags) & RTC_SLEEP_PD_BT) ? 1 : 0, \ - .cpu_pd_en = ((sleep_flags) & RTC_SLEEP_PD_CPU) ? 1 : 0, \ - .int_8m_pd_en = ((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? 1 : 0, \ - .dig_peri_pd_en = ((sleep_flags) & RTC_SLEEP_PD_DIG_PERIPH) ? 1 : 0, \ - .deep_slp = ((sleep_flags) & RTC_SLEEP_PD_DIG) ? 1 : 0, \ - .wdt_flashboot_mod_en = 0, \ - .dig_dbias_wak = RTC_CNTL_DBIAS_1V10, \ - .dig_dbias_slp = is_dslp(sleep_flags) ? RTC_CNTL_DBIAS_SLP \ - : !((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? RTC_CNTL_DBIAS_1V10 \ - : RTC_CNTL_DBIAS_SLP, \ - .rtc_dbias_wak = RTC_CNTL_DBIAS_1V10, \ - .rtc_dbias_slp = is_dslp(sleep_flags) ? RTC_CNTL_DBIAS_SLP \ - : !((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? RTC_CNTL_DBIAS_1V10 \ - : RTC_CNTL_DBIAS_SLP, \ - .vddsdio_pd_en = ((sleep_flags) & RTC_SLEEP_PD_VDDSDIO) ? 1 : 0, \ - .xtal_fpu = ((sleep_flags) & RTC_SLEEP_PD_XTAL) ? 0 : 1, \ - .deep_slp_reject = 1, \ - .light_slp_reject = 1 \ -}; - #define RTC_SLEEP_PD_DIG BIT(0) //!< Deep sleep (power down digital domain) #define RTC_SLEEP_PD_RTC_PERIPH BIT(1) //!< Power down RTC peripherals #define RTC_SLEEP_PD_RTC_SLOW_MEM BIT(2) //!< Power down RTC SLOW memory @@ -702,6 +672,21 @@ typedef struct { #define RTC_SLEEP_PD_INT_8M BIT(10) //!< Power down Internal 8M oscillator #define RTC_SLEEP_PD_XTAL BIT(11) //!< Power down main XTAL +//These flags are not power domains, but will affect some sleep parameters +#define RTC_SLEEP_DIG_USE_8M BIT(16) +#define RTC_SLEEP_USE_ADC_TESEN_MONITOR BIT(17) +#define RTC_SLEEP_NO_ULTRA_LOW BIT(18) //!< Avoid using ultra low power in deep sleep, in which RTCIO cannot be used as input, and RTCMEM can't work under high temperature + +/** + * Default initializer for rtc_sleep_config_t + * + * This initializer sets all fields to "reasonable" values (e.g. suggested for + * production use) based on a combination of RTC_SLEEP_PD_x flags. + * + * @param RTC_SLEEP_PD_x flags combined using bitwise OR + */ +void rtc_sleep_get_default_config(uint32_t sleep_flags, rtc_sleep_config_t *out_config); + /** * @brief Prepare the chip to enter sleep mode * diff --git a/components/soc/esp32h2/include/soc/rtc.h b/components/soc/esp32h2/include/soc/rtc.h index 21cc956f73..596e130588 100644 --- a/components/soc/esp32h2/include/soc/rtc.h +++ b/components/soc/esp32h2/include/soc/rtc.h @@ -666,48 +666,16 @@ typedef struct { uint32_t dig_dbias_slp : 5; //!< set bias for digital domain, in sleep mode uint32_t rtc_dbias_wak : 5; //!< set bias for RTC domain, in active mode uint32_t rtc_dbias_slp : 5; //!< set bias for RTC domain, in sleep mode + uint32_t bias_sleep_monitor : 1; //!< circuit control parameter, in monitor mode + uint32_t bias_sleep_slp : 1; //!< circuit control parameter, in sleep mode + uint32_t pd_cur_monitor : 1; //!< circuit control parameter, in monitor mode + uint32_t pd_cur_slp : 1; //!< circuit control parameter, in sleep mode uint32_t vddsdio_pd_en : 1; //!< power down VDDSDIO regulator uint32_t xtal_fpu : 1; //!< keep main XTAL powered up in sleep uint32_t deep_slp_reject : 1; uint32_t light_slp_reject : 1; } rtc_sleep_config_t; -/** - * Default initializer for rtc_sleep_config_t - * - * This initializer sets all fields to "reasonable" values (e.g. suggested for - * production use) based on a combination of RTC_SLEEP_PD_x flags. - * - * @param RTC_SLEEP_PD_x flags combined using bitwise OR - */ -#define is_dslp(pd_flags) ((pd_flags) & RTC_SLEEP_PD_DIG) -#define RTC_SLEEP_CONFIG_DEFAULT(sleep_flags) { \ - .lslp_mem_inf_fpu = 0, \ - .rtc_mem_inf_follow_cpu = ((sleep_flags) & RTC_SLEEP_PD_RTC_MEM_FOLLOW_CPU) ? 1 : 0, \ - .rtc_fastmem_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_FAST_MEM) ? 1 : 0, \ - .rtc_slowmem_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_SLOW_MEM) ? 1 : 0, \ - .rtc_peri_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_PERIPH) ? 1 : 0, \ - .dig_ret_pd_en = ((sleep_flags) & RTC_SLEEP_PD_DIG_RET) ? 1 : 0, \ - .bt_pd_en = ((sleep_flags) & RTC_SLEEP_PD_BT) ? 1 : 0, \ - .cpu_pd_en = ((sleep_flags) & RTC_SLEEP_PD_CPU) ? 1 : 0, \ - .int_8m_pd_en = ((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? 1 : 0, \ - .dig_peri_pd_en = ((sleep_flags) & RTC_SLEEP_PD_DIG_PERIPH) ? 1 : 0, \ - .deep_slp = ((sleep_flags) & RTC_SLEEP_PD_DIG) ? 1 : 0, \ - .wdt_flashboot_mod_en = 0, \ - .dig_dbias_wak = RTC_CNTL_DBIAS_1V10, \ - .dig_dbias_slp = is_dslp(sleep_flags) ? RTC_CNTL_DBIAS_SLP \ - : !((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? RTC_CNTL_DBIAS_1V10 \ - : RTC_CNTL_DBIAS_SLP, \ - .rtc_dbias_wak = RTC_CNTL_DBIAS_1V10, \ - .rtc_dbias_slp = is_dslp(sleep_flags) ? RTC_CNTL_DBIAS_SLP \ - : !((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? RTC_CNTL_DBIAS_1V10 \ - : RTC_CNTL_DBIAS_SLP, \ - .vddsdio_pd_en = ((sleep_flags) & RTC_SLEEP_PD_VDDSDIO) ? 1 : 0, \ - .xtal_fpu = ((sleep_flags) & RTC_SLEEP_PD_XTAL) ? 0 : 1, \ - .deep_slp_reject = 1, \ - .light_slp_reject = 1 \ -}; - #define RTC_SLEEP_PD_DIG BIT(0) //!< Deep sleep (power down digital domain) #define RTC_SLEEP_PD_RTC_PERIPH BIT(1) //!< Power down RTC peripherals #define RTC_SLEEP_PD_RTC_SLOW_MEM BIT(2) //!< Power down RTC SLOW memory @@ -721,6 +689,21 @@ typedef struct { #define RTC_SLEEP_PD_INT_8M BIT(10) //!< Power down Internal 8M oscillator #define RTC_SLEEP_PD_XTAL BIT(11) //!< Power down main XTAL +//These flags are not power domains, but will affect some sleep parameters +#define RTC_SLEEP_DIG_USE_8M BIT(16) +#define RTC_SLEEP_USE_ADC_TESEN_MONITOR BIT(17) +#define RTC_SLEEP_NO_ULTRA_LOW BIT(18) //!< Avoid using ultra low power in deep sleep, in which RTCIO cannot be used as input, and RTCMEM can't work under high temperature + +/** + * Default initializer for rtc_sleep_config_t + * + * This initializer sets all fields to "reasonable" values (e.g. suggested for + * production use) based on a combination of RTC_SLEEP_PD_x flags. + * + * @param RTC_SLEEP_PD_x flags combined using bitwise OR + */ +void rtc_sleep_get_default_config(uint32_t sleep_flags, rtc_sleep_config_t *out_config); + /** * @brief Prepare the chip to enter sleep mode * diff --git a/components/soc/esp32s2/include/soc/rtc.h b/components/soc/esp32s2/include/soc/rtc.h index 62f1e0d2ea..12cb8ba1e8 100644 --- a/components/soc/esp32s2/include/soc/rtc.h +++ b/components/soc/esp32s2/include/soc/rtc.h @@ -673,47 +673,18 @@ typedef struct { uint32_t dig_dbias_slp : 3; //!< set bias for digital domain, in sleep mode uint32_t rtc_dbias_wak : 3; //!< set bias for RTC domain, in active mode uint32_t rtc_dbias_slp : 3; //!< set bias for RTC domain, in sleep mode + uint32_t dbg_atten_monitor : 4; //!< voltage parameter, in monitor mode + uint32_t bias_sleep_monitor : 1; //!< circuit control parameter, in monitor mode + uint32_t dbg_atten_slp : 4; //!< voltage parameter, in sleep mode + uint32_t bias_sleep_slp : 1; //!< circuit control parameter, in sleep mode + uint32_t pd_cur_monitor : 1; //!< circuit control parameter, in monitor mode + uint32_t pd_cur_slp : 1; //!< circuit control parameter, in sleep mode uint32_t vddsdio_pd_en : 1; //!< power down VDDSDIO regulator uint32_t xtal_fpu : 1; //!< keep main XTAL powered up in sleep uint32_t deep_slp_reject : 1; uint32_t light_slp_reject : 1; } rtc_sleep_config_t; -/** - * Default initializer for rtc_sleep_config_t - * - * This initializer sets all fields to "reasonable" values (e.g. suggested for - * production use) based on a combination of RTC_SLEEP_PD_x flags. - * - * @param RTC_SLEEP_PD_x flags combined using bitwise OR - */ -#define is_dslp(pd_flags) ((pd_flags) & RTC_SLEEP_PD_DIG) -#define RTC_SLEEP_CONFIG_DEFAULT(sleep_flags) { \ - .lslp_mem_inf_fpu = 0, \ - .rtc_mem_inf_follow_cpu = ((sleep_flags) & RTC_SLEEP_PD_RTC_MEM_FOLLOW_CPU) ? 1 : 0, \ - .rtc_fastmem_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_FAST_MEM) ? 1 : 0, \ - .rtc_slowmem_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_SLOW_MEM) ? 1 : 0, \ - .rtc_peri_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_PERIPH) ? 1 : 0, \ - .wifi_pd_en = ((sleep_flags) & RTC_SLEEP_PD_WIFI) ? 1 : 0, \ - .int_8m_pd_en = ((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? 1 : 0, \ - .deep_slp = ((sleep_flags) & RTC_SLEEP_PD_DIG) ? 1 : 0, \ - .wdt_flashboot_mod_en = 0, \ - .dig_dbias_wak = RTC_CNTL_DIG_DBIAS_1V10, \ - .dig_dbias_slp = is_dslp(sleep_flags) ? RTC_CNTL_DIG_DBIAS_0V90 \ - : !((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? RTC_CNTL_DIG_DBIAS_1V10 \ - : !((sleep_flags) & RTC_SLEEP_PD_XTAL) ? RTC_CNTL_DIG_DBIAS_1V10 \ - : RTC_CNTL_DIG_DBIAS_0V90, \ - .rtc_dbias_wak = RTC_CNTL_DBIAS_1V10, \ - .rtc_dbias_slp = is_dslp(sleep_flags) ? RTC_CNTL_DBIAS_1V00 \ - : !((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? RTC_CNTL_DBIAS_1V10 \ - : !((sleep_flags) & RTC_SLEEP_PD_XTAL) ? RTC_CNTL_DBIAS_1V10 \ - : RTC_CNTL_DBIAS_1V00, \ - .vddsdio_pd_en = ((sleep_flags) & RTC_SLEEP_PD_VDDSDIO) ? 1 : 0, \ - .xtal_fpu = ((sleep_flags) & RTC_SLEEP_PD_XTAL) ? 0 : 1, \ - .deep_slp_reject = 1, \ - .light_slp_reject = 1 \ -}; - #define RTC_SLEEP_PD_DIG BIT(0) //!< Deep sleep (power down digital domain) #define RTC_SLEEP_PD_RTC_PERIPH BIT(1) //!< Power down RTC peripherals #define RTC_SLEEP_PD_RTC_SLOW_MEM BIT(2) //!< Power down RTC SLOW memory @@ -724,6 +695,21 @@ typedef struct { #define RTC_SLEEP_PD_INT_8M BIT(7) //!< Power down Internal 8M oscillator #define RTC_SLEEP_PD_XTAL BIT(8) //!< Power down main XTAL +//These flags are not power domains, but will affect some sleep parameters +#define RTC_SLEEP_DIG_USE_8M BIT(16) +#define RTC_SLEEP_USE_ADC_TESEN_MONITOR BIT(17) +#define RTC_SLEEP_NO_ULTRA_LOW BIT(18) //!< Avoid using ultra low power in deep sleep, in which RTCIO cannot be used as input, and RTCMEM can't work under high temperature + +/** + * Default initializer for rtc_sleep_config_t + * + * This initializer sets all fields to "reasonable" values (e.g. suggested for + * production use) based on a combination of RTC_SLEEP_PD_x flags. + * + * @param RTC_SLEEP_PD_x flags combined using bitwise OR + */ +void rtc_sleep_get_default_config(uint32_t sleep_flags, rtc_sleep_config_t *out_config); + /** * @brief Prepare the chip to enter sleep mode * diff --git a/components/soc/esp32s3/include/soc/rtc.h b/components/soc/esp32s3/include/soc/rtc.h index 433beb72ac..228075405f 100644 --- a/components/soc/esp32s3/include/soc/rtc.h +++ b/components/soc/esp32s3/include/soc/rtc.h @@ -654,48 +654,18 @@ typedef struct { uint32_t dig_dbias_slp : 5; //!< set bias for digital domain, in sleep mode uint32_t rtc_dbias_wak : 5; //!< set bias for RTC domain, in active mode uint32_t rtc_dbias_slp : 5; //!< set bias for RTC domain, in sleep mode + uint32_t dbg_atten_monitor : 4; //!< voltage parameter, in monitor mode + uint32_t bias_sleep_monitor : 1; //!< circuit control parameter, in monitor mode + uint32_t dbg_atten_slp : 4; //!< voltage parameter, in sleep mode + uint32_t bias_sleep_slp : 1; //!< circuit control parameter, in sleep mode + uint32_t pd_cur_monitor : 1; //!< circuit control parameter, in monitor mode + uint32_t pd_cur_slp : 1; //!< circuit control parameter, in sleep mode uint32_t vddsdio_pd_en : 1; //!< power down VDDSDIO regulator uint32_t xtal_fpu : 1; //!< keep main XTAL powered up in sleep uint32_t deep_slp_reject : 1; uint32_t light_slp_reject : 1; } rtc_sleep_config_t; -/** - * Default initializer for rtc_sleep_config_t - * - * This initializer sets all fields to "reasonable" values (e.g. suggested for - * production use) based on a combination of RTC_SLEEP_PD_x flags. - * - * @param RTC_SLEEP_PD_x flags combined using bitwise OR - */ -#define is_dslp(pd_flags) ((pd_flags) & RTC_SLEEP_PD_DIG) -#define RTC_SLEEP_CONFIG_DEFAULT(sleep_flags) { \ - .lslp_mem_inf_fpu = 0, \ - .rtc_mem_inf_follow_cpu = ((sleep_flags) & RTC_SLEEP_PD_RTC_MEM_FOLLOW_CPU) ? 1 : 0, \ - .rtc_fastmem_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_FAST_MEM) ? 1 : 0, \ - .rtc_slowmem_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_SLOW_MEM) ? 1 : 0, \ - .rtc_peri_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_PERIPH) ? 1 : 0, \ - .wifi_pd_en = ((sleep_flags) & RTC_SLEEP_PD_WIFI) ? 1 : 0, \ - .bt_pd_en = ((sleep_flags) & RTC_SLEEP_PD_BT) ? 1 : 0, \ - .cpu_pd_en = ((sleep_flags) & RTC_SLEEP_PD_CPU) ? 1 : 0, \ - .int_8m_pd_en = ((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? 1 : 0, \ - .dig_peri_pd_en = ((sleep_flags) & RTC_SLEEP_PD_DIG_PERIPH) ? 1 : 0, \ - .deep_slp = ((sleep_flags) & RTC_SLEEP_PD_DIG) ? 1 : 0, \ - .wdt_flashboot_mod_en = 0, \ - .dig_dbias_wak = RTC_CNTL_DBIAS_1V10, \ - .dig_dbias_slp = is_dslp(sleep_flags) ? RTC_CNTL_DBIAS_SLP \ - : !((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? RTC_CNTL_DBIAS_1V10 \ - : RTC_CNTL_DBIAS_SLP, \ - .rtc_dbias_wak = RTC_CNTL_DBIAS_1V10, \ - .rtc_dbias_slp = is_dslp(sleep_flags) ? RTC_CNTL_DBIAS_SLP \ - : !((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? RTC_CNTL_DBIAS_1V10 \ - : RTC_CNTL_DBIAS_SLP, \ - .vddsdio_pd_en = ((sleep_flags) & RTC_SLEEP_PD_VDDSDIO) ? 1 : 0, \ - .xtal_fpu = ((sleep_flags) & RTC_SLEEP_PD_XTAL) ? 0 : 1, \ - .deep_slp_reject = 1, \ - .light_slp_reject = 1 \ -}; - #define RTC_SLEEP_PD_DIG BIT(0) //!< Deep sleep (power down digital domain) #define RTC_SLEEP_PD_RTC_PERIPH BIT(1) //!< Power down RTC peripherals #define RTC_SLEEP_PD_RTC_SLOW_MEM BIT(2) //!< Power down RTC SLOW memory @@ -709,6 +679,21 @@ typedef struct { #define RTC_SLEEP_PD_INT_8M BIT(10) //!< Power down Internal 8M oscillator #define RTC_SLEEP_PD_XTAL BIT(11) //!< Power down main XTAL +//These flags are not power domains, but will affect some sleep parameters +#define RTC_SLEEP_DIG_USE_8M BIT(16) +#define RTC_SLEEP_USE_ADC_TESEN_MONITOR BIT(17) +#define RTC_SLEEP_NO_ULTRA_LOW BIT(18) //!< Avoid using ultra low power in deep sleep, in which RTCIO cannot be used as input, and RTCMEM can't work under high temperature + +/** + * Default initializer for rtc_sleep_config_t + * + * This initializer sets all fields to "reasonable" values (e.g. suggested for + * production use) based on a combination of RTC_SLEEP_PD_x flags. + * + * @param RTC_SLEEP_PD_x flags combined using bitwise OR + */ +void rtc_sleep_get_default_config(uint32_t sleep_flags, rtc_sleep_config_t *out_config); + /** * @brief Prepare the chip to enter sleep mode * From a2e1b6756e2bb053c3699856d3b902bebe5f5912 Mon Sep 17 00:00:00 2001 From: "Michael (XIAO Xufeng)" Date: Thu, 19 May 2022 15:25:19 +0800 Subject: [PATCH 3/7] esp32s3: fixed dangerous power parameters in sleep modes --- .../esp_hw_support/port/esp32s3/rtc_sleep.c | 90 +++++++++++++++---- components/soc/esp32s3/include/soc/rtc.h | 4 +- 2 files changed, 75 insertions(+), 19 deletions(-) diff --git a/components/esp_hw_support/port/esp32s3/rtc_sleep.c b/components/esp_hw_support/port/esp32s3/rtc_sleep.c index 4df230e6d7..305e1ad35d 100644 --- a/components/esp_hw_support/port/esp32s3/rtc_sleep.c +++ b/components/esp_hw_support/port/esp32s3/rtc_sleep.c @@ -74,30 +74,82 @@ void rtc_sleep_get_default_config(uint32_t sleep_flags, rtc_sleep_config_t *out_ .light_slp_reject = 1 }; + out_config->dig_dbias_wak = RTC_CNTL_DBIAS_1V10; + out_config->rtc_dbias_wak = RTC_CNTL_DBIAS_1V10; + if (sleep_flags & RTC_SLEEP_PD_DIG) { - out_config->dig_dbias_wak = RTC_CNTL_DBIAS_1V10; + assert(sleep_flags & RTC_SLEEP_PD_XTAL); out_config->dig_dbias_slp = RTC_CNTL_DBIAS_SLP; - out_config->rtc_dbias_wak = RTC_CNTL_DBIAS_1V10; - out_config->rtc_dbias_slp = RTC_CNTL_DBIAS_SLP; - out_config->dbg_atten_monitor = RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT; - out_config->bias_sleep_monitor = RTC_CNTL_BIASSLP_MONITOR_DEFAULT; - out_config->dbg_atten_slp = RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT; - out_config->bias_sleep_slp = RTC_CNTL_BIASSLP_SLEEP_DEFAULT; - out_config->pd_cur_monitor = RTC_CNTL_PD_CUR_MONITOR_DEFAULT; - out_config->pd_cur_slp = RTC_CNTL_PD_CUR_SLEEP_DEFAULT; + //voltage from high to low + if (sleep_flags & RTC_SLEEP_USE_ADC_TESEN_MONITOR) { + /* + * Voltage for all features: + * - ADC/Temperature sensor in monitor mode (ULP) + * - RTC IO as input + * - RTC Memory at high temperature + * - ULP + * - Touch sensor + * - 8MD256 as RTC slow clock src + */ + out_config->dbg_atten_monitor = RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT; + out_config->dbg_atten_slp = RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT; + out_config->rtc_dbias_slp = RTC_CNTL_DBIAS_SLP; + } else if (sleep_flags & RTC_SLEEP_NO_ULTRA_LOW) { + //default mode, can't use ADC/Temperature sensor in monitor mode + out_config->dbg_atten_monitor = RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT; + out_config->dbg_atten_slp = RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT; + out_config->rtc_dbias_slp = RTC_CNTL_DBIAS_SLP; + } else { + //ultra low power, also can't use RTC IO as input, RTC memory can't work under high temperature + out_config->dbg_atten_monitor = RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT; + out_config->dbg_atten_slp = RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT; + out_config->rtc_dbias_slp = RTC_CNTL_DBIAS_SLP; + } } else { - out_config->dig_dbias_wak = RTC_CNTL_DBIAS_1V10; - out_config->dig_dbias_slp = !(sleep_flags & RTC_SLEEP_PD_INT_8M) ? RTC_CNTL_DBIAS_1V10 : RTC_CNTL_DBIAS_SLP; - out_config->rtc_dbias_wak = RTC_CNTL_DBIAS_1V10; - out_config->rtc_dbias_slp = !(sleep_flags & RTC_SLEEP_PD_INT_8M) ? RTC_CNTL_DBIAS_1V10 : RTC_CNTL_DBIAS_SLP; + //voltage from high to low + if (!(sleep_flags & RTC_SLEEP_DIG_USE_8M) || !(sleep_flags & RTC_SLEEP_PD_XTAL)) { + /* + * Voltage for all features: + * - XTAL + * - RC 8M used by digital system + * - ADC/Temperature sensor in monitor mode (ULP) + * - ULP + * - Touch sensor + * - 8MD256 as RTC slow clock src + */ + out_config->dbg_atten_monitor = RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT; + out_config->dbg_atten_slp = RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_NODROP; + out_config->dig_dbias_slp = RTC_CNTL_DBIAS_1V10; + out_config->rtc_dbias_slp = RTC_CNTL_DBIAS_1V10; + } else if (sleep_flags & RTC_SLEEP_USE_ADC_TESEN_MONITOR) { + //can't use XTAL, or RC 8M in digital system + out_config->dbg_atten_monitor = RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT; + out_config->dbg_atten_slp = RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT; + out_config->dig_dbias_slp = RTC_CNTL_DBIAS_SLP; + out_config->rtc_dbias_slp = RTC_CNTL_DBIAS_SLP; + } else { + //also can't use ADC/Temperature sensor in monitor mode + out_config->dbg_atten_monitor = RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT; + out_config->dbg_atten_slp = RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT; + out_config->dig_dbias_slp = RTC_CNTL_DBIAS_SLP; + out_config->rtc_dbias_slp = RTC_CNTL_DBIAS_SLP; + } + } - out_config->dbg_atten_monitor = RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT; + if (!(sleep_flags & RTC_SLEEP_PD_XTAL)) { + out_config->bias_sleep_monitor = RTC_CNTL_BIASSLP_MONITOR_ON; + out_config->pd_cur_monitor = RTC_CNTL_PD_CUR_MONITOR_ON; + + out_config->bias_sleep_slp = RTC_CNTL_BIASSLP_SLEEP_ON; + out_config->pd_cur_slp = RTC_CNTL_PD_CUR_SLEEP_ON; + } else { out_config->bias_sleep_monitor = RTC_CNTL_BIASSLP_MONITOR_DEFAULT; - out_config->dbg_atten_slp = (sleep_flags & RTC_SLEEP_PD_INT_8M) ? RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT : RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_NODROP; - out_config->bias_sleep_slp = !(sleep_flags & RTC_SLEEP_PD_XTAL) ? RTC_CNTL_BIASSLP_SLEEP_ON : RTC_CNTL_BIASSLP_SLEEP_DEFAULT; - out_config->pd_cur_monitor = RTC_CNTL_PD_CUR_MONITOR_DEFAULT; - out_config->pd_cur_slp = !(sleep_flags & RTC_SLEEP_PD_XTAL) ? RTC_CNTL_PD_CUR_SLEEP_ON : RTC_CNTL_PD_CUR_SLEEP_DEFAULT; + out_config->pd_cur_monitor = (sleep_flags & RTC_SLEEP_USE_ADC_TESEN_MONITOR)? + RTC_CNTL_PD_CUR_MONITOR_ON : RTC_CNTL_PD_CUR_MONITOR_DEFAULT; + + out_config->bias_sleep_slp = RTC_CNTL_BIASSLP_SLEEP_DEFAULT; + out_config->pd_cur_slp = RTC_CNTL_PD_CUR_SLEEP_DEFAULT; } } @@ -144,6 +196,8 @@ void rtc_sleep_init(rtc_sleep_config_t cfg) CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_PD_EN); } + assert(!cfg.pd_cur_monitor || cfg.bias_sleep_monitor); + assert(!cfg.pd_cur_slp || cfg.bias_sleep_slp); REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG_SLEEP, cfg.rtc_dbias_slp); REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG, cfg.rtc_dbias_wak); REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG_SLEEP, cfg.dig_dbias_slp); diff --git a/components/soc/esp32s3/include/soc/rtc.h b/components/soc/esp32s3/include/soc/rtc.h index 228075405f..1ff784bb38 100644 --- a/components/soc/esp32s3/include/soc/rtc.h +++ b/components/soc/esp32s3/include/soc/rtc.h @@ -117,9 +117,11 @@ set sleep_init default param #define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_NODROP 0 #define RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT 15 #define RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT 0 -#define RTC_CNTL_BIASSLP_MONITOR_DEFAULT 0 +#define RTC_CNTL_BIASSLP_MONITOR_ON 0 +#define RTC_CNTL_BIASSLP_MONITOR_DEFAULT 1 #define RTC_CNTL_BIASSLP_SLEEP_ON 0 #define RTC_CNTL_BIASSLP_SLEEP_DEFAULT 1 +#define RTC_CNTL_PD_CUR_MONITOR_ON 0 #define RTC_CNTL_PD_CUR_MONITOR_DEFAULT 1 #define RTC_CNTL_PD_CUR_SLEEP_ON 0 #define RTC_CNTL_PD_CUR_SLEEP_DEFAULT 1 From 2a1002b4a45d9440d6f79b3e8ab1ceedfae5bdad Mon Sep 17 00:00:00 2001 From: chaijie Date: Fri, 20 May 2022 19:29:20 +0800 Subject: [PATCH 4/7] modify voltage param to fit all mode of S3 --- .../esp_hw_support/port/esp32s3/rtc_pm.c | 2 - .../esp_hw_support/port/esp32s3/rtc_sleep.c | 68 +++++++++---------- components/soc/esp32s3/include/soc/rtc.h | 8 ++- 3 files changed, 37 insertions(+), 41 deletions(-) diff --git a/components/esp_hw_support/port/esp32s3/rtc_pm.c b/components/esp_hw_support/port/esp32s3/rtc_pm.c index 04c5356c59..4bf523eb20 100644 --- a/components/esp_hw_support/port/esp32s3/rtc_pm.c +++ b/components/esp_hw_support/port/esp32s3/rtc_pm.c @@ -45,9 +45,7 @@ pm_sw_reject_t pm_set_sleep_mode(pm_sleep_mode_t sleep_mode, void(*pmac_save_par switch (sleep_mode) { case PM_LIGHT_SLEEP: cfg.wifi_pd_en = 1; - cfg.dig_dbias_wak = 4; cfg.dig_dbias_slp = 0; - cfg.rtc_dbias_wak = 0; cfg.rtc_dbias_slp = 0; rtc_sleep_init(cfg); break; diff --git a/components/esp_hw_support/port/esp32s3/rtc_sleep.c b/components/esp_hw_support/port/esp32s3/rtc_sleep.c index 305e1ad35d..e2a9cde90e 100644 --- a/components/esp_hw_support/port/esp32s3/rtc_sleep.c +++ b/components/esp_hw_support/port/esp32s3/rtc_sleep.c @@ -71,46 +71,50 @@ void rtc_sleep_get_default_config(uint32_t sleep_flags, rtc_sleep_config_t *out_ .vddsdio_pd_en = (sleep_flags & RTC_SLEEP_PD_VDDSDIO) ? 1 : 0, .xtal_fpu = (sleep_flags & RTC_SLEEP_PD_XTAL) ? 0 : 1, .deep_slp_reject = 1, - .light_slp_reject = 1 + .light_slp_reject = 1, + .dbg_atten_monitor = RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT, + .rtc_dbias_slp = RTC_CNTL_DBIAS_1V10 }; - out_config->dig_dbias_wak = RTC_CNTL_DBIAS_1V10; - out_config->rtc_dbias_wak = RTC_CNTL_DBIAS_1V10; - if (sleep_flags & RTC_SLEEP_PD_DIG) { assert(sleep_flags & RTC_SLEEP_PD_XTAL); - out_config->dig_dbias_slp = RTC_CNTL_DBIAS_SLP; - - //voltage from high to low + out_config->dig_dbias_slp = 0; //not used + //rtc voltage from high to low if (sleep_flags & RTC_SLEEP_USE_ADC_TESEN_MONITOR) { /* - * Voltage for all features: - * - ADC/Temperature sensor in monitor mode (ULP) + * rtc voltage in sleep mode >= 1.1v + * Support all features: + * - ADC/Temperature sensor in monitor mode (ULP) (also need pd_cur_monotor = 0) * - RTC IO as input * - RTC Memory at high temperature * - ULP * - Touch sensor * - 8MD256 as RTC slow clock src */ - out_config->dbg_atten_monitor = RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT; - out_config->dbg_atten_slp = RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT; - out_config->rtc_dbias_slp = RTC_CNTL_DBIAS_SLP; + out_config->rtc_regulator_fpu = 1; + out_config->dbg_atten_slp = RTC_CNTL_DBG_ATTEN_DEEPSLEEP_NODROP; } else if (sleep_flags & RTC_SLEEP_NO_ULTRA_LOW) { - //default mode, can't use ADC/Temperature sensor in monitor mode - out_config->dbg_atten_monitor = RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT; + /* + * rtc voltage in sleep need stable and not less than 0.7v (default mode): + * can't use ADC/Temperature sensor in monitor mode + */ + out_config->rtc_regulator_fpu = 1; out_config->dbg_atten_slp = RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT; - out_config->rtc_dbias_slp = RTC_CNTL_DBIAS_SLP; } else { - //ultra low power, also can't use RTC IO as input, RTC memory can't work under high temperature - out_config->dbg_atten_monitor = RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT; - out_config->dbg_atten_slp = RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT; - out_config->rtc_dbias_slp = RTC_CNTL_DBIAS_SLP; + /* + * rtc regulator not opened and rtc voltage is about 0.66v (ultra low power): + also can't use RTC IO as input, RTC memory can't work under high temperature + */ + out_config->rtc_regulator_fpu = 0; + out_config->dbg_atten_slp = RTC_CNTL_DBG_ATTEN_DEEPSLEEP_ULTRA_LOW; } } else { + out_config->rtc_regulator_fpu = 1; //voltage from high to low - if (!(sleep_flags & RTC_SLEEP_DIG_USE_8M) || !(sleep_flags & RTC_SLEEP_PD_XTAL)) { + if ((sleep_flags & RTC_SLEEP_DIG_USE_8M) || !(sleep_flags & RTC_SLEEP_PD_XTAL)) { /* - * Voltage for all features: + * digital voltage not less than 1.1v, rtc voltage not less than 1.1v to keep system stable + * Support all features: * - XTAL * - RC 8M used by digital system * - ADC/Temperature sensor in monitor mode (ULP) @@ -118,22 +122,17 @@ void rtc_sleep_get_default_config(uint32_t sleep_flags, rtc_sleep_config_t *out_ * - Touch sensor * - 8MD256 as RTC slow clock src */ - out_config->dbg_atten_monitor = RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT; out_config->dbg_atten_slp = RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_NODROP; out_config->dig_dbias_slp = RTC_CNTL_DBIAS_1V10; - out_config->rtc_dbias_slp = RTC_CNTL_DBIAS_1V10; - } else if (sleep_flags & RTC_SLEEP_USE_ADC_TESEN_MONITOR) { - //can't use XTAL, or RC 8M in digital system - out_config->dbg_atten_monitor = RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT; - out_config->dbg_atten_slp = RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT; - out_config->dig_dbias_slp = RTC_CNTL_DBIAS_SLP; - out_config->rtc_dbias_slp = RTC_CNTL_DBIAS_SLP; } else { - //also can't use ADC/Temperature sensor in monitor mode - out_config->dbg_atten_monitor = RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT; + /* + * digital voltage not less than 0.6v + * if use RTC_SLEEP_USE_ADC_TESEN_MONITOR, rtc voltage need to be >= 0.9v(default voltage), others just use default rtc voltage. + * - not support XTAL + * - not support RC 8M in digital system + */ out_config->dbg_atten_slp = RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT; out_config->dig_dbias_slp = RTC_CNTL_DBIAS_SLP; - out_config->rtc_dbias_slp = RTC_CNTL_DBIAS_SLP; } } @@ -199,9 +198,7 @@ void rtc_sleep_init(rtc_sleep_config_t cfg) assert(!cfg.pd_cur_monitor || cfg.bias_sleep_monitor); assert(!cfg.pd_cur_slp || cfg.bias_sleep_slp); REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG_SLEEP, cfg.rtc_dbias_slp); - REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG, cfg.rtc_dbias_wak); REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG_SLEEP, cfg.dig_dbias_slp); - REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG, cfg.dig_dbias_wak); REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN_MONITOR, cfg.dbg_atten_monitor); REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_BIAS_SLEEP_MONITOR, cfg.bias_sleep_monitor); @@ -211,7 +208,6 @@ void rtc_sleep_init(rtc_sleep_config_t cfg) REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_PD_CUR_DEEP_SLP, cfg.pd_cur_slp); if (cfg.deep_slp) { - CLEAR_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU); SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_PD_EN); CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_CKGEN_I2C_PU | RTC_CNTL_PLL_I2C_PU | @@ -219,12 +215,12 @@ void rtc_sleep_init(rtc_sleep_config_t cfg) CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BB_I2C_FORCE_PU); } else { REG_SET_FIELD(RTC_CNTL_REGULATOR_DRV_CTRL_REG, RTC_CNTL_DG_VDD_DRV_B_SLP, RTC_CNTL_DG_VDD_DRV_B_SLP_DEFAULT); - SET_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU); CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_PD_EN); } /* mem pd */ CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_LSLP_MEM_FORCE_PU); + REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU, cfg.rtc_regulator_fpu); if (!cfg.int_8m_pd_en) { REG_SET_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU); } else { diff --git a/components/soc/esp32s3/include/soc/rtc.h b/components/soc/esp32s3/include/soc/rtc.h index 1ff784bb38..479e2c2073 100644 --- a/components/soc/esp32s3/include/soc/rtc.h +++ b/components/soc/esp32s3/include/soc/rtc.h @@ -115,7 +115,9 @@ set sleep_init default param */ #define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT 5 #define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_NODROP 0 -#define RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT 15 +#define RTC_CNTL_DBG_ATTEN_DEEPSLEEP_NODROP 0 +#define RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT 14 +#define RTC_CNTL_DBG_ATTEN_DEEPSLEEP_ULTRA_LOW 15 #define RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT 0 #define RTC_CNTL_BIASSLP_MONITOR_ON 0 #define RTC_CNTL_BIASSLP_MONITOR_DEFAULT 1 @@ -127,6 +129,7 @@ set sleep_init default param #define RTC_CNTL_PD_CUR_SLEEP_DEFAULT 1 #define RTC_CNTL_DG_VDD_DRV_B_SLP_DEFAULT 0xf + /** * @brief Possible main XTAL frequency values. * @@ -652,9 +655,7 @@ typedef struct { uint32_t dig_peri_pd_en : 1; //!< power down digital peripherals uint32_t deep_slp : 1; //!< power down digital domain uint32_t wdt_flashboot_mod_en : 1; //!< enable WDT flashboot mode - uint32_t dig_dbias_wak : 5; //!< set bias for digital domain, in active mode uint32_t dig_dbias_slp : 5; //!< set bias for digital domain, in sleep mode - uint32_t rtc_dbias_wak : 5; //!< set bias for RTC domain, in active mode uint32_t rtc_dbias_slp : 5; //!< set bias for RTC domain, in sleep mode uint32_t dbg_atten_monitor : 4; //!< voltage parameter, in monitor mode uint32_t bias_sleep_monitor : 1; //!< circuit control parameter, in monitor mode @@ -664,6 +665,7 @@ typedef struct { uint32_t pd_cur_slp : 1; //!< circuit control parameter, in sleep mode uint32_t vddsdio_pd_en : 1; //!< power down VDDSDIO regulator uint32_t xtal_fpu : 1; //!< keep main XTAL powered up in sleep + uint32_t rtc_regulator_fpu : 1; //!< keep rtc regulator powered up in sleep uint32_t deep_slp_reject : 1; uint32_t light_slp_reject : 1; } rtc_sleep_config_t; From deea85b84864d505674c86a0e542866d354d64c9 Mon Sep 17 00:00:00 2001 From: "Michael (XIAO Xufeng)" Date: Wed, 4 May 2022 11:55:23 +0800 Subject: [PATCH 5/7] pm: add test for RTC using 8MD256 as clock source --- .../test_apps/rtc_8md256/CMakeLists.txt | 7 ++ .../test_apps/rtc_8md256/component_ut_test.py | 69 ++++++++++++++ .../test_apps/rtc_8md256/main/CMakeLists.txt | 2 + .../rtc_8md256/main/test_rtc_8md256.c | 95 +++++++++++++++++++ .../test_apps/rtc_8md256/sdkconfig.defaults | 3 + 5 files changed, 176 insertions(+) create mode 100644 components/esp_system/test_apps/rtc_8md256/CMakeLists.txt create mode 100644 components/esp_system/test_apps/rtc_8md256/component_ut_test.py create mode 100644 components/esp_system/test_apps/rtc_8md256/main/CMakeLists.txt create mode 100644 components/esp_system/test_apps/rtc_8md256/main/test_rtc_8md256.c create mode 100644 components/esp_system/test_apps/rtc_8md256/sdkconfig.defaults diff --git a/components/esp_system/test_apps/rtc_8md256/CMakeLists.txt b/components/esp_system/test_apps/rtc_8md256/CMakeLists.txt new file mode 100644 index 0000000000..46c2c5b8ac --- /dev/null +++ b/components/esp_system/test_apps/rtc_8md256/CMakeLists.txt @@ -0,0 +1,7 @@ +# This is the project CMakeLists.txt file for the test subproject +cmake_minimum_required(VERSION 3.5) + +set(EXTRA_COMPONENT_DIRS "$ENV{IDF_PATH}/tools/unit-test-app/components") + +include($ENV{IDF_PATH}/tools/cmake/project.cmake) +project(rtc_8md256) diff --git a/components/esp_system/test_apps/rtc_8md256/component_ut_test.py b/components/esp_system/test_apps/rtc_8md256/component_ut_test.py new file mode 100644 index 0000000000..969609b72e --- /dev/null +++ b/components/esp_system/test_apps/rtc_8md256/component_ut_test.py @@ -0,0 +1,69 @@ +# SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD +# SPDX-License-Identifier: CC0-1.0 + +import re +import typing + +import tiny_test_fw +import ttfw_idf +from ttfw_idf import IDFDUT + + +def deepsleep_test(dut: IDFDUT, case_name: str) -> None: + dut.expect('Press ENTER to see the list of tests') + dut.write(case_name) + reset_reason = 'DEEPSLEEP_RESET' if dut.TARGET == 'esp32' else 'DSLEEP' + if dut.TARGET == 'esp32c3': + # Known issue: IDF-5003 + dut.expect(re.compile(r'rst:.*\(%s\)' % reset_reason), timeout=40) + else: + dut.expect(re.compile(r'rst:.*\(%s\)' % reset_reason), timeout=10) + + +@ttfw_idf.idf_component_unit_test(env_tag='COMPONENT_UT_GENERIC', target=['esp32', 'esp32s2', 'esp32s3']) +def test_component_ut_rtc_8md256_deepsleep_force_rtcperiph(env, _): # type: (tiny_test_fw.Env, typing.Any) -> None + dut = env.get_dut('rtc_8md256', 'components/esp_system/test_apps/rtc_8md256') + dut.start_app() + + deepsleep_test(dut, '"Can use 8MD256 as RTC clock source in deepsleep (force rtc_periph)"') + + +@ttfw_idf.idf_component_unit_test(env_tag='COMPONENT_UT_GENERIC', target=['esp32', 'esp32s2', 'esp32s3', 'esp32c3']) +def test_component_ut_rtc_8md256_deepsleep(env, _): # type: (tiny_test_fw.Env, typing.Any) -> None + dut = env.get_dut('rtc_8md256', 'components/esp_system/test_apps/rtc_8md256') + dut.start_app() + + deepsleep_test(dut, '"Can use 8MD256 as RTC clock source in deepsleep"') + + +def lightsleep_test(dut: IDFDUT, case_name: str) -> None: + dut.expect('Press ENTER to see the list of tests') + dut.write(case_name) + if dut.TARGET == 'esp32c3': + # Known issue: IDF-5003 + dut.expect(r'Returned from light sleep, reason: timer', timeout=40) + else: + dut.expect(r'Returned from light sleep, reason: timer', timeout=10) + + +@ttfw_idf.idf_component_unit_test(env_tag='COMPONENT_UT_GENERIC', target=['esp32', 'esp32s2', 'esp32s3', 'esp32c3']) +def test_component_ut_rtc_8md256_lightsleep(env, _): # type: (tiny_test_fw.Env, typing.Any) -> None + dut = env.get_dut('rtc_8md256', 'components/esp_system/test_apps/rtc_8md256') + dut.start_app() + + lightsleep_test(dut, '"Can use 8MD256 as RTC clock source in lightsleep"') + + +@ttfw_idf.idf_component_unit_test(env_tag='COMPONENT_UT_GENERIC', target=['esp32', 'esp32s2', 'esp32s3']) +def test_component_ut_rtc_8md256_lightsleep_force_rtcperiph(env, _): # type: (tiny_test_fw.Env, typing.Any) -> None + dut = env.get_dut('rtc_8md256', 'components/esp_system/test_apps/rtc_8md256') + dut.start_app() + + lightsleep_test(dut, '"Can use 8MD256 as RTC clock source in lightsleep (force rtc_periph)"') + + +if __name__ == '__main__': + test_component_ut_rtc_8md256_deepsleep() + test_component_ut_rtc_8md256_deepsleep_force_rtcperiph() + test_component_ut_rtc_8md256_lightsleep() + test_component_ut_rtc_8md256_lightsleep_force_rtcperiph() diff --git a/components/esp_system/test_apps/rtc_8md256/main/CMakeLists.txt b/components/esp_system/test_apps/rtc_8md256/main/CMakeLists.txt new file mode 100644 index 0000000000..de06a799d0 --- /dev/null +++ b/components/esp_system/test_apps/rtc_8md256/main/CMakeLists.txt @@ -0,0 +1,2 @@ +idf_component_register(SRCS "test_rtc_8md256.c" + PRIV_REQUIRES unity) diff --git a/components/esp_system/test_apps/rtc_8md256/main/test_rtc_8md256.c b/components/esp_system/test_apps/rtc_8md256/main/test_rtc_8md256.c new file mode 100644 index 0000000000..73c46a38c7 --- /dev/null +++ b/components/esp_system/test_apps/rtc_8md256/main/test_rtc_8md256.c @@ -0,0 +1,95 @@ +/* + * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include "esp_sleep.h" +#include "unity.h" +#include "esp_log.h" +#include "freertos/FreeRTOS.h" +#include "freertos/task.h" +#include "driver/uart.h" +#include "soc/soc_caps.h" + +static const char TAG[] = "rtc_8m"; + +static void test_deepsleep(bool force_rtc_periph) +{ + esp_sleep_enable_timer_wakeup(2000000); +#if SOC_PM_SUPPORT_RTC_PERIPH_PD + if (force_rtc_periph) { + esp_sleep_pd_config(ESP_PD_DOMAIN_RTC_PERIPH, ESP_PD_OPTION_ON); + } +#else + (void)force_rtc_periph; +#endif + + ESP_LOGI(TAG, "Entering deep sleep"); + esp_deep_sleep_start(); +} + +TEST_CASE("Can use 8MD256 as RTC clock source in deepsleep", "[pm]") +{ + test_deepsleep(false); +} + +static void test_lightsleep(bool force_rtc_periph) +{ + esp_sleep_enable_timer_wakeup(2000000); +#if SOC_PM_SUPPORT_RTC_PERIPH_PD + if (force_rtc_periph) { + esp_sleep_pd_config(ESP_PD_DOMAIN_RTC_PERIPH, ESP_PD_OPTION_ON); + } +#else + (void)force_rtc_periph; +#endif + + while (true) { + printf("Entering light sleep\n"); + /* To make sure the complete line is printed before entering sleep mode, + * need to wait until UART TX FIFO is empty: + */ + uart_wait_tx_idle_polling(CONFIG_ESP_CONSOLE_UART_NUM); + + /* Enter sleep mode */ + esp_light_sleep_start(); + + /* Determine wake up reason */ + const char* wakeup_reason; + switch (esp_sleep_get_wakeup_cause()) { + case ESP_SLEEP_WAKEUP_TIMER: + wakeup_reason = "timer"; + break; + default: + wakeup_reason = "other"; + break; + } + printf("Returned from light sleep, reason: %s\n", wakeup_reason); + vTaskDelay(1000/portTICK_PERIOD_MS); + } +} + +TEST_CASE("Can use 8MD256 as RTC clock source in lightsleep", "[pm]") +{ + test_lightsleep(false); +} + +#if SOC_PM_SUPPORT_RTC_PERIPH_PD +TEST_CASE("Can use 8MD256 as RTC clock source in deepsleep (force rtc_periph)", "[pm]") +{ + test_deepsleep(true); +} + +TEST_CASE("Can use 8MD256 as RTC clock source in lightsleep (force rtc_periph)", "[pm]") +{ + test_lightsleep(true); +} +#endif + +void app_main(void) +{ + unity_run_menu(); +} diff --git a/components/esp_system/test_apps/rtc_8md256/sdkconfig.defaults b/components/esp_system/test_apps/rtc_8md256/sdkconfig.defaults new file mode 100644 index 0000000000..3660129c9f --- /dev/null +++ b/components/esp_system/test_apps/rtc_8md256/sdkconfig.defaults @@ -0,0 +1,3 @@ +CONFIG_FREERTOS_HZ=1000 +CONFIG_ESP_TASK_WDT=n +CONFIG_RTC_CLK_SRC_INT_8MD256=y From c61db5e9c97bf72862cc1a5081505f2a7f9f6834 Mon Sep 17 00:00:00 2001 From: "Michael (XIAO Xufeng)" Date: Mon, 6 Jun 2022 00:17:39 +0800 Subject: [PATCH 6/7] soc_caps: add SOC_PM_SUPPORT_RTC_PERIPH_PD Partially pick 6336f8191ecc10340033fb2bac30ccc446129fdf --- components/soc/esp32/include/soc/soc_caps.h | 2 ++ components/soc/esp32s2/include/soc/soc_caps.h | 4 ++-- components/soc/esp32s3/include/soc/soc_caps.h | 7 ++----- 3 files changed, 6 insertions(+), 7 deletions(-) diff --git a/components/soc/esp32/include/soc/soc_caps.h b/components/soc/esp32/include/soc/soc_caps.h index 15ca029b3c..b4c9404441 100644 --- a/components/soc/esp32/include/soc/soc_caps.h +++ b/components/soc/esp32/include/soc/soc_caps.h @@ -298,6 +298,8 @@ #define SOC_PM_SUPPORT_EXT_WAKEUP (1) #define SOC_PM_SUPPORT_TOUCH_SENSOR_WAKEUP (1) /*! Date: Fri, 27 May 2022 02:11:25 +0800 Subject: [PATCH 7/7] test_rtc: add test_app to test power consumption --- .../test_apps/rtc_power_modes/CMakeLists.txt | 7 + .../test_apps/rtc_power_modes/README.md | 19 +++ .../rtc_power_modes/main/CMakeLists.txt | 2 + .../rtc_power_modes/main/test_app_main.c | 27 ++++ .../rtc_power_modes/main/test_rtc_power.c | 124 ++++++++++++++++++ .../rtc_power_modes/sdkconfig.defaults | 2 + 6 files changed, 181 insertions(+) create mode 100644 components/esp_system/test_apps/rtc_power_modes/CMakeLists.txt create mode 100644 components/esp_system/test_apps/rtc_power_modes/README.md create mode 100644 components/esp_system/test_apps/rtc_power_modes/main/CMakeLists.txt create mode 100644 components/esp_system/test_apps/rtc_power_modes/main/test_app_main.c create mode 100644 components/esp_system/test_apps/rtc_power_modes/main/test_rtc_power.c create mode 100644 components/esp_system/test_apps/rtc_power_modes/sdkconfig.defaults diff --git a/components/esp_system/test_apps/rtc_power_modes/CMakeLists.txt b/components/esp_system/test_apps/rtc_power_modes/CMakeLists.txt new file mode 100644 index 0000000000..a5579444f2 --- /dev/null +++ b/components/esp_system/test_apps/rtc_power_modes/CMakeLists.txt @@ -0,0 +1,7 @@ +# This is the project CMakeLists.txt file for the test subproject +cmake_minimum_required(VERSION 3.5) + +set(EXTRA_COMPONENT_DIRS "$ENV{IDF_PATH}/tools/unit-test-app/components") + +include($ENV{IDF_PATH}/tools/cmake/project.cmake) +project(rtc_power_modes) diff --git a/components/esp_system/test_apps/rtc_power_modes/README.md b/components/esp_system/test_apps/rtc_power_modes/README.md new file mode 100644 index 0000000000..5c923a3eee --- /dev/null +++ b/components/esp_system/test_apps/rtc_power_modes/README.md @@ -0,0 +1,19 @@ +| Supported Targets | ESP32-S3 | +| ----------------- | -------- | + +# RTC power test + +This test app is to enter 7 different sub power modes we have, so that the power consumption under different power modes can be measured. + +Currently there are 6 sub power modes, 3 for deepsleep and 3 for lightsleep. Show as below (priority from high to low). + +## Deepsleep +1. Mode for ADC/Temp Sensor in monitor mode (ULP). To enable this mode, call `rtc_sleep_enable_adc_tesn_monitor`. +2. Default mode. +3. Ultra low power mode. To enable this mode, call `rtc_sleep_enable_ultra_low`. Note if mode 1 has higher priority than this. + +## Lightsleep +1. Mode for using 40 MHz XTAL in lightsleep. To enable this mode, call `esp_sleep_pd_config(ESP_PD_DOMAIN_XTAL, ESP_PD_OPTION_ON)`. +2. Mode for using 8M clock by digital system (peripherals). To enable this mode, initialize LEDC with 8M clock source. +3. Mode for ADC/Temp Sensor in monitor mode (ULP). To enable this mdoe, call `rtc_sleep_enable_adc_tesn_monitor`. +4. Default mode. diff --git a/components/esp_system/test_apps/rtc_power_modes/main/CMakeLists.txt b/components/esp_system/test_apps/rtc_power_modes/main/CMakeLists.txt new file mode 100644 index 0000000000..201f4fcddb --- /dev/null +++ b/components/esp_system/test_apps/rtc_power_modes/main/CMakeLists.txt @@ -0,0 +1,2 @@ +idf_component_register(SRCS "test_rtc_power.c" + PRIV_REQUIRES unity) diff --git a/components/esp_system/test_apps/rtc_power_modes/main/test_app_main.c b/components/esp_system/test_apps/rtc_power_modes/main/test_app_main.c new file mode 100644 index 0000000000..1d34b63e44 --- /dev/null +++ b/components/esp_system/test_apps/rtc_power_modes/main/test_app_main.c @@ -0,0 +1,27 @@ +/* + * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "unity.h" +#include "unity_test_runner.h" +#include "unity_test_utils.h" + +#define LEAKS (400) + + +void setUp(void) +{ + unity_utils_record_free_mem(); +} + +void tearDown(void) +{ + unity_utils_evaluate_leaks_direct(LEAKS); +} + +void app_main(void) +{ + unity_run_menu(); +} diff --git a/components/esp_system/test_apps/rtc_power_modes/main/test_rtc_power.c b/components/esp_system/test_apps/rtc_power_modes/main/test_rtc_power.c new file mode 100644 index 0000000000..16d9ff09c2 --- /dev/null +++ b/components/esp_system/test_apps/rtc_power_modes/main/test_rtc_power.c @@ -0,0 +1,124 @@ +/* + * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include "esp_sleep.h" +#include "unity.h" +#include "esp_log.h" +#include "freertos/FreeRTOS.h" +#include "freertos/task.h" +#include "driver/uart.h" +#include "soc/soc_caps.h" +#include "driver/ledc.h" +#include "soc/rtc.h" + +static const char TAG[] = "rtc_power"; + +static void test_deepsleep(void) +{ + esp_sleep_enable_timer_wakeup(2000000); + ESP_LOGI(TAG, "Entering deep sleep"); + esp_deep_sleep_start(); +} + +TEST_CASE("Power Test: Deepsleep (with ADC/TSEN in monitor)", "[pm]") +{ + rtc_dig_clk8m_disable(); //This is workaround for bootloader not disable 8M as digital clock source + + extern void rtc_sleep_enable_adc_tesn_monitor(bool); + rtc_sleep_enable_adc_tesn_monitor(true); + test_deepsleep(); +} + +TEST_CASE("Power Test: Deepsleep (default)", "[pm]") +{ + rtc_dig_clk8m_disable(); //This is workaround for bootloader not disable 8M as digital clock source + + test_deepsleep(); +} + +TEST_CASE("Power Test: Deepsleep (ultra-low power)", "[pm]") +{ + rtc_dig_clk8m_disable(); //This is workaround for bootloader not disable 8M as digital clock source + + extern void rtc_sleep_enable_ultra_low(bool); + rtc_sleep_enable_ultra_low(true); + test_deepsleep(); +} + +static void test_lightsleep(void) +{ + esp_sleep_enable_timer_wakeup(2000000); + + while (true) { + printf("Entering light sleep\n"); + /* To make sure the complete line is printed before entering sleep mode, + * need to wait until UART TX FIFO is empty: + */ + uart_wait_tx_idle_polling(CONFIG_ESP_CONSOLE_UART_NUM); + + /* Enter sleep mode */ + esp_light_sleep_start(); + + /* Determine wake up reason */ + const char* wakeup_reason; + switch (esp_sleep_get_wakeup_cause()) { + case ESP_SLEEP_WAKEUP_TIMER: + wakeup_reason = "timer"; + break; + default: + wakeup_reason = "other"; + break; + } + printf("Returned from light sleep, reason: %s\n", wakeup_reason); + + vTaskDelay(1000/portTICK_PERIOD_MS); + } +} + +TEST_CASE("Power Test: Lightsleep (XTAL 40M)", "[pm]") +{ + rtc_dig_clk8m_disable(); //This is workaround for bootloader not disable 8M as digital clock source + + esp_sleep_pd_config(ESP_PD_DOMAIN_XTAL, ESP_PD_OPTION_ON); + test_lightsleep(); +} + +TEST_CASE("Power Test: Lightsleep (8M by digital)", "[pm]") +{ + rtc_dig_clk8m_disable(); //This is workaround for bootloader not disable 8M as digital clock source + + ledc_timer_config_t config = { + .speed_mode = LEDC_LOW_SPEED_MODE, + .duty_resolution = LEDC_TIMER_12_BIT, + .timer_num = 0, + .freq_hz = 2 * 1000, + .clk_cfg = LEDC_USE_RTC8M_CLK, + }; + ledc_timer_config(&config); + test_lightsleep(); +} + +TEST_CASE("Power Test: Lightsleep (with ADC/TSEN in monitor)", "[pm]") +{ + rtc_dig_clk8m_disable(); //This is workaround for bootloader not disable 8M as digital clock source + + extern void rtc_sleep_enable_adc_tesn_monitor(bool); + rtc_sleep_enable_adc_tesn_monitor(true); + test_lightsleep(); +} + +TEST_CASE("Power Test: Lightsleep (default)", "[pm]") +{ + rtc_dig_clk8m_disable(); //This is workaround for bootloader not disable 8M as digital clock source + test_lightsleep(); +} + +void app_main(void) +{ + unity_run_menu(); +} diff --git a/components/esp_system/test_apps/rtc_power_modes/sdkconfig.defaults b/components/esp_system/test_apps/rtc_power_modes/sdkconfig.defaults new file mode 100644 index 0000000000..b308cb2ddd --- /dev/null +++ b/components/esp_system/test_apps/rtc_power_modes/sdkconfig.defaults @@ -0,0 +1,2 @@ +CONFIG_FREERTOS_HZ=1000 +CONFIG_ESP_TASK_WDT=n