diff --git a/components/bootloader_support/src/esp32/bootloader_esp32.c b/components/bootloader_support/src/esp32/bootloader_esp32.c index f57816a4ec..26468105ce 100644 --- a/components/bootloader_support/src/esp32/bootloader_esp32.c +++ b/components/bootloader_support/src/esp32/bootloader_esp32.c @@ -167,7 +167,7 @@ esp_err_t bootloader_init(void) #if XCHAL_ERRATUM_572 uint32_t memctl = XCHAL_CACHE_MEMCTL_DEFAULT; - WSR(MEMCTL, memctl); + WSR(XT_REG_MEMCTL, memctl); #endif // XCHAL_ERRATUM_572 // In RAM_APP, memory will be initialized in `call_start_cpu0` diff --git a/components/bootloader_support/src/esp32s3/bootloader_esp32s3.c b/components/bootloader_support/src/esp32s3/bootloader_esp32s3.c index 56f1dda2bb..777ead0e1a 100644 --- a/components/bootloader_support/src/esp32s3/bootloader_esp32s3.c +++ b/components/bootloader_support/src/esp32s3/bootloader_esp32s3.c @@ -144,7 +144,7 @@ esp_err_t bootloader_init(void) #if XCHAL_ERRATUM_572 uint32_t memctl = XCHAL_CACHE_MEMCTL_DEFAULT; - WSR(MEMCTL, memctl); + WSR(XT_REG_MEMCTL, memctl); #endif // XCHAL_ERRATUM_572 bootloader_ana_reset_config(); diff --git a/components/bt/controller/esp32/hli_vectors.S b/components/bt/controller/esp32/hli_vectors.S index 2af6ffae7c..25a631d7ed 100644 --- a/components/bt/controller/esp32/hli_vectors.S +++ b/components/bt/controller/esp32/hli_vectors.S @@ -57,17 +57,17 @@ xt_highint4: wsr a0, CCOMPARE2 /* Enable Timer 2 interrupt */ - rsr a0, INTENABLE + rsr a0, XT_REG_INTENABLE extui a0, a0, 16, 1 bnez a0, 1f movi a0, 0 - xsr a0, INTENABLE /* disable all interrupts */ + xsr a0, XT_REG_INTENABLE /* disable all interrupts */ /* And a0 with (1 << 16) for Timer 2 interrupt mask */ addmi a0, a0, (1<<14) addmi a0, a0, (1<<14) addmi a0, a0, (1<<14) addmi a0, a0, (1<<14) - wsr a0, INTENABLE /* Enable Timer 2 */ + wsr a0, XT_REG_INTENABLE /* Enable Timer 2 */ 1: #endif @@ -76,37 +76,37 @@ xt_highint4: s32i a1, a0, 4 s32i a2, a0, 8 s32i a3, a0, 12 - rsr a2, EXCSAVE_4 /* holds the value of a0 */ + rsr a2, XT_REG_EXCSAVE_4 /* holds the value of a0 */ s32i a2, a0, 0 /* Save special registers */ addi a0, a0, SPECREG_OFFSET - rsr a2, WINDOWBASE + rsr a2, XT_REG_WINDOWBASE s32i a2, a0, 0 - rsr a2, WINDOWSTART + rsr a2, XT_REG_WINDOWSTART s32i a2, a0, 4 - rsr a2, SAR + rsr a2, XT_REG_SAR s32i a2, a0, 8 - rsr a2, LBEG + rsr a2, XT_REG_LBEG s32i a2, a0, 12 - rsr a2, LEND + rsr a2, XT_REG_LEND s32i a2, a0, 16 - rsr a2, LCOUNT + rsr a2, XT_REG_LCOUNT s32i a2, a0, 20 rsr a2, EPC1 s32i a2, a0, 24 #if CONFIG_ESP32_ECO3_CACHE_LOCK_FIX movi a0, 0 - xsr a0, INTENABLE /* disable all interrupts */ + xsr a0, XT_REG_INTENABLE /* disable all interrupts */ movi a2, ~(1<<16) and a0, a2, a0 - wsr a0, INTENABLE + wsr a0, XT_REG_INTENABLE #endif /* disable exception mode, window overflow */ movi a0, PS_INTLEVEL(5) | PS_EXCM - wsr a0, PS + wsr a0, XT_REG_PS rsync /* Save the remaining physical registers. @@ -153,12 +153,12 @@ xt_highint4: /* a0 still points to _l4_save_ctx */ /* Can clear WINDOWSTART now, all registers are saved */ - rsr a2, WINDOWBASE + rsr a2, XT_REG_WINDOWBASE /* WINDOWSTART = (1 << WINDOWBASE) */ movi a3, 1 ssl a2 sll a3, a3 - wsr a3, WINDOWSTART + wsr a3, XT_REG_WINDOWSTART _highint4_stack_switch: movi a0, 0 @@ -169,7 +169,7 @@ _highint4_stack_switch: /* Set up PS for C, disable all interrupts except NMI and debug, and clear EXCM. */ movi a6, PS_INTLEVEL(4) | PS_UM | PS_WOE - wsr a6, PS + wsr a6, XT_REG_PS rsync /* Call C handler */ @@ -180,7 +180,7 @@ _highint4_stack_switch: /* Done with C handler; re-enable exception mode, disabling window overflow */ movi a2, PS_INTLEVEL(5) | PS_EXCM /* TOCHECK */ - wsr a2, PS + wsr a2, XT_REG_PS rsync /* Restore the special registers. @@ -188,13 +188,13 @@ _highint4_stack_switch: */ movi a0, _l4_save_ctx + SPECREG_OFFSET l32i a2, a0, 8 - wsr a2, SAR + wsr a2, XT_REG_SAR l32i a2, a0, 12 - wsr a2, LBEG + wsr a2, XT_REG_LBEG l32i a2, a0, 16 - wsr a2, LEND + wsr a2, XT_REG_LEND l32i a2, a0, 20 - wsr a2, LCOUNT + wsr a2, XT_REG_LCOUNT l32i a2, a0, 24 wsr a2, EPC1 @@ -247,12 +247,12 @@ _highint4_stack_switch: movi a0, _l4_save_ctx l32i a2, a0, SPECREG_OFFSET + 4 - wsr a2, WINDOWSTART + wsr a2, XT_REG_WINDOWSTART l32i a1, a0, 4 l32i a2, a0, 8 l32i a3, a0, 12 - rsr a0, EXCSAVE_4 /* holds the value of a0 before the interrupt handler */ + rsr a0, XT_REG_EXCSAVE_4 /* holds the value of a0 before the interrupt handler */ /* Return from the interrupt, restoring PS from EPS_4 */ rfi 4 diff --git a/components/esp_gdbstub/src/port/xtensa/gdbstub-entry.S b/components/esp_gdbstub/src/port/xtensa/gdbstub-entry.S index adc423d3f0..bfabdf2df3 100644 --- a/components/esp_gdbstub/src/port/xtensa/gdbstub-entry.S +++ b/components/esp_gdbstub/src/port/xtensa/gdbstub-entry.S @@ -24,9 +24,9 @@ esp_gdbstub_int: #if XCHAL_HAVE_WINDOWED s32e a0, sp, -12 /* for debug backtrace */ #endif - rsr a0, PS /* save interruptee's PS */ + rsr a0, XT_REG_PS /* save interruptee's PS */ s32i a0, sp, XT_STK_PS - rsr a0, EPC_1 /* save interruptee's PC */ + rsr a0, XT_REG_EPC_1 /* save interruptee's PC */ s32i a0, sp, XT_STK_PC #if XCHAL_HAVE_WINDOWED s32e a0, sp, -16 /* for debug backtrace */ @@ -35,21 +35,21 @@ esp_gdbstub_int: s32i a13, sp, XT_STK_A13 /* A13 to have already been saved */ /* Save exc cause and vaddr into exception frame */ - rsr a0, EXCCAUSE + rsr a0, XT_REG_EXCCAUSE s32i a0, sp, XT_STK_EXCCAUSE - rsr a0, EXCVADDR + rsr a0, XT_REG_EXCVADDR s32i a0, sp, XT_STK_EXCVADDR /* _xt_context_save seems to save the current a0, but we need the interuptees a0. Fix this. */ - rsr a0, EXCSAVE_1 /* save interruptee's a0 */ + rsr a0, XT_REG_EXCSAVE_1 /* save interruptee's a0 */ s32i a0, sp, XT_STK_A0 /* Save context pointer as input parameter */ rsr a6, excsave1 - rsr a3, EPS + rsr a3, XT_REG_EPS s32i a3, sp, XT_STK_PS // store PS to the ps place movi a3, gdbstub_handle_uart_int callx0 a3 diff --git a/components/esp_gdbstub/src/port/xtensa/gdbstub_xtensa.c b/components/esp_gdbstub/src/port/xtensa/gdbstub_xtensa.c index 99141e94b3..60eaa7bc80 100644 --- a/components/esp_gdbstub/src/port/xtensa/gdbstub_xtensa.c +++ b/components/esp_gdbstub/src/port/xtensa/gdbstub_xtensa.c @@ -7,7 +7,7 @@ #include #include "esp_gdbstub_common.h" #include "soc/soc_memory_layout.h" -#include "xtensa/config/specreg.h" +#include "xtensa/config/xt_specreg.h" #include "sdkconfig.h" #include "esp_cpu.h" #include "esp_ipc_isr.h" @@ -35,8 +35,8 @@ static void update_regfile_common(esp_gdbstub_gdb_regfile_t *dst) } dst->windowbase = 0; dst->windowstart = 0x1; - RSR(CONFIGID0, dst->configid0); - RSR(CONFIGID1, dst->configid1); + RSR(XT_REG_CONFIGID0, dst->configid0); + RSR(XT_REG_CONFIGID1, dst->configid1); } #if XCHAL_HAVE_FP @@ -111,7 +111,7 @@ void esp_gdbstub_frame_to_regfile(const esp_gdbstub_frame_t *frame, esp_gdbstub_ current_tcb_ptr = pxCurrentTCBs[esp_cpu_get_core_id()]; #endif uint32_t cp_enabled; - RSR(CPENABLE, cp_enabled); + RSR(XT_REG_CPENABLE, cp_enabled); // Check if the co-processor is enabled if (cp_enabled) { @@ -182,7 +182,7 @@ void esp_gdbstub_tcb_frame_to_regfile(dummy_tcb_t *tcb, esp_gdbstub_gdb_regfile_ #endif uint32_t cp_enabled; - RSR(CPENABLE, cp_enabled); + RSR(XT_REG_CPENABLE, cp_enabled); void *current_tcb_ptr = tcb; uint32_t *current_fpu_ptr = NULL; @@ -309,8 +309,8 @@ void esp_gdbstub_stall_other_cpus_end(void) * */ void esp_gdbstub_clear_step(void) { - WSR(ICOUNT, 0); - WSR(ICOUNTLEVEL, 0); + WSR(XT_REG_ICOUNT, 0); + WSR(XT_REG_ICOUNTLEVEL, 0); } /** @brief GDB do step @@ -326,8 +326,8 @@ void esp_gdbstub_do_step( esp_gdbstub_frame_t *frame) level &= 0x7; level += 1; - WSR(ICOUNTLEVEL, level); - WSR(ICOUNT, -2); + WSR(XT_REG_ICOUNTLEVEL, level); + WSR(XT_REG_ICOUNT, -2); } /** @brief GDB trigger other CPU @@ -364,7 +364,7 @@ void esp_gdbstub_set_register(esp_gdbstub_frame_t *frame, uint32_t reg_index, ui #if XCHAL_HAVE_FP void *ptr1; uint32_t cp_enabled; - RSR(CPENABLE, cp_enabled); + RSR(XT_REG_CPENABLE, cp_enabled); if (cp_enabled != 0) { if (reg_index == 87) { asm volatile ("lsi f0, %0, 0" :: "a" (ptr0)); diff --git a/components/esp_gdbstub/src/port/xtensa/xt_debugexception.S b/components/esp_gdbstub/src/port/xtensa/xt_debugexception.S index da9b489077..40cbb68129 100644 --- a/components/esp_gdbstub/src/port/xtensa/xt_debugexception.S +++ b/components/esp_gdbstub/src/port/xtensa/xt_debugexception.S @@ -22,9 +22,9 @@ _xt_panic_gdbstub: s32i a0, sp, XT_STK_EXIT s32i a0, sp, XT_STK_A0 - rsr a0, PS /* save interruptee's PS */ + rsr a0, XT_REG_PS /* save interruptee's PS */ s32i a0, sp, XT_STK_PS - rsr a0, EPC_1 /* save interruptee's PC */ + rsr a0, XT_REG_EPC_1 /* save interruptee's PC */ s32i a0, sp, XT_STK_PC call0 _xt_context_save /* Save full context*/ addi a7, sp, XT_STK_FRMSZ @@ -33,29 +33,29 @@ _xt_panic_gdbstub: s32i a13, sp, XT_STK_A13 /* Save exc cause and vaddr into exception frame */ - rsr a0, EXCCAUSE + rsr a0, XT_REG_EXCCAUSE s32i a0, sp, XT_STK_EXCCAUSE - rsr a0, EXCVADDR + rsr a0, XT_REG_EXCVADDR s32i a0, sp, XT_STK_EXCVADDR /* _xt_context_save seems to save the current a0, but we need the interuptees a0. Fix this. */ - rsr a0, EXCSAVE_1 /* save interruptee's a0 */ + rsr a0, XT_REG_EXCSAVE_1 /* save interruptee's a0 */ /* Set up PS for C, disable all interrupts except NMI and debug, and clear EXCM. */ movi a0, PS_INTLEVEL(5) | PS_UM | PS_WOE - wsr a0, PS + wsr a0, XT_REG_PS //Call gdbstub handler - rsr a0,(EPC + XCHAL_DEBUGLEVEL) + rsr a0,(XT_REG_EPC + XCHAL_DEBUGLEVEL) s32i a0, sp, XT_STK_PC mov a6, sp - rsr a9, EPS_6 + rsr a9, XT_REG_EPS_6 s32i a9, sp, XT_STK_PS // store PS to the ps place movi a11, gdbstub_handle_debug_int callx4 a11 /* Call interrupt handler */ l32i a0, sp, XT_STK_PC - wsr a0,(EPC + XCHAL_DEBUGLEVEL) + wsr a0,(XT_REG_EPC + XCHAL_DEBUGLEVEL) call0 _xt_context_restore /* Restore full context*/ l32i a12, sp, XT_STK_A12 l32i a13, sp, XT_STK_A13 diff --git a/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/test_dport.c b/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/test_dport.c index 834771d629..fa6d329c40 100644 --- a/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/test_dport.c +++ b/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/test_dport.c @@ -307,11 +307,11 @@ TEST_CASE("test for DPORT access performance", "[esp32]") static uint32_t start, end; #define BENCHMARK_START() do { \ - RSR(CCOUNT, start); \ + RSR(XT_REG_CCOUNT, start); \ } while(0) #define BENCHMARK_END(OPERATION) do { \ - RSR(CCOUNT, end); \ + RSR(XT_REG_CCOUNT, end); \ printf("%s took %"PRIu32" cycles/op (%"PRIu32" cycles for %d ops)\n", \ OPERATION, (end - start)/REPEAT_OPS, \ (end - start), REPEAT_OPS); \ diff --git a/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/test_dport_xt_highint5.S b/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/test_dport_xt_highint5.S index 40589b1192..1b644099fd 100644 --- a/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/test_dport_xt_highint5.S +++ b/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/test_dport_xt_highint5.S @@ -40,7 +40,7 @@ xt_highint5: wsr a0, CCOMPARE2 esync - rsr a0, EXCSAVE_5 // restore a0 + rsr a0, XT_REG_EXCSAVE_5 // restore a0 rfi 5 @@ -74,7 +74,7 @@ xt_highint5: l32i a4, a0, L5_INTR_A4_OFFSET rsync .L_xt_highint5_exit: - rsr a0, EXCSAVE_5 // restore a0 + rsr a0, XT_REG_EXCSAVE_5 // restore a0 rfi 5 /* The linker has no reason to link in this file; all symbols it exports are already defined diff --git a/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/test_fp.c b/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/test_fp.c index 22ca5ba699..217d94ce9d 100644 --- a/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/test_fp.c +++ b/components/esp_hw_support/test_apps/esp_hw_support_unity_tests/main/test_fp.c @@ -215,13 +215,13 @@ float IRAM_ATTR test_fp_benchmark_fp_divide(int counts, unsigned *cycles) { float f = MAXFLOAT; uint32_t before, after; - RSR(CCOUNT, before); + RSR(XT_REG_CCOUNT, before); for (int i = 0; i < counts; i++) { f /= 1.000432f; } - RSR(CCOUNT, after); + RSR(XT_REG_CCOUNT, after); *cycles = (after - before) / counts; return f; @@ -254,13 +254,13 @@ float IRAM_ATTR test_fp_benchmark_fp_sqrt(int counts, unsigned *cycles) { float f = MAXFLOAT; uint32_t before, after; - RSR(CCOUNT, before); + RSR(XT_REG_CCOUNT, before); for (int i = 0; i < counts; i++) { f = sqrtf(f); } - RSR(CCOUNT, after); + RSR(XT_REG_CCOUNT, after); *cycles = (after - before) / counts; return f; diff --git a/components/esp_system/port/arch/xtensa/esp_ipc_isr_handler.S b/components/esp_system/port/arch/xtensa/esp_ipc_isr_handler.S index 2d6d6a5032..2779a813bc 100644 --- a/components/esp_system/port/arch/xtensa/esp_ipc_isr_handler.S +++ b/components/esp_system/port/arch/xtensa/esp_ipc_isr_handler.S @@ -21,7 +21,7 @@ #define LX_INTR_A2_OFFSET 4 #define LX_INTR_A3_OFFSET 8 #define LX_INTR_A4_OFFSET 12 -#define EXCSAVE_X EXCSAVE_5 +#define XT_REG_EXCSAVE_X XT_REG_EXCSAVE_5 #define RFI_X 5 #elif CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_4 @@ -31,7 +31,7 @@ #define LX_INTR_A2_OFFSET 4 #define LX_INTR_A3_OFFSET 8 #define LX_INTR_A4_OFFSET 12 -#define EXCSAVE_X EXCSAVE_4 +#define XT_REG_EXCSAVE_X XT_REG_EXCSAVE_4 #define RFI_X 4 #endif /* CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_5 */ @@ -55,14 +55,14 @@ esp_ipc_isr_handler: s32i a2, a0, LX_INTR_A2_OFFSET s32i a3, a0, LX_INTR_A3_OFFSET s32i a4, a0, LX_INTR_A4_OFFSET - rsr a2, EXCSAVE_X + rsr a2, XT_REG_EXCSAVE_X s32i a2, a0, LX_INTR_A0_OFFSET - /* disable nested iterrupts */ + /* disable nested interrupts */ /* PS.EXCM is changed from 1 to 0 . It allows using usually exception handler instead of the Double exception handler. */ /* PS_UM = 1 */ movi a0, PS_INTLEVEL(5) | PS_UM - wsr a0, PS + wsr a0, XT_REG_PS rsync /* restore PS will be done by rfi the end */ @@ -75,7 +75,7 @@ esp_ipc_isr_handler: #elif CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_4 /* This int is edge-triggered and needs clearing. */ movi a3, (1 << ETS_IPC_ISR_INUM) - wsr a3, INTCLEAR + wsr a3, XT_REG_INTCLEAR #endif /* CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_5 */ /* get CORE_ID */ @@ -118,6 +118,6 @@ esp_ipc_isr_handler: s32i a0, a0, 0 /* restore a0 */ - rsr a0, EXCSAVE_X + rsr a0, XT_REG_EXCSAVE_X /* restores PS from EPS[X] and jumps to the address in EPC[X] */ rfi RFI_X diff --git a/components/esp_system/port/arch/xtensa/panic_handler_asm.S b/components/esp_system/port/arch/xtensa/panic_handler_asm.S index a452c5f6a1..2e42364152 100644 --- a/components/esp_system/port/arch/xtensa/panic_handler_asm.S +++ b/components/esp_system/port/arch/xtensa/panic_handler_asm.S @@ -1,3 +1,8 @@ +/* + * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #include "freertos/xtensa_rtos.h" #include "esp_private/panic_reason.h" #include "soc/soc.h" @@ -31,11 +36,11 @@ _xt_panic: #if XCHAL_HAVE_WINDOWED s32e a0, sp, -12 /* for debug backtrace */ #endif - rsr a0, PS /* save interruptee's PS */ + rsr a0, XT_REG_PS /* save interruptee's PS */ s32i a0, sp, XT_STK_PS - rsr a0, EPC_1 /* save interruptee's PC */ + rsr a0, XT_REG_EPC_1 /* save interruptee's PC */ s32i a0, sp, XT_STK_PC - rsr a0, EXCSAVE_1 /* save interruptee's a0 */ + rsr a0, XT_REG_EXCSAVE_1 /* save interruptee's a0 */ s32i a0, sp, XT_STK_A0 #if XCHAL_HAVE_WINDOWED s32e a0, sp, -16 /* for debug backtrace */ @@ -45,14 +50,14 @@ _xt_panic: call0 _xt_context_save /* Save exc cause and vaddr into exception frame */ - rsr a0, EXCCAUSE + rsr a0, XT_REG_EXCCAUSE s32i a0, sp, XT_STK_EXCCAUSE - rsr a0, EXCVADDR + rsr a0, XT_REG_EXCVADDR s32i a0, sp, XT_STK_EXCVADDR /* Set up PS for C, disable all interrupts except NMI and debug, and clear EXCM. */ movi a0, PS_INTLEVEL(XCHAL_DEBUGLEVEL - 2) | PS_UM | PS_WOE - wsr a0, PS + wsr a0, XT_REG_PS //Call panic handler mov a6,sp diff --git a/components/esp_system/port/soc/esp32/highint_hdl.S b/components/esp_system/port/soc/esp32/highint_hdl.S index 1cc51b18dd..a8ea491ddb 100644 --- a/components/esp_system/port/soc/esp32/highint_hdl.S +++ b/components/esp_system/port/soc/esp32/highint_hdl.S @@ -32,8 +32,8 @@ Interrupt , a high-priority interrupt, is used for several things: #define LX_INTR_A2_OFFSET 0 #define LX_INTR_A3_OFFSET 4 #define LX_INTR_A4_OFFSET 8 -#define EPC_X EPC_5 -#define EXCSAVE_X EXCSAVE_5 +#define XT_REG_EPC_X XT_REG_EPC_5 +#define XT_REG_EXCSAVE_X XT_REG_EXCSAVE_5 #define RFI_X 5 #define xt_highintx xt_highint5 @@ -43,8 +43,8 @@ Interrupt , a high-priority interrupt, is used for several things: #define LX_INTR_A2_OFFSET 0 #define LX_INTR_A3_OFFSET 4 #define LX_INTR_A4_OFFSET 8 -#define EPC_X EPC_4 -#define EXCSAVE_X EXCSAVE_4 +#define XT_REG_EPC_X XT_REG_EPC_4 +#define XT_REG_EXCSAVE_X XT_REG_EXCSAVE_4 #define RFI_X 4 #define xt_highintx xt_highint4 @@ -114,7 +114,7 @@ Interrupt , a high-priority interrupt, is used for several things: .endm .macro get_int_status_tg1wdt reg - rsr \reg, INTERRUPT + rsr \reg, XT_REG_INTERRUPT extui \reg, \reg, ETS_T1_WDT_CACHEERR_INUM, 1 beqz \reg, 99f /* not ETS_T1_WDT_INUM or ETS_CACHEERR_INUM */ @@ -165,7 +165,7 @@ xt_highintx: #ifndef CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE /* See if we're here for the IPC_ISR interrupt */ - rsr a0, INTERRUPT + rsr a0, XT_REG_INTERRUPT extui a0, a0, ETS_IPC_ISR_INUM, 1 beqz a0, 1f /* Jump to `esp_ipc_isr_handler` which is non-returning. We need to use `jx` @@ -182,10 +182,10 @@ xt_highintx: #if CONFIG_BTDM_CTRL_HLI /* Timer 2 interrupt */ - rsr a0, INTENABLE + rsr a0, XT_REG_INTENABLE extui a0, a0, 16, 1 beqz a0, 1f - rsr a0, INTERRUPT + rsr a0, XT_REG_INTERRUPT extui a0, a0, 16, 1 bnez a0, .handle_multicore_debug_int 1: @@ -219,11 +219,11 @@ xt_highintx: #if XCHAL_HAVE_WINDOWED s32e a0, sp, -12 /* for debug backtrace */ #endif - rsr a0, PS /* save interruptee's PS */ + rsr a0, XT_REG_PS /* save interruptee's PS */ s32i a0, sp, XT_STK_PS - rsr a0, EPC_X /* save interruptee's PC */ + rsr a0, XT_REG_EPC_X /* save interruptee's PC */ s32i a0, sp, XT_STK_PC - rsr a0, EXCSAVE_X /* save interruptee's a0 */ + rsr a0, XT_REG_EXCSAVE_X /* save interruptee's a0 */ s32i a0, sp, XT_STK_A0 #if XCHAL_HAVE_WINDOWED s32e a0, sp, -16 /* for debug backtrace */ @@ -233,7 +233,7 @@ xt_highintx: call0 _xt_context_save /* Save vaddr into exception frame */ - rsr a0, EXCVADDR + rsr a0, XT_REG_EXCVADDR s32i a0, sp, XT_STK_EXCVADDR /* Figure out reason, save into EXCCAUSE reg */ @@ -249,10 +249,10 @@ xt_highintx: #endif /* CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_5 */ /* Kill this interrupt; we cannot reset it. */ - rsr a0, INTENABLE + rsr a0, XT_REG_INTENABLE movi a4, ~(1<exccause; - s_extra_info.exccause.reg_index = EXCCAUSE; + s_extra_info.exccause.reg_index = XT_REG_EXCCAUSE; s_extra_info.excvaddr.reg_val = exc_frame->excvaddr; - s_extra_info.excvaddr.reg_index = EXCVADDR; + s_extra_info.excvaddr.reg_index = XT_REG_EXCVADDR; // get InterruptException registers into extra_info core_dump_reg_pair_t *regs_ptr = esp_core_dump_get_eps_regs(s_extra_info.extra_regs); esp_core_dump_get_epc_regs(regs_ptr); @@ -257,7 +257,7 @@ inline void esp_core_dump_port_init(panic_info_t *info, bool isr_context) s_extra_info.crashed_task_tcb = COREDUMP_CURR_TASK_MARKER; // Initialize exccause register to default value (required if current task corrupted) s_extra_info.exccause.reg_val = COREDUMP_INVALID_CAUSE_VALUE; - s_extra_info.exccause.reg_index = EXCCAUSE; + s_extra_info.exccause.reg_index = XT_REG_EXCCAUSE; XtExcFrame *s_exc_frame = (XtExcFrame *) info->frame; s_exc_frame->exit = COREDUMP_CURR_TASK_MARKER; @@ -486,10 +486,10 @@ void esp_core_dump_summary_parse_extra_info(esp_core_dump_summary_t *summary, vo memset(summary->ex_info.epcx, 0, sizeof(summary->ex_info.epcx)); summary->ex_info.epcx_reg_bits = 0; for (i = 0; i < COREDUMP_EXTRA_REG_NUM; i++) { - if (ei->extra_regs[i].reg_index >= EPC_1 - && ei->extra_regs[i].reg_index < (EPC_1 + XCHAL_NUM_INTLEVELS)) { - summary->ex_info.epcx[ei->extra_regs[i].reg_index - EPC_1] = ei->extra_regs[i].reg_val; - summary->ex_info.epcx_reg_bits |= (1 << (ei->extra_regs[i].reg_index - EPC_1)); + if (ei->extra_regs[i].reg_index >= XT_REG_EPC_1 + && ei->extra_regs[i].reg_index < (XT_REG_EPC_1 + XCHAL_NUM_INTLEVELS)) { + summary->ex_info.epcx[ei->extra_regs[i].reg_index - XT_REG_EPC_1] = ei->extra_regs[i].reg_val; + summary->ex_info.epcx_reg_bits |= (1 << (ei->extra_regs[i].reg_index - XT_REG_EPC_1)); } } } diff --git a/components/freertos/FreeRTOS-Kernel-SMP/portable/xtensa/include/freertos/portmacro.h b/components/freertos/FreeRTOS-Kernel-SMP/portable/xtensa/include/freertos/portmacro.h index 422ad60977..43a61fc2b4 100644 --- a/components/freertos/FreeRTOS-Kernel-SMP/portable/xtensa/include/freertos/portmacro.h +++ b/components/freertos/FreeRTOS-Kernel-SMP/portable/xtensa/include/freertos/portmacro.h @@ -12,7 +12,7 @@ #include "xtensa/xtruntime.h" #include "xtensa/config/core.h" #include "xtensa/config/core-isa.h" -#include "xtensa/config/specreg.h" +#include "xtensa/config/xt_specreg.h" #include "xt_instr_macros.h" #include "portbenchmark.h" #include "esp_macros.h" @@ -181,7 +181,7 @@ Note: XTOS_RESTORE_INTLEVEL() will overwrite entire PS register on XEA2. So we n */ #define portCLEAR_INTERRUPT_MASK(x) ({ \ unsigned int ps_reg; \ - RSR(PS, ps_reg); \ + RSR(XT_REG_PS, ps_reg); \ ps_reg = (ps_reg & ~XCHAL_PS_INTLEVEL_MASK); \ ps_reg |= ((x << XCHAL_PS_INTLEVEL_SHIFT) & XCHAL_PS_INTLEVEL_MASK); \ XTOS_RESTORE_INTLEVEL(ps_reg); \ @@ -360,7 +360,7 @@ static inline bool IRAM_ATTR xPortCanYield(void) uint32_t ps_reg = 0; //Get the current value of PS (processor status) register - RSR(PS, ps_reg); + RSR(XT_REG_PS, ps_reg); /* * intlevel = (ps_reg & 0xf); diff --git a/components/freertos/FreeRTOS-Kernel/portable/xtensa/include/freertos/portmacro.h b/components/freertos/FreeRTOS-Kernel/portable/xtensa/include/freertos/portmacro.h index 14091c9c05..4a5b0fb87d 100644 --- a/components/freertos/FreeRTOS-Kernel/portable/xtensa/include/freertos/portmacro.h +++ b/components/freertos/FreeRTOS-Kernel/portable/xtensa/include/freertos/portmacro.h @@ -604,7 +604,7 @@ FORCE_INLINE_ATTR bool xPortCanYield(void) uint32_t ps_reg = 0; //Get the current value of PS (processor status) register - RSR(PS, ps_reg); + RSR(XT_REG_PS, ps_reg); /* * intlevel = (ps_reg & 0xf); diff --git a/components/freertos/FreeRTOS-Kernel/portable/xtensa/portasm.S b/components/freertos/FreeRTOS-Kernel/portable/xtensa/portasm.S index c4723ee83f..756fae8481 100644 --- a/components/freertos/FreeRTOS-Kernel/portable/xtensa/portasm.S +++ b/components/freertos/FreeRTOS-Kernel/portable/xtensa/portasm.S @@ -281,7 +281,7 @@ _frxt_int_exit: * Manages the tick timer and calls xPortSysTickHandler() every tick. * See the detailed description of the XT_RTOS_ENTER macro in xtensa_rtos.h. * -* Callable from C (obeys ABI conventions). Implemented in assmebly code for performance. +* Callable from C (obeys ABI conventions). Implemented in assembly code for performance. * ********************************************************************************************************** */ @@ -352,7 +352,7 @@ _frxt_timer_int: /* Check if we need to process more ticks to catch up. */ esync /* ensure comparator update complete */ - rsr a4, CCOUNT /* a4 = cycle count */ + rsr a4, XT_REG_CCOUNT /* a4 = cycle count */ sub a4, a4, a3 /* diff = ccount - old comparator */ blt a2, a4, .L_xt_timer_int_catchup /* repeat while diff > divisor */ @@ -370,7 +370,7 @@ _frxt_timer_int: * _frxt_tick_timer_init * void _frxt_tick_timer_init(void) * -* Initialize timer and timer interrrupt handler (_xt_tick_divisor_init() has already been been called). +* Initialize timer and timer interrupt handler (_xt_tick_divisor_init() has already been been called). * Callable from C (obeys ABI conventions on entry). * ********************************************************************************************************** @@ -391,7 +391,7 @@ _frxt_tick_timer_init: movi a2, _xt_tick_divisor l32i a3, a2, 0 #endif - rsr a2, CCOUNT /* current cycle count */ + rsr a2, XT_REG_CCOUNT /* current cycle count */ add a2, a2, a3 /* time of first timer interrupt */ wsr a2, XT_CCOMPARE /* set the comparator */ @@ -481,7 +481,7 @@ _frxt_dispatch: rsync #endif /* As soons as PS is restored, interrupts can happen. No need to sync PS. */ - wsr a3, PS + wsr a3, XT_REG_PS #ifdef __XTENSA_CALL0_ABI__ addi sp, sp, XT_SOL_FRMSZ ret @@ -499,7 +499,7 @@ _frxt_dispatch: l32i a2, a2, 0 get_cpsa_from_tcb a2, a3 /* After this, pointer to CP save area is in a2, a3 is destroyed */ l16ui a3, a2, XT_CPENABLE /* CPENABLE = cp_state->cpenable; */ - wsr a3, CPENABLE + wsr a3, XT_REG_CPENABLE #endif /* Interrupt stack frame. Restore full context and return to exit dispatcher. */ @@ -552,7 +552,7 @@ vPortYield: entry sp, XT_SOL_FRMSZ #endif - rsr a2, PS + rsr a2, XT_REG_PS s32i a0, sp, XT_SOL_PC s32i a2, sp, XT_SOL_PS #if XCHAL_HAVE_THREADPTR @@ -571,11 +571,11 @@ vPortYield: movi a6, ~(PS_WOE_MASK|PS_INTLEVEL_MASK) /* spills a4-a7 if needed */ and a2, a2, a6 /* clear WOE, INTLEVEL */ addi a2, a2, XCHAL_EXCM_LEVEL /* set INTLEVEL */ - wsr a2, PS + wsr a2, XT_REG_PS rsync call0 xthal_window_spill_nw l32i a2, sp, XT_SOL_PS /* restore PS */ - wsr a2, PS + wsr a2, XT_REG_PS #endif rsil a2, XCHAL_EXCM_LEVEL /* disable low/med interrupts */ @@ -598,7 +598,7 @@ vPortYield: /* Clear CPENABLE, also in task's co-processor state save area. */ get_cpsa_from_tcb a2, a3 /* After this, pointer to CP save area is in a2, a3 is destroyed */ movi a3, 0 - wsr a3, CPENABLE + wsr a3, XT_REG_CPENABLE beqz a2, 1f s16i a3, a2, XT_CPENABLE /* clear saved cpenable */ 1: @@ -644,10 +644,10 @@ vPortYieldFromInt: get_cpsa_from_tcb a2, a3 /* After this, pointer to CP save area is in a2, a3 is destroyed */ - rsr a3, CPENABLE + rsr a3, XT_REG_CPENABLE s16i a3, a2, XT_CPENABLE /* cp_state->cpenable = CPENABLE; */ movi a3, 0 - wsr a3, CPENABLE /* disable all co-processors */ + wsr a3, XT_REG_CPENABLE /* disable all co-processors */ #endif #ifdef __XTENSA_CALL0_ABI__ diff --git a/components/hal/esp32s3/include/hal/dedic_gpio_cpu_ll.h b/components/hal/esp32s3/include/hal/dedic_gpio_cpu_ll.h index b11330fbf6..faeb9cdfff 100644 --- a/components/hal/esp32s3/include/hal/dedic_gpio_cpu_ll.h +++ b/components/hal/esp32s3/include/hal/dedic_gpio_cpu_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -8,15 +8,6 @@ #include -#include "soc/soc_caps.h" - -#include "xt_instr_macros.h" -#include "xtensa/config/specreg.h" -#include "xtensa/config/extreg.h" -#include "esp_bit_defs.h" -#include "esp_attr.h" -#include "xtensa/config/core.h" - #ifdef __cplusplus extern "C" { #endif diff --git a/components/xtensa/esp32/include/xtensa/config/specreg.h b/components/xtensa/esp32/include/xtensa/config/specreg.h index 2da7bae5b0..9015ded38c 100644 --- a/components/xtensa/esp32/include/xtensa/config/specreg.h +++ b/components/xtensa/esp32/include/xtensa/config/specreg.h @@ -28,6 +28,8 @@ #ifndef XTENSA_SPECREG_H #define XTENSA_SPECREG_H +#warning "xtensa/config/specreg.h is deprecated, please use xtensa/config/xt_specreg.h instead" + /* Include these special register bitfield definitions, for historical reasons: */ #include diff --git a/components/xtensa/esp32/include/xtensa/config/xt_specreg.h b/components/xtensa/esp32/include/xtensa/config/xt_specreg.h new file mode 100644 index 0000000000..380fe61961 --- /dev/null +++ b/components/xtensa/esp32/include/xtensa/config/xt_specreg.h @@ -0,0 +1,124 @@ +/* + * Xtensa Special Register symbolic names + */ + +/* SPDX-FileCopyrightText: 1998-2002 Tensilica Inc. + * + * SPDX-License-Identifier: MIT + * + * SPDX-FileContributor: 2025 Espressif Systems (Shanghai) CO LTD + */ + +/* $Id: //depot/rel/Eaglenest/Xtensa/SWConfig/hal/specreg.h.tpp#1 $ */ + +/* Customer ID=11657; Build=0x5fe96; Copyright (c) 1998-2002 Tensilica Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + +#ifndef XTENSA_XT_SPECREG_H +#define XTENSA_XT_SPECREG_H + +/* Include these special register bitfield definitions, for historical reasons: */ +#include + +/* Special registers: */ +#define XT_REG_LBEG 0 +#define XT_REG_LEND 1 +#define XT_REG_LCOUNT 2 +#define XT_REG_SAR 3 +#define XT_REG_BR 4 +#define XT_REG_SCOMPARE1 12 +#define XT_REG_ACCLO 16 +#define XT_REG_ACCHI 17 +#define XT_REG_MR_0 32 +#define XT_REG_MR_1 33 +#define XT_REG_MR_2 34 +#define XT_REG_MR_3 35 +#define XT_REG_WINDOWBASE 72 +#define XT_REG_WINDOWSTART 73 +#define XT_REG_IBREAKENABLE 96 +#define XT_REG_MEMCTL 97 +#define XT_REG_ATOMCTL 99 +#define XT_REG_DDR 104 +#define XT_REG_IBREAKA_0 128 +#define XT_REG_IBREAKA_1 129 +#define XT_REG_DBREAKA_0 144 +#define XT_REG_DBREAKA_1 145 +#define XT_REG_DBREAKC_0 160 +#define XT_REG_DBREAKC_1 161 +#define XT_REG_CONFIGID0 176 +#define XT_REG_EPC_1 177 +#define XT_REG_EPC_2 178 +#define XT_REG_EPC_3 179 +#define XT_REG_EPC_4 180 +#define XT_REG_EPC_5 181 +#define XT_REG_EPC_6 182 +#define XT_REG_EPC_7 183 +#define XT_REG_DEPC 192 +#define XT_REG_EPS_2 194 +#define XT_REG_EPS_3 195 +#define XT_REG_EPS_4 196 +#define XT_REG_EPS_5 197 +#define XT_REG_EPS_6 198 +#define XT_REG_EPS_7 199 +#define XT_REG_CONFIGID1 208 +#define XT_REG_EXCSAVE_1 209 +#define XT_REG_EXCSAVE_2 210 +#define XT_REG_EXCSAVE_3 211 +#define XT_REG_EXCSAVE_4 212 +#define XT_REG_EXCSAVE_5 213 +#define XT_REG_EXCSAVE_6 214 +#define XT_REG_EXCSAVE_7 215 +#define XT_REG_CPENABLE 224 +#define XT_REG_INTERRUPT 226 +#define XT_REG_INTENABLE 228 +#define XT_REG_PS 230 +#define XT_REG_VECBASE 231 +#define XT_REG_EXCCAUSE 232 +#define XT_REG_DEBUGCAUSE 233 +#define XT_REG_CCOUNT 234 +#define XT_REG_PRID 235 +#define XT_REG_ICOUNT 236 +#define XT_REG_ICOUNTLEVEL 237 +#define XT_REG_EXCVADDR 238 +#define XT_REG_CCOMPARE_0 240 +#define XT_REG_CCOMPARE_1 241 +#define XT_REG_CCOMPARE_2 242 +#define XT_REG_MISC_REG_0 244 +#define XT_REG_MISC_REG_1 245 +#define XT_REG_MISC_REG_2 246 +#define XT_REG_MISC_REG_3 247 + +/* Special cases (bases of special register series): */ +#define XT_REG_MR 32 +#define XT_REG_IBREAKA 128 +#define XT_REG_DBREAKA 144 +#define XT_REG_DBREAKC 160 +#define XT_REG_EPC 176 +#define XT_REG_EPS 192 +#define XT_REG_EXCSAVE 208 +#define XT_REG_CCOMPARE 240 + +/* Special names for read-only and write-only interrupt registers: */ +#define XT_REG_INTREAD 226 +#define XT_REG_INTSET 226 +#define XT_REG_INTCLEAR 227 + +#endif /* XTENSA_XT_SPECREG_H */ diff --git a/components/xtensa/esp32s2/include/xtensa/config/specreg.h b/components/xtensa/esp32s2/include/xtensa/config/specreg.h index 355283c9c9..1e94b5ddbe 100644 --- a/components/xtensa/esp32s2/include/xtensa/config/specreg.h +++ b/components/xtensa/esp32s2/include/xtensa/config/specreg.h @@ -28,6 +28,8 @@ #ifndef XTENSA_SPECREG_H #define XTENSA_SPECREG_H +#warning "xtensa/config/specreg.h is deprecated, please use xtensa/config/xt_specreg.h instead" + /* Include these special register bitfield definitions, for historical reasons: */ #include diff --git a/components/xtensa/esp32s2/include/xtensa/config/xt_specreg.h b/components/xtensa/esp32s2/include/xtensa/config/xt_specreg.h new file mode 100644 index 0000000000..77c1142999 --- /dev/null +++ b/components/xtensa/esp32s2/include/xtensa/config/xt_specreg.h @@ -0,0 +1,110 @@ +/* + * Xtensa Special Register symbolic names + */ + +/* SPDX-FileCopyrightText: 1998-2002 Tensilica Inc. + * + * SPDX-License-Identifier: MIT + * + * SPDX-FileContributor: 2025 Espressif Systems (Shanghai) CO LTD + */ + +/* $Id: //depot/rel/Foxhill/dot.8/Xtensa/SWConfig/hal/specreg.h.tpp#1 $ */ + +/* Copyright (c) 1998-2002 Tensilica Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + +#ifndef XTENSA_XT_SPECREG_H +#define XTENSA_XT_SPECREG_H + +/* Include these special register bitfield definitions, for historical reasons: */ +#include + +/* Special registers: */ +#define XT_REG_SAR 3 +#define XT_REG_WINDOWBASE 72 +#define XT_REG_WINDOWSTART 73 +#define XT_REG_IBREAKENABLE 96 +#define XT_REG_DDR 104 +#define XT_REG_IBREAKA_0 128 +#define XT_REG_IBREAKA_1 129 +#define XT_REG_DBREAKA_0 144 +#define XT_REG_DBREAKA_1 145 +#define XT_REG_DBREAKC_0 160 +#define XT_REG_DBREAKC_1 161 +#define XT_REG_CONFIGID0 176 +#define XT_REG_EPC_1 177 +#define XT_REG_EPC_2 178 +#define XT_REG_EPC_3 179 +#define XT_REG_EPC_4 180 +#define XT_REG_EPC_5 181 +#define XT_REG_EPC_6 182 +#define XT_REG_EPC_7 183 +#define XT_REG_DEPC 192 +#define XT_REG_EPS_2 194 +#define XT_REG_EPS_3 195 +#define XT_REG_EPS_4 196 +#define XT_REG_EPS_5 197 +#define XT_REG_EPS_6 198 +#define XT_REG_EPS_7 199 +#define XT_REG_CONFIGID1 208 +#define XT_REG_EXCSAVE_1 209 +#define XT_REG_EXCSAVE_2 210 +#define XT_REG_EXCSAVE_3 211 +#define XT_REG_EXCSAVE_4 212 +#define XT_REG_EXCSAVE_5 213 +#define XT_REG_EXCSAVE_6 214 +#define XT_REG_EXCSAVE_7 215 +#define XT_REG_CPENABLE 224 +#define XT_REG_INTERRUPT 226 +#define XT_REG_INTENABLE 228 +#define XT_REG_PS 230 +#define XT_REG_VECBASE 231 +#define XT_REG_EXCCAUSE 232 +#define XT_REG_DEBUGCAUSE 233 +#define XT_REG_CCOUNT 234 +#define XT_REG_PRID 235 +#define XT_REG_ICOUNT 236 +#define XT_REG_ICOUNTLEVEL 237 +#define XT_REG_EXCVADDR 238 +#define XT_REG_CCOMPARE_0 240 +#define XT_REG_CCOMPARE_1 241 +#define XT_REG_CCOMPARE_2 242 +#define XT_REG_MISC_REG_0 244 +#define XT_REG_MISC_REG_1 245 +#define XT_REG_MISC_REG_2 246 +#define XT_REG_MISC_REG_3 247 + +/* Special cases (bases of special register series): */ +#define XT_REG_IBREAKA 128 +#define XT_REG_DBREAKA 144 +#define XT_REG_DBREAKC 160 +#define XT_REG_EPC 176 +#define XT_REG_EPS 192 +#define XT_REG_EXCSAVE 208 +#define XT_REG_CCOMPARE 240 + +/* Special names for read-only and write-only interrupt registers: */ +#define XT_REG_INTREAD 226 +#define XT_REG_INTSET 226 +#define XT_REG_INTCLEAR 227 + +#endif /* XTENSA_XT_SPECREG_H */ diff --git a/components/xtensa/esp32s3/include/xtensa/config/specreg.h b/components/xtensa/esp32s3/include/xtensa/config/specreg.h index a49974c1ca..e7b90223c1 100644 --- a/components/xtensa/esp32s3/include/xtensa/config/specreg.h +++ b/components/xtensa/esp32s3/include/xtensa/config/specreg.h @@ -28,6 +28,8 @@ #ifndef XTENSA_SPECREG_H #define XTENSA_SPECREG_H +#warning "xtensa/config/specreg.h is deprecated, please use xtensa/config/xt_specreg.h instead" + /* Include these special register bitfield definitions, for historical reasons: */ #include diff --git a/components/xtensa/esp32s3/include/xtensa/config/xt_specreg.h b/components/xtensa/esp32s3/include/xtensa/config/xt_specreg.h new file mode 100644 index 0000000000..7b7bda6ae7 --- /dev/null +++ b/components/xtensa/esp32s3/include/xtensa/config/xt_specreg.h @@ -0,0 +1,124 @@ +/* + * Xtensa Special Register symbolic names + */ + +/* SPDX-FileCopyrightText: 1998-2002 Tensilica Inc. + * + * SPDX-License-Identifier: MIT + * + * SPDX-FileContributor: 2025 Espressif Systems (Shanghai) CO LTD + */ + +/* $Id: //depot/rel/Foxhill/dot.12/Xtensa/SWConfig/hal/specreg.h.tpp#1 $ */ + +/* Customer ID=15128; Build=0x90f1f; Copyright (c) 1998-2002 Tensilica Inc. + + Permission is hereby granted, free of charge, to any person obtaining + a copy of this software and associated documentation files (the + "Software"), to deal in the Software without restriction, including + without limitation the rights to use, copy, modify, merge, publish, + distribute, sublicense, and/or sell copies of the Software, and to + permit persons to whom the Software is furnished to do so, subject to + the following conditions: + + The above copyright notice and this permission notice shall be included + in all copies or substantial portions of the Software. + + THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ + +#ifndef XTENSA_XT_SPECREG_H +#define XTENSA_XT_SPECREG_H + +/* Include these special register bitfield definitions, for historical reasons: */ +#include + +/* Special registers: */ +#define XT_REG_LBEG 0 +#define XT_REG_LEND 1 +#define XT_REG_LCOUNT 2 +#define XT_REG_SAR 3 +#define XT_REG_BR 4 +#define XT_REG_SCOMPARE1 12 +#define XT_REG_ACCLO 16 +#define XT_REG_ACCHI 17 +#define XT_REG_MR_0 32 +#define XT_REG_MR_1 33 +#define XT_REG_MR_2 34 +#define XT_REG_MR_3 35 +#define XT_REG_WINDOWBASE 72 +#define XT_REG_WINDOWSTART 73 +#define XT_REG_IBREAKENABLE 96 +#define XT_REG_MEMCTL 97 +#define XT_REG_ATOMCTL 99 +#define XT_REG_DDR 104 +#define XT_REG_IBREAKA_0 128 +#define XT_REG_IBREAKA_1 129 +#define XT_REG_DBREAKA_0 144 +#define XT_REG_DBREAKA_1 145 +#define XT_REG_DBREAKC_0 160 +#define XT_REG_DBREAKC_1 161 +#define XT_REG_CONFIGID0 176 +#define XT_REG_EPC_1 177 +#define XT_REG_EPC_2 178 +#define XT_REG_EPC_3 179 +#define XT_REG_EPC_4 180 +#define XT_REG_EPC_5 181 +#define XT_REG_EPC_6 182 +#define XT_REG_EPC_7 183 +#define XT_REG_DEPC 192 +#define XT_REG_EPS_2 194 +#define XT_REG_EPS_3 195 +#define XT_REG_EPS_4 196 +#define XT_REG_EPS_5 197 +#define XT_REG_EPS_6 198 +#define XT_REG_EPS_7 199 +#define XT_REG_CONFIGID1 208 +#define XT_REG_EXCSAVE_1 209 +#define XT_REG_EXCSAVE_2 210 +#define XT_REG_EXCSAVE_3 211 +#define XT_REG_EXCSAVE_4 212 +#define XT_REG_EXCSAVE_5 213 +#define XT_REG_EXCSAVE_6 214 +#define XT_REG_EXCSAVE_7 215 +#define XT_REG_CPENABLE 224 +#define XT_REG_INTERRUPT 226 +#define XT_REG_INTENABLE 228 +#define XT_REG_PS 230 +#define XT_REG_VECBASE 231 +#define XT_REG_EXCCAUSE 232 +#define XT_REG_DEBUGCAUSE 233 +#define XT_REG_CCOUNT 234 +#define XT_REG_PRID 235 +#define XT_REG_ICOUNT 236 +#define XT_REG_ICOUNTLEVEL 237 +#define XT_REG_EXCVADDR 238 +#define XT_REG_CCOMPARE_0 240 +#define XT_REG_CCOMPARE_1 241 +#define XT_REG_CCOMPARE_2 242 +#define XT_REG_MISC_REG_0 244 +#define XT_REG_MISC_REG_1 245 +#define XT_REG_MISC_REG_2 246 +#define XT_REG_MISC_REG_3 247 + +/* Special cases (bases of special register series): */ +#define XT_REG_MR 32 +#define XT_REG_IBREAKA 128 +#define XT_REG_DBREAKA 144 +#define XT_REG_DBREAKC 160 +#define XT_REG_EPC 176 +#define XT_REG_EPS 192 +#define XT_REG_EXCSAVE 208 +#define XT_REG_CCOMPARE 240 + +/* Special names for read-only and write-only interrupt registers: */ +#define XT_REG_INTREAD 226 +#define XT_REG_INTSET 226 +#define XT_REG_INTCLEAR 227 + +#endif /* XTENSA_XT_SPECREG_H */ diff --git a/components/xtensa/include/xt_asm_utils.h b/components/xtensa/include/xt_asm_utils.h index 42a0af6db2..d156fd23e8 100644 --- a/components/xtensa/include/xt_asm_utils.h +++ b/components/xtensa/include/xt_asm_utils.h @@ -77,7 +77,7 @@ Macro spinlock_take This macro will repeatedley attempt to atomically set a spinlock variable - using the s32c1i instruciton. A spinlock is considered free if its value is 0. + using the s32c1i instruction. A spinlock is considered free if its value is 0. Entry: - "reg_A/B" as scratch registers @@ -96,9 +96,9 @@ movi \reg_A, \lock_var /* reg_A = &lock_var */ .L_spinlock_loop: movi \reg_B, 0 /* Load spinlock free value (0) into SCOMPARE1 */ - wsr \reg_B, SCOMPARE1 + wsr \reg_B, XT_REG_SCOMPARE1 rsync /* Ensure that SCOMPARE1 is set before s32c1i executes */ - rsr \reg_B, PRID /* Load the current core's ID into reg_B */ + rsr \reg_B, XT_REG_PRID /* Load the current core's ID into reg_B */ s32c1i \reg_B, \reg_A, 0 /* Attempt *lock_var = reg_B */ bnez \reg_B, .L_spinlock_loop /* If the write was successful (i.e., lock was free), 0 will have been written back to reg_B */ diff --git a/components/xtensa/include/xt_utils.h b/components/xtensa/include/xt_utils.h index d4678002d9..ea0eb5496e 100644 --- a/components/xtensa/include/xt_utils.h +++ b/components/xtensa/include/xt_utils.h @@ -11,7 +11,7 @@ #include "xtensa/config/core-isa.h" #include "xtensa/config/core.h" #include "xtensa/config/extreg.h" -#include "xtensa/config/specreg.h" +#include "xtensa/config/xt_specreg.h" #include "xtensa/xtruntime.h" #include "xt_instr_macros.h" #include "esp_bit_defs.h" @@ -68,13 +68,13 @@ FORCE_INLINE_ATTR void *xt_utils_get_sp(void) FORCE_INLINE_ATTR uint32_t xt_utils_get_cycle_count(void) { uint32_t ccount; - RSR(CCOUNT, ccount); + RSR(XT_REG_CCOUNT, ccount); return ccount; } static inline void xt_utils_set_cycle_count(uint32_t ccount) { - WSR(CCOUNT, ccount); + WSR(XT_REG_CCOUNT, ccount); } FORCE_INLINE_ATTR void xt_utils_wait_for_intr(void) @@ -100,7 +100,7 @@ FORCE_INLINE_ATTR void xt_utils_set_vecbase(uint32_t vecbase) FORCE_INLINE_ATTR uint32_t xt_utils_intr_get_enabled_mask(void) { uint32_t intr_mask; - RSR(INTENABLE, intr_mask); + RSR(XT_REG_INTENABLE, intr_mask); return intr_mask; } @@ -118,30 +118,30 @@ FORCE_INLINE_ATTR void xt_utils_set_breakpoint(int bp_num, uint32_t bp_addr) { //Set the breakpoint's address if (bp_num == 1) { - WSR(IBREAKA_1, bp_addr); + WSR(XT_REG_IBREAKA_1, bp_addr); } else { - WSR(IBREAKA_0, bp_addr); + WSR(XT_REG_IBREAKA_0, bp_addr); } //Enable the breakpoint uint32_t brk_ena_reg; - RSR(IBREAKENABLE, brk_ena_reg); + RSR(XT_REG_IBREAKENABLE, brk_ena_reg); brk_ena_reg |= BIT(bp_num); - WSR(IBREAKENABLE, brk_ena_reg); + WSR(XT_REG_IBREAKENABLE, brk_ena_reg); } FORCE_INLINE_ATTR void xt_utils_clear_breakpoint(int bp_num) { // Disable the breakpoint using the break enable register uint32_t bp_en = 0; - RSR(IBREAKENABLE, bp_en); + RSR(XT_REG_IBREAKENABLE, bp_en); bp_en &= ~BIT(bp_num); - WSR(IBREAKENABLE, bp_en); + WSR(XT_REG_IBREAKENABLE, bp_en); // Zero the break address register uint32_t bp_addr = 0; if (bp_num == 1) { - WSR(IBREAKA_1, bp_addr); + WSR(XT_REG_IBREAKA_1, bp_addr); } else { - WSR(IBREAKA_0, bp_addr); + WSR(XT_REG_IBREAKA_0, bp_addr); } } @@ -163,11 +163,11 @@ FORCE_INLINE_ATTR void xt_utils_set_watchpoint(int wp_num, } // Enable break address and break control register if (wp_num == 1) { - WSR(DBREAKA_1, (uint32_t) wp_addr); - WSR(DBREAKC_1, dbreakc_reg); + WSR(XT_REG_DBREAKA_1, (uint32_t) wp_addr); + WSR(XT_REG_DBREAKC_1, dbreakc_reg); } else { - WSR(DBREAKA_0, (uint32_t) wp_addr); - WSR(DBREAKC_0, dbreakc_reg); + WSR(XT_REG_DBREAKA_0, (uint32_t) wp_addr); + WSR(XT_REG_DBREAKC_0, dbreakc_reg); } } @@ -175,11 +175,11 @@ FORCE_INLINE_ATTR void xt_utils_clear_watchpoint(int wp_num) { // Clear both break control and break address register if (wp_num == 1) { - WSR(DBREAKC_1, 0); - WSR(DBREAKA_1, 0); + WSR(XT_REG_DBREAKC_1, 0); + WSR(XT_REG_DBREAKA_1, 0); } else { - WSR(DBREAKC_0, 0); - WSR(DBREAKA_0, 0); + WSR(XT_REG_DBREAKC_0, 0); + WSR(XT_REG_DBREAKA_0, 0); } } diff --git a/components/xtensa/include/xtensa/coreasm.h b/components/xtensa/include/xtensa/coreasm.h index 0dea3b094f..5dac8f23c0 100644 --- a/components/xtensa/include/xtensa/coreasm.h +++ b/components/xtensa/include/xtensa/coreasm.h @@ -50,7 +50,7 @@ #endif #include -#include +#include #include /* diff --git a/components/xtensa/include/xtensa/specreg.h b/components/xtensa/include/xtensa/specreg.h index 8f8222c2ad..2695a2c722 100644 --- a/components/xtensa/include/xtensa/specreg.h +++ b/components/xtensa/include/xtensa/specreg.h @@ -30,6 +30,8 @@ #ifndef XTENSA_SPECREG_H #define XTENSA_SPECREG_H +#warning "xtensa/specreg.h is deprecated, please use xtensa/xt_specreg.h instead" + /* Special registers: */ #define LBEG 0 #define LEND 1 diff --git a/components/xtensa/include/xtensa/xt_specreg.h b/components/xtensa/include/xtensa/xt_specreg.h new file mode 100644 index 0000000000..b23c73dd13 --- /dev/null +++ b/components/xtensa/include/xtensa/xt_specreg.h @@ -0,0 +1,150 @@ +/* + * Xtensa Special Register symbolic names + */ + +/* SPDX-FileCopyrightText: 2005-2011 Tensilica Inc. + * + * SPDX-License-Identifier: MIT + * + * SPDX-FileContributor: 2025 Espressif Systems (Shanghai) CO LTD + */ + +/* $Id: //depot/rel/Foxhill/dot.9/Xtensa/OS/include/xtensa/specreg.h#1 $ */ + +/* + * Copyright (c) 2005-2011 Tensilica Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining + * a copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sublicense, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. + * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY + * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef XTENSA_XT_SPECREG_H +#define XTENSA_XT_SPECREG_H + +/* Special registers: */ +#define XT_REG_LBEG 0 +#define XT_REG_LEND 1 +#define XT_REG_LCOUNT 2 +#define XT_REG_SAR 3 +#define XT_REG_BR 4 +#define XT_REG_LITBASE 5 +#define XT_REG_SCOMPARE1 12 +#define XT_REG_ACCLO 16 +#define XT_REG_ACCHI 17 +#define XT_REG_MR_0 32 +#define XT_REG_MR_1 33 +#define XT_REG_MR_2 34 +#define XT_REG_MR_3 35 +#define XT_REG_PREFCTL 40 +#define XT_REG_WINDOWBASE 72 +#define XT_REG_WINDOWSTART 73 +#define XT_REG_PTEVADDR 83 +#define XT_REG_RASID 90 +#define XT_REG_ITLBCFG 91 +#define XT_REG_DTLBCFG 92 +#define XT_REG_IBREAKENABLE 96 +#define XT_REG_MEMCTL 97 +#define XT_REG_CACHEATTR 98 /* until T1050, XEA1 */ +#define XT_REG_CACHEADRDIS 98 /* LX7+ */ +#define XT_REG_ATOMCTL 99 +#define XT_REG_DDR 104 +#define XT_REG_MECR 110 +#define XT_REG_IBREAKA_0 128 +#define XT_REG_IBREAKA_1 129 +#define XT_REG_DBREAKA_0 144 +#define XT_REG_DBREAKA_1 145 +#define XT_REG_DBREAKC_0 160 +#define XT_REG_DBREAKC_1 161 +#define XT_REG_CONFIGID0 176 +#define XT_REG_EPC_1 177 +#define XT_REG_EPC_2 178 +#define XT_REG_EPC_3 179 +#define XT_REG_EPC_4 180 +#define XT_REG_EPC_5 181 +#define XT_REG_EPC_6 182 +#define XT_REG_EPC_7 183 +#define XT_REG_DEPC 192 +#define XT_REG_EPS_2 194 +#define XT_REG_EPS_3 195 +#define XT_REG_EPS_4 196 +#define XT_REG_EPS_5 197 +#define XT_REG_EPS_6 198 +#define XT_REG_EPS_7 199 +#define XT_REG_CONFIGID1 208 +#define XT_REG_EXCSAVE_1 209 +#define XT_REG_EXCSAVE_2 210 +#define XT_REG_EXCSAVE_3 211 +#define XT_REG_EXCSAVE_4 212 +#define XT_REG_EXCSAVE_5 213 +#define XT_REG_EXCSAVE_6 214 +#define XT_REG_EXCSAVE_7 215 +#define XT_REG_CPENABLE 224 +#define XT_REG_INTERRUPT 226 +#define XT_REG_INTREAD INTERRUPT /* alternate name for backward compatibility */ +#define XT_REG_INTSET INTERRUPT /* alternate name for backward compatibility */ +#define XT_REG_INTCLEAR 227 +#define XT_REG_INTENABLE 228 +#define XT_REG_PS 230 +#define XT_REG_VECBASE 231 +#define XT_REG_EXCCAUSE 232 +#define XT_REG_DEBUGCAUSE 233 +#define XT_REG_CCOUNT 234 +#define XT_REG_PRID 235 +#define XT_REG_ICOUNT 236 +#define XT_REG_ICOUNTLEVEL 237 +#define XT_REG_EXCVADDR 238 +#define XT_REG_CCOMPARE_0 240 +#define XT_REG_CCOMPARE_1 241 +#define XT_REG_CCOMPARE_2 242 +#define XT_REG_MISC_REG_0 244 +#define XT_REG_MISC_REG_1 245 +#define XT_REG_MISC_REG_2 246 +#define XT_REG_MISC_REG_3 247 + +/* Special cases (bases of special register series): */ +#define XT_REG_MR 32 +#define XT_REG_IBREAKA 128 +#define XT_REG_DBREAKA 144 +#define XT_REG_DBREAKC 160 +#define XT_REG_EPC 176 +#define XT_REG_EPS 192 +#define XT_REG_EXCSAVE 208 +#define XT_REG_CCOMPARE 240 +#define XT_REG_MISC_REG 244 + +/* Tensilica-defined user registers: */ +#if 0 +/*#define ... 21..24 */ /* (545CK) */ +/*#define ... 140..143 */ /* (545CK) */ +#define XT_REG_EXPSTATE 230 /* Diamond */ +#define XT_REG_THREADPTR 231 /* threadptr option */ +#define XT_REG_FCR 232 /* FPU */ +#define XT_REG_FSR 233 /* FPU */ +#define XT_REG_AE_OVF_SAR 240 /* HiFi2 */ +#define XT_REG_AE_BITHEAD 241 /* HiFi2 */ +#define XT_REG_AE_TS_FTS_BU_BP 242 /* HiFi2 */ +#define XT_REG_AE_SD_NO 243 /* HiFi2 */ +#define XT_REG_VSAR 240 /* VectraLX */ +#define XT_REG_ROUND_LO 242 /* VectraLX */ +#define XT_REG_ROUND_HI 243 /* VectraLX */ +#define XT_REG_CBEGIN 246 /* VectraLX */ +#define XT_REG_CEND 247 /* VectraLX */ +#endif + +#endif /* XTENSA_XT_SPECREG_H */ diff --git a/components/xtensa/include/xtensa/xtruntime.h b/components/xtensa/include/xtensa/xtruntime.h index b6d35184d8..90240c677b 100644 --- a/components/xtensa/include/xtensa/xtruntime.h +++ b/components/xtensa/include/xtensa/xtruntime.h @@ -27,7 +27,7 @@ #define XTRUNTIME_H #include -#include +#include #include #ifndef XTSTR diff --git a/components/xtensa/include/xtensa_timer.h b/components/xtensa/include/xtensa_timer.h index afffcdf25f..3ade39089d 100644 --- a/components/xtensa/include/xtensa_timer.h +++ b/components/xtensa/include/xtensa_timer.h @@ -100,7 +100,7 @@ Otherwise select the first low or medium priority interrupt timer available. #error "There is no suitable timer in this Xtensa configuration." #endif -#define XT_CCOMPARE (CCOMPARE + XT_TIMER_INDEX) +#define XT_CCOMPARE (XT_REG_CCOMPARE + XT_TIMER_INDEX) #define XT_TIMER_INTNUM XCHAL_TIMER_INTERRUPT(XT_TIMER_INDEX) #define XT_TIMER_INTPRI XCHAL_INT_LEVEL(XT_TIMER_INTNUM) #define XT_TIMER_INTEN (1 << XT_TIMER_INTNUM) diff --git a/components/xtensa/xtensa_context.S b/components/xtensa/xtensa_context.S index cde52ea40e..05b962710a 100644 --- a/components/xtensa/xtensa_context.S +++ b/components/xtensa/xtensa_context.S @@ -127,15 +127,15 @@ _xt_context_save: s32i a15, sp, XT_STK_A15 #endif - rsr a3, SAR + rsr a3, XT_REG_SAR s32i a3, sp, XT_STK_SAR #if XCHAL_HAVE_LOOPS - rsr a3, LBEG + rsr a3, XT_REG_LBEG s32i a3, sp, XT_STK_LBEG - rsr a3, LEND + rsr a3, XT_REG_LEND s32i a3, sp, XT_STK_LEND - rsr a3, LCOUNT + rsr a3, XT_REG_LCOUNT s32i a3, sp, XT_STK_LCOUNT #endif @@ -188,7 +188,7 @@ _xt_context_save: * used as a temporary by this code, the temporary value would get stored * onto the stack, instead of the real value. */ - rsr a2, PS /* to be restored after SPILL_ALL_WINDOWS */ + rsr a2, XT_REG_PS /* to be restored after SPILL_ALL_WINDOWS */ movi a0, PS_INTLEVEL_MASK and a3, a2, a0 /* get the current INTLEVEL */ bgeui a3, XCHAL_EXCM_LEVEL, 1f /* calculate max(INTLEVEL, XCHAL_EXCM_LEVEL) */ @@ -203,7 +203,7 @@ _xt_context_save: SPILL_ALL_WINDOWS /* place the live register windows there */ addi sp, sp, -XT_STK_FRMSZ /* return the current stack pointer and proceed with context save*/ - wsr a2, PS /* restore to the value at entry */ + wsr a2, XT_REG_PS /* restore to the value at entry */ rsync wsr a0, EPC1 /* likewise */ @@ -274,10 +274,10 @@ _xt_context_restore: #if XCHAL_HAVE_LOOPS l32i a2, sp, XT_STK_LBEG l32i a3, sp, XT_STK_LEND - wsr a2, LBEG + wsr a2, XT_REG_LBEG l32i a2, sp, XT_STK_LCOUNT - wsr a3, LEND - wsr a2, LCOUNT + wsr a3, XT_REG_LEND + wsr a2, XT_REG_LCOUNT #endif #ifdef XT_USE_OVLY @@ -309,7 +309,7 @@ _xt_context_restore: l32i a3, sp, XT_STK_SAR l32i a2, sp, XT_STK_A2 - wsr a3, SAR + wsr a3, XT_REG_SAR l32i a3, sp, XT_STK_A3 l32i a4, sp, XT_STK_A4 l32i a5, sp, XT_STK_A5 @@ -445,7 +445,7 @@ _xt_coproc_release: /* Release previously taken spinlock */ spinlock_release a7 a8 _xt_coproc_owner_sa_lock #endif /* portNUM_PROCESSORS > 1 */ - wsr a6, PS /* restore interrupts */ + wsr a6, XT_REG_PS /* restore interrupts */ RET0 @@ -484,7 +484,7 @@ _xt_coproc_savecs: /* At entry, CPENABLE should be showing which CPs are enabled. */ - rsr a2, CPENABLE /* a2 = which CPs are enabled */ + rsr a2, XT_REG_CPENABLE /* a2 = which CPs are enabled */ beqz a2, .Ldone /* quick exit if none */ mov a14, a0 /* save return address */ call0 XT_RTOS_CP_STATE /* get address of CP save area */ diff --git a/components/xtensa/xtensa_intr_asm.S b/components/xtensa/xtensa_intr_asm.S index 27fe781bfd..2a49440f0d 100644 --- a/components/xtensa/xtensa_intr_asm.S +++ b/components/xtensa/xtensa_intr_asm.S @@ -168,14 +168,14 @@ xt_ints_on: or a5, a3, a2 /* a5 = _xt_intenable | mask */ s32i a5, a4, 0 /* _xt_intenable |= mask */ and a5, a5, a6 /* a5 = _xt_intenable & _xt_vpri_mask */ - wsr a5, INTENABLE /* Reenable interrupts */ + wsr a5, XT_REG_INTENABLE /* Re-enable interrupts */ mov a2, a3 /* Previous mask */ #else movi a3, 0 - xsr a3, INTENABLE /* Disables all interrupts */ + xsr a3, XT_REG_INTENABLE /* Disables all interrupts */ rsync or a2, a3, a2 /* set bits in mask */ - wsr a2, INTENABLE /* Re-enable ints */ + wsr a2, XT_REG_INTENABLE /* Re-enable ints */ rsync mov a2, a3 /* return prev mask */ #endif @@ -218,15 +218,15 @@ xt_ints_off: xor a5, a5, a2 /* a5 = _xt_intenable & ~mask */ s32i a5, a4, 0 /* _xt_intenable &= ~mask */ and a5, a5, a6 /* a5 = _xt_intenable & _xt_vpri_mask */ - wsr a5, INTENABLE /* Reenable interrupts */ + wsr a5, XT_REG_INTENABLE /* Re-enable interrupts */ mov a2, a3 /* Previous mask */ #else movi a4, 0 - xsr a4, INTENABLE /* Disables all interrupts */ + xsr a4, XT_REG_INTENABLE /* Disables all interrupts */ rsync or a3, a4, a2 /* set bits in mask */ xor a3, a3, a2 /* invert bits in mask set in mask, essentially clearing them */ - wsr a3, INTENABLE /* Re-enable ints */ + wsr a3, XT_REG_INTENABLE /* Re-enable ints */ rsync mov a2, a4 /* return prev mask */ #endif diff --git a/components/xtensa/xtensa_vectors.S b/components/xtensa/xtensa_vectors.S index c677f29b31..e1ce82bdee 100644 --- a/components/xtensa/xtensa_vectors.S +++ b/components/xtensa/xtensa_vectors.S @@ -212,8 +212,8 @@ /* Get mask of pending, enabled interrupts at this level into a2. */ .L_xt_user_int_\level : - rsr a2, INTENABLE - rsr a3, INTERRUPT + rsr a2, XT_REG_INTENABLE + rsr a3, XT_REG_INTERRUPT movi a4, \mask and a2, a2, a3 and a2, a2, a4 @@ -229,7 +229,7 @@ */ #ifdef XT_DEBUG_BACKTRACE #ifndef __XTENSA_CALL0_ABI__ - rsr a0, EXCSAVE_1 + \level - 1 /* Get exception frame pointer stored in EXCSAVE_x */ + rsr a0, XT_REG_EXCSAVE_1 + \level - 1 /* Get exception frame pointer stored in EXCSAVE_x */ l32i a3, a0, XT_STK_A0 /* Copy pre-exception a0 (return address) */ s32e a3, a1, -16 l32i a3, a0, XT_STK_A1 /* Copy pre-exception a1 (stack pointer) */ @@ -238,7 +238,7 @@ Also need to change current frame's return address to point to pre-exception's last run instruction. */ - rsr a0, EPC_1 + \level - 1 /* return address */ + rsr a0, XT_REG_EPC_1 + \level - 1 /* return address */ movi a4, 0xC0000000 /* constant with top 2 bits set (call size) */ or a0, a0, a4 /* set top 2 bits */ addx2 a0, a4, a0 /* clear top bit -- simulating call4 size */ @@ -294,10 +294,10 @@ #ifdef XT_RTOS_TIMER_INT movi a3, XT_TIMER_INTEN /* a3 = timer interrupt bit */ - wsr a4, INTCLEAR /* clear sw or edge-triggered interrupt */ + wsr a4, XT_REG_INTCLEAR /* clear sw or edge-triggered interrupt */ beq a3, a4, 7f /* if timer interrupt then skip table */ #else - wsr a4, INTCLEAR /* clear sw or edge-triggered interrupt */ + wsr a4, XT_REG_INTCLEAR /* clear sw or edge-triggered interrupt */ #endif // XT_RTOS_TIMER_INT find_ms_setbit a3, a4, a3, 0 /* a3 = interrupt number */ @@ -437,7 +437,7 @@ Debug Exception. .align 4 .global xt_debugexception _DebugExceptionVector: - wsr a0, EXCSAVE+XCHAL_DEBUGLEVEL /* preserve a0 */ + wsr a0, XT_REG_EXCSAVE+XCHAL_DEBUGLEVEL /* preserve a0 */ J xt_debugexception /* load exception handler */ .end literal_prefix @@ -460,21 +460,21 @@ _xt_debugexception: bnez a0, 1f #endif - rsr a0, DEBUGCAUSE + rsr a0, XT_REG_DEBUGCAUSE extui a0, a0, XT_DEBUGCAUSE_DI, 1 bnez a0, _xt_debug_di_exc 1: #endif //(CONFIG_ESP32_ECO3_CACHE_LOCK_FIX && CONFIG_BTDM_CTRL_HLI) movi a0,PANIC_RSN_DEBUGEXCEPTION - wsr a0,EXCCAUSE + wsr a0,XT_REG_EXCCAUSE /* _xt_panic assumes a level 1 exception. As we're crashing anyhow, copy EPC & EXCSAVE from DEBUGLEVEL to level 1. */ - rsr a0,(EPC + XCHAL_DEBUGLEVEL) - wsr a0,EPC_1 - rsr a0,(EXCSAVE + XCHAL_DEBUGLEVEL) - wsr a0,EXCSAVE_1 + rsr a0,(XT_REG_EPC + XCHAL_DEBUGLEVEL) + wsr a0,XT_REG_EPC_1 + rsr a0,(XT_REG_EXCSAVE + XCHAL_DEBUGLEVEL) + wsr a0,XT_REG_EXCSAVE_1 #if CONFIG_ESP_SYSTEM_GDBSTUB_RUNTIME J _xt_panic_gdbstub /* For gdbstub we make jump */ #else @@ -539,7 +539,7 @@ _xt_debug_di_exc: .endr bnez a0, 1b - rsr a0, EXCSAVE+XCHAL_DEBUGLEVEL + rsr a0, XT_REG_EXCSAVE+XCHAL_DEBUGLEVEL rfi XCHAL_DEBUGLEVEL #endif //(CONFIG_ESP32_ECO3_CACHE_LOCK_FIX && CONFIG_BTDM_CTRL_HLI) #endif // XCHAL_HAVE_DEBUG @@ -564,7 +564,7 @@ _DoubleExceptionVector: break 1, 4 /* unhandled double exception */ #endif movi a0,PANIC_RSN_DOUBLEEXCEPTION - wsr a0,EXCCAUSE + wsr a0,XT_REG_EXCCAUSE call0 _xt_panic /* does not return */ rfde /* make a0 point here not later */ @@ -585,7 +585,7 @@ Kernel Exception (including Level 1 Interrupt from kernel mode). _KernelExceptionVector: - wsr a0, EXCSAVE_1 /* preserve a0 */ + wsr a0, XT_REG_EXCSAVE_1 /* preserve a0 */ call0 _xt_kernel_exc /* kernel exception handler */ /* never returns here - call0 is used as a jump (see note at top) */ @@ -599,7 +599,7 @@ _xt_kernel_exc: break 1, 0 /* unhandled kernel exception */ #endif movi a0,PANIC_RSN_KERNELEXCEPTION - wsr a0,EXCCAUSE + wsr a0,XT_REG_EXCCAUSE call0 _xt_panic /* does not return */ rfe /* make a0 point here not there */ @@ -618,7 +618,7 @@ User Exception (including Level 1 Interrupt from user mode). _UserExceptionVector: - wsr a0, EXCSAVE_1 /* preserve a0 */ + wsr a0, XT_REG_EXCSAVE_1 /* preserve a0 */ call0 _xt_user_exc /* user exception handler */ /* never returns here - call0 is used as a jump (see note at top) */ @@ -686,7 +686,7 @@ _call_alignment_handler: _xt_user_exc: /* If level 1 interrupt then jump to the dispatcher */ - rsr a0, EXCCAUSE + rsr a0, XT_REG_EXCCAUSE bnei a0, EXCCAUSE_LEVEL1INTERRUPT, _xt_handle_exc j _xt_lowint1 _xt_handle_exc: @@ -722,11 +722,11 @@ _xt_handle_exc: #if XCHAL_HAVE_WINDOWED s32e a0, sp, -12 /* for debug backtrace */ #endif - rsr a0, PS /* save interruptee's PS */ + rsr a0, XT_REG_PS /* save interruptee's PS */ s32i a0, sp, XT_STK_PS - rsr a0, EPC_1 /* save interruptee's PC */ + rsr a0, XT_REG_EPC_1 /* save interruptee's PC */ s32i a0, sp, XT_STK_PC - rsr a0, EXCSAVE_1 /* save interruptee's a0 */ + rsr a0, XT_REG_EXCSAVE_1 /* save interruptee's a0 */ s32i a0, sp, XT_STK_A0 #if XCHAL_HAVE_WINDOWED s32e a0, sp, -16 /* for debug backtrace */ @@ -736,9 +736,9 @@ _xt_handle_exc: call0 _xt_context_save /* Save exc cause and vaddr into exception frame */ - rsr a0, EXCCAUSE + rsr a0, XT_REG_EXCCAUSE s32i a0, sp, XT_STK_EXCCAUSE - rsr a0, EXCVADDR + rsr a0, XT_REG_EXCVADDR s32i a0, sp, XT_STK_EXCVADDR /* Set up PS for C, re-enable debug and NMI interrupts, and clear EXCM. */ @@ -747,7 +747,7 @@ _xt_handle_exc: #else movi a0, PS_INTLEVEL(XCHAL_DEBUGLEVEL - 2) | PS_UM | PS_WOE #endif - wsr a0, PS + wsr a0, XT_REG_PS /* Create pseudo base save area. At this point, sp is still pointing to the @@ -759,7 +759,7 @@ _xt_handle_exc: s32e a3, sp, -16 l32i a3, sp, XT_STK_A1 /* Copy pre-exception a1 (stack pointer) */ s32e a3, sp, -12 - rsr a0, EPC_1 /* return address for debug backtrace */ + rsr a0, XT_REG_EPC_1 /* return address for debug backtrace */ movi a5, 0xC0000000 /* constant with top 2 bits set (call size) */ rsync /* wait for WSR.PS to complete */ or a0, a0, a5 /* set top 2 bits */ @@ -769,7 +769,7 @@ _xt_handle_exc: #endif #endif - rsr a2, EXCCAUSE /* recover exc cause */ + rsr a2, XT_REG_EXCCAUSE /* recover exc cause */ #ifdef XT_INTEXC_HOOKS /* @@ -792,7 +792,7 @@ _xt_handle_exc: 1: #endif - rsr a2, EXCCAUSE /* recover exc cause */ + rsr a2, XT_REG_EXCCAUSE /* recover exc cause */ movi a3, _xt_exception_table get_percpu_entry_for a2, a4 addx4 a4, a2, a3 /* a4 = address of exception table entry */ @@ -810,9 +810,9 @@ _xt_handle_exc: /* Restore context and return */ call0 _xt_context_restore l32i a0, sp, XT_STK_PS /* retrieve interruptee's PS */ - wsr a0, PS + wsr a0, XT_REG_PS l32i a0, sp, XT_STK_PC /* retrieve interruptee's PC */ - wsr a0, EPC_1 + wsr a0, XT_REG_EPC_1 l32i a0, sp, XT_STK_A0 /* retrieve interruptee's A0 */ l32i sp, sp, XT_STK_A1 /* remove exception frame */ rsync /* ensure PS and EPC written */ @@ -831,9 +831,9 @@ _xt_handle_exc: .align 4 _xt_user_exit: l32i a0, sp, XT_STK_PS /* retrieve interruptee's PS */ - wsr a0, PS + wsr a0, XT_REG_PS l32i a0, sp, XT_STK_PC /* retrieve interruptee's PC */ - wsr a0, EPC_1 + wsr a0, XT_REG_EPC_1 l32i a0, sp, XT_STK_A0 /* retrieve interruptee's A0 */ l32i sp, sp, XT_STK_A1 /* remove interrupt stack frame */ rsync /* ensure PS and EPC written */ @@ -884,18 +884,18 @@ _xt_syscall_exc: If it's at the end of a zero-overhead loop and it's not on the last iteration, decrement loop counter and skip to beginning of loop. */ - rsr a2, EPC_1 /* a2 = PC of 'syscall' */ + rsr a2, XT_REG_EPC_1 /* a2 = PC of 'syscall' */ addi a3, a2, 3 /* ++PC */ #if XCHAL_HAVE_LOOPS - rsr a0, LEND /* if (PC == LEND */ + rsr a0, XT_REG_LEND /* if (PC == LEND */ bne a3, a0, 1f - rsr a0, LCOUNT /* && LCOUNT != 0) */ + rsr a0, XT_REG_LCOUNT /* && LCOUNT != 0) */ beqz a0, 1f /* { */ addi a0, a0, -1 /* --LCOUNT */ - rsr a3, LBEG /* PC = LBEG */ - wsr a0, LCOUNT /* } */ + rsr a3, XT_REG_LBEG /* PC = LBEG */ + wsr a0, XT_REG_LCOUNT /* } */ #endif -1: wsr a3, EPC_1 /* update PC */ +1: wsr a3, XT_REG_EPC_1 /* update PC */ /* Restore interruptee's context and return from exception. */ #ifdef __XTENSA_CALL0_ABI__ @@ -908,7 +908,7 @@ _xt_syscall_exc: #endif movi a0, -1 movnez a2, a0, a2 /* return -1 if not syscall 0 */ - rsr a0, EXCSAVE_1 + rsr a0, XT_REG_EXCSAVE_1 rfe /* @@ -996,11 +996,11 @@ _xt_coproc_exc: #if XCHAL_HAVE_WINDOWED s32e a0, sp, -12 /* for debug backtrace */ #endif - rsr a0, PS /* save interruptee's PS */ + rsr a0, XT_REG_PS /* save interruptee's PS */ s32i a0, sp, XT_STK_PS - rsr a0, EPC_1 /* save interruptee's PC */ + rsr a0, XT_REG_EPC_1 /* save interruptee's PC */ s32i a0, sp, XT_STK_PC - rsr a0, EXCSAVE_1 /* save interruptee's a0 */ + rsr a0, XT_REG_EXCSAVE_1 /* save interruptee's a0 */ s32i a0, sp, XT_STK_A0 #if XCHAL_HAVE_WINDOWED s32e a0, sp, -16 /* for debug backtrace */ @@ -1008,7 +1008,7 @@ _xt_coproc_exc: movi a0, _xt_user_exit /* save exit point for dispatch */ s32i a0, sp, XT_STK_EXIT - rsr a0, EXCCAUSE + rsr a0, XT_REG_EXCCAUSE s32i a5, sp, XT_STK_A5 /* save a5 */ addi a5, a0, -EXCCAUSE_CP0_DISABLED /* a5 = CP index */ @@ -1035,12 +1035,12 @@ _xt_coproc_exc: /* Enable the co-processor's bit in CPENABLE. */ movi a0, _xt_coproc_mask - rsr a4, CPENABLE /* a4 = CPENABLE */ + rsr a4, XT_REG_CPENABLE /* a4 = CPENABLE */ addx4 a0, a5, a0 /* a0 = &_xt_coproc_mask[n] */ l32i a0, a0, 0 /* a0 = (n << 16) | (1 << n) */ extui a2, a0, 0, 16 /* coprocessor bitmask portion */ or a4, a4, a2 /* a4 = CPENABLE | (1 << n) */ - wsr a4, CPENABLE + wsr a4, XT_REG_CPENABLE /* Grab the xt_coproc_owner_sa owner array for current core */ getcoreid a3 /* a3 = current core ID */ @@ -1181,7 +1181,7 @@ _xt_coproc_exc: /* Co-processor exception occurred outside a thread (not supported). */ .L_xt_coproc_invalid: movi a0,PANIC_RSN_COPROCEXCEPTION - wsr a0,EXCCAUSE + wsr a0,XT_REG_EXCCAUSE call0 _xt_panic /* not in a thread (invalid) */ /* never returns */ @@ -1203,11 +1203,11 @@ _xt_lowint1: mov a0, sp /* sp == a1 */ addi sp, sp, -XT_STK_FRMSZ /* allocate interrupt stack frame */ s32i a0, sp, XT_STK_A1 /* save pre-interrupt SP */ - rsr a0, PS /* save interruptee's PS */ + rsr a0, XT_REG_PS /* save interruptee's PS */ s32i a0, sp, XT_STK_PS - rsr a0, EPC_1 /* save interruptee's PC */ + rsr a0, XT_REG_EPC_1 /* save interruptee's PC */ s32i a0, sp, XT_STK_PC - rsr a0, EXCSAVE_1 /* save interruptee's a0 */ + rsr a0, XT_REG_EXCSAVE_1 /* save interruptee's a0 */ s32i a0, sp, XT_STK_A0 movi a0, _xt_user_exit /* save exit point for dispatch */ s32i a0, sp, XT_STK_EXIT @@ -1217,7 +1217,7 @@ _xt_lowint1: #ifdef XT_DEBUG_BACKTRACE #ifndef __XTENSA_CALL0_ABI__ mov a0, sp - wsr a0, EXCSAVE_1 + wsr a0, XT_REG_EXCSAVE_1 #endif #endif @@ -1232,7 +1232,7 @@ _xt_lowint1: #else movi a0, PS_INTLEVEL(1) | PS_UM | PS_WOE #endif - wsr a0, PS + wsr a0, XT_REG_PS rsync /* OK to call C code at this point, dispatch user ISRs */ @@ -1279,7 +1279,7 @@ _xt_lowint1: .type _Level2Vector,@function .align 4 _Level2Vector: - wsr a0, EXCSAVE_2 /* preserve a0 */ + wsr a0, XT_REG_EXCSAVE_2 /* preserve a0 */ call0 _xt_medint2 /* load interrupt handler */ /* never returns here - call0 is used as a jump (see note at top) */ @@ -1292,11 +1292,11 @@ _xt_medint2: mov a0, sp /* sp == a1 */ addi sp, sp, -XT_STK_FRMSZ /* allocate interrupt stack frame */ s32i a0, sp, XT_STK_A1 /* save pre-interrupt SP */ - rsr a0, EPS_2 /* save interruptee's PS */ + rsr a0, XT_REG_EPS_2 /* save interruptee's PS */ s32i a0, sp, XT_STK_PS - rsr a0, EPC_2 /* save interruptee's PC */ + rsr a0, XT_REG_EPC_2 /* save interruptee's PC */ s32i a0, sp, XT_STK_PC - rsr a0, EXCSAVE_2 /* save interruptee's a0 */ + rsr a0, XT_REG_EXCSAVE_2 /* save interruptee's a0 */ s32i a0, sp, XT_STK_A0 movi a0, _xt_medint2_exit /* save exit point for dispatch */ s32i a0, sp, XT_STK_EXIT @@ -1306,7 +1306,7 @@ _xt_medint2: #ifdef XT_DEBUG_BACKTRACE #ifndef __XTENSA_CALL0_ABI__ mov a0, sp - wsr a0, EXCSAVE_2 + wsr a0, XT_REG_EXCSAVE_2 #endif #endif @@ -1321,7 +1321,7 @@ _xt_medint2: #else movi a0, PS_INTLEVEL(2) | PS_UM | PS_WOE #endif - wsr a0, PS + wsr a0, XT_REG_PS rsync /* OK to call C code at this point, dispatch user ISRs */ @@ -1341,9 +1341,9 @@ _xt_medint2: _xt_medint2_exit: /* Restore only level-specific regs (the rest were already restored) */ l32i a0, sp, XT_STK_PS /* retrieve interruptee's PS */ - wsr a0, EPS_2 + wsr a0, XT_REG_EPS_2 l32i a0, sp, XT_STK_PC /* retrieve interruptee's PC */ - wsr a0, EPC_2 + wsr a0, XT_REG_EPC_2 l32i a0, sp, XT_STK_A0 /* retrieve interruptee's A0 */ l32i sp, sp, XT_STK_A1 /* remove interrupt stack frame */ rsync /* ensure EPS and EPC written */ @@ -1359,7 +1359,7 @@ _xt_medint2_exit: .type _Level3Vector,@function .align 4 _Level3Vector: - wsr a0, EXCSAVE_3 /* preserve a0 */ + wsr a0, XT_REG_EXCSAVE_3 /* preserve a0 */ call0 _xt_medint3 /* load interrupt handler */ /* never returns here - call0 is used as a jump (see note at top) */ @@ -1372,11 +1372,11 @@ _xt_medint3: mov a0, sp /* sp == a1 */ addi sp, sp, -XT_STK_FRMSZ /* allocate interrupt stack frame */ s32i a0, sp, XT_STK_A1 /* save pre-interrupt SP */ - rsr a0, EPS_3 /* save interruptee's PS */ + rsr a0, XT_REG_EPS_3 /* save interruptee's PS */ s32i a0, sp, XT_STK_PS - rsr a0, EPC_3 /* save interruptee's PC */ + rsr a0, XT_REG_EPC_3 /* save interruptee's PC */ s32i a0, sp, XT_STK_PC - rsr a0, EXCSAVE_3 /* save interruptee's a0 */ + rsr a0, XT_REG_EXCSAVE_3 /* save interruptee's a0 */ s32i a0, sp, XT_STK_A0 movi a0, _xt_medint3_exit /* save exit point for dispatch */ s32i a0, sp, XT_STK_EXIT @@ -1386,7 +1386,7 @@ _xt_medint3: #ifdef XT_DEBUG_BACKTRACE #ifndef __XTENSA_CALL0_ABI__ mov a0, sp - wsr a0, EXCSAVE_3 + wsr a0, XT_REG_EXCSAVE_3 #endif #endif @@ -1401,7 +1401,7 @@ _xt_medint3: #else movi a0, PS_INTLEVEL(3) | PS_UM | PS_WOE #endif - wsr a0, PS + wsr a0, XT_REG_PS rsync /* OK to call C code at this point, dispatch user ISRs */ @@ -1421,9 +1421,9 @@ _xt_medint3: _xt_medint3_exit: /* Restore only level-specific regs (the rest were already restored) */ l32i a0, sp, XT_STK_PS /* retrieve interruptee's PS */ - wsr a0, EPS_3 + wsr a0, XT_REG_EPS_3 l32i a0, sp, XT_STK_PC /* retrieve interruptee's PC */ - wsr a0, EPC_3 + wsr a0, XT_REG_EPC_3 l32i a0, sp, XT_STK_A0 /* retrieve interruptee's A0 */ l32i sp, sp, XT_STK_A1 /* remove interrupt stack frame */ rsync /* ensure EPS and EPC written */ @@ -1803,7 +1803,7 @@ _xt_highint3: .global xt_highint4 .align 4 _Level4Vector: - wsr a0, EXCSAVE_4 /* preserve a0 */ + wsr a0, XT_REG_EXCSAVE_4 /* preserve a0 */ call0 xt_highint4 /* load interrupt handler */ /* never returns here - call0 is used as a jump (see note at top) */ @@ -1833,7 +1833,7 @@ _xt_highint4: .align 4 .L_xt_highint4_exit: - rsr a0, EXCSAVE_4 /* restore a0 */ + rsr a0, XT_REG_EXCSAVE_4 /* restore a0 */ rfi 4 #endif /* Level 4 */ @@ -1847,7 +1847,7 @@ _xt_highint4: .global xt_highint5 .align 4 _Level5Vector: - wsr a0, EXCSAVE_5 /* preserve a0 */ + wsr a0, XT_REG_EXCSAVE_5 /* preserve a0 */ call0 xt_highint5 /* load interrupt handler */ /* never returns here - call0 is used as a jump (see note at top) */ @@ -1877,7 +1877,7 @@ _xt_highint5: .align 4 .L_xt_highint5_exit: - rsr a0, EXCSAVE_5 /* restore a0 */ + rsr a0, XT_REG_EXCSAVE_5 /* restore a0 */ rfi 5 #endif /* Level 5 */ @@ -1935,7 +1935,7 @@ _xt_highint6: .global xt_nmi .align 4 _NMIExceptionVector: - wsr a0, EXCSAVE + XCHAL_NMILEVEL /* preserve a0 */ + wsr a0, XT_REG_EXCSAVE + XCHAL_NMILEVEL /* preserve a0 */ call0 xt_nmi /* load interrupt handler */ /* never returns here - call0 is used as a jump (see note at top) */ @@ -1965,7 +1965,7 @@ _xt_nmi: .align 4 .L_xt_nmi_exit: - rsr a0, EXCSAVE + XCHAL_NMILEVEL /* restore a0 */ + rsr a0, XT_REG_EXCSAVE + XCHAL_NMILEVEL /* restore a0 */ rfi XCHAL_NMILEVEL #endif /* NMI */ @@ -2072,15 +2072,15 @@ The code is optimized to avoid unaligned branches and minimize cache misses. .global _xt_alloca_exc _xt_alloca_exc: - rsr a0, WINDOWBASE /* grab WINDOWBASE before rotw changes it */ + rsr a0, XT_REG_WINDOWBASE /* grab WINDOWBASE before rotw changes it */ rotw -1 /* WINDOWBASE goes to a4, new a0-a3 are scratch */ - rsr a2, PS + rsr a2, XT_REG_PS extui a3, a2, XCHAL_PS_OWB_SHIFT, XCHAL_PS_OWB_BITS xor a3, a3, a4 /* bits changed from old to current windowbase */ - rsr a4, EXCSAVE_1 /* restore original a0 (now in a4) */ + rsr a4, XT_REG_EXCSAVE_1 /* restore original a0 (now in a4) */ slli a3, a3, XCHAL_PS_OWB_SHIFT xor a2, a2, a3 /* flip changed bits in old window base */ - wsr a2, PS /* update PS.OWB to new window base */ + wsr a2, XT_REG_PS /* update PS.OWB to new window base */ rsync bbci.l a4, 31, _WindowUnderflow4 diff --git a/docs/en/migration-guides/release-6.x/6.0/index.rst b/docs/en/migration-guides/release-6.x/6.0/index.rst index d62ea27dca..cb0cbec001 100644 --- a/docs/en/migration-guides/release-6.x/6.0/index.rst +++ b/docs/en/migration-guides/release-6.x/6.0/index.rst @@ -10,3 +10,4 @@ Migration from 5.5 to 6.0 peripherals security tools + system diff --git a/docs/en/migration-guides/release-6.x/6.0/system.rst b/docs/en/migration-guides/release-6.x/6.0/system.rst new file mode 100644 index 0000000000..a2911f75de --- /dev/null +++ b/docs/en/migration-guides/release-6.x/6.0/system.rst @@ -0,0 +1,10 @@ +System +====== + +:link_to_translation:`zh_CN:[中文]` + +Xtensa +------ + +The Xtensa special register header files have been updated to use a new naming convention. The old ``specreg.h`` header files are now deprecated and will be removed in a future release. +The register names have been updated to use the ``XT_REG_`` prefix. Please use the new ``xt_specreg.h`` file instead. diff --git a/docs/zh_CN/migration-guides/release-6.x/6.0/index.rst b/docs/zh_CN/migration-guides/release-6.x/6.0/index.rst index 7229b90a50..5e5c9e2ae0 100644 --- a/docs/zh_CN/migration-guides/release-6.x/6.0/index.rst +++ b/docs/zh_CN/migration-guides/release-6.x/6.0/index.rst @@ -10,3 +10,4 @@ peripherals security tools + system diff --git a/docs/zh_CN/migration-guides/release-6.x/6.0/system.rst b/docs/zh_CN/migration-guides/release-6.x/6.0/system.rst new file mode 100644 index 0000000000..bfbf93eea6 --- /dev/null +++ b/docs/zh_CN/migration-guides/release-6.x/6.0/system.rst @@ -0,0 +1,11 @@ +系统 +==== + +:link_to_translation:`en:[English]` + +Xtensa +------ + +Xtensa 特殊寄存器头文件已更新，使用新的命名约定。旧的 ``specreg.h`` 头文件现已被弃用，并将在未来版本中移除。 + +寄存器名称已更新为使用 ``XT_REG_`` 前缀。请使用新的 ``xt_specreg.h`` 文件。 diff --git a/examples/system/nmi_isr/main/asm_funcs.S b/examples/system/nmi_isr/main/asm_funcs.S index 437de583b1..6744cd7d5c 100644 --- a/examples/system/nmi_isr/main/asm_funcs.S +++ b/examples/system/nmi_isr/main/asm_funcs.S @@ -17,7 +17,7 @@ nmi_triggered: /** * @brief This current ISR was called via `call0` instruction, so `a0` (return address) - * was altered. Fortunately, `a0` was saved in EXCSAVE registers, restore it before + * was altered. Fortunately, `a0` was saved in XT_REG_EXCSAVE registers, restore it before * returning */ .section .iram1, "ax" @@ -41,7 +41,7 @@ xt_nmi: /* Restore a3 and a0 before leaving*/ l32i a3, sp, 0 addi sp, sp, 16 - rsr a0, EXCSAVE + XCHAL_NMILEVEL + rsr a0, XT_REG_EXCSAVE + XCHAL_NMILEVEL /* Return from NMI, we need to specify the level */ rfi XCHAL_NMILEVEL