Merge branch 'change/ble_update_lib_20250828_v5.3' into 'release/v5.3'

change(ble): [AUTO_MR] 20250828 - Update ESP BLE Controller Lib (v5.3)

See merge request espressif/esp-idf!41960

components/bt/controller/esp32c6/bt.c

@@ -82,7 +82,7 @@
 #define OSI_COEX_VERSION              0x00010006
 #define OSI_COEX_MAGIC_VALUE          0xFADEBEAD
 
-#define EXT_FUNC_VERSION             0x20250415
+#define EXT_FUNC_VERSION             0x20250825
 #define EXT_FUNC_MAGIC_VALUE         0xA5A5A5A5
 
 #define BT_ASSERT_PRINT              ets_printf

components/bt/controller/esp32h2/bt.c

@@ -74,7 +74,7 @@
 #define OSI_COEX_VERSION              0x00010006
 #define OSI_COEX_MAGIC_VALUE          0xFADEBEAD
 
-#define EXT_FUNC_VERSION             0x20250415
+#define EXT_FUNC_VERSION             0x20250825
 #define EXT_FUNC_MAGIC_VALUE         0xA5A5A5A5
 
 #define BT_ASSERT_PRINT              ets_printf
@@ -105,6 +105,7 @@ struct ext_funcs_t {
     int (* _ecc_gen_key_pair)(uint8_t *public, uint8_t *priv);
     int (* _ecc_gen_dh_key)(const uint8_t *remote_pub_key_x, const uint8_t *remote_pub_key_y,
                             const uint8_t *local_priv_key, uint8_t *dhkey);
+    void (* _esp_reset_modem)(uint8_t mdl_opts, uint8_t start);
     uint32_t magic;
 };
 
@@ -119,6 +120,11 @@ enum {
 /* External functions or variables
  ************************************************************************
  */
+#if CONFIG_SW_COEXIST_ENABLE || CONFIG_EXTERNAL_COEX_ENABLE
+extern void coex_hw_timer_set(uint8_t idx,uint8_t src, uint8_t pti,uint32_t latency, uint32_t perioidc);
+extern void coex_hw_timer_enable(uint8_t idx);
+extern void coex_hw_timer_disable(uint8_t idx);
+#endif // CONFIG_SW_COEXIST_ENABLE || CONFIG_EXTERNAL_COEX_ENABLE
 extern int ble_osi_coex_funcs_register(struct osi_coex_funcs_t *coex_funcs);
 extern int r_ble_controller_init(esp_bt_controller_config_t *cfg);
 extern void esp_ble_controller_info_capture(uint32_t cycle_times);
@@ -194,6 +200,7 @@ static int esp_intr_alloc_wrapper(int source, int flags, intr_handler_t handler,
 static int esp_intr_free_wrapper(void **ret_handle);
 static void osi_assert_wrapper(const uint32_t ln, const char *fn, uint32_t param1, uint32_t param2);
 static uint32_t osi_random_wrapper(void);
+static void esp_reset_modem(uint8_t mdl_opts,uint8_t start);
 static int esp_ecc_gen_key_pair(uint8_t *pub, uint8_t *priv);
 static int esp_ecc_gen_dh_key(const uint8_t *peer_pub_key_x, const uint8_t *peer_pub_key_y,
                               const uint8_t *our_priv_key, uint8_t *out_dhkey);
@@ -533,9 +540,29 @@ struct ext_funcs_t ext_funcs_ro = {
     ._os_random = osi_random_wrapper,
     ._ecc_gen_key_pair = esp_ecc_gen_key_pair,
     ._ecc_gen_dh_key = esp_ecc_gen_dh_key,
+    ._esp_reset_modem = esp_reset_modem,
     .magic = EXT_FUNC_MAGIC_VALUE,
 };
 
+static void IRAM_ATTR esp_reset_modem(uint8_t mdl_opts,uint8_t start)
+{
+    if (mdl_opts == 0x05) {
+        if (start) {
+#if CONFIG_SW_COEXIST_ENABLE || CONFIG_EXTERNAL_COEX_ENABLE
+            coex_hw_timer_set(0x04, 0x02, 15, 0, 5000);
+            coex_hw_timer_enable(0x04);
+#endif // CONFIG_SW_COEXIST_ENABLE || CONFIG_EXTERNAL_COEX_ENABLE
+            MODEM_SYSCON.modem_rst_conf.val |= (BIT(16) | BIT(18));
+            MODEM_SYSCON.modem_rst_conf.val &= ~(BIT(16) | BIT(18));
+        } else {
+#if CONFIG_SW_COEXIST_ENABLE || CONFIG_EXTERNAL_COEX_ENABLE
+            coex_hw_timer_disable(0x04);
+#endif // CONFIG_SW_COEXIST_ENABLE || CONFIG_EXTERNAL_COEX_ENABLE
+        }
+
+    }
+}
+
 static void IRAM_ATTR osi_assert_wrapper(const uint32_t ln, const char *fn,
                                          uint32_t param1, uint32_t param2)
 {

components/esp_rom/esp32c2/ld/esp32c2.rom.ble-eco4.ld

@@ -293,7 +293,7 @@ r_ble_ll_ctrl_rx_feature_req = 0x40000ee0;
 r_ble_ll_ctrl_rx_feature_rsp = 0x40000ee4;
 r_ble_ll_ctrl_rx_pause_enc_req = 0x40000ee8;
 r_ble_ll_ctrl_rx_pause_enc_rsp = 0x40000eec;
-r_ble_ll_ctrl_rx_pdu = 0x40000ef0;
+//r_ble_ll_ctrl_rx_pdu = 0x40000ef0;
 r_ble_ll_ctrl_rx_periodic_sync_ind = 0x40000ef4;
 r_ble_ll_ctrl_rx_phy_req = 0x40000ef8;
 r_ble_ll_ctrl_rx_phy_rsp = 0x40000efc;
@@ -726,15 +726,15 @@ r_ble_lll_dtm_ev_rx_restart_cb = 0x400015ac;
 r_ble_lll_dtm_ev_tx_resched_cb = 0x400015b0;
 r_ble_lll_dtm_init = 0x400015b4;
 r_ble_lll_dtm_reset = 0x400015b8;
-r_ble_lll_dtm_rx_create_ctx = 0x400015bc;
+//r_ble_lll_dtm_rx_create_ctx = 0x400015bc;
 r_ble_lll_dtm_rx_isr_end = 0x400015c0;
 r_ble_lll_dtm_rx_isr_start = 0x400015c4;
-r_ble_lll_dtm_rx_pkt_in = 0x400015c8;
+//r_ble_lll_dtm_rx_pkt_in = 0x400015c8;
 r_ble_lll_dtm_rx_sched_cb = 0x400015cc;
 r_ble_lll_dtm_rx_start = 0x400015d0;
 r_ble_lll_dtm_rx_test = 0x400015d4;
 r_ble_lll_dtm_set_next = 0x400015d8;
-r_ble_lll_dtm_tx_create_ctx = 0x400015dc;
+//r_ble_lll_dtm_tx_create_ctx = 0x400015dc;
 r_ble_lll_dtm_tx_done = 0x400015e0;
 r_ble_lll_dtm_tx_sched_cb = 0x400015e4;
 r_ble_lll_dtm_tx_test = 0x400015e8;
@@ -761,7 +761,7 @@ r_ble_lll_per_adv_coex_dpc_update_on_data_updated = 0x40001638;
 r_ble_lll_per_adv_coex_dpc_update_on_scheduled = 0x4000163c;
 r_ble_lll_per_adv_coex_dpc_update_on_start = 0x40001640;
 r_ble_lll_reset = 0x40001644;
-r_ble_lll_rfmgmt_controller_sleep_en = 0x40001648;
+//r_ble_lll_rfmgmt_controller_sleep_en = 0x40001648;
 r_ble_lll_rfmgmt_deinit = 0x4000164c;
 //r_ble_lll_rfmgmt_disable = 0x40001650;
 //r_ble_lll_rfmgmt_enable = 0x40001654;
@@ -770,7 +770,7 @@ r_ble_lll_rfmgmt_init = 0x4000165c;
 //r_ble_lll_rfmgmt_is_enabled = 0x40001660;
 r_ble_lll_rfmgmt_release = 0x40001664;
 r_ble_lll_rfmgmt_release_ev = 0x40001668;
-r_ble_lll_rfmgmt_reset = 0x4000166c;
+//r_ble_lll_rfmgmt_reset = 0x4000166c;
 r_ble_lll_rfmgmt_scan_changed = 0x40001670;
 r_ble_lll_rfmgmt_sched_changed = 0x40001674;
 r_ble_lll_rfmgmt_set_sleep_cb = 0x40001678;
@@ -1199,7 +1199,7 @@ r_ble_lll_rfmgmt_wake_up_ev = 0x40002fc4;
 r_ble_lll_sched_env_deinit = 0x40002fc8;
 r_ble_phy_env_deinit = 0x40002fcc;
 r_ble_hw_driver_env_deinit = 0x40002fd0;
-r_ble_lll_dtm_env_init = 0x40002fd4;
+//r_ble_lll_dtm_env_init = 0x40002fd4;
 r_ble_lll_dtm_env_deinit = 0x40002fd8;
 r_ble_lll_scan_callout_env_init = 0x40002fdc;
 r_ble_lll_scan_callout_env_deinit = 0x40002fe0;

components/esp_rom/esp32c2/ld/esp32c2.rom.ble.ld

@@ -577,10 +577,10 @@ r_ble_lll_dtm_end_test = 0x400015a8;
 r_ble_lll_dtm_ev_rx_restart_cb = 0x400015ac;
 r_ble_lll_dtm_ev_tx_resched_cb = 0x400015b0;
 r_ble_lll_dtm_reset = 0x400015b8;
-r_ble_lll_dtm_rx_create_ctx = 0x400015bc;
+//r_ble_lll_dtm_rx_create_ctx = 0x400015bc;
 r_ble_lll_dtm_rx_isr_end = 0x400015c0;
 r_ble_lll_dtm_rx_isr_start = 0x400015c4;
-r_ble_lll_dtm_rx_pkt_in = 0x400015c8;
+//r_ble_lll_dtm_rx_pkt_in = 0x400015c8;
 r_ble_lll_dtm_rx_sched_cb = 0x400015cc;
 r_ble_lll_dtm_rx_start = 0x400015d0;
 r_ble_lll_dtm_rx_test = 0x400015d4;

examples/bluetooth/nimble/hci/main/dtm_configuration_command.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Unlicense OR CC0-1.0
  */
@@ -67,6 +67,36 @@ static int dtm_reconfig_uart_pins_command(int argc, char **argv)
     return 0;
 }
 
+extern int8_t esp_ble_get_dtm_rx_rssi(void);
+static int dtm_get_ble_rx_rssi_command(int argc, char **argv)
+{
+    int8_t rx_rssi = 0x7F;
+    if (esp_bt_controller_get_status() != ESP_BT_CONTROLLER_STATUS_ENABLED) {
+        esp_rom_printf("\nPlease enable BLE DTM mode first by using the command enable_ble_dtm -e 1 before sending this command.\n");
+        return 2;
+    }
+
+    rx_rssi = esp_ble_get_dtm_rx_rssi();
+    if (rx_rssi == 0x7f) {
+        esp_rom_printf("\nRx RSSI is not available!\n");
+    } else {
+        esp_rom_printf("\nRx RSSI is %d dBm\n", rx_rssi);
+    }
+
+    return 0;
+}
+
+esp_err_t esp_console_register_get_ble_rx_rssi_command(void)
+{
+    esp_console_cmd_t command = {
+        .command = "get_ble_rx_rssi",
+        .help = "Get ble rx rssi during DTM",
+        .func = &dtm_get_ble_rx_rssi_command,
+    };
+
+    return esp_console_cmd_register(&command);
+}
+
 esp_err_t esp_console_register_set_ble_tx_power_command(void)
 {
     dtm_set_tx_power_cmd_args.cmd_params = arg_int1("i", "index", "<index>","tx power level index");
@@ -122,6 +152,7 @@ esp_err_t dtm_configuration_command_enable(void)
     esp_console_register_set_ble_tx_power_command();
     esp_console_register_get_ble_tx_power_command();
     esp_console_register_reconfig_dtm_pins_command();
+    esp_console_register_get_ble_rx_rssi_command();
     esp_console_dev_uart_config_t hw_config = ESP_CONSOLE_DEV_UART_CONFIG_DEFAULT();
     ESP_ERROR_CHECK(esp_console_new_repl_uart(&hw_config, &repl_config, &repl));
     ESP_ERROR_CHECK(esp_console_start_repl(repl));

examples/phy/cert_test/main/cmd_ble_dtm.c

@@ -121,6 +121,36 @@ static int dtm_test_enable_command(int argc, char **argv)
     return 0;
 }
 
+extern int8_t esp_ble_get_dtm_rx_rssi(void);
+static int dtm_get_ble_rx_rssi_command(int argc, char **argv)
+{
+    int8_t rx_rssi = 0x7F;
+    if (esp_bt_controller_get_status() != ESP_BT_CONTROLLER_STATUS_ENABLED) {
+        esp_rom_printf("\nPlease enable BLE DTM mode first by using the command enable_ble_dtm -e 1 before sending this command.\n");
+        return 2;
+    }
+
+    rx_rssi = esp_ble_get_dtm_rx_rssi();
+    if (rx_rssi == 0x7f) {
+        esp_rom_printf("\nRx RSSI is not available!\n");
+    } else {
+        esp_rom_printf("\nRx RSSI is %d dBm\n", rx_rssi);
+    }
+
+    return 0;
+}
+
+esp_err_t esp_console_register_get_ble_rx_rssi_command(void)
+{
+    esp_console_cmd_t command = {
+        .command = "get_ble_rx_rssi",
+        .help = "Get ble rx rssi during DTM",
+        .func = &dtm_get_ble_rx_rssi_command,
+    };
+
+    return esp_console_cmd_register(&command);
+}
+
 esp_err_t esp_console_register_set_ble_tx_power_command(void)
 {
     dtm_set_tx_power_cmd_args.cmd_params = arg_int1("i", "index", "<index>","tx power level index");
@@ -185,5 +215,6 @@ esp_err_t dtm_configuration_command_register(void)
     esp_console_register_get_ble_tx_power_command();
     esp_console_register_reconfig_dtm_pins_command();
     esp_console_register_enable_ble_dtm_command();
+    esp_console_register_get_ble_rx_rssi_command();
     return ESP_OK;
 }

examples/phy/cert_test/sdkconfig.defaults.esp32c6

@@ -4,6 +4,7 @@
 
 CONFIG_COMMANDS_ENABLE_BLE_DTM_TEST=y
 CONFIG_BT_CONTROLLER_ONLY=y
+CONFIG_BT_LE_DTM_ENABLED=y
 CONFIG_BT_LE_HCI_INTERFACE_USE_UART=y
 CONFIG_BT_LE_HCI_UART_TX_PIN=8
 CONFIG_BT_LE_HCI_UART_RX_PIN=9

examples/phy/cert_test/sdkconfig.defaults.esp32h2

@@ -1,8 +1,9 @@
 #
-# ESP32C6-specific
+# ESP32H2-specific
 #
 CONFIG_COMMANDS_ENABLE_BLE_DTM_TEST=y
 CONFIG_BT_CONTROLLER_ONLY=y
+CONFIG_BT_LE_DTM_ENABLED=y
 CONFIG_BT_LE_HCI_INTERFACE_USE_UART=y
 CONFIG_BT_LE_HCI_UART_TX_PIN=8
 CONFIG_BT_LE_HCI_UART_RX_PIN=9