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change(drivers): other driver changes for cache malloc

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This commit is contained in:
Armando
2024-04-08 11:01:05 +08:00
parent 0df418facd
commit d341540a5e
9 changed files with 11 additions and 11 deletions
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2
components/esp_driver_cam/csi/src/esp_cam_ctlr_csi.c
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@@ -149,7 +149,7 @@ esp_err_t esp_cam_new_csi_ctlr(const esp_cam_ctlr_csi_config_t *config, esp_cam_
size_t dma_alignment = 4; //TODO: IDF-9126, replace with dwgdma alignment API size_t dma_alignment = 4; //TODO: IDF-9126, replace with dwgdma alignment API
size_t cache_alignment = 1; size_t cache_alignment = 1;
ESP_GOTO_ON_ERROR(esp_cache_get_alignment(ESP_CACHE_MALLOC_FLAG_PSRAM | ESP_CACHE_MALLOC_FLAG_DMA, &cache_alignment), err, TAG, "failed to get cache alignment"); ESP_GOTO_ON_ERROR(esp_cache_get_alignment(MALLOC_CAP_SPIRAM | MALLOC_CAP_DMA, &cache_alignment), err, TAG, "failed to get cache alignment");
size_t alignment = MAX(cache_alignment, dma_alignment); size_t alignment = MAX(cache_alignment, dma_alignment);
ESP_LOGD(TAG, "alignment: 0x%x\n", alignment); ESP_LOGD(TAG, "alignment: 0x%x\n", alignment);

2
components/esp_driver_jpeg/jpeg_decode.c
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@@ -289,7 +289,7 @@ void *jpeg_alloc_decoder_mem(size_t size, const jpeg_decode_memory_alloc_cfg_t *
FOr input buffer(for decoder is PSRAM write to 2DDMA), no restriction for any align (both cache writeback and requirement from 2DDMA). FOr input buffer(for decoder is PSRAM write to 2DDMA), no restriction for any align (both cache writeback and requirement from 2DDMA).
*/ */
size_t cache_align = 0; size_t cache_align = 0;
esp_cache_get_alignment(ESP_CACHE_MALLOC_FLAG_PSRAM, &cache_align); esp_cache_get_alignment(MALLOC_CAP_SPIRAM, &cache_align);
if (mem_cfg->buffer_direction == JPEG_DEC_ALLOC_OUTPUT_BUFFER) { if (mem_cfg->buffer_direction == JPEG_DEC_ALLOC_OUTPUT_BUFFER) {
size = JPEG_ALIGN_UP(size, cache_align); size = JPEG_ALIGN_UP(size, cache_align);
*allocated_size = size; *allocated_size = size;

2
components/esp_driver_jpeg/jpeg_emit_marker.c
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@@ -228,7 +228,7 @@ esp_err_t emit_com_marker(jpeg_enc_header_info_t *header_info)
{ {
// Calculate how many bytes should be compensate to make it byte aligned. // Calculate how many bytes should be compensate to make it byte aligned.
size_t cache_align = 0; size_t cache_align = 0;
esp_cache_get_alignment(ESP_CACHE_MALLOC_FLAG_PSRAM, &cache_align); esp_cache_get_alignment(MALLOC_CAP_SPIRAM, &cache_align);
// compensate_size = aligned_size - SOS marker size(2 * header_info->num_components + 2 + 1 + 3 + 2) - COM marker size(4). // compensate_size = aligned_size - SOS marker size(2 * header_info->num_components + 2 + 1 + 3 + 2) - COM marker size(4).
int compensate_size = ((header_info->header_len / cache_align + 1) * cache_align) - header_info->header_len - (2 * header_info->num_components + 2 + 1 + 3 + 2) - 4; int compensate_size = ((header_info->header_len / cache_align + 1) * cache_align) - header_info->header_len - (2 * header_info->num_components + 2 + 1 + 3 + 2) - 4;
if (compensate_size < 0) { if (compensate_size < 0) {

2
components/esp_driver_jpeg/jpeg_encode.c
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@@ -294,7 +294,7 @@ void *jpeg_alloc_encoder_mem(size_t size, const jpeg_encode_memory_alloc_cfg_t *
For input buffer(for decoder is PSRAM write to 2DDMA), no restriction for any align (both cache writeback and requirement from 2DDMA). For input buffer(for decoder is PSRAM write to 2DDMA), no restriction for any align (both cache writeback and requirement from 2DDMA).
*/ */
size_t cache_align = 0; size_t cache_align = 0;
esp_cache_get_alignment(ESP_CACHE_MALLOC_FLAG_PSRAM, &cache_align); esp_cache_get_alignment(MALLOC_CAP_SPIRAM, &cache_align);
if (mem_cfg->buffer_direction == JPEG_ENC_ALLOC_OUTPUT_BUFFER) { if (mem_cfg->buffer_direction == JPEG_ENC_ALLOC_OUTPUT_BUFFER) {
size = JPEG_ALIGN_UP(size, cache_align); size = JPEG_ALIGN_UP(size, cache_align);
*allocated_size = size; *allocated_size = size;

2
components/esp_driver_spi/src/gpspi/spi_common.c
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@@ -835,7 +835,7 @@ esp_err_t spi_bus_initialize(spi_host_device_t host_id, const spi_bus_config_t *
goto cleanup; goto cleanup;
} }
#if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE #if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE
esp_cache_get_alignment(ESP_CACHE_MALLOC_FLAG_DMA, (size_t *)&bus_attr->internal_mem_align_size); esp_cache_get_alignment(MALLOC_CAP_DMA, (size_t *)&bus_attr->internal_mem_align_size);
#else #else
bus_attr->internal_mem_align_size = 4; bus_attr->internal_mem_align_size = 4;
#endif #endif

2
components/esp_driver_spi/src/gpspi/spi_slave.c
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@@ -192,7 +192,7 @@ esp_err_t spi_slave_initialize(spi_host_device_t host, const spi_bus_config_t *b
#if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE #if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE
size_t alignment; size_t alignment;
esp_cache_get_alignment(ESP_CACHE_MALLOC_FLAG_DMA, &alignment); esp_cache_get_alignment(MALLOC_CAP_DMA, &alignment);
spihost[host]->internal_mem_align_size = alignment; spihost[host]->internal_mem_align_size = alignment;
#else #else
spihost[host]->internal_mem_align_size = 4; spihost[host]->internal_mem_align_size = 4;

2
components/esp_driver_spi/src/gpspi/spi_slave_hd.c
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@@ -122,7 +122,7 @@ esp_err_t spi_slave_hd_init(spi_host_device_t host_id, const spi_bus_config_t *b
#if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE #if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE
size_t alignment; size_t alignment;
esp_cache_get_alignment(ESP_CACHE_MALLOC_FLAG_DMA, &alignment); esp_cache_get_alignment(MALLOC_CAP_DMA, &alignment);
host->internal_mem_align_size = alignment; host->internal_mem_align_size = alignment;
#else #else
host->internal_mem_align_size = 4; host->internal_mem_align_size = 4;

6
components/mbedtls/port/aes/dma/esp_aes_dma_core.c
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@@ -291,11 +291,11 @@ static inline size_t get_cache_line_size(const void *addr)
#if (CONFIG_SPIRAM && SOC_PSRAM_DMA_CAPABLE) #if (CONFIG_SPIRAM && SOC_PSRAM_DMA_CAPABLE)
if (esp_ptr_external_ram(addr)) { if (esp_ptr_external_ram(addr)) {
ret = esp_cache_get_alignment(ESP_CACHE_MALLOC_FLAG_PSRAM, &cache_line_size); ret = esp_cache_get_alignment(MALLOC_CAP_SPIRAM, &cache_line_size);
} else } else
#endif #endif
{ {
ret = esp_cache_get_alignment(ESP_CACHE_MALLOC_FLAG_DMA, &cache_line_size); ret = esp_cache_get_alignment(MALLOC_CAP_DMA, &cache_line_size);
} }
if (ret != ESP_OK) { if (ret != ESP_OK) {
@@ -949,7 +949,7 @@ int esp_aes_process_dma(esp_aes_context *ctx, const unsigned char *input, unsign
} }
if (esp_ptr_external_ram(output)) { if (esp_ptr_external_ram(output)) {
size_t dcache_line_size; size_t dcache_line_size;
ret = esp_cache_get_alignment(ESP_CACHE_MALLOC_FLAG_PSRAM, &dcache_line_size); ret = esp_cache_get_alignment(MALLOC_CAP_SPIRAM, &dcache_line_size);
if (ret != ESP_OK) { if (ret != ESP_OK) {
return ret; return ret;
} }

2
components/usb/hcd_dwc.c
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@@ -1065,7 +1065,7 @@ void *transfer_descriptor_list_alloc(size_t list_len, size_t *list_len_bytes_out
#if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE #if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE
// Required Transfer Descriptor List size (in bytes) might not be aligned to cache line size, align the size up // Required Transfer Descriptor List size (in bytes) might not be aligned to cache line size, align the size up
size_t data_cache_line_size = 0; size_t data_cache_line_size = 0;
esp_cache_get_alignment(ESP_CACHE_MALLOC_FLAG_DMA, &data_cache_line_size); esp_cache_get_alignment(MALLOC_CAP_DMA, &data_cache_line_size);
const size_t required_list_len_bytes = list_len * sizeof(usb_dwc_ll_dma_qtd_t); const size_t required_list_len_bytes = list_len * sizeof(usb_dwc_ll_dma_qtd_t);
*list_len_bytes_out = ALIGN_UP_BY(required_list_len_bytes, data_cache_line_size); *list_len_bytes_out = ALIGN_UP_BY(required_list_len_bytes, data_cache_line_size);
#else #else