espressif/esp-idf
1
0
Fork 1
mirror of https://github.com/espressif/esp-idf.git synced 2025-07-30 10:47:19 +02:00
Code Issues Packages Projects Releases Wiki Activity

bootloader: fixed super watchdog not enabled issue on C3, S3, H4

Browse Source
This commit is contained in:
Xiao Xufeng
2023-03-07 11:13:18 +08:00
parent 1392cce5e1
commit d43934f32d
6 changed files with 12 additions and 12 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
components/bootloader_support/src/esp32c3/bootloader_esp32c3.c
View File

@ -269,20 +269,20 @@ static inline void bootloader_ana_reset_config(void)
switch (efuse_hal_chip_revision()) { switch (efuse_hal_chip_revision()) {
case 0: case 0:
case 1: case 1:
//Enable WDT reset. Disable BOR and GLITCH reset //Enable WDT reset. Disable BOD and GLITCH reset
bootloader_ana_super_wdt_reset_config(true); bootloader_ana_super_wdt_reset_config(true);
bootloader_ana_bod_reset_config(false); bootloader_ana_bod_reset_config(false);
bootloader_ana_clock_glitch_reset_config(false); bootloader_ana_clock_glitch_reset_config(false);
break; break;
case 2: case 2:
//Enable WDT and BOR reset. Disable GLITCH reset //Enable WDT and BOD reset. Disable GLITCH reset
bootloader_ana_super_wdt_reset_config(true); bootloader_ana_super_wdt_reset_config(true);
bootloader_ana_bod_reset_config(true); bootloader_ana_bod_reset_config(true);
bootloader_ana_clock_glitch_reset_config(false); bootloader_ana_clock_glitch_reset_config(false);
break; break;
case 3: case 3:
default: default:
//Enable WDT, BOR, and GLITCH reset //Enable WDT, BOD, and GLITCH reset
bootloader_ana_super_wdt_reset_config(true); bootloader_ana_super_wdt_reset_config(true);
bootloader_ana_bod_reset_config(true); bootloader_ana_bod_reset_config(true);
bootloader_ana_clock_glitch_reset_config(true); bootloader_ana_clock_glitch_reset_config(true);

6
components/bootloader_support/src/esp32c3/bootloader_soc.c
View File

@ -12,15 +12,15 @@ void bootloader_ana_super_wdt_reset_config(bool enable)
REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_SUPER_WDT_RST); REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_SUPER_WDT_RST);
if (enable) { if (enable) {
REG_SET_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_BYPASS_RST);
} else {
REG_CLR_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_BYPASS_RST); REG_CLR_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_BYPASS_RST);
} else {
REG_SET_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_BYPASS_RST);
} }
} }
void bootloader_ana_bod_reset_config(bool enable) void bootloader_ana_bod_reset_config(bool enable)
{ {
REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_BOR_RST); REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_BOD_RST);
if (enable) { if (enable) {
REG_SET_BIT(RTC_CNTL_BROWN_OUT_REG, RTC_CNTL_BROWN_OUT_ANA_RST_EN); REG_SET_BIT(RTC_CNTL_BROWN_OUT_REG, RTC_CNTL_BROWN_OUT_ANA_RST_EN);

2
components/bootloader_support/src/esp32s3/bootloader_esp32s3.c
View File

@ -314,7 +314,7 @@ static void bootloader_super_wdt_auto_feed(void)
static inline void bootloader_ana_reset_config(void) static inline void bootloader_ana_reset_config(void)
{ {
//Enable WDT, BOR, and GLITCH reset //Enable WDT, BOD, and GLITCH reset
bootloader_ana_super_wdt_reset_config(true); bootloader_ana_super_wdt_reset_config(true);
bootloader_ana_bod_reset_config(true); bootloader_ana_bod_reset_config(true);
bootloader_ana_clock_glitch_reset_config(true); bootloader_ana_clock_glitch_reset_config(true);

6
components/bootloader_support/src/esp32s3/bootloader_soc.c
View File

@ -12,15 +12,15 @@ void bootloader_ana_super_wdt_reset_config(bool enable)
REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_SUPER_WDT_RST); REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_SUPER_WDT_RST);
if (enable) { if (enable) {
REG_SET_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_BYPASS_RST);
} else {
REG_CLR_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_BYPASS_RST); REG_CLR_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_BYPASS_RST);
} else {
REG_SET_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_BYPASS_RST);
} }
} }
void bootloader_ana_bod_reset_config(bool enable) void bootloader_ana_bod_reset_config(bool enable)
{ {
REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_BOR_RST); REG_CLR_BIT(RTC_CNTL_FIB_SEL_REG, RTC_CNTL_FIB_BOD_RST);
if (enable) { if (enable) {
REG_SET_BIT(RTC_CNTL_BROWN_OUT_REG, RTC_CNTL_BROWN_OUT_ANA_RST_EN); REG_SET_BIT(RTC_CNTL_BROWN_OUT_REG, RTC_CNTL_BROWN_OUT_ANA_RST_EN);

2
components/soc/esp32c3/include/soc/rtc_cntl_reg.h
View File

@ -2353,7 +2353,7 @@ extern "C" {
#define RTC_CNTL_FIB_SEL_S 0 #define RTC_CNTL_FIB_SEL_S 0
#define RTC_CNTL_FIB_GLITCH_RST BIT(0) #define RTC_CNTL_FIB_GLITCH_RST BIT(0)
#define RTC_CNTL_FIB_BOR_RST BIT(1) #define RTC_CNTL_FIB_BOD_RST BIT(1)
#define RTC_CNTL_FIB_SUPER_WDT_RST BIT(2) #define RTC_CNTL_FIB_SUPER_WDT_RST BIT(2)
#define RTC_CNTL_GPIO_WAKEUP_REG (DR_REG_RTCCNTL_BASE + 0x0110) #define RTC_CNTL_GPIO_WAKEUP_REG (DR_REG_RTCCNTL_BASE + 0x0110)

2
components/soc/esp32s3/include/soc/rtc_cntl_reg.h
View File

@ -3571,7 +3571,7 @@ ork.*/
#define RTC_CNTL_FIB_SEL_S 0 #define RTC_CNTL_FIB_SEL_S 0
#define RTC_CNTL_FIB_GLITCH_RST BIT(0) #define RTC_CNTL_FIB_GLITCH_RST BIT(0)
#define RTC_CNTL_FIB_BOR_RST BIT(1) #define RTC_CNTL_FIB_BOD_RST BIT(1)
#define RTC_CNTL_FIB_SUPER_WDT_RST BIT(2) #define RTC_CNTL_FIB_SUPER_WDT_RST BIT(2)
#define RTC_CNTL_TOUCH_DAC_REG (DR_REG_RTCCNTL_BASE + 0x14C) #define RTC_CNTL_TOUCH_DAC_REG (DR_REG_RTCCNTL_BASE + 0x14C)