From f99c3c6343df5badd3d28e8410c7b77724961a4f Mon Sep 17 00:00:00 2001 From: wuzhenghui Date: Thu, 6 Mar 2025 21:02:37 +0800 Subject: [PATCH] fix(esp_system): fix possible cache_error by another core accessing flash in esp_restart --- .../esp_system/port/soc/esp32s3/system_internal.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/components/esp_system/port/soc/esp32s3/system_internal.c b/components/esp_system/port/soc/esp32s3/system_internal.c index 3450f4a6ce..6b5ab825d9 100644 --- a/components/esp_system/port/soc/esp32s3/system_internal.c +++ b/components/esp_system/port/soc/esp32s3/system_internal.c @@ -1,6 +1,6 @@ /* - * SPDX-FileCopyrightText: 2018-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2018-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -101,10 +101,6 @@ void IRAM_ATTR esp_restart_noos(void) } #endif - // Disable cache - Cache_Disable_ICache(); - Cache_Disable_DCache(); - // Reset and stall the other CPU. // CPU must be reset before stalling, in case it was running a s32c1i // instruction. This would cause memory pool to be locked by arbiter @@ -116,6 +112,10 @@ void IRAM_ATTR esp_restart_noos(void) esp_cpu_stall(other_core_id); #endif + // Disable cache + Cache_Disable_ICache(); + Cache_Disable_DCache(); + // 2nd stage bootloader reconfigures SPI flash signals. // Reset them to the defaults expected by ROM. WRITE_PERI_REG(GPIO_FUNC0_IN_SEL_CFG_REG, 0x30);