From d798f6f1a77aa0385d89cc19be9c57dd90c0ea2c Mon Sep 17 00:00:00 2001 From: gaoxu Date: Thu, 12 Dec 2024 18:26:35 +0800 Subject: [PATCH] feat(esp32h21): update pmu reg and struct files (stage 2-3) --- .../soc/esp32h21/register/soc/pmu_reg.h | 1114 ++++++++++++++--- .../soc/esp32h21/register/soc/pmu_struct.h | 993 +++++++++------ 2 files changed, 1551 insertions(+), 556 deletions(-) diff --git a/components/soc/esp32h21/register/soc/pmu_reg.h b/components/soc/esp32h21/register/soc/pmu_reg.h index 4394e9e124..7f6a61fda8 100644 --- a/components/soc/esp32h21/register/soc/pmu_reg.h +++ b/components/soc/esp32h21/register/soc/pmu_reg.h @@ -15,13 +15,13 @@ extern "C" { * need_des */ #define PMU_HP_ACTIVE_DIG_POWER_REG (DR_REG_PMU_BASE + 0x0) -/** PMU_HP_ACTIVE_VDD_SPI_PD_EN : R/W; bitpos: [21]; default: 0; +/** PMU_HP_ACTIVE_VDD_FLASH_MODE : R/W; bitpos: [21:18]; default: 0; * need_des */ -#define PMU_HP_ACTIVE_VDD_SPI_PD_EN (BIT(21)) -#define PMU_HP_ACTIVE_VDD_SPI_PD_EN_M (PMU_HP_ACTIVE_VDD_SPI_PD_EN_V << PMU_HP_ACTIVE_VDD_SPI_PD_EN_S) -#define PMU_HP_ACTIVE_VDD_SPI_PD_EN_V 0x00000001U -#define PMU_HP_ACTIVE_VDD_SPI_PD_EN_S 21 +#define PMU_HP_ACTIVE_VDD_FLASH_MODE 0x0000000FU +#define PMU_HP_ACTIVE_VDD_FLASH_MODE_M (PMU_HP_ACTIVE_VDD_FLASH_MODE_V << PMU_HP_ACTIVE_VDD_FLASH_MODE_S) +#define PMU_HP_ACTIVE_VDD_FLASH_MODE_V 0x0000000FU +#define PMU_HP_ACTIVE_VDD_FLASH_MODE_S 18 /** PMU_HP_ACTIVE_HP_MEM_DSLP : R/W; bitpos: [22]; default: 0; * need_des */ @@ -43,6 +43,13 @@ extern "C" { #define PMU_HP_ACTIVE_PD_HP_WIFI_PD_EN_M (PMU_HP_ACTIVE_PD_HP_WIFI_PD_EN_V << PMU_HP_ACTIVE_PD_HP_WIFI_PD_EN_S) #define PMU_HP_ACTIVE_PD_HP_WIFI_PD_EN_V 0x00000001U #define PMU_HP_ACTIVE_PD_HP_WIFI_PD_EN_S 27 +/** PMU_HP_ACTIVE_PD_HP_PERI_PD_EN : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_PD_HP_PERI_PD_EN (BIT(28)) +#define PMU_HP_ACTIVE_PD_HP_PERI_PD_EN_M (PMU_HP_ACTIVE_PD_HP_PERI_PD_EN_V << PMU_HP_ACTIVE_PD_HP_PERI_PD_EN_S) +#define PMU_HP_ACTIVE_PD_HP_PERI_PD_EN_V 0x00000001U +#define PMU_HP_ACTIVE_PD_HP_PERI_PD_EN_S 28 /** PMU_HP_ACTIVE_PD_HP_CPU_PD_EN : R/W; bitpos: [29]; default: 0; * need_des */ @@ -192,6 +199,48 @@ extern "C" { * need_des */ #define PMU_HP_ACTIVE_BIAS_REG (DR_REG_PMU_BASE + 0x18) +/** PMU_HP_ACTIVE_DCDC_CCM_ENB : R/W; bitpos: [9]; default: 1; + * need_des + */ +#define PMU_HP_ACTIVE_DCDC_CCM_ENB (BIT(9)) +#define PMU_HP_ACTIVE_DCDC_CCM_ENB_M (PMU_HP_ACTIVE_DCDC_CCM_ENB_V << PMU_HP_ACTIVE_DCDC_CCM_ENB_S) +#define PMU_HP_ACTIVE_DCDC_CCM_ENB_V 0x00000001U +#define PMU_HP_ACTIVE_DCDC_CCM_ENB_S 9 +/** PMU_HP_ACTIVE_DCDC_CLEAR_RDY : R/W; bitpos: [10]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_DCDC_CLEAR_RDY (BIT(10)) +#define PMU_HP_ACTIVE_DCDC_CLEAR_RDY_M (PMU_HP_ACTIVE_DCDC_CLEAR_RDY_V << PMU_HP_ACTIVE_DCDC_CLEAR_RDY_S) +#define PMU_HP_ACTIVE_DCDC_CLEAR_RDY_V 0x00000001U +#define PMU_HP_ACTIVE_DCDC_CLEAR_RDY_S 10 +/** PMU_HP_ACTIVE_DIG_PMU_DPCUR_BIAS : R/W; bitpos: [12:11]; default: 3; + * need_des + */ +#define PMU_HP_ACTIVE_DIG_PMU_DPCUR_BIAS 0x00000003U +#define PMU_HP_ACTIVE_DIG_PMU_DPCUR_BIAS_M (PMU_HP_ACTIVE_DIG_PMU_DPCUR_BIAS_V << PMU_HP_ACTIVE_DIG_PMU_DPCUR_BIAS_S) +#define PMU_HP_ACTIVE_DIG_PMU_DPCUR_BIAS_V 0x00000003U +#define PMU_HP_ACTIVE_DIG_PMU_DPCUR_BIAS_S 11 +/** PMU_HP_ACTIVE_DIG_PMU_DSFMOS : R/W; bitpos: [16:13]; default: 6; + * need_des + */ +#define PMU_HP_ACTIVE_DIG_PMU_DSFMOS 0x0000000FU +#define PMU_HP_ACTIVE_DIG_PMU_DSFMOS_M (PMU_HP_ACTIVE_DIG_PMU_DSFMOS_V << PMU_HP_ACTIVE_DIG_PMU_DSFMOS_S) +#define PMU_HP_ACTIVE_DIG_PMU_DSFMOS_V 0x0000000FU +#define PMU_HP_ACTIVE_DIG_PMU_DSFMOS_S 13 +/** PMU_HP_ACTIVE_DCM_VSET : R/W; bitpos: [21:17]; default: 23; + * need_des + */ +#define PMU_HP_ACTIVE_DCM_VSET 0x0000001FU +#define PMU_HP_ACTIVE_DCM_VSET_M (PMU_HP_ACTIVE_DCM_VSET_V << PMU_HP_ACTIVE_DCM_VSET_S) +#define PMU_HP_ACTIVE_DCM_VSET_V 0x0000001FU +#define PMU_HP_ACTIVE_DCM_VSET_S 17 +/** PMU_HP_ACTIVE_DCM_MODE : R/W; bitpos: [23:22]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_DCM_MODE 0x00000003U +#define PMU_HP_ACTIVE_DCM_MODE_M (PMU_HP_ACTIVE_DCM_MODE_V << PMU_HP_ACTIVE_DCM_MODE_S) +#define PMU_HP_ACTIVE_DCM_MODE_V 0x00000003U +#define PMU_HP_ACTIVE_DCM_MODE_S 22 /** PMU_HP_ACTIVE_XPD_TRX : R/W; bitpos: [24]; default: 1; * need_des */ @@ -206,6 +255,13 @@ extern "C" { #define PMU_HP_ACTIVE_XPD_BIAS_M (PMU_HP_ACTIVE_XPD_BIAS_V << PMU_HP_ACTIVE_XPD_BIAS_S) #define PMU_HP_ACTIVE_XPD_BIAS_V 0x00000001U #define PMU_HP_ACTIVE_XPD_BIAS_S 25 +/** PMU_HP_ACTIVE_DISCNNT_DIG_RTC : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_ACTIVE_DISCNNT_DIG_RTC (BIT(29)) +#define PMU_HP_ACTIVE_DISCNNT_DIG_RTC_M (PMU_HP_ACTIVE_DISCNNT_DIG_RTC_V << PMU_HP_ACTIVE_DISCNNT_DIG_RTC_S) +#define PMU_HP_ACTIVE_DISCNNT_DIG_RTC_V 0x00000001U +#define PMU_HP_ACTIVE_DISCNNT_DIG_RTC_S 29 /** PMU_HP_ACTIVE_PD_CUR : R/W; bitpos: [30]; default: 0; * need_des */ @@ -239,27 +295,6 @@ extern "C" { #define PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE_M (PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE_V << PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE_S) #define PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE_V 0x00000003U #define PMU_HP_MODEM2ACTIVE_BACKUP_MODEM_CLK_CODE_S 6 -/** PMU_HP_ACTIVE_RETENTION_MODE : R/W; bitpos: [10]; default: 0; - * need_des - */ -#define PMU_HP_ACTIVE_RETENTION_MODE (BIT(10)) -#define PMU_HP_ACTIVE_RETENTION_MODE_M (PMU_HP_ACTIVE_RETENTION_MODE_V << PMU_HP_ACTIVE_RETENTION_MODE_S) -#define PMU_HP_ACTIVE_RETENTION_MODE_V 0x00000001U -#define PMU_HP_ACTIVE_RETENTION_MODE_S 10 -/** PMU_HP_SLEEP2ACTIVE_RETENTION_EN : R/W; bitpos: [11]; default: 0; - * need_des - */ -#define PMU_HP_SLEEP2ACTIVE_RETENTION_EN (BIT(11)) -#define PMU_HP_SLEEP2ACTIVE_RETENTION_EN_M (PMU_HP_SLEEP2ACTIVE_RETENTION_EN_V << PMU_HP_SLEEP2ACTIVE_RETENTION_EN_S) -#define PMU_HP_SLEEP2ACTIVE_RETENTION_EN_V 0x00000001U -#define PMU_HP_SLEEP2ACTIVE_RETENTION_EN_S 11 -/** PMU_HP_MODEM2ACTIVE_RETENTION_EN : R/W; bitpos: [12]; default: 0; - * need_des - */ -#define PMU_HP_MODEM2ACTIVE_RETENTION_EN (BIT(12)) -#define PMU_HP_MODEM2ACTIVE_RETENTION_EN_M (PMU_HP_MODEM2ACTIVE_RETENTION_EN_V << PMU_HP_MODEM2ACTIVE_RETENTION_EN_S) -#define PMU_HP_MODEM2ACTIVE_RETENTION_EN_V 0x00000001U -#define PMU_HP_MODEM2ACTIVE_RETENTION_EN_S 12 /** PMU_HP_SLEEP2ACTIVE_BACKUP_CLK_SEL : R/W; bitpos: [15:14]; default: 0; * need_des */ @@ -274,19 +309,19 @@ extern "C" { #define PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL_M (PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL_V << PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL_S) #define PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL_V 0x00000003U #define PMU_HP_MODEM2ACTIVE_BACKUP_CLK_SEL_S 16 -/** PMU_HP_SLEEP2ACTIVE_BACKUP_MODE : R/W; bitpos: [22:20]; default: 0; +/** PMU_HP_SLEEP2ACTIVE_BACKUP_MODE : R/W; bitpos: [22:18]; default: 0; * need_des */ -#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODE 0x00000007U +#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODE 0x0000001FU #define PMU_HP_SLEEP2ACTIVE_BACKUP_MODE_M (PMU_HP_SLEEP2ACTIVE_BACKUP_MODE_V << PMU_HP_SLEEP2ACTIVE_BACKUP_MODE_S) -#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODE_V 0x00000007U -#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODE_S 20 -/** PMU_HP_MODEM2ACTIVE_BACKUP_MODE : R/W; bitpos: [25:23]; default: 0; +#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODE_V 0x0000001FU +#define PMU_HP_SLEEP2ACTIVE_BACKUP_MODE_S 18 +/** PMU_HP_MODEM2ACTIVE_BACKUP_MODE : R/W; bitpos: [27:23]; default: 0; * need_des */ -#define PMU_HP_MODEM2ACTIVE_BACKUP_MODE 0x00000007U +#define PMU_HP_MODEM2ACTIVE_BACKUP_MODE 0x0000001FU #define PMU_HP_MODEM2ACTIVE_BACKUP_MODE_M (PMU_HP_MODEM2ACTIVE_BACKUP_MODE_V << PMU_HP_MODEM2ACTIVE_BACKUP_MODE_S) -#define PMU_HP_MODEM2ACTIVE_BACKUP_MODE_V 0x00000007U +#define PMU_HP_MODEM2ACTIVE_BACKUP_MODE_V 0x0000001FU #define PMU_HP_MODEM2ACTIVE_BACKUP_MODE_S 23 /** PMU_HP_SLEEP2ACTIVE_BACKUP_EN : R/W; bitpos: [29]; default: 0; * need_des @@ -366,14 +401,14 @@ extern "C" { #define PMU_HP_ACTIVE_HP_POWER_DET_BYPASS_M (PMU_HP_ACTIVE_HP_POWER_DET_BYPASS_V << PMU_HP_ACTIVE_HP_POWER_DET_BYPASS_S) #define PMU_HP_ACTIVE_HP_POWER_DET_BYPASS_V 0x00000001U #define PMU_HP_ACTIVE_HP_POWER_DET_BYPASS_S 0 -/** PMU_LP_DBIAS_VOL : RO; bitpos: [8:4]; default: 17; +/** PMU_LP_DBIAS_VOL : RO; bitpos: [8:4]; default: 24; * need_des */ #define PMU_LP_DBIAS_VOL 0x0000001FU #define PMU_LP_DBIAS_VOL_M (PMU_LP_DBIAS_VOL_V << PMU_LP_DBIAS_VOL_S) #define PMU_LP_DBIAS_VOL_V 0x0000001FU #define PMU_LP_DBIAS_VOL_S 4 -/** PMU_HP_DBIAS_VOL : RO; bitpos: [13:9]; default: 16; +/** PMU_HP_DBIAS_VOL : RO; bitpos: [13:9]; default: 24; * need_des */ #define PMU_HP_DBIAS_VOL 0x0000001FU @@ -453,6 +488,13 @@ extern "C" { * need_des */ #define PMU_HP_ACTIVE_XTAL_REG (DR_REG_PMU_BASE + 0x30) +/** PMU_HP_ACTIVE_XPD_XTALX2 : R/W; bitpos: [30]; default: 1; + * need_des + */ +#define PMU_HP_ACTIVE_XPD_XTALX2 (BIT(30)) +#define PMU_HP_ACTIVE_XPD_XTALX2_M (PMU_HP_ACTIVE_XPD_XTALX2_V << PMU_HP_ACTIVE_XPD_XTALX2_S) +#define PMU_HP_ACTIVE_XPD_XTALX2_V 0x00000001U +#define PMU_HP_ACTIVE_XPD_XTALX2_S 30 /** PMU_HP_ACTIVE_XPD_XTAL : R/W; bitpos: [31]; default: 1; * need_des */ @@ -465,13 +507,13 @@ extern "C" { * need_des */ #define PMU_HP_MODEM_DIG_POWER_REG (DR_REG_PMU_BASE + 0x34) -/** PMU_HP_MODEM_VDD_SPI_PD_EN : R/W; bitpos: [21]; default: 0; +/** PMU_HP_MODEM_VDD_FLASH_MODE : R/W; bitpos: [21:18]; default: 0; * need_des */ -#define PMU_HP_MODEM_VDD_SPI_PD_EN (BIT(21)) -#define PMU_HP_MODEM_VDD_SPI_PD_EN_M (PMU_HP_MODEM_VDD_SPI_PD_EN_V << PMU_HP_MODEM_VDD_SPI_PD_EN_S) -#define PMU_HP_MODEM_VDD_SPI_PD_EN_V 0x00000001U -#define PMU_HP_MODEM_VDD_SPI_PD_EN_S 21 +#define PMU_HP_MODEM_VDD_FLASH_MODE 0x0000000FU +#define PMU_HP_MODEM_VDD_FLASH_MODE_M (PMU_HP_MODEM_VDD_FLASH_MODE_V << PMU_HP_MODEM_VDD_FLASH_MODE_S) +#define PMU_HP_MODEM_VDD_FLASH_MODE_V 0x0000000FU +#define PMU_HP_MODEM_VDD_FLASH_MODE_S 18 /** PMU_HP_MODEM_HP_MEM_DSLP : R/W; bitpos: [22]; default: 0; * need_des */ @@ -493,6 +535,13 @@ extern "C" { #define PMU_HP_MODEM_PD_HP_WIFI_PD_EN_M (PMU_HP_MODEM_PD_HP_WIFI_PD_EN_V << PMU_HP_MODEM_PD_HP_WIFI_PD_EN_S) #define PMU_HP_MODEM_PD_HP_WIFI_PD_EN_V 0x00000001U #define PMU_HP_MODEM_PD_HP_WIFI_PD_EN_S 27 +/** PMU_HP_MODEM_PD_HP_PERI_PD_EN : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_PD_HP_PERI_PD_EN (BIT(28)) +#define PMU_HP_MODEM_PD_HP_PERI_PD_EN_M (PMU_HP_MODEM_PD_HP_PERI_PD_EN_V << PMU_HP_MODEM_PD_HP_PERI_PD_EN_S) +#define PMU_HP_MODEM_PD_HP_PERI_PD_EN_V 0x00000001U +#define PMU_HP_MODEM_PD_HP_PERI_PD_EN_S 28 /** PMU_HP_MODEM_PD_HP_CPU_PD_EN : R/W; bitpos: [29]; default: 0; * need_des */ @@ -642,6 +691,48 @@ extern "C" { * need_des */ #define PMU_HP_MODEM_BIAS_REG (DR_REG_PMU_BASE + 0x4c) +/** PMU_HP_MODEM_DCDC_CCM_ENB : R/W; bitpos: [9]; default: 1; + * need_des + */ +#define PMU_HP_MODEM_DCDC_CCM_ENB (BIT(9)) +#define PMU_HP_MODEM_DCDC_CCM_ENB_M (PMU_HP_MODEM_DCDC_CCM_ENB_V << PMU_HP_MODEM_DCDC_CCM_ENB_S) +#define PMU_HP_MODEM_DCDC_CCM_ENB_V 0x00000001U +#define PMU_HP_MODEM_DCDC_CCM_ENB_S 9 +/** PMU_HP_MODEM_DCDC_CLEAR_RDY : R/W; bitpos: [10]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_DCDC_CLEAR_RDY (BIT(10)) +#define PMU_HP_MODEM_DCDC_CLEAR_RDY_M (PMU_HP_MODEM_DCDC_CLEAR_RDY_V << PMU_HP_MODEM_DCDC_CLEAR_RDY_S) +#define PMU_HP_MODEM_DCDC_CLEAR_RDY_V 0x00000001U +#define PMU_HP_MODEM_DCDC_CLEAR_RDY_S 10 +/** PMU_HP_MODEM_DIG_PMU_DPCUR_BIAS : R/W; bitpos: [12:11]; default: 1; + * need_des + */ +#define PMU_HP_MODEM_DIG_PMU_DPCUR_BIAS 0x00000003U +#define PMU_HP_MODEM_DIG_PMU_DPCUR_BIAS_M (PMU_HP_MODEM_DIG_PMU_DPCUR_BIAS_V << PMU_HP_MODEM_DIG_PMU_DPCUR_BIAS_S) +#define PMU_HP_MODEM_DIG_PMU_DPCUR_BIAS_V 0x00000003U +#define PMU_HP_MODEM_DIG_PMU_DPCUR_BIAS_S 11 +/** PMU_HP_MODEM_DIG_PMU_DSFMOS : R/W; bitpos: [16:13]; default: 4; + * need_des + */ +#define PMU_HP_MODEM_DIG_PMU_DSFMOS 0x0000000FU +#define PMU_HP_MODEM_DIG_PMU_DSFMOS_M (PMU_HP_MODEM_DIG_PMU_DSFMOS_V << PMU_HP_MODEM_DIG_PMU_DSFMOS_S) +#define PMU_HP_MODEM_DIG_PMU_DSFMOS_V 0x0000000FU +#define PMU_HP_MODEM_DIG_PMU_DSFMOS_S 13 +/** PMU_HP_MODEM_DCM_VSET : R/W; bitpos: [21:17]; default: 23; + * need_des + */ +#define PMU_HP_MODEM_DCM_VSET 0x0000001FU +#define PMU_HP_MODEM_DCM_VSET_M (PMU_HP_MODEM_DCM_VSET_V << PMU_HP_MODEM_DCM_VSET_S) +#define PMU_HP_MODEM_DCM_VSET_V 0x0000001FU +#define PMU_HP_MODEM_DCM_VSET_S 17 +/** PMU_HP_MODEM_DCM_MODE : R/W; bitpos: [23:22]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_DCM_MODE 0x00000003U +#define PMU_HP_MODEM_DCM_MODE_M (PMU_HP_MODEM_DCM_MODE_V << PMU_HP_MODEM_DCM_MODE_S) +#define PMU_HP_MODEM_DCM_MODE_V 0x00000003U +#define PMU_HP_MODEM_DCM_MODE_S 22 /** PMU_HP_MODEM_XPD_TRX : R/W; bitpos: [24]; default: 1; * need_des */ @@ -656,6 +747,13 @@ extern "C" { #define PMU_HP_MODEM_XPD_BIAS_M (PMU_HP_MODEM_XPD_BIAS_V << PMU_HP_MODEM_XPD_BIAS_S) #define PMU_HP_MODEM_XPD_BIAS_V 0x00000001U #define PMU_HP_MODEM_XPD_BIAS_S 25 +/** PMU_HP_MODEM_DISCNNT_DIG_RTC : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_MODEM_DISCNNT_DIG_RTC (BIT(29)) +#define PMU_HP_MODEM_DISCNNT_DIG_RTC_M (PMU_HP_MODEM_DISCNNT_DIG_RTC_V << PMU_HP_MODEM_DISCNNT_DIG_RTC_S) +#define PMU_HP_MODEM_DISCNNT_DIG_RTC_V 0x00000001U +#define PMU_HP_MODEM_DISCNNT_DIG_RTC_S 29 /** PMU_HP_MODEM_PD_CUR : R/W; bitpos: [30]; default: 0; * need_des */ @@ -682,20 +780,6 @@ extern "C" { #define PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE_M (PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE_V << PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE_S) #define PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE_V 0x00000003U #define PMU_HP_SLEEP2MODEM_BACKUP_MODEM_CLK_CODE_S 4 -/** PMU_HP_MODEM_RETENTION_MODE : R/W; bitpos: [10]; default: 0; - * need_des - */ -#define PMU_HP_MODEM_RETENTION_MODE (BIT(10)) -#define PMU_HP_MODEM_RETENTION_MODE_M (PMU_HP_MODEM_RETENTION_MODE_V << PMU_HP_MODEM_RETENTION_MODE_S) -#define PMU_HP_MODEM_RETENTION_MODE_V 0x00000001U -#define PMU_HP_MODEM_RETENTION_MODE_S 10 -/** PMU_HP_SLEEP2MODEM_RETENTION_EN : R/W; bitpos: [11]; default: 0; - * need_des - */ -#define PMU_HP_SLEEP2MODEM_RETENTION_EN (BIT(11)) -#define PMU_HP_SLEEP2MODEM_RETENTION_EN_M (PMU_HP_SLEEP2MODEM_RETENTION_EN_V << PMU_HP_SLEEP2MODEM_RETENTION_EN_S) -#define PMU_HP_SLEEP2MODEM_RETENTION_EN_V 0x00000001U -#define PMU_HP_SLEEP2MODEM_RETENTION_EN_S 11 /** PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL : R/W; bitpos: [15:14]; default: 0; * need_des */ @@ -703,12 +787,12 @@ extern "C" { #define PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL_M (PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL_V << PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL_S) #define PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL_V 0x00000003U #define PMU_HP_SLEEP2MODEM_BACKUP_CLK_SEL_S 14 -/** PMU_HP_SLEEP2MODEM_BACKUP_MODE : R/W; bitpos: [22:20]; default: 0; +/** PMU_HP_SLEEP2MODEM_BACKUP_MODE : R/W; bitpos: [24:20]; default: 0; * need_des */ -#define PMU_HP_SLEEP2MODEM_BACKUP_MODE 0x00000007U +#define PMU_HP_SLEEP2MODEM_BACKUP_MODE 0x0000001FU #define PMU_HP_SLEEP2MODEM_BACKUP_MODE_M (PMU_HP_SLEEP2MODEM_BACKUP_MODE_V << PMU_HP_SLEEP2MODEM_BACKUP_MODE_S) -#define PMU_HP_SLEEP2MODEM_BACKUP_MODE_V 0x00000007U +#define PMU_HP_SLEEP2MODEM_BACKUP_MODE_V 0x0000001FU #define PMU_HP_SLEEP2MODEM_BACKUP_MODE_S 20 /** PMU_HP_SLEEP2MODEM_BACKUP_EN : R/W; bitpos: [29]; default: 0; * need_des @@ -840,6 +924,13 @@ extern "C" { * need_des */ #define PMU_HP_MODEM_XTAL_REG (DR_REG_PMU_BASE + 0x64) +/** PMU_HP_MODEM_XPD_XTALX2 : R/W; bitpos: [30]; default: 1; + * need_des + */ +#define PMU_HP_MODEM_XPD_XTALX2 (BIT(30)) +#define PMU_HP_MODEM_XPD_XTALX2_M (PMU_HP_MODEM_XPD_XTALX2_V << PMU_HP_MODEM_XPD_XTALX2_S) +#define PMU_HP_MODEM_XPD_XTALX2_V 0x00000001U +#define PMU_HP_MODEM_XPD_XTALX2_S 30 /** PMU_HP_MODEM_XPD_XTAL : R/W; bitpos: [31]; default: 1; * need_des */ @@ -852,13 +943,13 @@ extern "C" { * need_des */ #define PMU_HP_SLEEP_DIG_POWER_REG (DR_REG_PMU_BASE + 0x68) -/** PMU_HP_SLEEP_VDD_SPI_PD_EN : R/W; bitpos: [21]; default: 0; +/** PMU_HP_SLEEP_VDD_FLASH_MODE : R/W; bitpos: [21:18]; default: 0; * need_des */ -#define PMU_HP_SLEEP_VDD_SPI_PD_EN (BIT(21)) -#define PMU_HP_SLEEP_VDD_SPI_PD_EN_M (PMU_HP_SLEEP_VDD_SPI_PD_EN_V << PMU_HP_SLEEP_VDD_SPI_PD_EN_S) -#define PMU_HP_SLEEP_VDD_SPI_PD_EN_V 0x00000001U -#define PMU_HP_SLEEP_VDD_SPI_PD_EN_S 21 +#define PMU_HP_SLEEP_VDD_FLASH_MODE 0x0000000FU +#define PMU_HP_SLEEP_VDD_FLASH_MODE_M (PMU_HP_SLEEP_VDD_FLASH_MODE_V << PMU_HP_SLEEP_VDD_FLASH_MODE_S) +#define PMU_HP_SLEEP_VDD_FLASH_MODE_V 0x0000000FU +#define PMU_HP_SLEEP_VDD_FLASH_MODE_S 18 /** PMU_HP_SLEEP_HP_MEM_DSLP : R/W; bitpos: [22]; default: 0; * need_des */ @@ -880,6 +971,13 @@ extern "C" { #define PMU_HP_SLEEP_PD_HP_WIFI_PD_EN_M (PMU_HP_SLEEP_PD_HP_WIFI_PD_EN_V << PMU_HP_SLEEP_PD_HP_WIFI_PD_EN_S) #define PMU_HP_SLEEP_PD_HP_WIFI_PD_EN_V 0x00000001U #define PMU_HP_SLEEP_PD_HP_WIFI_PD_EN_S 27 +/** PMU_HP_SLEEP_PD_HP_PERI_PD_EN : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_PD_HP_PERI_PD_EN (BIT(28)) +#define PMU_HP_SLEEP_PD_HP_PERI_PD_EN_M (PMU_HP_SLEEP_PD_HP_PERI_PD_EN_V << PMU_HP_SLEEP_PD_HP_PERI_PD_EN_S) +#define PMU_HP_SLEEP_PD_HP_PERI_PD_EN_V 0x00000001U +#define PMU_HP_SLEEP_PD_HP_PERI_PD_EN_S 28 /** PMU_HP_SLEEP_PD_HP_CPU_PD_EN : R/W; bitpos: [29]; default: 0; * need_des */ @@ -1029,6 +1127,48 @@ extern "C" { * need_des */ #define PMU_HP_SLEEP_BIAS_REG (DR_REG_PMU_BASE + 0x80) +/** PMU_HP_SLEEP_DCDC_CCM_ENB : R/W; bitpos: [9]; default: 1; + * need_des + */ +#define PMU_HP_SLEEP_DCDC_CCM_ENB (BIT(9)) +#define PMU_HP_SLEEP_DCDC_CCM_ENB_M (PMU_HP_SLEEP_DCDC_CCM_ENB_V << PMU_HP_SLEEP_DCDC_CCM_ENB_S) +#define PMU_HP_SLEEP_DCDC_CCM_ENB_V 0x00000001U +#define PMU_HP_SLEEP_DCDC_CCM_ENB_S 9 +/** PMU_HP_SLEEP_DCDC_CLEAR_RDY : R/W; bitpos: [10]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_DCDC_CLEAR_RDY (BIT(10)) +#define PMU_HP_SLEEP_DCDC_CLEAR_RDY_M (PMU_HP_SLEEP_DCDC_CLEAR_RDY_V << PMU_HP_SLEEP_DCDC_CLEAR_RDY_S) +#define PMU_HP_SLEEP_DCDC_CLEAR_RDY_V 0x00000001U +#define PMU_HP_SLEEP_DCDC_CLEAR_RDY_S 10 +/** PMU_HP_SLEEP_DIG_PMU_DPCUR_BIAS : R/W; bitpos: [12:11]; default: 1; + * need_des + */ +#define PMU_HP_SLEEP_DIG_PMU_DPCUR_BIAS 0x00000003U +#define PMU_HP_SLEEP_DIG_PMU_DPCUR_BIAS_M (PMU_HP_SLEEP_DIG_PMU_DPCUR_BIAS_V << PMU_HP_SLEEP_DIG_PMU_DPCUR_BIAS_S) +#define PMU_HP_SLEEP_DIG_PMU_DPCUR_BIAS_V 0x00000003U +#define PMU_HP_SLEEP_DIG_PMU_DPCUR_BIAS_S 11 +/** PMU_HP_SLEEP_DIG_PMU_DSFMOS : R/W; bitpos: [16:13]; default: 4; + * need_des + */ +#define PMU_HP_SLEEP_DIG_PMU_DSFMOS 0x0000000FU +#define PMU_HP_SLEEP_DIG_PMU_DSFMOS_M (PMU_HP_SLEEP_DIG_PMU_DSFMOS_V << PMU_HP_SLEEP_DIG_PMU_DSFMOS_S) +#define PMU_HP_SLEEP_DIG_PMU_DSFMOS_V 0x0000000FU +#define PMU_HP_SLEEP_DIG_PMU_DSFMOS_S 13 +/** PMU_HP_SLEEP_DCM_VSET : R/W; bitpos: [21:17]; default: 23; + * need_des + */ +#define PMU_HP_SLEEP_DCM_VSET 0x0000001FU +#define PMU_HP_SLEEP_DCM_VSET_M (PMU_HP_SLEEP_DCM_VSET_V << PMU_HP_SLEEP_DCM_VSET_S) +#define PMU_HP_SLEEP_DCM_VSET_V 0x0000001FU +#define PMU_HP_SLEEP_DCM_VSET_S 17 +/** PMU_HP_SLEEP_DCM_MODE : R/W; bitpos: [23:22]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_DCM_MODE 0x00000003U +#define PMU_HP_SLEEP_DCM_MODE_M (PMU_HP_SLEEP_DCM_MODE_V << PMU_HP_SLEEP_DCM_MODE_S) +#define PMU_HP_SLEEP_DCM_MODE_V 0x00000003U +#define PMU_HP_SLEEP_DCM_MODE_S 22 /** PMU_HP_SLEEP_XPD_TRX : R/W; bitpos: [24]; default: 1; * need_des */ @@ -1043,6 +1183,13 @@ extern "C" { #define PMU_HP_SLEEP_XPD_BIAS_M (PMU_HP_SLEEP_XPD_BIAS_V << PMU_HP_SLEEP_XPD_BIAS_S) #define PMU_HP_SLEEP_XPD_BIAS_V 0x00000001U #define PMU_HP_SLEEP_XPD_BIAS_S 25 +/** PMU_HP_SLEEP_DISCNNT_DIG_RTC : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_DISCNNT_DIG_RTC (BIT(29)) +#define PMU_HP_SLEEP_DISCNNT_DIG_RTC_M (PMU_HP_SLEEP_DISCNNT_DIG_RTC_V << PMU_HP_SLEEP_DISCNNT_DIG_RTC_S) +#define PMU_HP_SLEEP_DISCNNT_DIG_RTC_V 0x00000001U +#define PMU_HP_SLEEP_DISCNNT_DIG_RTC_S 29 /** PMU_HP_SLEEP_PD_CUR : R/W; bitpos: [30]; default: 0; * need_des */ @@ -1076,27 +1223,6 @@ extern "C" { #define PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE_M (PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE_V << PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE_S) #define PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE_V 0x00000003U #define PMU_HP_ACTIVE2SLEEP_BACKUP_MODEM_CLK_CODE_S 8 -/** PMU_HP_SLEEP_RETENTION_MODE : R/W; bitpos: [10]; default: 0; - * need_des - */ -#define PMU_HP_SLEEP_RETENTION_MODE (BIT(10)) -#define PMU_HP_SLEEP_RETENTION_MODE_M (PMU_HP_SLEEP_RETENTION_MODE_V << PMU_HP_SLEEP_RETENTION_MODE_S) -#define PMU_HP_SLEEP_RETENTION_MODE_V 0x00000001U -#define PMU_HP_SLEEP_RETENTION_MODE_S 10 -/** PMU_HP_MODEM2SLEEP_RETENTION_EN : R/W; bitpos: [12]; default: 0; - * need_des - */ -#define PMU_HP_MODEM2SLEEP_RETENTION_EN (BIT(12)) -#define PMU_HP_MODEM2SLEEP_RETENTION_EN_M (PMU_HP_MODEM2SLEEP_RETENTION_EN_V << PMU_HP_MODEM2SLEEP_RETENTION_EN_S) -#define PMU_HP_MODEM2SLEEP_RETENTION_EN_V 0x00000001U -#define PMU_HP_MODEM2SLEEP_RETENTION_EN_S 12 -/** PMU_HP_ACTIVE2SLEEP_RETENTION_EN : R/W; bitpos: [13]; default: 0; - * need_des - */ -#define PMU_HP_ACTIVE2SLEEP_RETENTION_EN (BIT(13)) -#define PMU_HP_ACTIVE2SLEEP_RETENTION_EN_M (PMU_HP_ACTIVE2SLEEP_RETENTION_EN_V << PMU_HP_ACTIVE2SLEEP_RETENTION_EN_S) -#define PMU_HP_ACTIVE2SLEEP_RETENTION_EN_V 0x00000001U -#define PMU_HP_ACTIVE2SLEEP_RETENTION_EN_S 13 /** PMU_HP_MODEM2SLEEP_BACKUP_CLK_SEL : R/W; bitpos: [17:16]; default: 0; * need_des */ @@ -1111,20 +1237,20 @@ extern "C" { #define PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL_M (PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL_V << PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL_S) #define PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL_V 0x00000003U #define PMU_HP_ACTIVE2SLEEP_BACKUP_CLK_SEL_S 18 -/** PMU_HP_MODEM2SLEEP_BACKUP_MODE : R/W; bitpos: [25:23]; default: 0; +/** PMU_HP_MODEM2SLEEP_BACKUP_MODE : R/W; bitpos: [24:20]; default: 0; * need_des */ -#define PMU_HP_MODEM2SLEEP_BACKUP_MODE 0x00000007U +#define PMU_HP_MODEM2SLEEP_BACKUP_MODE 0x0000001FU #define PMU_HP_MODEM2SLEEP_BACKUP_MODE_M (PMU_HP_MODEM2SLEEP_BACKUP_MODE_V << PMU_HP_MODEM2SLEEP_BACKUP_MODE_S) -#define PMU_HP_MODEM2SLEEP_BACKUP_MODE_V 0x00000007U -#define PMU_HP_MODEM2SLEEP_BACKUP_MODE_S 23 -/** PMU_HP_ACTIVE2SLEEP_BACKUP_MODE : R/W; bitpos: [28:26]; default: 0; +#define PMU_HP_MODEM2SLEEP_BACKUP_MODE_V 0x0000001FU +#define PMU_HP_MODEM2SLEEP_BACKUP_MODE_S 20 +/** PMU_HP_ACTIVE2SLEEP_BACKUP_MODE : R/W; bitpos: [29:25]; default: 0; * need_des */ -#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODE 0x00000007U +#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODE 0x0000001FU #define PMU_HP_ACTIVE2SLEEP_BACKUP_MODE_M (PMU_HP_ACTIVE2SLEEP_BACKUP_MODE_V << PMU_HP_ACTIVE2SLEEP_BACKUP_MODE_S) -#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODE_V 0x00000007U -#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODE_S 26 +#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODE_V 0x0000001FU +#define PMU_HP_ACTIVE2SLEEP_BACKUP_MODE_S 25 /** PMU_HP_MODEM2SLEEP_BACKUP_EN : R/W; bitpos: [30]; default: 0; * need_des */ @@ -1262,6 +1388,13 @@ extern "C" { * need_des */ #define PMU_HP_SLEEP_XTAL_REG (DR_REG_PMU_BASE + 0x98) +/** PMU_HP_SLEEP_XPD_XTALX2 : R/W; bitpos: [30]; default: 1; + * need_des + */ +#define PMU_HP_SLEEP_XPD_XTALX2 (BIT(30)) +#define PMU_HP_SLEEP_XPD_XTALX2_M (PMU_HP_SLEEP_XPD_XTALX2_V << PMU_HP_SLEEP_XPD_XTALX2_S) +#define PMU_HP_SLEEP_XPD_XTALX2_V 0x00000001U +#define PMU_HP_SLEEP_XPD_XTALX2_S 30 /** PMU_HP_SLEEP_XPD_XTAL : R/W; bitpos: [31]; default: 1; * need_des */ @@ -1295,7 +1428,7 @@ extern "C" { #define PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS_M (PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS_V << PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS_S) #define PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS_V 0x0000000FU #define PMU_HP_SLEEP_LP_REGULATOR_SLP_DBIAS_S 23 -/** PMU_HP_SLEEP_LP_REGULATOR_DBIAS : R/W; bitpos: [31:27]; default: 17; +/** PMU_HP_SLEEP_LP_REGULATOR_DBIAS : R/W; bitpos: [31:27]; default: 0; * need_des */ #define PMU_HP_SLEEP_LP_REGULATOR_DBIAS 0x0000001FU @@ -1331,6 +1464,13 @@ extern "C" { * need_des */ #define PMU_HP_SLEEP_LP_DIG_POWER_REG (DR_REG_PMU_BASE + 0xa8) +/** PMU_HP_SLEEP_VDD_IO_MODE : R/W; bitpos: [26:23]; default: 0; + * need_des + */ +#define PMU_HP_SLEEP_VDD_IO_MODE 0x0000000FU +#define PMU_HP_SLEEP_VDD_IO_MODE_M (PMU_HP_SLEEP_VDD_IO_MODE_V << PMU_HP_SLEEP_VDD_IO_MODE_S) +#define PMU_HP_SLEEP_VDD_IO_MODE_V 0x0000000FU +#define PMU_HP_SLEEP_VDD_IO_MODE_S 23 /** PMU_HP_SLEEP_BOD_SOURCE_SEL : R/W; bitpos: [27]; default: 0; * need_des */ @@ -1437,7 +1577,7 @@ extern "C" { #define PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS_M (PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS_V << PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS_S) #define PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS_V 0x0000000FU #define PMU_LP_SLEEP_LP_REGULATOR_SLP_DBIAS_S 23 -/** PMU_LP_SLEEP_LP_REGULATOR_DBIAS : R/W; bitpos: [31:27]; default: 17; +/** PMU_LP_SLEEP_LP_REGULATOR_DBIAS : R/W; bitpos: [31:27]; default: 0; * need_des */ #define PMU_LP_SLEEP_LP_REGULATOR_DBIAS 0x0000001FU @@ -1461,6 +1601,13 @@ extern "C" { * need_des */ #define PMU_LP_SLEEP_XTAL_REG (DR_REG_PMU_BASE + 0xbc) +/** PMU_LP_SLEEP_XPD_XTALX2 : R/W; bitpos: [30]; default: 1; + * need_des + */ +#define PMU_LP_SLEEP_XPD_XTALX2 (BIT(30)) +#define PMU_LP_SLEEP_XPD_XTALX2_M (PMU_LP_SLEEP_XPD_XTALX2_V << PMU_LP_SLEEP_XPD_XTALX2_S) +#define PMU_LP_SLEEP_XPD_XTALX2_V 0x00000001U +#define PMU_LP_SLEEP_XPD_XTALX2_S 30 /** PMU_LP_SLEEP_XPD_XTAL : R/W; bitpos: [31]; default: 1; * need_des */ @@ -1473,6 +1620,13 @@ extern "C" { * need_des */ #define PMU_LP_SLEEP_LP_DIG_POWER_REG (DR_REG_PMU_BASE + 0xc0) +/** PMU_LP_SLEEP_VDD_IO_MODE : R/W; bitpos: [26:23]; default: 0; + * need_des + */ +#define PMU_LP_SLEEP_VDD_IO_MODE 0x0000000FU +#define PMU_LP_SLEEP_VDD_IO_MODE_M (PMU_LP_SLEEP_VDD_IO_MODE_V << PMU_LP_SLEEP_VDD_IO_MODE_S) +#define PMU_LP_SLEEP_VDD_IO_MODE_V 0x0000000FU +#define PMU_LP_SLEEP_VDD_IO_MODE_S 23 /** PMU_LP_SLEEP_BOD_SOURCE_SEL : R/W; bitpos: [27]; default: 0; * need_des */ @@ -1546,6 +1700,48 @@ extern "C" { * need_des */ #define PMU_LP_SLEEP_BIAS_REG (DR_REG_PMU_BASE + 0xc8) +/** PMU_LP_SLEEP_DCDC_CCM_ENB : R/W; bitpos: [9]; default: 1; + * need_des + */ +#define PMU_LP_SLEEP_DCDC_CCM_ENB (BIT(9)) +#define PMU_LP_SLEEP_DCDC_CCM_ENB_M (PMU_LP_SLEEP_DCDC_CCM_ENB_V << PMU_LP_SLEEP_DCDC_CCM_ENB_S) +#define PMU_LP_SLEEP_DCDC_CCM_ENB_V 0x00000001U +#define PMU_LP_SLEEP_DCDC_CCM_ENB_S 9 +/** PMU_LP_SLEEP_DCDC_CLEAR_RDY : R/W; bitpos: [10]; default: 0; + * need_des + */ +#define PMU_LP_SLEEP_DCDC_CLEAR_RDY (BIT(10)) +#define PMU_LP_SLEEP_DCDC_CLEAR_RDY_M (PMU_LP_SLEEP_DCDC_CLEAR_RDY_V << PMU_LP_SLEEP_DCDC_CLEAR_RDY_S) +#define PMU_LP_SLEEP_DCDC_CLEAR_RDY_V 0x00000001U +#define PMU_LP_SLEEP_DCDC_CLEAR_RDY_S 10 +/** PMU_LP_SLEEP_DIG_PMU_DPCUR_BIAS : R/W; bitpos: [12:11]; default: 1; + * need_des + */ +#define PMU_LP_SLEEP_DIG_PMU_DPCUR_BIAS 0x00000003U +#define PMU_LP_SLEEP_DIG_PMU_DPCUR_BIAS_M (PMU_LP_SLEEP_DIG_PMU_DPCUR_BIAS_V << PMU_LP_SLEEP_DIG_PMU_DPCUR_BIAS_S) +#define PMU_LP_SLEEP_DIG_PMU_DPCUR_BIAS_V 0x00000003U +#define PMU_LP_SLEEP_DIG_PMU_DPCUR_BIAS_S 11 +/** PMU_LP_SLEEP_DIG_PMU_DSFMOS : R/W; bitpos: [16:13]; default: 4; + * need_des + */ +#define PMU_LP_SLEEP_DIG_PMU_DSFMOS 0x0000000FU +#define PMU_LP_SLEEP_DIG_PMU_DSFMOS_M (PMU_LP_SLEEP_DIG_PMU_DSFMOS_V << PMU_LP_SLEEP_DIG_PMU_DSFMOS_S) +#define PMU_LP_SLEEP_DIG_PMU_DSFMOS_V 0x0000000FU +#define PMU_LP_SLEEP_DIG_PMU_DSFMOS_S 13 +/** PMU_LP_SLEEP_DCM_VSET : R/W; bitpos: [21:17]; default: 23; + * need_des + */ +#define PMU_LP_SLEEP_DCM_VSET 0x0000001FU +#define PMU_LP_SLEEP_DCM_VSET_M (PMU_LP_SLEEP_DCM_VSET_V << PMU_LP_SLEEP_DCM_VSET_S) +#define PMU_LP_SLEEP_DCM_VSET_V 0x0000001FU +#define PMU_LP_SLEEP_DCM_VSET_S 17 +/** PMU_LP_SLEEP_DCM_MODE : R/W; bitpos: [23:22]; default: 0; + * need_des + */ +#define PMU_LP_SLEEP_DCM_MODE 0x00000003U +#define PMU_LP_SLEEP_DCM_MODE_M (PMU_LP_SLEEP_DCM_MODE_V << PMU_LP_SLEEP_DCM_MODE_S) +#define PMU_LP_SLEEP_DCM_MODE_V 0x00000003U +#define PMU_LP_SLEEP_DCM_MODE_S 22 /** PMU_LP_SLEEP_XPD_BIAS : R/W; bitpos: [25]; default: 0; * need_des */ @@ -1553,6 +1749,13 @@ extern "C" { #define PMU_LP_SLEEP_XPD_BIAS_M (PMU_LP_SLEEP_XPD_BIAS_V << PMU_LP_SLEEP_XPD_BIAS_S) #define PMU_LP_SLEEP_XPD_BIAS_V 0x00000001U #define PMU_LP_SLEEP_XPD_BIAS_S 25 +/** PMU_LP_SLEEP_DISCNNT_DIG_RTC : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_LP_SLEEP_DISCNNT_DIG_RTC (BIT(29)) +#define PMU_LP_SLEEP_DISCNNT_DIG_RTC_M (PMU_LP_SLEEP_DISCNNT_DIG_RTC_V << PMU_LP_SLEEP_DISCNNT_DIG_RTC_S) +#define PMU_LP_SLEEP_DISCNNT_DIG_RTC_V 0x00000001U +#define PMU_LP_SLEEP_DISCNNT_DIG_RTC_S 29 /** PMU_LP_SLEEP_PD_CUR : R/W; bitpos: [30]; default: 0; * need_des */ @@ -1621,6 +1824,34 @@ extern "C" { #define PMU_TIE_LOW_XPD_XTAL_M (PMU_TIE_LOW_XPD_XTAL_V << PMU_TIE_LOW_XPD_XTAL_S) #define PMU_TIE_LOW_XPD_XTAL_V 0x00000001U #define PMU_TIE_LOW_XPD_XTAL_S 6 +/** PMU_TIE_LOW_GLOBAL_XTALX2_ICG : WT; bitpos: [7]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_GLOBAL_XTALX2_ICG (BIT(7)) +#define PMU_TIE_LOW_GLOBAL_XTALX2_ICG_M (PMU_TIE_LOW_GLOBAL_XTALX2_ICG_V << PMU_TIE_LOW_GLOBAL_XTALX2_ICG_S) +#define PMU_TIE_LOW_GLOBAL_XTALX2_ICG_V 0x00000001U +#define PMU_TIE_LOW_GLOBAL_XTALX2_ICG_S 7 +/** PMU_TIE_LOW_XPD_XTALX2 : WT; bitpos: [8]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_XPD_XTALX2 (BIT(8)) +#define PMU_TIE_LOW_XPD_XTALX2_M (PMU_TIE_LOW_XPD_XTALX2_V << PMU_TIE_LOW_XPD_XTALX2_S) +#define PMU_TIE_LOW_XPD_XTALX2_V 0x00000001U +#define PMU_TIE_LOW_XPD_XTALX2_S 8 +/** PMU_TIE_HIGH_XTALX2 : WT; bitpos: [23]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_XTALX2 (BIT(23)) +#define PMU_TIE_HIGH_XTALX2_M (PMU_TIE_HIGH_XTALX2_V << PMU_TIE_HIGH_XTALX2_S) +#define PMU_TIE_HIGH_XTALX2_V 0x00000001U +#define PMU_TIE_HIGH_XTALX2_S 23 +/** PMU_TIE_HIGH_GLOBAL_XTALX2_ICG : WT; bitpos: [24]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_GLOBAL_XTALX2_ICG (BIT(24)) +#define PMU_TIE_HIGH_GLOBAL_XTALX2_ICG_M (PMU_TIE_HIGH_GLOBAL_XTALX2_ICG_V << PMU_TIE_HIGH_GLOBAL_XTALX2_ICG_S) +#define PMU_TIE_HIGH_GLOBAL_XTALX2_ICG_V 0x00000001U +#define PMU_TIE_HIGH_GLOBAL_XTALX2_ICG_S 24 /** PMU_TIE_HIGH_GLOBAL_BBPLL_ICG : WT; bitpos: [25]; default: 0; * need_des */ @@ -1763,6 +1994,20 @@ extern "C" { * need_des */ #define PMU_IMM_PAD_HOLD_ALL_REG (DR_REG_PMU_BASE + 0xe4) +/** PMU_TIE_HIGH_DIG_PAD_SLP_SEL : WT; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_TIE_HIGH_DIG_PAD_SLP_SEL (BIT(26)) +#define PMU_TIE_HIGH_DIG_PAD_SLP_SEL_M (PMU_TIE_HIGH_DIG_PAD_SLP_SEL_V << PMU_TIE_HIGH_DIG_PAD_SLP_SEL_S) +#define PMU_TIE_HIGH_DIG_PAD_SLP_SEL_V 0x00000001U +#define PMU_TIE_HIGH_DIG_PAD_SLP_SEL_S 26 +/** PMU_TIE_LOW_DIG_PAD_SLP_SEL : WT; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_TIE_LOW_DIG_PAD_SLP_SEL (BIT(27)) +#define PMU_TIE_LOW_DIG_PAD_SLP_SEL_M (PMU_TIE_LOW_DIG_PAD_SLP_SEL_V << PMU_TIE_LOW_DIG_PAD_SLP_SEL_S) +#define PMU_TIE_LOW_DIG_PAD_SLP_SEL_V 0x00000001U +#define PMU_TIE_LOW_DIG_PAD_SLP_SEL_S 27 /** PMU_TIE_HIGH_LP_PAD_HOLD_ALL : WT; bitpos: [28]; default: 0; * need_des */ @@ -1829,44 +2074,77 @@ extern "C" { #define PMU_DG_HP_POWERUP_TIMER_M (PMU_DG_HP_POWERUP_TIMER_V << PMU_DG_HP_POWERUP_TIMER_S) #define PMU_DG_HP_POWERUP_TIMER_V 0x000001FFU #define PMU_DG_HP_POWERUP_TIMER_S 14 -/** PMU_DG_HP_WAIT_TIMER : R/W; bitpos: [31:23]; default: 255; +/** PMU_DG_HP_PD_WAIT_TIMER : R/W; bitpos: [31:23]; default: 255; * need_des */ -#define PMU_DG_HP_WAIT_TIMER 0x000001FFU -#define PMU_DG_HP_WAIT_TIMER_M (PMU_DG_HP_WAIT_TIMER_V << PMU_DG_HP_WAIT_TIMER_S) -#define PMU_DG_HP_WAIT_TIMER_V 0x000001FFU -#define PMU_DG_HP_WAIT_TIMER_S 23 +#define PMU_DG_HP_PD_WAIT_TIMER 0x000001FFU +#define PMU_DG_HP_PD_WAIT_TIMER_M (PMU_DG_HP_PD_WAIT_TIMER_V << PMU_DG_HP_PD_WAIT_TIMER_S) +#define PMU_DG_HP_PD_WAIT_TIMER_V 0x000001FFU +#define PMU_DG_HP_PD_WAIT_TIMER_S 23 /** PMU_POWER_WAIT_TIMER1_REG register * need_des */ #define PMU_POWER_WAIT_TIMER1_REG (DR_REG_PMU_BASE + 0xf0) -/** PMU_DG_LP_POWERDOWN_TIMER : R/W; bitpos: [15:9]; default: 255; +/** PMU_DG_LP_POWERDOWN_TIMER : R/W; bitpos: [15:9]; default: 63; * need_des */ #define PMU_DG_LP_POWERDOWN_TIMER 0x0000007FU #define PMU_DG_LP_POWERDOWN_TIMER_M (PMU_DG_LP_POWERDOWN_TIMER_V << PMU_DG_LP_POWERDOWN_TIMER_S) #define PMU_DG_LP_POWERDOWN_TIMER_V 0x0000007FU #define PMU_DG_LP_POWERDOWN_TIMER_S 9 -/** PMU_DG_LP_POWERUP_TIMER : R/W; bitpos: [22:16]; default: 255; +/** PMU_DG_LP_POWERUP_TIMER : R/W; bitpos: [22:16]; default: 63; * need_des */ #define PMU_DG_LP_POWERUP_TIMER 0x0000007FU #define PMU_DG_LP_POWERUP_TIMER_M (PMU_DG_LP_POWERUP_TIMER_V << PMU_DG_LP_POWERUP_TIMER_S) #define PMU_DG_LP_POWERUP_TIMER_V 0x0000007FU #define PMU_DG_LP_POWERUP_TIMER_S 16 -/** PMU_DG_LP_WAIT_TIMER : R/W; bitpos: [31:23]; default: 255; +/** PMU_DG_LP_PD_WAIT_TIMER : R/W; bitpos: [31:23]; default: 255; * need_des */ -#define PMU_DG_LP_WAIT_TIMER 0x000001FFU -#define PMU_DG_LP_WAIT_TIMER_M (PMU_DG_LP_WAIT_TIMER_V << PMU_DG_LP_WAIT_TIMER_S) -#define PMU_DG_LP_WAIT_TIMER_V 0x000001FFU -#define PMU_DG_LP_WAIT_TIMER_S 23 +#define PMU_DG_LP_PD_WAIT_TIMER 0x000001FFU +#define PMU_DG_LP_PD_WAIT_TIMER_M (PMU_DG_LP_PD_WAIT_TIMER_V << PMU_DG_LP_PD_WAIT_TIMER_S) +#define PMU_DG_LP_PD_WAIT_TIMER_V 0x000001FFU +#define PMU_DG_LP_PD_WAIT_TIMER_S 23 + +/** PMU_POWER_WAIT_TIMER2_REG register + * need_des + */ +#define PMU_POWER_WAIT_TIMER2_REG (DR_REG_PMU_BASE + 0xf4) +/** PMU_DG_LP_ISO_WAIT_TIMER : R/W; bitpos: [7:0]; default: 255; + * need_des + */ +#define PMU_DG_LP_ISO_WAIT_TIMER 0x000000FFU +#define PMU_DG_LP_ISO_WAIT_TIMER_M (PMU_DG_LP_ISO_WAIT_TIMER_V << PMU_DG_LP_ISO_WAIT_TIMER_S) +#define PMU_DG_LP_ISO_WAIT_TIMER_V 0x000000FFU +#define PMU_DG_LP_ISO_WAIT_TIMER_S 0 +/** PMU_DG_LP_RST_WAIT_TIMER : R/W; bitpos: [15:8]; default: 255; + * need_des + */ +#define PMU_DG_LP_RST_WAIT_TIMER 0x000000FFU +#define PMU_DG_LP_RST_WAIT_TIMER_M (PMU_DG_LP_RST_WAIT_TIMER_V << PMU_DG_LP_RST_WAIT_TIMER_S) +#define PMU_DG_LP_RST_WAIT_TIMER_V 0x000000FFU +#define PMU_DG_LP_RST_WAIT_TIMER_S 8 +/** PMU_DG_HP_ISO_WAIT_TIMER : R/W; bitpos: [23:16]; default: 255; + * need_des + */ +#define PMU_DG_HP_ISO_WAIT_TIMER 0x000000FFU +#define PMU_DG_HP_ISO_WAIT_TIMER_M (PMU_DG_HP_ISO_WAIT_TIMER_V << PMU_DG_HP_ISO_WAIT_TIMER_S) +#define PMU_DG_HP_ISO_WAIT_TIMER_V 0x000000FFU +#define PMU_DG_HP_ISO_WAIT_TIMER_S 16 +/** PMU_DG_HP_RST_WAIT_TIMER : R/W; bitpos: [31:24]; default: 255; + * need_des + */ +#define PMU_DG_HP_RST_WAIT_TIMER 0x000000FFU +#define PMU_DG_HP_RST_WAIT_TIMER_M (PMU_DG_HP_RST_WAIT_TIMER_V << PMU_DG_HP_RST_WAIT_TIMER_S) +#define PMU_DG_HP_RST_WAIT_TIMER_V 0x000000FFU +#define PMU_DG_HP_RST_WAIT_TIMER_S 24 /** PMU_POWER_PD_TOP_CNTL_REG register * need_des */ -#define PMU_POWER_PD_TOP_CNTL_REG (DR_REG_PMU_BASE + 0xf4) +#define PMU_POWER_PD_TOP_CNTL_REG (DR_REG_PMU_BASE + 0xf8) /** PMU_FORCE_TOP_RESET : R/W; bitpos: [0]; default: 0; * need_des */ @@ -1927,7 +2205,7 @@ extern "C" { /** PMU_POWER_PD_HPAON_CNTL_REG register * need_des */ -#define PMU_POWER_PD_HPAON_CNTL_REG (DR_REG_PMU_BASE + 0xf8) +#define PMU_POWER_PD_HPAON_CNTL_REG (DR_REG_PMU_BASE + 0xfc) /** PMU_FORCE_HP_AON_RESET : R/W; bitpos: [0]; default: 0; * need_des */ @@ -1988,7 +2266,7 @@ extern "C" { /** PMU_POWER_PD_HPCPU_CNTL_REG register * need_des */ -#define PMU_POWER_PD_HPCPU_CNTL_REG (DR_REG_PMU_BASE + 0xfc) +#define PMU_POWER_PD_HPCPU_CNTL_REG (DR_REG_PMU_BASE + 0x100) /** PMU_FORCE_HP_CPU_RESET : R/W; bitpos: [0]; default: 0; * need_des */ @@ -2049,19 +2327,68 @@ extern "C" { /** PMU_POWER_PD_HPPERI_RESERVE_REG register * need_des */ -#define PMU_POWER_PD_HPPERI_RESERVE_REG (DR_REG_PMU_BASE + 0x100) -/** PMU_HP_PERI_RESERVE : WT; bitpos: [31:0]; default: 0; +#define PMU_POWER_PD_HPPERI_RESERVE_REG (DR_REG_PMU_BASE + 0x104) +/** PMU_FORCE_HP_PERI_RESET : R/W; bitpos: [0]; default: 0; * need_des */ -#define PMU_HP_PERI_RESERVE 0xFFFFFFFFU -#define PMU_HP_PERI_RESERVE_M (PMU_HP_PERI_RESERVE_V << PMU_HP_PERI_RESERVE_S) -#define PMU_HP_PERI_RESERVE_V 0xFFFFFFFFU -#define PMU_HP_PERI_RESERVE_S 0 +#define PMU_FORCE_HP_PERI_RESET (BIT(0)) +#define PMU_FORCE_HP_PERI_RESET_M (PMU_FORCE_HP_PERI_RESET_V << PMU_FORCE_HP_PERI_RESET_S) +#define PMU_FORCE_HP_PERI_RESET_V 0x00000001U +#define PMU_FORCE_HP_PERI_RESET_S 0 +/** PMU_FORCE_HP_PERI_ISO : R/W; bitpos: [1]; default: 0; + * need_des + */ +#define PMU_FORCE_HP_PERI_ISO (BIT(1)) +#define PMU_FORCE_HP_PERI_ISO_M (PMU_FORCE_HP_PERI_ISO_V << PMU_FORCE_HP_PERI_ISO_S) +#define PMU_FORCE_HP_PERI_ISO_V 0x00000001U +#define PMU_FORCE_HP_PERI_ISO_S 1 +/** PMU_FORCE_HP_PERI_PU : R/W; bitpos: [2]; default: 1; + * need_des + */ +#define PMU_FORCE_HP_PERI_PU (BIT(2)) +#define PMU_FORCE_HP_PERI_PU_M (PMU_FORCE_HP_PERI_PU_V << PMU_FORCE_HP_PERI_PU_S) +#define PMU_FORCE_HP_PERI_PU_V 0x00000001U +#define PMU_FORCE_HP_PERI_PU_S 2 +/** PMU_FORCE_HP_PERI_NO_RESET : R/W; bitpos: [3]; default: 1; + * need_des + */ +#define PMU_FORCE_HP_PERI_NO_RESET (BIT(3)) +#define PMU_FORCE_HP_PERI_NO_RESET_M (PMU_FORCE_HP_PERI_NO_RESET_V << PMU_FORCE_HP_PERI_NO_RESET_S) +#define PMU_FORCE_HP_PERI_NO_RESET_V 0x00000001U +#define PMU_FORCE_HP_PERI_NO_RESET_S 3 +/** PMU_FORCE_HP_PERI_NO_ISO : R/W; bitpos: [4]; default: 1; + * need_des + */ +#define PMU_FORCE_HP_PERI_NO_ISO (BIT(4)) +#define PMU_FORCE_HP_PERI_NO_ISO_M (PMU_FORCE_HP_PERI_NO_ISO_V << PMU_FORCE_HP_PERI_NO_ISO_S) +#define PMU_FORCE_HP_PERI_NO_ISO_V 0x00000001U +#define PMU_FORCE_HP_PERI_NO_ISO_S 4 +/** PMU_FORCE_HP_PERI_PD : R/W; bitpos: [5]; default: 0; + * need_des + */ +#define PMU_FORCE_HP_PERI_PD (BIT(5)) +#define PMU_FORCE_HP_PERI_PD_M (PMU_FORCE_HP_PERI_PD_V << PMU_FORCE_HP_PERI_PD_S) +#define PMU_FORCE_HP_PERI_PD_V 0x00000001U +#define PMU_FORCE_HP_PERI_PD_S 5 +/** PMU_PD_HP_PERI_MASK : R/W; bitpos: [10:6]; default: 0; + * need_des + */ +#define PMU_PD_HP_PERI_MASK 0x0000001FU +#define PMU_PD_HP_PERI_MASK_M (PMU_PD_HP_PERI_MASK_V << PMU_PD_HP_PERI_MASK_S) +#define PMU_PD_HP_PERI_MASK_V 0x0000001FU +#define PMU_PD_HP_PERI_MASK_S 6 +/** PMU_PD_HP_PERI_PD_MASK : R/W; bitpos: [31:27]; default: 0; + * need_des + */ +#define PMU_PD_HP_PERI_PD_MASK 0x0000001FU +#define PMU_PD_HP_PERI_PD_MASK_M (PMU_PD_HP_PERI_PD_MASK_V << PMU_PD_HP_PERI_PD_MASK_S) +#define PMU_PD_HP_PERI_PD_MASK_V 0x0000001FU +#define PMU_PD_HP_PERI_PD_MASK_S 27 /** PMU_POWER_PD_HPWIFI_CNTL_REG register * need_des */ -#define PMU_POWER_PD_HPWIFI_CNTL_REG (DR_REG_PMU_BASE + 0x104) +#define PMU_POWER_PD_HPWIFI_CNTL_REG (DR_REG_PMU_BASE + 0x108) /** PMU_FORCE_HP_WIFI_RESET : R/W; bitpos: [0]; default: 0; * need_des */ @@ -2122,7 +2449,7 @@ extern "C" { /** PMU_POWER_PD_LPPERI_CNTL_REG register * need_des */ -#define PMU_POWER_PD_LPPERI_CNTL_REG (DR_REG_PMU_BASE + 0x108) +#define PMU_POWER_PD_LPPERI_CNTL_REG (DR_REG_PMU_BASE + 0x10c) /** PMU_FORCE_LP_PERI_RESET : R/W; bitpos: [0]; default: 0; * need_des */ @@ -2169,7 +2496,7 @@ extern "C" { /** PMU_POWER_PD_MEM_CNTL_REG register * need_des */ -#define PMU_POWER_PD_MEM_CNTL_REG (DR_REG_PMU_BASE + 0x10c) +#define PMU_POWER_PD_MEM_CNTL_REG (DR_REG_PMU_BASE + 0x110) /** PMU_FORCE_HP_MEM_ISO : R/W; bitpos: [3:0]; default: 0; * need_des */ @@ -2202,7 +2529,7 @@ extern "C" { /** PMU_POWER_PD_MEM_MASK_REG register * need_des */ -#define PMU_POWER_PD_MEM_MASK_REG (DR_REG_PMU_BASE + 0x110) +#define PMU_POWER_PD_MEM_MASK_REG (DR_REG_PMU_BASE + 0x114) /** PMU_PD_HP_MEM2_PD_MASK : R/W; bitpos: [4:0]; default: 0; * need_des */ @@ -2249,7 +2576,7 @@ extern "C" { /** PMU_POWER_HP_PAD_REG register * need_des */ -#define PMU_POWER_HP_PAD_REG (DR_REG_PMU_BASE + 0x114) +#define PMU_POWER_HP_PAD_REG (DR_REG_PMU_BASE + 0x118) /** PMU_FORCE_HP_PAD_NO_ISO_ALL : R/W; bitpos: [0]; default: 0; * need_des */ @@ -2265,36 +2592,350 @@ extern "C" { #define PMU_FORCE_HP_PAD_ISO_ALL_V 0x00000001U #define PMU_FORCE_HP_PAD_ISO_ALL_S 1 -/** PMU_POWER_VDD_SPI_CNTL_REG register +/** PMU_POWER_FLASH1P8_LDO_REG register * need_des */ -#define PMU_POWER_VDD_SPI_CNTL_REG (DR_REG_PMU_BASE + 0x118) -/** PMU_VDD_SPI_PWR_WAIT : R/W; bitpos: [28:18]; default: 255; +#define PMU_POWER_FLASH1P8_LDO_REG (DR_REG_PMU_BASE + 0x11c) +/** PMU_FLASH1P8_LDO_RDY : RO; bitpos: [0]; default: 1; * need_des */ -#define PMU_VDD_SPI_PWR_WAIT 0x000007FFU -#define PMU_VDD_SPI_PWR_WAIT_M (PMU_VDD_SPI_PWR_WAIT_V << PMU_VDD_SPI_PWR_WAIT_S) -#define PMU_VDD_SPI_PWR_WAIT_V 0x000007FFU -#define PMU_VDD_SPI_PWR_WAIT_S 18 -/** PMU_VDD_SPI_PWR_SW : R/W; bitpos: [30:29]; default: 3; +#define PMU_FLASH1P8_LDO_RDY (BIT(0)) +#define PMU_FLASH1P8_LDO_RDY_M (PMU_FLASH1P8_LDO_RDY_V << PMU_FLASH1P8_LDO_RDY_S) +#define PMU_FLASH1P8_LDO_RDY_V 0x00000001U +#define PMU_FLASH1P8_LDO_RDY_S 0 +/** PMU_FLASH1P8_SW_EN_XPD : R/W; bitpos: [1]; default: 0; * need_des */ -#define PMU_VDD_SPI_PWR_SW 0x00000003U -#define PMU_VDD_SPI_PWR_SW_M (PMU_VDD_SPI_PWR_SW_V << PMU_VDD_SPI_PWR_SW_S) -#define PMU_VDD_SPI_PWR_SW_V 0x00000003U -#define PMU_VDD_SPI_PWR_SW_S 29 -/** PMU_VDD_SPI_PWR_SEL_SW : R/W; bitpos: [31]; default: 0; +#define PMU_FLASH1P8_SW_EN_XPD (BIT(1)) +#define PMU_FLASH1P8_SW_EN_XPD_M (PMU_FLASH1P8_SW_EN_XPD_V << PMU_FLASH1P8_SW_EN_XPD_S) +#define PMU_FLASH1P8_SW_EN_XPD_V 0x00000001U +#define PMU_FLASH1P8_SW_EN_XPD_S 1 +/** PMU_FLASH1P8_SW_EN_THRU : R/W; bitpos: [2]; default: 0; * need_des */ -#define PMU_VDD_SPI_PWR_SEL_SW (BIT(31)) -#define PMU_VDD_SPI_PWR_SEL_SW_M (PMU_VDD_SPI_PWR_SEL_SW_V << PMU_VDD_SPI_PWR_SEL_SW_S) -#define PMU_VDD_SPI_PWR_SEL_SW_V 0x00000001U -#define PMU_VDD_SPI_PWR_SEL_SW_S 31 +#define PMU_FLASH1P8_SW_EN_THRU (BIT(2)) +#define PMU_FLASH1P8_SW_EN_THRU_M (PMU_FLASH1P8_SW_EN_THRU_V << PMU_FLASH1P8_SW_EN_THRU_S) +#define PMU_FLASH1P8_SW_EN_THRU_V 0x00000001U +#define PMU_FLASH1P8_SW_EN_THRU_S 2 +/** PMU_FLASH1P8_SW_EN_STANDBY : R/W; bitpos: [3]; default: 0; + * need_des + */ +#define PMU_FLASH1P8_SW_EN_STANDBY (BIT(3)) +#define PMU_FLASH1P8_SW_EN_STANDBY_M (PMU_FLASH1P8_SW_EN_STANDBY_V << PMU_FLASH1P8_SW_EN_STANDBY_S) +#define PMU_FLASH1P8_SW_EN_STANDBY_V 0x00000001U +#define PMU_FLASH1P8_SW_EN_STANDBY_S 3 +/** PMU_FLASH1P8_SW_EN_POWER_ADJUST : R/W; bitpos: [4]; default: 0; + * need_des + */ +#define PMU_FLASH1P8_SW_EN_POWER_ADJUST (BIT(4)) +#define PMU_FLASH1P8_SW_EN_POWER_ADJUST_M (PMU_FLASH1P8_SW_EN_POWER_ADJUST_V << PMU_FLASH1P8_SW_EN_POWER_ADJUST_S) +#define PMU_FLASH1P8_SW_EN_POWER_ADJUST_V 0x00000001U +#define PMU_FLASH1P8_SW_EN_POWER_ADJUST_S 4 +/** PMU_FLASH1P8_SW_EN_ENDET : R/W; bitpos: [5]; default: 0; + * need_des + */ +#define PMU_FLASH1P8_SW_EN_ENDET (BIT(5)) +#define PMU_FLASH1P8_SW_EN_ENDET_M (PMU_FLASH1P8_SW_EN_ENDET_V << PMU_FLASH1P8_SW_EN_ENDET_S) +#define PMU_FLASH1P8_SW_EN_ENDET_V 0x00000001U +#define PMU_FLASH1P8_SW_EN_ENDET_S 5 +/** PMU_FLASH1P8_BYPASS_LDO_RDY : R/W; bitpos: [22]; default: 0; + * need_des + */ +#define PMU_FLASH1P8_BYPASS_LDO_RDY (BIT(22)) +#define PMU_FLASH1P8_BYPASS_LDO_RDY_M (PMU_FLASH1P8_BYPASS_LDO_RDY_V << PMU_FLASH1P8_BYPASS_LDO_RDY_S) +#define PMU_FLASH1P8_BYPASS_LDO_RDY_V 0x00000001U +#define PMU_FLASH1P8_BYPASS_LDO_RDY_S 22 +/** PMU_FLASH1P8_XPD : R/W; bitpos: [23]; default: 0; + * need_des + */ +#define PMU_FLASH1P8_XPD (BIT(23)) +#define PMU_FLASH1P8_XPD_M (PMU_FLASH1P8_XPD_V << PMU_FLASH1P8_XPD_S) +#define PMU_FLASH1P8_XPD_V 0x00000001U +#define PMU_FLASH1P8_XPD_S 23 +/** PMU_FLASH1P8_THRU : R/W; bitpos: [24]; default: 1; + * need_des + */ +#define PMU_FLASH1P8_THRU (BIT(24)) +#define PMU_FLASH1P8_THRU_M (PMU_FLASH1P8_THRU_V << PMU_FLASH1P8_THRU_S) +#define PMU_FLASH1P8_THRU_V 0x00000001U +#define PMU_FLASH1P8_THRU_S 24 +/** PMU_FLASH1P8_STANDBY : R/W; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_FLASH1P8_STANDBY (BIT(25)) +#define PMU_FLASH1P8_STANDBY_M (PMU_FLASH1P8_STANDBY_V << PMU_FLASH1P8_STANDBY_S) +#define PMU_FLASH1P8_STANDBY_V 0x00000001U +#define PMU_FLASH1P8_STANDBY_S 25 +/** PMU_FLASH1P8_POWER_ADJUST : R/W; bitpos: [30:26]; default: 0; + * need_des + */ +#define PMU_FLASH1P8_POWER_ADJUST 0x0000001FU +#define PMU_FLASH1P8_POWER_ADJUST_M (PMU_FLASH1P8_POWER_ADJUST_V << PMU_FLASH1P8_POWER_ADJUST_S) +#define PMU_FLASH1P8_POWER_ADJUST_V 0x0000001FU +#define PMU_FLASH1P8_POWER_ADJUST_S 26 +/** PMU_FLASH1P8_ENDET : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_FLASH1P8_ENDET (BIT(31)) +#define PMU_FLASH1P8_ENDET_M (PMU_FLASH1P8_ENDET_V << PMU_FLASH1P8_ENDET_S) +#define PMU_FLASH1P8_ENDET_V 0x00000001U +#define PMU_FLASH1P8_ENDET_S 31 + +/** PMU_POWER_FLASH1P2_LDO_REG register + * need_des + */ +#define PMU_POWER_FLASH1P2_LDO_REG (DR_REG_PMU_BASE + 0x120) +/** PMU_FLASH1P2_LDO_RDY : RO; bitpos: [0]; default: 1; + * need_des + */ +#define PMU_FLASH1P2_LDO_RDY (BIT(0)) +#define PMU_FLASH1P2_LDO_RDY_M (PMU_FLASH1P2_LDO_RDY_V << PMU_FLASH1P2_LDO_RDY_S) +#define PMU_FLASH1P2_LDO_RDY_V 0x00000001U +#define PMU_FLASH1P2_LDO_RDY_S 0 +/** PMU_FLASH1P2_SW_EN_XPD : R/W; bitpos: [1]; default: 0; + * need_des + */ +#define PMU_FLASH1P2_SW_EN_XPD (BIT(1)) +#define PMU_FLASH1P2_SW_EN_XPD_M (PMU_FLASH1P2_SW_EN_XPD_V << PMU_FLASH1P2_SW_EN_XPD_S) +#define PMU_FLASH1P2_SW_EN_XPD_V 0x00000001U +#define PMU_FLASH1P2_SW_EN_XPD_S 1 +/** PMU_FLASH1P2_SW_EN_THRU : R/W; bitpos: [2]; default: 0; + * need_des + */ +#define PMU_FLASH1P2_SW_EN_THRU (BIT(2)) +#define PMU_FLASH1P2_SW_EN_THRU_M (PMU_FLASH1P2_SW_EN_THRU_V << PMU_FLASH1P2_SW_EN_THRU_S) +#define PMU_FLASH1P2_SW_EN_THRU_V 0x00000001U +#define PMU_FLASH1P2_SW_EN_THRU_S 2 +/** PMU_FLASH1P2_SW_EN_STANDBY : R/W; bitpos: [3]; default: 0; + * need_des + */ +#define PMU_FLASH1P2_SW_EN_STANDBY (BIT(3)) +#define PMU_FLASH1P2_SW_EN_STANDBY_M (PMU_FLASH1P2_SW_EN_STANDBY_V << PMU_FLASH1P2_SW_EN_STANDBY_S) +#define PMU_FLASH1P2_SW_EN_STANDBY_V 0x00000001U +#define PMU_FLASH1P2_SW_EN_STANDBY_S 3 +/** PMU_FLASH1P2_SW_EN_POWER_ADJUST : R/W; bitpos: [4]; default: 0; + * need_des + */ +#define PMU_FLASH1P2_SW_EN_POWER_ADJUST (BIT(4)) +#define PMU_FLASH1P2_SW_EN_POWER_ADJUST_M (PMU_FLASH1P2_SW_EN_POWER_ADJUST_V << PMU_FLASH1P2_SW_EN_POWER_ADJUST_S) +#define PMU_FLASH1P2_SW_EN_POWER_ADJUST_V 0x00000001U +#define PMU_FLASH1P2_SW_EN_POWER_ADJUST_S 4 +/** PMU_FLASH1P2_SW_EN_ENDET : R/W; bitpos: [5]; default: 0; + * need_des + */ +#define PMU_FLASH1P2_SW_EN_ENDET (BIT(5)) +#define PMU_FLASH1P2_SW_EN_ENDET_M (PMU_FLASH1P2_SW_EN_ENDET_V << PMU_FLASH1P2_SW_EN_ENDET_S) +#define PMU_FLASH1P2_SW_EN_ENDET_V 0x00000001U +#define PMU_FLASH1P2_SW_EN_ENDET_S 5 +/** PMU_FLASH1P2_BYPASS_LDO_RDY : R/W; bitpos: [22]; default: 0; + * need_des + */ +#define PMU_FLASH1P2_BYPASS_LDO_RDY (BIT(22)) +#define PMU_FLASH1P2_BYPASS_LDO_RDY_M (PMU_FLASH1P2_BYPASS_LDO_RDY_V << PMU_FLASH1P2_BYPASS_LDO_RDY_S) +#define PMU_FLASH1P2_BYPASS_LDO_RDY_V 0x00000001U +#define PMU_FLASH1P2_BYPASS_LDO_RDY_S 22 +/** PMU_FLASH1P2_XPD : R/W; bitpos: [23]; default: 0; + * need_des + */ +#define PMU_FLASH1P2_XPD (BIT(23)) +#define PMU_FLASH1P2_XPD_M (PMU_FLASH1P2_XPD_V << PMU_FLASH1P2_XPD_S) +#define PMU_FLASH1P2_XPD_V 0x00000001U +#define PMU_FLASH1P2_XPD_S 23 +/** PMU_FLASH1P2_THRU : R/W; bitpos: [24]; default: 1; + * need_des + */ +#define PMU_FLASH1P2_THRU (BIT(24)) +#define PMU_FLASH1P2_THRU_M (PMU_FLASH1P2_THRU_V << PMU_FLASH1P2_THRU_S) +#define PMU_FLASH1P2_THRU_V 0x00000001U +#define PMU_FLASH1P2_THRU_S 24 +/** PMU_FLASH1P2_STANDBY : R/W; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_FLASH1P2_STANDBY (BIT(25)) +#define PMU_FLASH1P2_STANDBY_M (PMU_FLASH1P2_STANDBY_V << PMU_FLASH1P2_STANDBY_S) +#define PMU_FLASH1P2_STANDBY_V 0x00000001U +#define PMU_FLASH1P2_STANDBY_S 25 +/** PMU_FLASH1P2_POWER_ADJUST : R/W; bitpos: [30:26]; default: 0; + * need_des + */ +#define PMU_FLASH1P2_POWER_ADJUST 0x0000001FU +#define PMU_FLASH1P2_POWER_ADJUST_M (PMU_FLASH1P2_POWER_ADJUST_V << PMU_FLASH1P2_POWER_ADJUST_S) +#define PMU_FLASH1P2_POWER_ADJUST_V 0x0000001FU +#define PMU_FLASH1P2_POWER_ADJUST_S 26 +/** PMU_FLASH1P2_ENDET : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_FLASH1P2_ENDET (BIT(31)) +#define PMU_FLASH1P2_ENDET_M (PMU_FLASH1P2_ENDET_V << PMU_FLASH1P2_ENDET_S) +#define PMU_FLASH1P2_ENDET_V 0x00000001U +#define PMU_FLASH1P2_ENDET_S 31 + +/** PMU_POWER_VDD_FLASH_REG register + * need_des + */ +#define PMU_POWER_VDD_FLASH_REG (DR_REG_PMU_BASE + 0x124) +/** PMU_FLASH_LDO_SW_EN_TIEL : R/W; bitpos: [22]; default: 0; + * need_des + */ +#define PMU_FLASH_LDO_SW_EN_TIEL (BIT(22)) +#define PMU_FLASH_LDO_SW_EN_TIEL_M (PMU_FLASH_LDO_SW_EN_TIEL_V << PMU_FLASH_LDO_SW_EN_TIEL_S) +#define PMU_FLASH_LDO_SW_EN_TIEL_V 0x00000001U +#define PMU_FLASH_LDO_SW_EN_TIEL_S 22 +/** PMU_FLASH_LDO_POWER_SEL : R/W; bitpos: [23]; default: 0; + * need_des + */ +#define PMU_FLASH_LDO_POWER_SEL (BIT(23)) +#define PMU_FLASH_LDO_POWER_SEL_M (PMU_FLASH_LDO_POWER_SEL_V << PMU_FLASH_LDO_POWER_SEL_S) +#define PMU_FLASH_LDO_POWER_SEL_V 0x00000001U +#define PMU_FLASH_LDO_POWER_SEL_S 23 +/** PMU_FLASH_LDO_SW_EN_POWER_SEL : R/W; bitpos: [24]; default: 0; + * need_des + */ +#define PMU_FLASH_LDO_SW_EN_POWER_SEL (BIT(24)) +#define PMU_FLASH_LDO_SW_EN_POWER_SEL_M (PMU_FLASH_LDO_SW_EN_POWER_SEL_V << PMU_FLASH_LDO_SW_EN_POWER_SEL_S) +#define PMU_FLASH_LDO_SW_EN_POWER_SEL_V 0x00000001U +#define PMU_FLASH_LDO_SW_EN_POWER_SEL_S 24 +/** PMU_FLASH_LDO_WAIT_TARGET : R/W; bitpos: [28:25]; default: 15; + * need_des + */ +#define PMU_FLASH_LDO_WAIT_TARGET 0x0000000FU +#define PMU_FLASH_LDO_WAIT_TARGET_M (PMU_FLASH_LDO_WAIT_TARGET_V << PMU_FLASH_LDO_WAIT_TARGET_S) +#define PMU_FLASH_LDO_WAIT_TARGET_V 0x0000000FU +#define PMU_FLASH_LDO_WAIT_TARGET_S 25 +/** PMU_FLASH_LDO_TIEL_EN : R/W; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_FLASH_LDO_TIEL_EN (BIT(29)) +#define PMU_FLASH_LDO_TIEL_EN_M (PMU_FLASH_LDO_TIEL_EN_V << PMU_FLASH_LDO_TIEL_EN_S) +#define PMU_FLASH_LDO_TIEL_EN_V 0x00000001U +#define PMU_FLASH_LDO_TIEL_EN_S 29 +/** PMU_FLASH_LDO_TIEL : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_FLASH_LDO_TIEL (BIT(30)) +#define PMU_FLASH_LDO_TIEL_M (PMU_FLASH_LDO_TIEL_V << PMU_FLASH_LDO_TIEL_S) +#define PMU_FLASH_LDO_TIEL_V 0x00000001U +#define PMU_FLASH_LDO_TIEL_S 30 +/** PMU_FLASH_LDO_SW_UPDATE : WT; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_FLASH_LDO_SW_UPDATE (BIT(31)) +#define PMU_FLASH_LDO_SW_UPDATE_M (PMU_FLASH_LDO_SW_UPDATE_V << PMU_FLASH_LDO_SW_UPDATE_S) +#define PMU_FLASH_LDO_SW_UPDATE_V 0x00000001U +#define PMU_FLASH_LDO_SW_UPDATE_S 31 + +/** PMU_POWER_IO_LDO_REG register + * need_des + */ +#define PMU_POWER_IO_LDO_REG (DR_REG_PMU_BASE + 0x128) +/** PMU_IO_LDO_RDY : RO; bitpos: [0]; default: 1; + * need_des + */ +#define PMU_IO_LDO_RDY (BIT(0)) +#define PMU_IO_LDO_RDY_M (PMU_IO_LDO_RDY_V << PMU_IO_LDO_RDY_S) +#define PMU_IO_LDO_RDY_V 0x00000001U +#define PMU_IO_LDO_RDY_S 0 +/** PMU_IO_SW_EN_XPD : R/W; bitpos: [1]; default: 0; + * need_des + */ +#define PMU_IO_SW_EN_XPD (BIT(1)) +#define PMU_IO_SW_EN_XPD_M (PMU_IO_SW_EN_XPD_V << PMU_IO_SW_EN_XPD_S) +#define PMU_IO_SW_EN_XPD_V 0x00000001U +#define PMU_IO_SW_EN_XPD_S 1 +/** PMU_IO_SW_EN_THRU : R/W; bitpos: [3]; default: 0; + * need_des + */ +#define PMU_IO_SW_EN_THRU (BIT(3)) +#define PMU_IO_SW_EN_THRU_M (PMU_IO_SW_EN_THRU_V << PMU_IO_SW_EN_THRU_S) +#define PMU_IO_SW_EN_THRU_V 0x00000001U +#define PMU_IO_SW_EN_THRU_S 3 +/** PMU_IO_SW_EN_STANDBY : R/W; bitpos: [4]; default: 0; + * need_des + */ +#define PMU_IO_SW_EN_STANDBY (BIT(4)) +#define PMU_IO_SW_EN_STANDBY_M (PMU_IO_SW_EN_STANDBY_V << PMU_IO_SW_EN_STANDBY_S) +#define PMU_IO_SW_EN_STANDBY_V 0x00000001U +#define PMU_IO_SW_EN_STANDBY_S 4 +/** PMU_IO_SW_EN_POWER_ADJUST : R/W; bitpos: [5]; default: 0; + * need_des + */ +#define PMU_IO_SW_EN_POWER_ADJUST (BIT(5)) +#define PMU_IO_SW_EN_POWER_ADJUST_M (PMU_IO_SW_EN_POWER_ADJUST_V << PMU_IO_SW_EN_POWER_ADJUST_S) +#define PMU_IO_SW_EN_POWER_ADJUST_V 0x00000001U +#define PMU_IO_SW_EN_POWER_ADJUST_S 5 +/** PMU_IO_SW_EN_ENDET : R/W; bitpos: [6]; default: 0; + * need_des + */ +#define PMU_IO_SW_EN_ENDET (BIT(6)) +#define PMU_IO_SW_EN_ENDET_M (PMU_IO_SW_EN_ENDET_V << PMU_IO_SW_EN_ENDET_S) +#define PMU_IO_SW_EN_ENDET_V 0x00000001U +#define PMU_IO_SW_EN_ENDET_S 6 +/** PMU_IO_BYPASS_LDO_RDY : R/W; bitpos: [22]; default: 0; + * need_des + */ +#define PMU_IO_BYPASS_LDO_RDY (BIT(22)) +#define PMU_IO_BYPASS_LDO_RDY_M (PMU_IO_BYPASS_LDO_RDY_V << PMU_IO_BYPASS_LDO_RDY_S) +#define PMU_IO_BYPASS_LDO_RDY_V 0x00000001U +#define PMU_IO_BYPASS_LDO_RDY_S 22 +/** PMU_IO_XPD : R/W; bitpos: [23]; default: 0; + * need_des + */ +#define PMU_IO_XPD (BIT(23)) +#define PMU_IO_XPD_M (PMU_IO_XPD_V << PMU_IO_XPD_S) +#define PMU_IO_XPD_V 0x00000001U +#define PMU_IO_XPD_S 23 +/** PMU_IO_THRU : R/W; bitpos: [24]; default: 1; + * need_des + */ +#define PMU_IO_THRU (BIT(24)) +#define PMU_IO_THRU_M (PMU_IO_THRU_V << PMU_IO_THRU_S) +#define PMU_IO_THRU_V 0x00000001U +#define PMU_IO_THRU_S 24 +/** PMU_IO_STANDBY : R/W; bitpos: [25]; default: 0; + * need_des + */ +#define PMU_IO_STANDBY (BIT(25)) +#define PMU_IO_STANDBY_M (PMU_IO_STANDBY_V << PMU_IO_STANDBY_S) +#define PMU_IO_STANDBY_V 0x00000001U +#define PMU_IO_STANDBY_S 25 +/** PMU_IO_POWER_ADJUST : R/W; bitpos: [30:26]; default: 0; + * need_des + */ +#define PMU_IO_POWER_ADJUST 0x0000001FU +#define PMU_IO_POWER_ADJUST_M (PMU_IO_POWER_ADJUST_V << PMU_IO_POWER_ADJUST_S) +#define PMU_IO_POWER_ADJUST_V 0x0000001FU +#define PMU_IO_POWER_ADJUST_S 26 +/** PMU_IO_ENDET : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_IO_ENDET (BIT(31)) +#define PMU_IO_ENDET_M (PMU_IO_ENDET_V << PMU_IO_ENDET_S) +#define PMU_IO_ENDET_V 0x00000001U +#define PMU_IO_ENDET_S 31 + +/** PMU_POWER_VDD_IO_REG register + * need_des + */ +#define PMU_POWER_VDD_IO_REG (DR_REG_PMU_BASE + 0x12c) +/** PMU_IO_LDO_POWER_SEL : R/W; bitpos: [23]; default: 0; + * need_des + */ +#define PMU_IO_LDO_POWER_SEL (BIT(23)) +#define PMU_IO_LDO_POWER_SEL_M (PMU_IO_LDO_POWER_SEL_V << PMU_IO_LDO_POWER_SEL_S) +#define PMU_IO_LDO_POWER_SEL_V 0x00000001U +#define PMU_IO_LDO_POWER_SEL_S 23 +/** PMU_IO_LDO_SW_EN_POWER_SEL : R/W; bitpos: [24]; default: 0; + * need_des + */ +#define PMU_IO_LDO_SW_EN_POWER_SEL (BIT(24)) +#define PMU_IO_LDO_SW_EN_POWER_SEL_M (PMU_IO_LDO_SW_EN_POWER_SEL_V << PMU_IO_LDO_SW_EN_POWER_SEL_S) +#define PMU_IO_LDO_SW_EN_POWER_SEL_V 0x00000001U +#define PMU_IO_LDO_SW_EN_POWER_SEL_S 24 /** PMU_POWER_CK_WAIT_CNTL_REG register * need_des */ -#define PMU_POWER_CK_WAIT_CNTL_REG (DR_REG_PMU_BASE + 0x11c) +#define PMU_POWER_CK_WAIT_CNTL_REG (DR_REG_PMU_BASE + 0x130) /** PMU_WAIT_XTL_STABLE : R/W; bitpos: [15:0]; default: 256; * need_des */ @@ -2313,7 +2954,7 @@ extern "C" { /** PMU_SLP_WAKEUP_CNTL0_REG register * need_des */ -#define PMU_SLP_WAKEUP_CNTL0_REG (DR_REG_PMU_BASE + 0x120) +#define PMU_SLP_WAKEUP_CNTL0_REG (DR_REG_PMU_BASE + 0x134) /** PMU_SLEEP_REQ : WT; bitpos: [31]; default: 0; * need_des */ @@ -2325,7 +2966,7 @@ extern "C" { /** PMU_SLP_WAKEUP_CNTL1_REG register * need_des */ -#define PMU_SLP_WAKEUP_CNTL1_REG (DR_REG_PMU_BASE + 0x124) +#define PMU_SLP_WAKEUP_CNTL1_REG (DR_REG_PMU_BASE + 0x138) /** PMU_SLEEP_REJECT_ENA : R/W; bitpos: [30:0]; default: 0; * need_des */ @@ -2344,7 +2985,7 @@ extern "C" { /** PMU_SLP_WAKEUP_CNTL2_REG register * need_des */ -#define PMU_SLP_WAKEUP_CNTL2_REG (DR_REG_PMU_BASE + 0x128) +#define PMU_SLP_WAKEUP_CNTL2_REG (DR_REG_PMU_BASE + 0x13c) /** PMU_WAKEUP_ENA : R/W; bitpos: [31:0]; default: 0; * need_des */ @@ -2356,7 +2997,7 @@ extern "C" { /** PMU_SLP_WAKEUP_CNTL3_REG register * need_des */ -#define PMU_SLP_WAKEUP_CNTL3_REG (DR_REG_PMU_BASE + 0x12c) +#define PMU_SLP_WAKEUP_CNTL3_REG (DR_REG_PMU_BASE + 0x140) /** PMU_LP_MIN_SLP_VAL : R/W; bitpos: [7:0]; default: 0; * need_des */ @@ -2382,7 +3023,7 @@ extern "C" { /** PMU_SLP_WAKEUP_CNTL4_REG register * need_des */ -#define PMU_SLP_WAKEUP_CNTL4_REG (DR_REG_PMU_BASE + 0x130) +#define PMU_SLP_WAKEUP_CNTL4_REG (DR_REG_PMU_BASE + 0x144) /** PMU_SLP_REJECT_CAUSE_CLR : WT; bitpos: [31]; default: 0; * need_des */ @@ -2394,7 +3035,7 @@ extern "C" { /** PMU_SLP_WAKEUP_CNTL5_REG register * need_des */ -#define PMU_SLP_WAKEUP_CNTL5_REG (DR_REG_PMU_BASE + 0x134) +#define PMU_SLP_WAKEUP_CNTL5_REG (DR_REG_PMU_BASE + 0x148) /** PMU_MODEM_WAIT_TARGET : R/W; bitpos: [19:0]; default: 128; * need_des */ @@ -2413,7 +3054,7 @@ extern "C" { /** PMU_SLP_WAKEUP_CNTL6_REG register * need_des */ -#define PMU_SLP_WAKEUP_CNTL6_REG (DR_REG_PMU_BASE + 0x138) +#define PMU_SLP_WAKEUP_CNTL6_REG (DR_REG_PMU_BASE + 0x14c) /** PMU_SOC_WAKEUP_WAIT : R/W; bitpos: [19:0]; default: 128; * need_des */ @@ -2432,7 +3073,14 @@ extern "C" { /** PMU_SLP_WAKEUP_CNTL7_REG register * need_des */ -#define PMU_SLP_WAKEUP_CNTL7_REG (DR_REG_PMU_BASE + 0x13c) +#define PMU_SLP_WAKEUP_CNTL7_REG (DR_REG_PMU_BASE + 0x150) +/** PMU_ANA_WAIT_CLK_SEL : R/W; bitpos: [15]; default: 0; + * need_des + */ +#define PMU_ANA_WAIT_CLK_SEL (BIT(15)) +#define PMU_ANA_WAIT_CLK_SEL_M (PMU_ANA_WAIT_CLK_SEL_V << PMU_ANA_WAIT_CLK_SEL_S) +#define PMU_ANA_WAIT_CLK_SEL_V 0x00000001U +#define PMU_ANA_WAIT_CLK_SEL_S 15 /** PMU_ANA_WAIT_TARGET : R/W; bitpos: [31:16]; default: 1; * need_des */ @@ -2444,7 +3092,7 @@ extern "C" { /** PMU_SLP_WAKEUP_STATUS0_REG register * need_des */ -#define PMU_SLP_WAKEUP_STATUS0_REG (DR_REG_PMU_BASE + 0x140) +#define PMU_SLP_WAKEUP_STATUS0_REG (DR_REG_PMU_BASE + 0x154) /** PMU_WAKEUP_CAUSE : RO; bitpos: [31:0]; default: 0; * need_des */ @@ -2456,7 +3104,7 @@ extern "C" { /** PMU_SLP_WAKEUP_STATUS1_REG register * need_des */ -#define PMU_SLP_WAKEUP_STATUS1_REG (DR_REG_PMU_BASE + 0x144) +#define PMU_SLP_WAKEUP_STATUS1_REG (DR_REG_PMU_BASE + 0x158) /** PMU_REJECT_CAUSE : RO; bitpos: [31:0]; default: 0; * need_des */ @@ -2468,7 +3116,7 @@ extern "C" { /** PMU_HP_CK_POWERON_REG register * need_des */ -#define PMU_HP_CK_POWERON_REG (DR_REG_PMU_BASE + 0x148) +#define PMU_HP_CK_POWERON_REG (DR_REG_PMU_BASE + 0x15c) /** PMU_I2C_POR_WAIT_TARGET : R/W; bitpos: [7:0]; default: 50; * need_des */ @@ -2480,7 +3128,7 @@ extern "C" { /** PMU_HP_CK_CNTL_REG register * need_des */ -#define PMU_HP_CK_CNTL_REG (DR_REG_PMU_BASE + 0x14c) +#define PMU_HP_CK_CNTL_REG (DR_REG_PMU_BASE + 0x160) /** PMU_MODIFY_ICG_CNTL_WAIT : R/W; bitpos: [7:0]; default: 10; * need_des */ @@ -2499,8 +3147,8 @@ extern "C" { /** PMU_POR_STATUS_REG register * need_des */ -#define PMU_POR_STATUS_REG (DR_REG_PMU_BASE + 0x150) -/** PMU_POR_DONE : RO; bitpos: [31]; default: 1; +#define PMU_POR_STATUS_REG (DR_REG_PMU_BASE + 0x164) +/** PMU_POR_DONE : RO; bitpos: [31]; default: 0; * need_des */ #define PMU_POR_DONE (BIT(31)) @@ -2511,7 +3159,14 @@ extern "C" { /** PMU_RF_PWC_REG register * need_des */ -#define PMU_RF_PWC_REG (DR_REG_PMU_BASE + 0x154) +#define PMU_RF_PWC_REG (DR_REG_PMU_BASE + 0x168) +/** PMU_XPD_FORCE_RFTX : R/W; bitpos: [26]; default: 0; + * need_des + */ +#define PMU_XPD_FORCE_RFTX (BIT(26)) +#define PMU_XPD_FORCE_RFTX_M (PMU_XPD_FORCE_RFTX_V << PMU_XPD_FORCE_RFTX_S) +#define PMU_XPD_FORCE_RFTX_V 0x00000001U +#define PMU_XPD_FORCE_RFTX_S 26 /** PMU_XPD_PERIF_I2C : R/W; bitpos: [27]; default: 1; * need_des */ @@ -2551,7 +3206,7 @@ extern "C" { /** PMU_VDDBAT_CFG_REG register * need_des */ -#define PMU_VDDBAT_CFG_REG (DR_REG_PMU_BASE + 0x158) +#define PMU_VDDBAT_CFG_REG (DR_REG_PMU_BASE + 0x16c) /** PMU_VDDBAT_MODE : RO; bitpos: [1:0]; default: 0; * need_des */ @@ -2570,7 +3225,7 @@ extern "C" { /** PMU_BACKUP_CFG_REG register * need_des */ -#define PMU_BACKUP_CFG_REG (DR_REG_PMU_BASE + 0x15c) +#define PMU_BACKUP_CFG_REG (DR_REG_PMU_BASE + 0x170) /** PMU_BACKUP_SYS_CLK_NO_DIV : R/W; bitpos: [31]; default: 1; * need_des */ @@ -2582,7 +3237,7 @@ extern "C" { /** PMU_INT_RAW_REG register * need_des */ -#define PMU_INT_RAW_REG (DR_REG_PMU_BASE + 0x160) +#define PMU_INT_RAW_REG (DR_REG_PMU_BASE + 0x174) /** PMU_LP_CPU_EXC_INT_RAW : R/WTC/SS; bitpos: [27]; default: 0; * need_des */ @@ -2622,7 +3277,7 @@ extern "C" { /** PMU_HP_INT_ST_REG register * need_des */ -#define PMU_HP_INT_ST_REG (DR_REG_PMU_BASE + 0x164) +#define PMU_HP_INT_ST_REG (DR_REG_PMU_BASE + 0x178) /** PMU_LP_CPU_EXC_INT_ST : RO; bitpos: [27]; default: 0; * need_des */ @@ -2662,7 +3317,7 @@ extern "C" { /** PMU_HP_INT_ENA_REG register * need_des */ -#define PMU_HP_INT_ENA_REG (DR_REG_PMU_BASE + 0x168) +#define PMU_HP_INT_ENA_REG (DR_REG_PMU_BASE + 0x17c) /** PMU_LP_CPU_EXC_INT_ENA : R/W; bitpos: [27]; default: 0; * need_des */ @@ -2702,7 +3357,7 @@ extern "C" { /** PMU_HP_INT_CLR_REG register * need_des */ -#define PMU_HP_INT_CLR_REG (DR_REG_PMU_BASE + 0x16c) +#define PMU_HP_INT_CLR_REG (DR_REG_PMU_BASE + 0x180) /** PMU_LP_CPU_EXC_INT_CLR : WT; bitpos: [27]; default: 0; * need_des */ @@ -2742,7 +3397,7 @@ extern "C" { /** PMU_LP_INT_RAW_REG register * need_des */ -#define PMU_LP_INT_RAW_REG (DR_REG_PMU_BASE + 0x170) +#define PMU_LP_INT_RAW_REG (DR_REG_PMU_BASE + 0x184) /** PMU_LP_CPU_WAKEUP_INT_RAW : R/WTC/SS; bitpos: [20]; default: 0; * need_des */ @@ -2831,7 +3486,7 @@ extern "C" { /** PMU_LP_INT_ST_REG register * need_des */ -#define PMU_LP_INT_ST_REG (DR_REG_PMU_BASE + 0x174) +#define PMU_LP_INT_ST_REG (DR_REG_PMU_BASE + 0x188) /** PMU_LP_CPU_WAKEUP_INT_ST : RO; bitpos: [20]; default: 0; * need_des */ @@ -2920,7 +3575,7 @@ extern "C" { /** PMU_LP_INT_ENA_REG register * need_des */ -#define PMU_LP_INT_ENA_REG (DR_REG_PMU_BASE + 0x178) +#define PMU_LP_INT_ENA_REG (DR_REG_PMU_BASE + 0x18c) /** PMU_LP_CPU_WAKEUP_INT_ENA : R/W; bitpos: [20]; default: 0; * need_des */ @@ -3009,7 +3664,7 @@ extern "C" { /** PMU_LP_INT_CLR_REG register * need_des */ -#define PMU_LP_INT_CLR_REG (DR_REG_PMU_BASE + 0x17c) +#define PMU_LP_INT_CLR_REG (DR_REG_PMU_BASE + 0x190) /** PMU_LP_CPU_WAKEUP_INT_CLR : WT; bitpos: [20]; default: 0; * need_des */ @@ -3098,7 +3753,7 @@ extern "C" { /** PMU_LP_CPU_PWR0_REG register * need_des */ -#define PMU_LP_CPU_PWR0_REG (DR_REG_PMU_BASE + 0x180) +#define PMU_LP_CPU_PWR0_REG (DR_REG_PMU_BASE + 0x194) /** PMU_LP_CPU_WAITI_RDY : RO; bitpos: [0]; default: 0; * need_des */ @@ -3166,7 +3821,7 @@ extern "C" { /** PMU_LP_CPU_PWR1_REG register * need_des */ -#define PMU_LP_CPU_PWR1_REG (DR_REG_PMU_BASE + 0x184) +#define PMU_LP_CPU_PWR1_REG (DR_REG_PMU_BASE + 0x198) /** PMU_LP_CPU_WAKEUP_EN : R/W; bitpos: [15:0]; default: 0; * need_des */ @@ -3185,7 +3840,7 @@ extern "C" { /** PMU_HP_LP_CPU_COMM_REG register * need_des */ -#define PMU_HP_LP_CPU_COMM_REG (DR_REG_PMU_BASE + 0x188) +#define PMU_HP_LP_CPU_COMM_REG (DR_REG_PMU_BASE + 0x19c) /** PMU_LP_TRIGGER_HP : WT; bitpos: [30]; default: 0; * need_des */ @@ -3204,7 +3859,7 @@ extern "C" { /** PMU_HP_REGULATOR_CFG_REG register * need_des */ -#define PMU_HP_REGULATOR_CFG_REG (DR_REG_PMU_BASE + 0x18c) +#define PMU_HP_REGULATOR_CFG_REG (DR_REG_PMU_BASE + 0x1a0) /** PMU_DIG_REGULATOR_EN_CAL : R/W; bitpos: [31]; default: 0; * need_des */ @@ -3216,8 +3871,8 @@ extern "C" { /** PMU_MAIN_STATE_REG register * need_des */ -#define PMU_MAIN_STATE_REG (DR_REG_PMU_BASE + 0x190) -/** PMU_MAIN_LAST_ST_STATE : RO; bitpos: [17:11]; default: 1; +#define PMU_MAIN_STATE_REG (DR_REG_PMU_BASE + 0x1a4) +/** PMU_MAIN_LAST_ST_STATE : RO; bitpos: [17:11]; default: 256; * need_des */ #define PMU_MAIN_LAST_ST_STATE 0x0000007FU @@ -3231,7 +3886,7 @@ extern "C" { #define PMU_MAIN_TAR_ST_STATE_M (PMU_MAIN_TAR_ST_STATE_V << PMU_MAIN_TAR_ST_STATE_S) #define PMU_MAIN_TAR_ST_STATE_V 0x0000007FU #define PMU_MAIN_TAR_ST_STATE_S 18 -/** PMU_MAIN_CUR_ST_STATE : RO; bitpos: [31:25]; default: 4; +/** PMU_MAIN_CUR_ST_STATE : RO; bitpos: [31:25]; default: 1; * need_des */ #define PMU_MAIN_CUR_ST_STATE 0x0000007FU @@ -3242,7 +3897,7 @@ extern "C" { /** PMU_PWR_STATE_REG register * need_des */ -#define PMU_PWR_STATE_REG (DR_REG_PMU_BASE + 0x194) +#define PMU_PWR_STATE_REG (DR_REG_PMU_BASE + 0x1a8) /** PMU_BACKUP_ST_STATE : RO; bitpos: [17:13]; default: 1; * need_des */ @@ -3268,15 +3923,15 @@ extern "C" { /** PMU_CLK_STATE0_REG register * need_des */ -#define PMU_CLK_STATE0_REG (DR_REG_PMU_BASE + 0x198) -/** PMU_STABLE_XPD_BBPLL_STATE : RO; bitpos: [0]; default: 1; +#define PMU_CLK_STATE0_REG (DR_REG_PMU_BASE + 0x1ac) +/** PMU_STABLE_XPD_BBPLL_STATE : RO; bitpos: [0]; default: 0; * need_des */ #define PMU_STABLE_XPD_BBPLL_STATE (BIT(0)) #define PMU_STABLE_XPD_BBPLL_STATE_M (PMU_STABLE_XPD_BBPLL_STATE_V << PMU_STABLE_XPD_BBPLL_STATE_S) #define PMU_STABLE_XPD_BBPLL_STATE_V 0x00000001U #define PMU_STABLE_XPD_BBPLL_STATE_S 0 -/** PMU_STABLE_XPD_XTAL_STATE : RO; bitpos: [1]; default: 1; +/** PMU_STABLE_XPD_XTAL_STATE : RO; bitpos: [1]; default: 0; * need_des */ #define PMU_STABLE_XPD_XTAL_STATE (BIT(1)) @@ -3304,7 +3959,7 @@ extern "C" { #define PMU_SYS_CLK_NO_DIV_STATE_M (PMU_SYS_CLK_NO_DIV_STATE_V << PMU_SYS_CLK_NO_DIV_STATE_S) #define PMU_SYS_CLK_NO_DIV_STATE_V 0x00000001U #define PMU_SYS_CLK_NO_DIV_STATE_S 18 -/** PMU_ICG_SYS_CLK_EN_STATE : RO; bitpos: [19]; default: 0; +/** PMU_ICG_SYS_CLK_EN_STATE : RO; bitpos: [19]; default: 1; * need_des */ #define PMU_ICG_SYS_CLK_EN_STATE (BIT(19)) @@ -3381,7 +4036,7 @@ extern "C" { #define PMU_ANA_XPD_BBPLL_STATE_M (PMU_ANA_XPD_BBPLL_STATE_V << PMU_ANA_XPD_BBPLL_STATE_S) #define PMU_ANA_XPD_BBPLL_STATE_V 0x00000001U #define PMU_ANA_XPD_BBPLL_STATE_S 30 -/** PMU_ANA_XPD_XTAL_STATE : RO; bitpos: [31]; default: 0; +/** PMU_ANA_XPD_XTAL_STATE : RO; bitpos: [31]; default: 1; * need_des */ #define PMU_ANA_XPD_XTAL_STATE (BIT(31)) @@ -3392,7 +4047,7 @@ extern "C" { /** PMU_CLK_STATE1_REG register * need_des */ -#define PMU_CLK_STATE1_REG (DR_REG_PMU_BASE + 0x19c) +#define PMU_CLK_STATE1_REG (DR_REG_PMU_BASE + 0x1b0) /** PMU_ICG_FUNC_EN_STATE : RO; bitpos: [31:0]; default: 4294967295; * need_des */ @@ -3404,7 +4059,7 @@ extern "C" { /** PMU_CLK_STATE2_REG register * need_des */ -#define PMU_CLK_STATE2_REG (DR_REG_PMU_BASE + 0x1a0) +#define PMU_CLK_STATE2_REG (DR_REG_PMU_BASE + 0x1b4) /** PMU_ICG_APB_EN_STATE : RO; bitpos: [31:0]; default: 4294967295; * need_des */ @@ -3413,23 +4068,112 @@ extern "C" { #define PMU_ICG_APB_EN_STATE_V 0xFFFFFFFFU #define PMU_ICG_APB_EN_STATE_S 0 -/** PMU_VDD_SPI_STATUS_REG register +/** PMU_DCM_CTRL_REG register * need_des */ -#define PMU_VDD_SPI_STATUS_REG (DR_REG_PMU_BASE + 0x1a4) -/** PMU_STABLE_VDD_SPI_PWR_DRV : RO; bitpos: [31]; default: 0; +#define PMU_DCM_CTRL_REG (DR_REG_PMU_BASE + 0x1b8) +/** PMU_DSFMOS_USE_POR : R/W; bitpos: [0]; default: 1; * need_des */ -#define PMU_STABLE_VDD_SPI_PWR_DRV (BIT(31)) -#define PMU_STABLE_VDD_SPI_PWR_DRV_M (PMU_STABLE_VDD_SPI_PWR_DRV_V << PMU_STABLE_VDD_SPI_PWR_DRV_S) -#define PMU_STABLE_VDD_SPI_PWR_DRV_V 0x00000001U -#define PMU_STABLE_VDD_SPI_PWR_DRV_S 31 +#define PMU_DSFMOS_USE_POR (BIT(0)) +#define PMU_DSFMOS_USE_POR_M (PMU_DSFMOS_USE_POR_V << PMU_DSFMOS_USE_POR_S) +#define PMU_DSFMOS_USE_POR_V 0x00000001U +#define PMU_DSFMOS_USE_POR_S 0 +/** PMU_DCDC_DCM_UPDATE : WT; bitpos: [22]; default: 0; + * need_des + */ +#define PMU_DCDC_DCM_UPDATE (BIT(22)) +#define PMU_DCDC_DCM_UPDATE_M (PMU_DCDC_DCM_UPDATE_V << PMU_DCDC_DCM_UPDATE_S) +#define PMU_DCDC_DCM_UPDATE_V 0x00000001U +#define PMU_DCDC_DCM_UPDATE_S 22 +/** PMU_DCDC_PCUR_LIMIT : R/W; bitpos: [25:23]; default: 1; + * need_des + */ +#define PMU_DCDC_PCUR_LIMIT 0x00000007U +#define PMU_DCDC_PCUR_LIMIT_M (PMU_DCDC_PCUR_LIMIT_V << PMU_DCDC_PCUR_LIMIT_S) +#define PMU_DCDC_PCUR_LIMIT_V 0x00000007U +#define PMU_DCDC_PCUR_LIMIT_S 23 +/** PMU_DCDC_BIAS_CAL_DONE : RO; bitpos: [26]; default: 1; + * need_des + */ +#define PMU_DCDC_BIAS_CAL_DONE (BIT(26)) +#define PMU_DCDC_BIAS_CAL_DONE_M (PMU_DCDC_BIAS_CAL_DONE_V << PMU_DCDC_BIAS_CAL_DONE_S) +#define PMU_DCDC_BIAS_CAL_DONE_V 0x00000001U +#define PMU_DCDC_BIAS_CAL_DONE_S 26 +/** PMU_DCDC_CCM_SW_EN : R/W; bitpos: [27]; default: 0; + * need_des + */ +#define PMU_DCDC_CCM_SW_EN (BIT(27)) +#define PMU_DCDC_CCM_SW_EN_M (PMU_DCDC_CCM_SW_EN_V << PMU_DCDC_CCM_SW_EN_S) +#define PMU_DCDC_CCM_SW_EN_V 0x00000001U +#define PMU_DCDC_CCM_SW_EN_S 27 +/** PMU_DCDC_VCM_ENB : R/W; bitpos: [28]; default: 0; + * need_des + */ +#define PMU_DCDC_VCM_ENB (BIT(28)) +#define PMU_DCDC_VCM_ENB_M (PMU_DCDC_VCM_ENB_V << PMU_DCDC_VCM_ENB_S) +#define PMU_DCDC_VCM_ENB_V 0x00000001U +#define PMU_DCDC_VCM_ENB_S 28 +/** PMU_DCDC_CCM_RDY : RO; bitpos: [29]; default: 0; + * need_des + */ +#define PMU_DCDC_CCM_RDY (BIT(29)) +#define PMU_DCDC_CCM_RDY_M (PMU_DCDC_CCM_RDY_V << PMU_DCDC_CCM_RDY_S) +#define PMU_DCDC_CCM_RDY_V 0x00000001U +#define PMU_DCDC_CCM_RDY_S 29 +/** PMU_DCDC_VCM_RDY : RO; bitpos: [30]; default: 1; + * need_des + */ +#define PMU_DCDC_VCM_RDY (BIT(30)) +#define PMU_DCDC_VCM_RDY_M (PMU_DCDC_VCM_RDY_V << PMU_DCDC_VCM_RDY_S) +#define PMU_DCDC_VCM_RDY_V 0x00000001U +#define PMU_DCDC_VCM_RDY_S 30 +/** PMU_DCDC_RDY_CLR : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_DCDC_RDY_CLR (BIT(31)) +#define PMU_DCDC_RDY_CLR_M (PMU_DCDC_RDY_CLR_V << PMU_DCDC_RDY_CLR_S) +#define PMU_DCDC_RDY_CLR_V 0x00000001U +#define PMU_DCDC_RDY_CLR_S 31 + +/** PMU_TOUCH_PWR_CTRL_REG register + * need_des + */ +#define PMU_TOUCH_PWR_CTRL_REG (DR_REG_PMU_BASE + 0x1bc) +/** PMU_TOUCH_SLEEP_CYCLES : R/W; bitpos: [15:0]; default: 0; + * need_des + */ +#define PMU_TOUCH_SLEEP_CYCLES 0x0000FFFFU +#define PMU_TOUCH_SLEEP_CYCLES_M (PMU_TOUCH_SLEEP_CYCLES_V << PMU_TOUCH_SLEEP_CYCLES_S) +#define PMU_TOUCH_SLEEP_CYCLES_V 0x0000FFFFU +#define PMU_TOUCH_SLEEP_CYCLES_S 0 +/** PMU_TOUCH_WAIT_CYCLES : R/W; bitpos: [29:21]; default: 0; + * need_des + */ +#define PMU_TOUCH_WAIT_CYCLES 0x000001FFU +#define PMU_TOUCH_WAIT_CYCLES_M (PMU_TOUCH_WAIT_CYCLES_V << PMU_TOUCH_WAIT_CYCLES_S) +#define PMU_TOUCH_WAIT_CYCLES_V 0x000001FFU +#define PMU_TOUCH_WAIT_CYCLES_S 21 +/** PMU_TOUCH_SLEEP_TIMER_EN : R/W; bitpos: [30]; default: 0; + * need_des + */ +#define PMU_TOUCH_SLEEP_TIMER_EN (BIT(30)) +#define PMU_TOUCH_SLEEP_TIMER_EN_M (PMU_TOUCH_SLEEP_TIMER_EN_V << PMU_TOUCH_SLEEP_TIMER_EN_S) +#define PMU_TOUCH_SLEEP_TIMER_EN_V 0x00000001U +#define PMU_TOUCH_SLEEP_TIMER_EN_S 30 +/** PMU_TOUCH_FORCE_DONE : R/W; bitpos: [31]; default: 0; + * need_des + */ +#define PMU_TOUCH_FORCE_DONE (BIT(31)) +#define PMU_TOUCH_FORCE_DONE_M (PMU_TOUCH_FORCE_DONE_V << PMU_TOUCH_FORCE_DONE_S) +#define PMU_TOUCH_FORCE_DONE_V 0x00000001U +#define PMU_TOUCH_FORCE_DONE_S 31 /** PMU_DATE_REG register * need_des */ #define PMU_DATE_REG (DR_REG_PMU_BASE + 0x3fc) -/** PMU_PMU_DATE : R/W; bitpos: [30:0]; default: 35688960; +/** PMU_PMU_DATE : R/W; bitpos: [30:0]; default: 37814400; * need_des */ #define PMU_PMU_DATE 0x7FFFFFFFU diff --git a/components/soc/esp32h21/register/soc/pmu_struct.h b/components/soc/esp32h21/register/soc/pmu_struct.h index 178613d23b..06a55454bc 100644 --- a/components/soc/esp32h21/register/soc/pmu_struct.h +++ b/components/soc/esp32h21/register/soc/pmu_struct.h @@ -6,36 +6,46 @@ #pragma once #include -#include "soc/pmu_reg.h" +#include #ifdef __cplusplus -extern "C" { +extern "C" +{ #endif -typedef union { - struct { - uint32_t reserved0 : 21; - uint32_t vdd_spi_pd_en: 1; - uint32_t mem_dslp : 1; - uint32_t mem_pd_en : 4; - uint32_t wifi_pd_en : 1; - uint32_t reserved1 : 1; - uint32_t cpu_pd_en : 1; - uint32_t aon_pd_en : 1; - uint32_t top_pd_en : 1; +#include "soc.h" +#include "soc/pmu_reg.h" + +typedef union +{ + struct + { + uint32_t reserved0 : 18; + uint32_t vdd_flash_mode: 4; + uint32_t mem_dslp : 1; + uint32_t mem_pd_en : 4; + uint32_t wifi_pd_en : 1; + uint32_t peri_pd_en : 1; + uint32_t cpu_pd_en : 1; + uint32_t aon_pd_en : 1; + uint32_t top_pd_en : 1; }; uint32_t val; } pmu_hp_dig_power_reg_t; -typedef union { - struct { +typedef union +{ + struct + { uint32_t reserved0: 30; uint32_t code : 2; }; uint32_t val; } pmu_hp_icg_modem_reg_t; -typedef union { - struct { +typedef union +{ + struct + { uint32_t reserved0 : 24; uint32_t uart_wakeup_en : 1; uint32_t lp_pad_hold_all: 1; @@ -48,8 +58,10 @@ typedef union { uint32_t val; } pmu_hp_sys_cntl_reg_t; -typedef union { - struct { +typedef union +{ + struct + { uint32_t reserved0 : 26; uint32_t i2c_iso_en : 1; uint32_t i2c_retention: 1; @@ -61,75 +73,76 @@ typedef union { uint32_t val; } pmu_hp_clk_power_reg_t; -typedef union { - struct { - uint32_t reserved0 : 24; - uint32_t xpd_trx : 1; - uint32_t xpd_bias : 1; - uint32_t reserved1 : 4; - uint32_t pd_cur : 1; - uint32_t bias_sleep: 1; +typedef union +{ + struct + { + uint32_t reserved0 : 9; + uint32_t dcdc_ccm_enb : 1; + uint32_t dcdc_clear_rdy : 1; + uint32_t dig_reg_dpcur_bias: 2; + uint32_t dig_reg_dsfmos : 4; + uint32_t dcm_vset : 5; + uint32_t dcm_mode : 2; + uint32_t xpd_trx : 1; + uint32_t xpd_bias : 1; + uint32_t reserved1 : 3; + uint32_t discnnt_dig_rtc : 1; + uint32_t pd_cur : 1; + uint32_t bias_sleep : 1; }; uint32_t val; } pmu_hp_bias_reg_t; -typedef union { - struct { /* HP: Active State */ +typedef union +{ + struct + { /* HP: Active State */ uint32_t reserved0 : 4; uint32_t hp_sleep2active_backup_modem_clk_code: 2; uint32_t hp_modem2active_backup_modem_clk_code: 2; - uint32_t reserved1 : 2; - uint32_t hp_active_retention_mode : 1; - uint32_t hp_sleep2active_retention_en : 1; - uint32_t hp_modem2active_retention_en : 1; - uint32_t reserved2 : 1; + uint32_t reserved1 : 6; uint32_t hp_sleep2active_backup_clk_sel : 2; uint32_t hp_modem2active_backup_clk_sel : 2; - uint32_t reserved3 : 2; - uint32_t hp_sleep2active_backup_mode : 3; - uint32_t hp_modem2active_backup_mode : 3; - uint32_t reserved4 : 3; + uint32_t hp_sleep2active_backup_mode : 5; + uint32_t hp_modem2active_backup_mode : 5; + uint32_t reserved2 : 1; uint32_t hp_sleep2active_backup_en : 1; uint32_t hp_modem2active_backup_en : 1; - uint32_t reserved5 : 1; + uint32_t reserved3 : 1; }; - struct { /* HP: Modem State */ - uint32_t reserved6 : 4; - uint32_t hp_sleep2modem_backup_modem_clk_code : 2; - uint32_t reserved7 : 4; - uint32_t hp_modem_retention_mode : 1; - uint32_t hp_sleep2modem_retention_en : 1; - uint32_t reserved8 : 2; - uint32_t hp_sleep2modem_backup_clk_sel : 2; - uint32_t reserved9 : 4; - uint32_t hp_sleep2modem_backup_mode : 3; - uint32_t reserved10 : 6; - uint32_t hp_sleep2modem_backup_en : 1; - uint32_t reserved11 : 2; + struct + { /* HP: Modem State */ + uint32_t reserved4 : 4; + uint32_t hp_sleep2modem_backup_modem_clk_code: 2; + uint32_t reserved5 : 8; + uint32_t hp_sleep2modem_backup_clk_sel : 2; + uint32_t reserved6 : 4; + uint32_t hp_sleep2modem_backup_mode : 5; + uint32_t reserved7 : 4; + uint32_t hp_sleep2modem_backup_en : 1; + uint32_t reserved8 : 2; }; - struct { /* HP: Sleep State */ - uint32_t reserved12 : 6; + struct + { /* HP: Sleep State */ + uint32_t reserved9 : 6; uint32_t hp_modem2sleep_backup_modem_clk_code : 2; uint32_t hp_active2sleep_backup_modem_clk_code: 2; - uint32_t hp_sleep_retention_mode : 1; - uint32_t reserved13 : 1; - uint32_t hp_modem2sleep_retention_en : 1; - uint32_t hp_active2sleep_retention_en : 1; - uint32_t reserved14 : 2; + uint32_t reserved10 : 6; uint32_t hp_modem2sleep_backup_clk_sel : 2; uint32_t hp_active2sleep_backup_clk_sel : 2; - uint32_t reserved15 : 3; - uint32_t hp_modem2sleep_backup_mode : 3; - uint32_t hp_active2sleep_backup_mode : 3; - uint32_t reserved16 : 1; + uint32_t hp_modem2sleep_backup_mode : 5; + uint32_t hp_active2sleep_backup_mode : 5; uint32_t hp_modem2sleep_backup_en : 1; uint32_t hp_active2sleep_backup_en : 1; }; uint32_t val; } pmu_hp_backup_reg_t; -typedef union { - struct { +typedef union +{ + struct + { uint32_t reserved0 : 26; uint32_t dig_sysclk_nodiv: 1; uint32_t icg_sysclk_en : 1; @@ -140,97 +153,116 @@ typedef union { uint32_t val; } pmu_hp_sysclk_reg_t; -typedef union { - struct { - uint32_t power_det_bypass : 1; - uint32_t reserved0 : 3; /* Only HP_ACTIVE modem under hp system is valid */ - uint32_t lp_dbias_vol : 5; /* Only HP_ACTIVE modem under hp system is valid */ - uint32_t hp_dbias_vol : 5; /* Only HP_ACTIVE modem under hp system is valid */ - uint32_t dbias_sel : 1; /* Only HP_ACTIVE modem under hp system is valid */ - uint32_t dbias_init : 1; /* Only HP_ACTIVE modem under hp system is valid */ - uint32_t slp_mem_xpd : 1; - uint32_t slp_logic_xpd : 1; - uint32_t xpd : 1; - uint32_t slp_mem_dbias : 4; - uint32_t slp_logic_dbias : 4; - uint32_t dbias : 5; +typedef union +{ + struct + { + uint32_t power_det_bypass: 1; + uint32_t reserved0 : 3; + uint32_t lp_dbias_vol : 5; /* Only HP_ACTIVE mode under hp system is valid */ + uint32_t hp_dbias_vol : 5; /* Only HP_ACTIVE mode under hp system is valid */ + uint32_t dbias_sel : 1; /* Only HP_ACTIVE mode under hp system is valid */ + uint32_t dbias_init : 1; /* Only HP_ACTIVE mode under hp system is valid */ + uint32_t slp_mem_xpd : 1; + uint32_t slp_logic_xpd : 1; + uint32_t xpd : 1; + uint32_t slp_mem_dbias : 4; + uint32_t slp_logic_dbias : 4; + uint32_t dbias : 5; }; uint32_t val; } pmu_hp_regulator0_reg_t; -typedef union { - struct { +typedef union +{ + struct + { uint32_t reserved0: 8; uint32_t drv_b : 24; }; uint32_t val; } pmu_hp_regulator1_reg_t; -typedef union { - struct { - uint32_t reserved0: 31; - uint32_t xpd_xtal : 1; +typedef union +{ + struct + { + uint32_t reserved0 : 30; + uint32_t xpd_xtalx2: 1; + uint32_t xpd_xtal : 1; }; uint32_t val; } pmu_hp_xtal_reg_t; -typedef struct pmu_hp_hw_regmap_t{ - pmu_hp_dig_power_reg_t dig_power; - uint32_t icg_func; - uint32_t icg_apb; - pmu_hp_icg_modem_reg_t icg_modem; - pmu_hp_sys_cntl_reg_t syscntl; - pmu_hp_clk_power_reg_t clk_power; - pmu_hp_bias_reg_t bias; - pmu_hp_backup_reg_t backup; - uint32_t backup_clk; - pmu_hp_sysclk_reg_t sysclk; - pmu_hp_regulator0_reg_t regulator0; - pmu_hp_regulator1_reg_t regulator1; - pmu_hp_xtal_reg_t xtal; +typedef struct pmu_hp_hw_regmap_t +{ + pmu_hp_dig_power_reg_t dig_power; + uint32_t icg_func; + uint32_t icg_apb; + pmu_hp_icg_modem_reg_t icg_modem; + pmu_hp_sys_cntl_reg_t syscntl; + pmu_hp_clk_power_reg_t clk_power; + pmu_hp_bias_reg_t bias; + pmu_hp_backup_reg_t backup; + uint32_t backup_clk; + pmu_hp_sysclk_reg_t sysclk; + pmu_hp_regulator0_reg_t regulator0; + pmu_hp_regulator1_reg_t regulator1; + pmu_hp_xtal_reg_t xtal; } pmu_hp_hw_regmap_t; -/** */ -typedef union { - struct { +typedef union +{ + struct + { uint32_t reserved0: 21; uint32_t slp_xpd : 1; - uint32_t xpd : 1; + uint32_t xpd : 1; uint32_t slp_dbias: 4; uint32_t dbias : 5; }; uint32_t val; } pmu_lp_regulator0_reg_t; -typedef union { - struct { +typedef union +{ + struct + { uint32_t reserved0: 28; uint32_t drv_b : 4; }; uint32_t val; } pmu_lp_regulator1_reg_t; -typedef union { - struct { - uint32_t reserved0: 31; - uint32_t xpd_xtal : 1; +typedef union +{ + struct + { + uint32_t reserved0 : 30; + uint32_t xpd_xtalx2: 1; + uint32_t xpd_xtal : 1; }; uint32_t val; } pmu_lp_xtal_reg_t; -typedef union { - struct { - uint32_t reserved0 : 27; - uint32_t bod_source_sel : 1; - uint32_t vddbat_mode : 2; - uint32_t mem_dslp : 1; - uint32_t peri_pd_en : 1; +typedef union +{ + struct + { + uint32_t reserved0 : 23; + uint32_t vdd_io_mode : 4; + uint32_t bod_source_sel: 1; + uint32_t vddbat_mode : 2; + uint32_t mem_dslp : 1; + uint32_t peri_pd_en : 1; }; uint32_t val; } pmu_lp_dig_power_reg_t; -typedef union { - struct { +typedef union +{ + struct + { uint32_t reserved0 : 27; uint32_t xpd_lppll : 1; uint32_t xpd_xtal32k: 1; @@ -241,50 +273,68 @@ typedef union { uint32_t val; } pmu_lp_clk_power_reg_t; -typedef union { - struct { - uint32_t reserved0 : 25; - uint32_t xpd_bias : 1; - uint32_t reserved1 : 4; - uint32_t pd_cur : 1; - uint32_t bias_sleep: 1; +typedef union +{ + struct + { + uint32_t reserved0 : 9; + uint32_t dcdc_ccm_enb : 1; + uint32_t dcdc_clear_rdy : 1; + uint32_t dig_reg_dpcur_bias: 2; + uint32_t dig_reg_dsfmos : 4; + uint32_t dcm_vset : 5; + uint32_t dcm_mode : 2; + uint32_t reserved1 : 1; + uint32_t xpd_bias : 1; + uint32_t reserved2 : 3; + uint32_t discnnt_dig_rtc : 1; + uint32_t pd_cur : 1; + uint32_t bias_sleep : 1; }; uint32_t val; } pmu_lp_bias_reg_t; -typedef struct pmu_lp_hw_regmap_t{ - pmu_lp_regulator0_reg_t regulator0; - pmu_lp_regulator1_reg_t regulator1; - pmu_lp_xtal_reg_t xtal; /* Only LP_SLEEP mode under lp system is valid */ - pmu_lp_dig_power_reg_t dig_power; - pmu_lp_clk_power_reg_t clk_power; - pmu_lp_bias_reg_t bias; /* Only LP_SLEEP mode under lp system is valid */ +typedef struct pmu_lp_hw_regmap_t +{ + pmu_lp_regulator0_reg_t regulator0; + pmu_lp_regulator1_reg_t regulator1; + pmu_lp_xtal_reg_t xtal; /* Only LP_SLEEP mode under lp system, xtal is valid */ + pmu_lp_dig_power_reg_t dig_power; + pmu_lp_clk_power_reg_t clk_power; + pmu_lp_bias_reg_t bias; /* Only LP_SLEEP mode under lp system, bias is valid */ } pmu_lp_hw_regmap_t; - -typedef union { - struct { - uint32_t tie_low_global_bbpll_icg : 1; - uint32_t tie_low_global_xtal_icg : 1; - uint32_t tie_low_i2c_retention : 1; - uint32_t tie_low_xpd_bb_i2c : 1; - uint32_t tie_low_xpd_bbpll_i2c : 1; - uint32_t tie_low_xpd_bbpll : 1; - uint32_t tie_low_xpd_xtal : 1; - uint32_t reserved0 : 18; - uint32_t tie_high_global_bbpll_icg: 1; - uint32_t tie_high_global_xtal_icg : 1; - uint32_t tie_high_i2c_retention : 1; - uint32_t tie_high_xpd_bb_i2c : 1; - uint32_t tie_high_xpd_bbpll_i2c : 1; - uint32_t tie_high_xpd_bbpll : 1; - uint32_t tie_high_xpd_xtal : 1; +typedef union +{ + struct + { + uint32_t tie_low_global_bbpll_icg : 1; + uint32_t tie_low_global_xtal_icg : 1; + uint32_t tie_low_i2c_retention : 1; + uint32_t tie_low_xpd_bb_i2c : 1; + uint32_t tie_low_xpd_bbpll_i2c : 1; + uint32_t tie_low_xpd_bbpll : 1; + uint32_t tie_low_xpd_xtal : 1; + uint32_t tie_low_global_xtalx2_icg : 1; + uint32_t tie_low_xpd_xtalx2 : 1; + uint32_t reserved0 : 14; + uint32_t tie_high_xtalx2 : 1; + uint32_t tie_high_global_xtalx2_icg: 1; + uint32_t tie_high_global_bbpll_icg : 1; + uint32_t tie_high_global_xtal_icg : 1; + uint32_t tie_high_i2c_retention : 1; + uint32_t tie_high_xpd_bb_i2c : 1; + uint32_t tie_high_xpd_bbpll_i2c : 1; + uint32_t tie_high_xpd_bbpll : 1; + uint32_t tie_high_xpd_xtal : 1; }; uint32_t val; } pmu_imm_hp_clk_power_reg_t; -typedef union { - struct { +typedef union +{ + struct + { uint32_t reserved0 : 28; uint32_t update_dig_icg_switch: 1; uint32_t tie_low_icg_slp_sel : 1; @@ -294,32 +344,40 @@ typedef union { uint32_t val; } pmu_imm_sleep_sysclk_reg_t; -typedef union { - struct { +typedef union +{ + struct + { uint32_t reserved0 : 31; uint32_t update_dig_icg_func_en: 1; }; uint32_t val; } pmu_imm_hp_func_icg_reg_t; -typedef union { - struct { +typedef union +{ + struct + { uint32_t reserved0 : 31; uint32_t update_dig_icg_apb_en: 1; }; uint32_t val; } pmu_imm_hp_apb_icg_reg_t; -typedef union { - struct { +typedef union +{ + struct + { uint32_t reserved0 : 31; uint32_t update_dig_icg_modem_en: 1; }; uint32_t val; } pmu_imm_modem_icg_reg_t; -typedef union { - struct { +typedef union +{ + struct + { uint32_t reserved0 : 30; uint32_t tie_low_lp_rootclk_sel : 1; uint32_t tie_high_lp_rootclk_sel: 1; @@ -327,9 +385,13 @@ typedef union { uint32_t val; } pmu_imm_lp_icg_reg_t; -typedef union { - struct { - uint32_t reserved0 : 28; +typedef union +{ + struct + { + uint32_t reserved0 : 26; + uint32_t tie_high_dig_pad_slp_sel: 1; + uint32_t tie_low_dig_pad_slp_sel : 1; uint32_t tie_high_lp_pad_hold_all: 1; uint32_t tie_low_lp_pad_hold_all : 1; uint32_t tie_high_hp_pad_hold_all: 1; @@ -338,8 +400,10 @@ typedef union { uint32_t val; } pmu_imm_pad_hold_all_reg_t; -typedef union { - struct { +typedef union +{ + struct + { uint32_t reserved0 : 30; uint32_t tie_high_i2c_iso_en: 1; uint32_t tie_low_i2c_iso_en : 1; @@ -347,19 +411,22 @@ typedef union { uint32_t val; } pmu_imm_i2c_isolate_reg_t; -typedef struct pmu_imm_hw_regmap_t{ - pmu_imm_hp_clk_power_reg_t clk_power; - pmu_imm_sleep_sysclk_reg_t sleep_sysclk; - pmu_imm_hp_func_icg_reg_t hp_func_icg; - pmu_imm_hp_apb_icg_reg_t hp_apb_icg; - pmu_imm_modem_icg_reg_t modem_icg; - pmu_imm_lp_icg_reg_t lp_icg; - pmu_imm_pad_hold_all_reg_t pad_hold_all; - pmu_imm_i2c_isolate_reg_t i2c_iso; +typedef struct pmu_imm_hw_regmap_t +{ + pmu_imm_hp_clk_power_reg_t clk_power; + pmu_imm_sleep_sysclk_reg_t sleep_sysclk; + pmu_imm_hp_func_icg_reg_t hp_func_icg; + pmu_imm_hp_apb_icg_reg_t hp_apb_icg; + pmu_imm_modem_icg_reg_t modem_icg; + pmu_imm_lp_icg_reg_t lp_icg; + pmu_imm_pad_hold_all_reg_t pad_hold_all; + pmu_imm_i2c_isolate_reg_t i2c_iso; } pmu_imm_hw_regmap_t; -typedef union { - struct { +typedef union +{ + struct + { uint32_t reserved0 : 5; uint32_t powerdown_timer: 9; uint32_t powerup_timer : 9; @@ -368,8 +435,10 @@ typedef union { uint32_t val; } pmu_power_wait_timer0_reg_t; -typedef union { - struct { +typedef union +{ + struct + { uint32_t reserved0 : 9; uint32_t powerdown_timer: 7; uint32_t powerup_timer : 7; @@ -378,23 +447,39 @@ typedef union { uint32_t val; } pmu_power_wait_timer1_reg_t; -typedef union { - struct { +typedef union +{ + struct + { + uint32_t lp_iso_wait_timer : 8; + uint32_t lp_rst_wait_timer : 8; + uint32_t hp_iso_wait_timer : 8; + uint32_t hp_rst_wait_timer : 8; + }; + uint32_t val; +} pmu_power_wait_timer2_reg_t; + +typedef union +{ + struct + { uint32_t force_reset : 1; uint32_t force_iso : 1; uint32_t force_pu : 1; uint32_t force_no_reset: 1; uint32_t force_no_iso : 1; uint32_t force_pd : 1; - uint32_t mask : 5; /* Invalid of lp peripherals */ - uint32_t reserved0 : 16; /* Invalid of lp peripherals */ - uint32_t pd_mask : 5; /* Invalid of lp peripherals */ + uint32_t mask : 5; /* Invalid of lp peripherals */ + uint32_t reserved0 : 16; /* Invalid of lp peripherals */ + uint32_t pd_mask : 5; /* Invalid of lp peripherals */ }; uint32_t val; } pmu_power_domain_cntl_reg_t; -typedef union { - struct { +typedef union +{ + struct + { uint32_t force_hp_mem_iso : 4; uint32_t force_hp_mem_pd : 4; uint32_t reserved0 : 16; @@ -404,8 +489,10 @@ typedef union { uint32_t val; } pmu_power_memory_cntl_reg_t; -typedef union { - struct { +typedef union +{ + struct + { uint32_t mem2_pd_mask: 5; uint32_t mem1_pd_mask: 5; uint32_t mem0_pd_mask: 5; @@ -417,8 +504,10 @@ typedef union { uint32_t val; } pmu_power_memory_mask_reg_t; -typedef union { - struct { +typedef union +{ + struct + { uint32_t force_hp_pad_no_iso_all: 1; uint32_t force_hp_pad_iso_all : 1; uint32_t reserved0 : 30; @@ -426,54 +515,128 @@ typedef union { uint32_t val; } pmu_power_hp_pad_reg_t; -typedef union { - struct { - uint32_t reserved0 : 18; - uint32_t pwr_wait : 11; - uint32_t pwr_sw : 2; - uint32_t pwr_sel_sw: 1; +typedef union +{ + struct + { + uint32_t ldo_rdy : 1; + uint32_t sw_en_xpd : 1; + uint32_t sw_en_through : 1; + uint32_t sw_en_standby : 1; + uint32_t sw_en_power_adjust: 1; + uint32_t sw_en_endet : 1; + uint32_t reserved0 : 16; + uint32_t bypass_ldo_rdy : 1; + uint32_t xpd : 1; + uint32_t through : 1; + uint32_t standby : 1; + uint32_t power_adjust : 5; + uint32_t endet : 1; }; uint32_t val; -} pmu_power_vdd_spi_cntl_reg_t; +} pmu_power_flash_ldo_reg_t; -typedef union { - struct { +typedef union +{ + struct + { + uint32_t reserved0 : 22; + uint32_t ldo_sw_en_tiel : 1; + uint32_t ldo_power_sel : 1; + uint32_t ldo_sw_en_power_sel: 1; + uint32_t ldo_wait_target : 4; + uint32_t ldo_tiel_en : 1; + uint32_t ldo_tiel : 1; + uint32_t ldo_sw_update : 1; + }; + uint32_t val; +} pmu_power_vdd_flash_reg_t; + +typedef union +{ + struct + { + uint32_t ldo_rdy : 1; + uint32_t sw_en_xpd : 1; + uint32_t reserved0 : 1; + uint32_t sw_en_through : 1; + uint32_t sw_en_standby : 1; + uint32_t sw_en_power_adjust: 1; + uint32_t sw_en_endet : 1; + uint32_t reserved1 : 15; + uint32_t bypass_ldo_rdy : 1; + uint32_t xpd : 1; + uint32_t through : 1; + uint32_t standby : 1; + uint32_t power_adjust : 5; + uint32_t endet : 1; + }; + uint32_t val; +} pmu_power_io_ldo_reg_t; + +typedef union +{ + struct + { + uint32_t reserved0 : 23; + uint32_t ldo_power_sel : 1; + uint32_t ldo_sw_en_power_sel: 1; + uint32_t reserved1 : 7; + }; + uint32_t val; +} pmu_power_vdd_io_reg_t; + +typedef union +{ + struct + { uint32_t wait_xtal_stable: 16; uint32_t wait_pll_stable : 16; }; uint32_t val; } pmu_power_clk_wait_cntl_reg_t; -typedef struct pmu_power_hw_regmap_t{ - pmu_power_wait_timer0_reg_t wait_timer0; - pmu_power_wait_timer1_reg_t wait_timer1; - pmu_power_domain_cntl_reg_t hp_pd[5]; - pmu_power_domain_cntl_reg_t lp_peri; - pmu_power_memory_cntl_reg_t mem_cntl; - pmu_power_memory_mask_reg_t mem_mask; - pmu_power_hp_pad_reg_t hp_pad; - pmu_power_vdd_spi_cntl_reg_t vdd_spi; - pmu_power_clk_wait_cntl_reg_t clk_wait; +typedef struct pmu_power_hw_regmap_t +{ + pmu_power_wait_timer0_reg_t wait_timer0; + pmu_power_wait_timer1_reg_t wait_timer1; + pmu_power_wait_timer2_reg_t wait_timer2; + pmu_power_domain_cntl_reg_t hp_pd[5]; /* for TOP, HPAON, HPCPU, HPPERI and HPWIFI domain power controller */ + pmu_power_domain_cntl_reg_t lp_peri; + pmu_power_memory_cntl_reg_t mem_cntl; + pmu_power_memory_mask_reg_t mem_mask; + pmu_power_hp_pad_reg_t hp_pad; + pmu_power_flash_ldo_reg_t flash_ldo[2]; + pmu_power_vdd_flash_reg_t vdd_flash; + pmu_power_io_ldo_reg_t io_ldo; + pmu_power_vdd_io_reg_t vdd_io; + pmu_power_clk_wait_cntl_reg_t clk_wait; } pmu_power_hw_regmap_t; -typedef union { - struct { +typedef union +{ + struct + { uint32_t reserved0: 31; uint32_t sleep_req: 1; }; uint32_t val; } pmu_slp_wakeup_cntl0_reg_t; -typedef union { - struct { +typedef union +{ + struct + { uint32_t sleep_reject_ena: 31; uint32_t slp_reject_en : 1; }; uint32_t val; } pmu_slp_wakeup_cntl1_reg_t; -typedef union { - struct { +typedef union +{ + struct + { uint32_t lp_min_slp_val: 8; uint32_t hp_min_slp_val: 8; uint32_t sleep_prt_sel : 2; @@ -482,16 +645,20 @@ typedef union { uint32_t val; } pmu_slp_wakeup_cntl3_reg_t; -typedef union { - struct { +typedef union +{ + struct + { uint32_t reserved0 : 31; uint32_t slp_reject_cause_clr: 1; }; uint32_t val; } pmu_slp_wakeup_cntl4_reg_t; -typedef union { - struct { +typedef union +{ + struct + { uint32_t modem_wait_target : 20; uint32_t reserved0 : 4; uint32_t lp_ana_wait_target: 8; @@ -499,8 +666,10 @@ typedef union { uint32_t val; } pmu_slp_wakeup_cntl5_reg_t; -typedef union { - struct { +typedef union +{ + struct + { uint32_t soc_wakeup_wait : 20; uint32_t reserved0 : 10; uint32_t soc_wakeup_wait_cfg: 2; @@ -508,37 +677,45 @@ typedef union { uint32_t val; } pmu_slp_wakeup_cntl6_reg_t; -typedef union { - struct { - uint32_t reserved0 : 16; - uint32_t ana_wait_target: 16; +typedef union +{ + struct + { + uint32_t reserved0 : 15; + uint32_t ana_wait_clk_sel: 1; + uint32_t ana_wait_target : 16; }; uint32_t val; } pmu_slp_wakeup_cntl7_reg_t; -typedef struct pmu_wakeup_hw_regmap_t{ - pmu_slp_wakeup_cntl0_reg_t cntl0; - pmu_slp_wakeup_cntl1_reg_t cntl1; - uint32_t cntl2; - pmu_slp_wakeup_cntl3_reg_t cntl3; - pmu_slp_wakeup_cntl4_reg_t cntl4; - pmu_slp_wakeup_cntl5_reg_t cntl5; - pmu_slp_wakeup_cntl6_reg_t cntl6; - pmu_slp_wakeup_cntl7_reg_t cntl7; - uint32_t status0; - uint32_t status1; +typedef struct pmu_wakeup_hw_regmap_t +{ + pmu_slp_wakeup_cntl0_reg_t cntl0; + pmu_slp_wakeup_cntl1_reg_t cntl1; + uint32_t cntl2; + pmu_slp_wakeup_cntl3_reg_t cntl3; + pmu_slp_wakeup_cntl4_reg_t cntl4; + pmu_slp_wakeup_cntl5_reg_t cntl5; + pmu_slp_wakeup_cntl6_reg_t cntl6; + pmu_slp_wakeup_cntl7_reg_t cntl7; + uint32_t status0; + uint32_t status1; } pmu_wakeup_hw_regmap_t; -typedef union { - struct { +typedef union +{ + struct + { uint32_t i2c_por_wait_target: 8; uint32_t reserved0 : 24; }; uint32_t val; } pmu_hp_clk_poweron_reg_t; -typedef union { - struct { +typedef union +{ + struct + { uint32_t modify_icg_cntl_wait: 8; uint32_t switch_icg_cntl_wait: 8; uint32_t reserved0 : 16; @@ -546,17 +723,22 @@ typedef union { uint32_t val; } pmu_hp_clk_cntl_reg_t; -typedef union { - struct { +typedef union +{ + struct + { uint32_t reserved0: 31; uint32_t por_done : 1; }; uint32_t val; } pmu_por_status_reg_t; -typedef union { - struct { - uint32_t reserved0 : 27; +typedef union +{ + struct + { + uint32_t reserved0 : 26; + uint32_t xpd_force_rftx : 1; uint32_t xpd_perif_i2c : 1; uint32_t xpd_rftx_i2c : 1; uint32_t xpd_rfrx_i2c : 1; @@ -566,57 +748,66 @@ typedef union { uint32_t val; } pmu_rf_pwc_reg_t; -typedef union { - struct { - uint32_t ana_vddbat_mode : 2; - uint32_t reserved2 : 29; - uint32_t vddbat_sw_update : 1; +typedef union +{ + struct + { + uint32_t vddbat_mode : 2; + uint32_t reserved0 : 29; + uint32_t vddbat_sw_update: 1; }; uint32_t val; } pmu_vddbat_cfg_reg_t; -typedef union { - struct { +typedef union +{ + struct + { uint32_t reserved0 : 31; uint32_t backup_sysclk_nodiv: 1; }; uint32_t val; } pmu_backup_cfg_reg_t; -typedef union { - struct { - uint32_t reserved0 : 27; - uint32_t lp_exception: 1; - uint32_t sdio_idle: 1; - uint32_t sw : 1; - uint32_t reject : 1; - uint32_t wakeup : 1; +typedef union +{ + struct + { + uint32_t reserved0 : 27; + uint32_t lp_cpu_exc : 1; + uint32_t sdio_idle : 1; + uint32_t sw : 1; + uint32_t soc_sleep_reject: 1; + uint32_t soc_wakeup : 1; }; uint32_t val; } pmu_hp_intr_reg_t; -typedef struct pmu_hp_ext_hw_regmap_t{ - pmu_hp_clk_poweron_reg_t clk_poweron; - pmu_hp_clk_cntl_reg_t clk_cntl; - pmu_por_status_reg_t por_status; - pmu_rf_pwc_reg_t rf_pwc; - pmu_vddbat_cfg_reg_t vddbat_cfg; - pmu_backup_cfg_reg_t backup_cfg; - pmu_hp_intr_reg_t int_raw; - pmu_hp_intr_reg_t int_st; - pmu_hp_intr_reg_t int_ena; - pmu_hp_intr_reg_t int_clr; +typedef struct pmu_hp_ext_hw_regmap_t +{ + pmu_hp_clk_poweron_reg_t clk_poweron; + pmu_hp_clk_cntl_reg_t clk_cntl; + pmu_por_status_reg_t por_status; + pmu_rf_pwc_reg_t rf_pwc; + pmu_vddbat_cfg_reg_t vddbat_cfg; + pmu_backup_cfg_reg_t backup_cfg; + pmu_hp_intr_reg_t int_raw; + pmu_hp_intr_reg_t int_st; + pmu_hp_intr_reg_t int_ena; + pmu_hp_intr_reg_t int_clr; } pmu_hp_ext_hw_regmap_t; -typedef union { - struct { +typedef union +{ + struct + { uint32_t reserved0 : 20; - uint32_t lp_wakeup : 1; + uint32_t lp_cpu_wakeup : 1; uint32_t modem_switch_active_end : 1; uint32_t sleep_switch_active_end : 1; uint32_t sleep_switch_modem_end : 1; uint32_t modem_switch_sleep_end : 1; - uint32_t active_switch_sleep_end : 1; + uint32_t active_swtich_sleep_end : 1; uint32_t modem_switch_active_start: 1; uint32_t sleep_switch_active_start: 1; uint32_t sleep_switch_modem_start : 1; @@ -627,8 +818,10 @@ typedef union { uint32_t val; } pmu_lp_intr_reg_t; -typedef union { - struct { +typedef union +{ + struct + { uint32_t waiti_rdy : 1; uint32_t stall_rdy : 1; uint32_t reserved0 : 16; @@ -643,8 +836,10 @@ typedef union { uint32_t val; } pmu_lp_cpu_pwr0_reg_t; -typedef union { - struct { +typedef union +{ + struct + { uint32_t wakeup_en: 16; uint32_t reserved0: 15; uint32_t sleep_req: 1; @@ -652,21 +847,136 @@ typedef union { uint32_t val; } pmu_lp_cpu_pwr1_reg_t; -typedef struct pmu_lp_ext_hw_regmap_t{ - pmu_lp_intr_reg_t int_raw; - pmu_lp_intr_reg_t int_st; - pmu_lp_intr_reg_t int_ena; - pmu_lp_intr_reg_t int_clr; - pmu_lp_cpu_pwr0_reg_t pwr0; - pmu_lp_cpu_pwr1_reg_t pwr1; +typedef struct pmu_lp_ext_hw_regmap_t +{ + pmu_lp_intr_reg_t int_raw; + pmu_lp_intr_reg_t int_st; + pmu_lp_intr_reg_t int_ena; + pmu_lp_intr_reg_t int_clr; + pmu_lp_cpu_pwr0_reg_t pwr0; + pmu_lp_cpu_pwr1_reg_t pwr1; } pmu_lp_ext_hw_regmap_t; -typedef struct { - volatile struct { - } common; -} pmu_hp_lp_hw_regmap_t; +typedef union +{ + struct + { + uint32_t reserved0 : 30; + uint32_t lp_trigger_hp: 1; + uint32_t hp_trigger_lp: 1; + }; + uint32_t val; +} pmu_hp_lp_cpu_comm_reg_t; -typedef struct pmu_dev_t{ +typedef union +{ + struct + { + uint32_t reserved0 : 31; + uint32_t dig_regulator_en_cal: 1; + }; + uint32_t val; +} pmu_hp_regulator_cfg_reg_t; + +typedef union +{ + struct + { + uint32_t reserved0 : 11; + uint32_t last_st : 7; + uint32_t target_st : 7; + uint32_t current_st: 7; + }; + uint32_t val; +} pmu_main_state_reg_t; + +typedef union +{ + struct + { + uint32_t reserved0: 13; + uint32_t backup_st: 5; + uint32_t lp_pwr_st: 5; + uint32_t hp_pwr_st: 9; + }; + uint32_t val; +} pmu_pwr_state_reg_t; + +typedef union +{ + struct + { + uint32_t stable_xpd_bbpll : 1; + uint32_t stable_xpd_xtal : 1; + uint32_t reserved0 : 13; + uint32_t sysclk_slp_sel : 1; + uint32_t sysclk_sel : 2; + uint32_t sysclk_nodiv : 1; + uint32_t icg_sysclk_en : 1; + uint32_t icg_modem_switch : 1; + uint32_t icg_modem_code : 2; + uint32_t icg_slp_sel : 1; + uint32_t icg_global_xtal : 1; + uint32_t icg_global_pll : 1; + uint32_t ana_i2c_iso_en : 1; + uint32_t ana_i2c_retention: 1; + uint32_t ana_xpd_bb_i2c : 1; + uint32_t ana_xpd_bbpll_i2c: 1; + uint32_t ana_xpd_bbpll : 1; + uint32_t ana_xpd_xtal : 1; + }; + uint32_t val; +} pmu_clk_state0_reg_t; + +typedef union +{ + struct { + uint32_t icg_func_en: 32; + }; + uint32_t val; +} pmu_clk_state1_reg_t; + +typedef union +{ + struct { + uint32_t icg_apb_en: 32; + }; + uint32_t val; +} pmu_clk_state2_reg_t; + +typedef union +{ + struct + { + uint32_t dsfmos_use_por : 1; + uint32_t reserved0 : 21; + uint32_t dcdc_dcm_update : 1; + uint32_t dcdc_pcur_limit : 3; + uint32_t dcdc_bias_cal_done: 1; + uint32_t dcdc_ccm_sw_en : 1; + uint32_t dcdc_vcm_enb : 1; + uint32_t dcdc_ccm_rdy : 1; + uint32_t dcdc_vcm_rdy : 1; + uint32_t dcdc_rdy_clr : 1; + }; + uint32_t val; +} pmu_dcm_ctrl_reg_t; + +typedef union +{ + struct + { + uint32_t sleep_cycles : 16; + uint32_t reserved0 : 5; + uint32_t wait_cycles : 9; + uint32_t sleep_timer_en: 1; + uint32_t force_done : 1; + }; + volatile uint32_t val; +} pmu_touch_pwr_ctrl_reg_t; + +typedef struct pmu_dev_t +{ volatile pmu_hp_hw_regmap_t hp_sys[3]; volatile pmu_lp_hw_regmap_t lp_sys[2]; volatile pmu_imm_hw_regmap_t imm; @@ -675,86 +985,28 @@ typedef struct pmu_dev_t{ volatile pmu_hp_ext_hw_regmap_t hp_ext; volatile pmu_lp_ext_hw_regmap_t lp_ext; - union { - struct { - uint32_t reserved0 : 30; - volatile uint32_t lp_trigger_hp: 1; - volatile uint32_t hp_trigger_lp: 1; + volatile pmu_hp_lp_cpu_comm_reg_t hp_lp_cpu_comm; + volatile pmu_hp_regulator_cfg_reg_t hp_regulator_cfg; + + volatile pmu_main_state_reg_t main_state; + volatile pmu_pwr_state_reg_t pwr_state; + volatile pmu_clk_state0_reg_t clk_state0; + volatile pmu_clk_state1_reg_t clk_state1; + volatile pmu_clk_state2_reg_t clk_state2; + + volatile pmu_dcm_ctrl_reg_t dcm_ctrl; + volatile pmu_touch_pwr_ctrl_reg_t touch_pwr_ctrl; + + uint32_t reserved[143]; + + union + { + struct + { + uint32_t pmu_date : 31; + uint32_t clk_en : 1; }; - volatile uint32_t val; - } hp_lp_cpu_comm; - - union { - struct { - uint32_t reserved0 : 31; - volatile uint32_t dig_regulator_en_cal: 1; - }; - volatile uint32_t val; - } hp_regulator_cfg; - - union { - struct { - uint32_t reserved0 : 11; - volatile uint32_t last_st : 7; - volatile uint32_t target_st : 7; - volatile uint32_t current_st: 7; - }; - volatile uint32_t val; - } main_state; - - union { - struct { - uint32_t reserved0: 13; - volatile uint32_t backup_st: 5; - volatile uint32_t lp_pwr_st: 5; - volatile uint32_t hp_pwr_st: 9; - }; - volatile uint32_t val; - } pwr_state; - - union { - struct { - volatile uint32_t stable_xpd_bbpll : 1; - volatile uint32_t stable_xpd_xtal : 1; - volatile uint32_t reserved0 : 13; - volatile uint32_t sysclk_slp_sel : 1; - volatile uint32_t sysclk_sel : 2; - volatile uint32_t sysclk_nodiv : 1; - volatile uint32_t icg_sysclk_en : 1; - volatile uint32_t icg_modem_switch : 1; - volatile uint32_t icg_modem_code : 2; - volatile uint32_t icg_slp_sel : 1; - volatile uint32_t icg_global_xtal : 1; - volatile uint32_t icg_global_pll : 1; - volatile uint32_t ana_i2c_iso_en : 1; - volatile uint32_t ana_i2c_retention: 1; - volatile uint32_t ana_xpd_bb_i2c : 1; - volatile uint32_t ana_xpd_bbpll_i2c: 1; - volatile uint32_t ana_xpd_bbpll : 1; - volatile uint32_t ana_xpd_xtal : 1; - }; - volatile uint32_t val; - } clk_state0; - - volatile uint32_t clk_state1; - volatile uint32_t clk_state2; - - union { - struct { - uint32_t reserved0 : 31; - volatile uint32_t stable_vdd_spi_pwr_drv: 1; - }; - volatile uint32_t val; - } vdd_spi_status; - - uint32_t reserved[149]; - - union { - struct { - volatile uint32_t pmu_date: 31; - volatile uint32_t clk_en : 1; - }; - volatile uint32_t val; + uint32_t val; } date; } pmu_dev_t; @@ -763,8 +1015,7 @@ extern pmu_dev_t PMU; #ifndef __cplusplus _Static_assert(sizeof(pmu_dev_t) == 0x400, "Invalid size of pmu_dev_t structure"); -// _Static_assert(offsetof(pmu_dev_t, reserved) == (PMU_VDD_SPI_STATUS_REG - DR_REG_PMU_BASE) + 4, "Invalid size of pmu_dev_t structure"); - +_Static_assert(offsetof(pmu_dev_t, reserved) == (PMU_TOUCH_PWR_CTRL_REG - DR_REG_PMU_BASE) + 4, "Invalid size of pmu_dev_t structure"); #endif #ifdef __cplusplus