diff --git a/components/bootloader_support/src/bootloader_console.c b/components/bootloader_support/src/bootloader_console.c
index 1d24f40e27..7fe7f60a08 100644
--- a/components/bootloader_support/src/bootloader_console.c
+++ b/components/bootloader_support/src/bootloader_console.c
@@ -101,8 +101,8 @@ void bootloader_console_init(void)
     esp_rom_uart_set_as_console(ESP_ROM_USB_OTG_NUM);
     esp_rom_install_channel_putc(1, bootloader_console_write_char_usb);
 #if SOC_USB_SERIAL_JTAG_SUPPORTED
-    usb_phy_ll_usb_wrap_pad_enable(&USB_WRAP, true);
-    usb_phy_ll_int_otg_enable(&USB_WRAP);
+    usb_fsls_phy_ll_usb_wrap_pad_enable(&USB_WRAP, true);
+    usb_fsls_phy_ll_int_otg_enable(&USB_WRAP);
 #endif
 }
 #endif //CONFIG_ESP_CONSOLE_USB_CDC
diff --git a/components/driver/usb_serial_jtag/usb_serial_jtag.c b/components/driver/usb_serial_jtag/usb_serial_jtag.c
index 943de1fd9c..901ed61323 100644
--- a/components/driver/usb_serial_jtag/usb_serial_jtag.c
+++ b/components/driver/usb_serial_jtag/usb_serial_jtag.c
@@ -155,7 +155,7 @@ esp_err_t usb_serial_jtag_driver_install(usb_serial_jtag_driver_config_t *usb_se
     usb_serial_jtag_ll_enable_bus_clock(true);
 
     // Configure PHY
-    usb_phy_ll_int_jtag_enable(&USB_SERIAL_JTAG);
+    usb_fsls_phy_ll_int_jtag_enable(&USB_SERIAL_JTAG);
 
     usb_serial_jtag_ll_clr_intsts_mask(USB_SERIAL_JTAG_INTR_SERIAL_IN_EMPTY|
                                          USB_SERIAL_JTAG_INTR_SERIAL_OUT_RECV_PKT);
diff --git a/components/hal/esp32c3/include/hal/usb_fsls_phy_ll.h b/components/hal/esp32c3/include/hal/usb_fsls_phy_ll.h
index 40d4cd1800..b8d98219b0 100644
--- a/components/hal/esp32c3/include/hal/usb_fsls_phy_ll.h
+++ b/components/hal/esp32c3/include/hal/usb_fsls_phy_ll.h
@@ -17,7 +17,7 @@ extern "C" {
  *
  * @param hw Start address of the USB Serial_JTAG registers
  */
-static inline void usb_phy_ll_int_jtag_enable(usb_serial_jtag_dev_t *hw)
+static inline void usb_fsls_phy_ll_int_jtag_enable(usb_serial_jtag_dev_t *hw)
 {
     // USB_Serial_JTAG use internal PHY
     hw->conf0.phy_sel = 0;
diff --git a/components/hal/esp32c6/include/hal/usb_fsls_phy_ll.h b/components/hal/esp32c6/include/hal/usb_fsls_phy_ll.h
index 312ff236cd..4893e96106 100644
--- a/components/hal/esp32c6/include/hal/usb_fsls_phy_ll.h
+++ b/components/hal/esp32c6/include/hal/usb_fsls_phy_ll.h
@@ -17,7 +17,7 @@ extern "C" {
  *
  * @param hw Start address of the USB Serial_JTAG registers
  */
-static inline void usb_phy_ll_int_jtag_enable(usb_serial_jtag_dev_t *hw)
+static inline void usb_fsls_phy_ll_int_jtag_enable(usb_serial_jtag_dev_t *hw)
 {
     // USB_Serial_JTAG use internal PHY
     hw->conf0.phy_sel = 0;
diff --git a/components/hal/esp32h2/include/hal/usb_fsls_phy_ll.h b/components/hal/esp32h2/include/hal/usb_fsls_phy_ll.h
index 9713aae330..271f2fd83b 100644
--- a/components/hal/esp32h2/include/hal/usb_fsls_phy_ll.h
+++ b/components/hal/esp32h2/include/hal/usb_fsls_phy_ll.h
@@ -17,7 +17,7 @@ extern "C" {
  *
  * @param hw Start address of the USB Serial_JTAG registers
  */
-static inline void usb_phy_ll_int_jtag_enable(usb_serial_jtag_dev_t *hw)
+static inline void usb_fsls_phy_ll_int_jtag_enable(usb_serial_jtag_dev_t *hw)
 {
     // USB_Serial_JTAG use internal PHY
     hw->conf0.phy_sel = 0;
diff --git a/components/hal/esp32s2/include/hal/usb_fsls_phy_ll.h b/components/hal/esp32s2/include/hal/usb_fsls_phy_ll.h
index a0b74f6727..e833d0a61c 100644
--- a/components/hal/esp32s2/include/hal/usb_fsls_phy_ll.h
+++ b/components/hal/esp32s2/include/hal/usb_fsls_phy_ll.h
@@ -21,7 +21,7 @@ extern "C" {
  *
  * @param hw Start address of the USB Wrap registers
  */
-static inline void usb_phy_ll_int_otg_enable(usb_wrap_dev_t *hw)
+static inline void usb_fsls_phy_ll_int_otg_enable(usb_wrap_dev_t *hw)
 {
     hw->otg_conf.phy_sel = 0;
 }
@@ -31,7 +31,7 @@ static inline void usb_phy_ll_int_otg_enable(usb_wrap_dev_t *hw)
  *
  * @param hw Start address of the USB Wrap registers
  */
-static inline void usb_phy_ll_ext_otg_enable(usb_wrap_dev_t *hw)
+static inline void usb_fsls_phy_ll_ext_otg_enable(usb_wrap_dev_t *hw)
 {
     //Enable external PHY
     hw->otg_conf.phy_sel = 1;
@@ -46,7 +46,7 @@ static inline void usb_phy_ll_ext_otg_enable(usb_wrap_dev_t *hw)
  * @param dm_pu D- pullup load
  * @param dm_pd D- pulldown load
  */
-static inline void usb_phy_ll_int_load_conf(usb_wrap_dev_t *hw, bool dp_pu, bool dp_pd, bool dm_pu, bool dm_pd)
+static inline void usb_fsls_phy_ll_int_load_conf(usb_wrap_dev_t *hw, bool dp_pu, bool dp_pd, bool dm_pu, bool dm_pd)
 {
     usb_wrap_otg_conf_reg_t conf = hw->otg_conf;
     conf.pad_pull_override = 1;
@@ -62,7 +62,7 @@ static inline void usb_phy_ll_int_load_conf(usb_wrap_dev_t *hw, bool dp_pu, bool
  * @param hw     Start address of the USB Wrap registers
  * @param pad_en Enable the PHY control to D+/D- pad
  */
-static inline void usb_phy_ll_usb_wrap_pad_enable(usb_wrap_dev_t *hw, bool pad_en)
+static inline void usb_fsls_phy_ll_usb_wrap_pad_enable(usb_wrap_dev_t *hw, bool pad_en)
 {
     hw->otg_conf.pad_enable = pad_en;
 }
@@ -73,7 +73,7 @@ static inline void usb_phy_ll_usb_wrap_pad_enable(usb_wrap_dev_t *hw, bool pad_e
  * @param hw Start address of the USB Wrap registers
  * @param en Whether to enable the internal PHY's test mode
  */
-static inline void usb_phy_ll_int_enable_test_mode(usb_wrap_dev_t *hw, bool en)
+static inline void usb_fsls_phy_ll_int_enable_test_mode(usb_wrap_dev_t *hw, bool en)
 {
     if (en) {
         // Clear USB_WRAP_TEST_CONF_REG
@@ -91,7 +91,7 @@ static inline void usb_phy_ll_int_enable_test_mode(usb_wrap_dev_t *hw, bool en)
  * Enable the bus clock for USB Wrap module
  * @param clk_en True if enable the clock of USB Wrap module
  */
-FORCE_INLINE_ATTR void usb_phy_ll_usb_wrap_enable_bus_clock(bool clk_en)
+FORCE_INLINE_ATTR void usb_fsls_phy_ll_usb_wrap_enable_bus_clock(bool clk_en)
 {
     REG_SET_FIELD(DPORT_PERIP_CLK_EN0_REG, DPORT_USB_CLK_EN, clk_en);
 }
@@ -99,7 +99,7 @@ FORCE_INLINE_ATTR void usb_phy_ll_usb_wrap_enable_bus_clock(bool clk_en)
 /**
  * @brief Reset the USB Wrap module
  */
-FORCE_INLINE_ATTR void usb_phy_ll_usb_wrap_reset_register(void)
+FORCE_INLINE_ATTR void usb_fsls_phy_ll_usb_wrap_reset_register(void)
 {
     REG_SET_FIELD(DPORT_PERIP_RST_EN0_REG, DPORT_USB_RST, 1);
     REG_SET_FIELD(DPORT_PERIP_RST_EN0_REG, DPORT_USB_RST, 0);
diff --git a/components/hal/esp32s3/include/hal/usb_fsls_phy_ll.h b/components/hal/esp32s3/include/hal/usb_fsls_phy_ll.h
index 133daf3054..74ec2979e8 100644
--- a/components/hal/esp32s3/include/hal/usb_fsls_phy_ll.h
+++ b/components/hal/esp32s3/include/hal/usb_fsls_phy_ll.h
@@ -23,7 +23,7 @@ extern "C" {
  *
  * @param hw Start address of the USB Wrap registers
  */
-static inline void usb_phy_ll_int_otg_enable(usb_wrap_dev_t *hw)
+static inline void usb_fsls_phy_ll_int_otg_enable(usb_wrap_dev_t *hw)
 {
     // USB_OTG use internal PHY
     hw->otg_conf.phy_sel = 0;
@@ -38,7 +38,7 @@ static inline void usb_phy_ll_int_otg_enable(usb_wrap_dev_t *hw)
  *
  * @param hw Start address of the USB Wrap registers
  */
-static inline void usb_phy_ll_ext_otg_enable(usb_wrap_dev_t *hw)
+static inline void usb_fsls_phy_ll_ext_otg_enable(usb_wrap_dev_t *hw)
 {
     // USB_OTG use external PHY
     hw->otg_conf.phy_sel = 1;
@@ -53,7 +53,7 @@ static inline void usb_phy_ll_ext_otg_enable(usb_wrap_dev_t *hw)
  *
  * @param hw Start address of the USB Serial_JTAG registers
  */
-static inline void usb_phy_ll_int_jtag_enable(usb_serial_jtag_dev_t *hw)
+static inline void usb_fsls_phy_ll_int_jtag_enable(usb_serial_jtag_dev_t *hw)
 {
     // USB_Serial_JTAG use internal PHY
     hw->conf0.phy_sel = 0;
@@ -74,7 +74,7 @@ static inline void usb_phy_ll_int_jtag_enable(usb_serial_jtag_dev_t *hw)
  *
  * @param hw Start address of the USB Serial_JTAG registers
  */
-static inline void usb_phy_ll_ext_jtag_enable(usb_serial_jtag_dev_t *hw)
+static inline void usb_fsls_phy_ll_ext_jtag_enable(usb_serial_jtag_dev_t *hw)
 {
     // USB_Serial_JTAG use external PHY
     hw->conf0.phy_sel = 1;
@@ -93,7 +93,7 @@ static inline void usb_phy_ll_ext_jtag_enable(usb_serial_jtag_dev_t *hw)
  * @param dm_pu D- pullup load
  * @param dm_pd D- pulldown load
  */
-static inline void usb_phy_ll_int_load_conf(usb_wrap_dev_t *hw, bool dp_pu, bool dp_pd, bool dm_pu, bool dm_pd)
+static inline void usb_fsls_phy_ll_int_load_conf(usb_wrap_dev_t *hw, bool dp_pu, bool dp_pd, bool dm_pu, bool dm_pd)
 {
     usb_wrap_otg_conf_reg_t conf = hw->otg_conf;
     conf.pad_pull_override = 1;
@@ -109,7 +109,7 @@ static inline void usb_phy_ll_int_load_conf(usb_wrap_dev_t *hw, bool dp_pu, bool
  * @param hw     Start address of the USB Wrap registers
  * @param pad_en Enable the PHY control to D+/D- pad
  */
-static inline void usb_phy_ll_usb_wrap_pad_enable(usb_wrap_dev_t *hw, bool pad_en)
+static inline void usb_fsls_phy_ll_usb_wrap_pad_enable(usb_wrap_dev_t *hw, bool pad_en)
 {
     hw->otg_conf.pad_enable = pad_en;
 }
@@ -120,7 +120,7 @@ static inline void usb_phy_ll_usb_wrap_pad_enable(usb_wrap_dev_t *hw, bool pad_e
  * @param hw Start address of the USB Wrap registers
  * @param en Whether to enable the internal PHY's test mode
  */
-static inline void usb_phy_ll_int_enable_test_mode(usb_wrap_dev_t *hw, bool en)
+static inline void usb_fsls_phy_ll_int_enable_test_mode(usb_wrap_dev_t *hw, bool en)
 {
     if (en) {
         // Clear USB_WRAP_TEST_CONF_REG
@@ -138,7 +138,7 @@ static inline void usb_phy_ll_int_enable_test_mode(usb_wrap_dev_t *hw, bool en)
  * Enable the bus clock for USB Wrap module
  * @param clk_en True if enable the clock of USB Wrap module
  */
-FORCE_INLINE_ATTR void usb_phy_ll_usb_wrap_enable_bus_clock(bool clk_en)
+FORCE_INLINE_ATTR void usb_fsls_phy_ll_usb_wrap_enable_bus_clock(bool clk_en)
 {
     SYSTEM.perip_clk_en0.usb_clk_en = clk_en;
 }
@@ -146,7 +146,7 @@ FORCE_INLINE_ATTR void usb_phy_ll_usb_wrap_enable_bus_clock(bool clk_en)
 /**
  * @brief Reset the USB Wrap module
  */
-FORCE_INLINE_ATTR void usb_phy_ll_usb_wrap_reset_register(void)
+FORCE_INLINE_ATTR void usb_fsls_phy_ll_usb_wrap_reset_register(void)
 {
     SYSTEM.perip_rst_en0.usb_rst = 1;
     SYSTEM.perip_rst_en0.usb_rst = 0;
diff --git a/components/hal/include/hal/usb_fsls_phy_hal.h b/components/hal/include/hal/usb_fsls_phy_hal.h
index b245d9ff4b..72e9551c45 100644
--- a/components/hal/include/hal/usb_fsls_phy_hal.h
+++ b/components/hal/include/hal/usb_fsls_phy_hal.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -27,14 +27,14 @@ typedef struct {
 #if SOC_USB_SERIAL_JTAG_SUPPORTED
     usb_serial_jtag_dev_t *jtag_dev;            /**< Pointer to base address of USB Serial JTAG registers */
 #endif
-} usb_phy_hal_context_t;
+} usb_fsls_phy_hal_context_t;
 
 /**
  * @brief Init the USB PHY hal. This function should be called first before other hal layer function is called
  *
  * @param hal Context of the HAL layer
  */
-void usb_phy_hal_init(usb_phy_hal_context_t *hal);
+void usb_fsls_phy_hal_init(usb_fsls_phy_hal_context_t *hal);
 
 /**
  * @brief Configure internal/external PHY for USB_OTG
@@ -42,7 +42,7 @@ void usb_phy_hal_init(usb_phy_hal_context_t *hal);
  * @param hal Context of the HAL layer
  * @param phy_target USB PHY target
  */
-void usb_phy_hal_otg_conf(usb_phy_hal_context_t *hal, usb_phy_target_t phy_target);
+void usb_fsls_phy_hal_otg_conf(usb_fsls_phy_hal_context_t *hal, usb_phy_target_t phy_target);
 
 #if SOC_USB_SERIAL_JTAG_SUPPORTED
 /**
@@ -51,7 +51,7 @@ void usb_phy_hal_otg_conf(usb_phy_hal_context_t *hal, usb_phy_target_t phy_targe
  * @param hal Context of the HAL layer
  * @param phy_target USB PHY target
  */
-void usb_phy_hal_jtag_conf(usb_phy_hal_context_t *hal, usb_phy_target_t phy_target);
+void usb_fsls_phy_hal_jtag_conf(usb_fsls_phy_hal_context_t *hal, usb_phy_target_t phy_target);
 #endif
 
 /**
@@ -59,7 +59,7 @@ void usb_phy_hal_jtag_conf(usb_phy_hal_context_t *hal, usb_phy_target_t phy_targ
  *
  * @param hal Context of the HAL layer
  */
-void usb_phy_hal_int_load_conf_host(usb_phy_hal_context_t *hal);
+void usb_fsls_phy_hal_int_load_conf_host(usb_fsls_phy_hal_context_t *hal);
 
 /**
  * @brief Configure pullup/pulldown loads for the D+/D- as a device
@@ -67,7 +67,7 @@ void usb_phy_hal_int_load_conf_host(usb_phy_hal_context_t *hal);
  * @param hal Context of the HAL layer
  * @param speed USB speed
  */
-void usb_phy_hal_int_load_conf_dev(usb_phy_hal_context_t *hal, usb_phy_speed_t speed);
+void usb_fsls_phy_hal_int_load_conf_dev(usb_fsls_phy_hal_context_t *hal, usb_phy_speed_t speed);
 
 /**
  * @brief Enable/Disable test mode for internal PHY to mimick host-device disconnection
@@ -75,7 +75,7 @@ void usb_phy_hal_int_load_conf_dev(usb_phy_hal_context_t *hal, usb_phy_speed_t s
  * @param hal Context of the HAL layer
  * @param disconn Whether to disconnect
  */
-void usb_phy_hal_int_mimick_disconn(usb_phy_hal_context_t *hal, bool disconn);
+void usb_fsls_phy_hal_int_mimick_disconn(usb_fsls_phy_hal_context_t *hal, bool disconn);
 
 #ifdef __cplusplus
 }
diff --git a/components/hal/usb_fsls_phy_hal.c b/components/hal/usb_fsls_phy_hal.c
index 796e01a862..7bceb8c364 100644
--- a/components/hal/usb_fsls_phy_hal.c
+++ b/components/hal/usb_fsls_phy_hal.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -7,7 +7,7 @@
 #include "hal/usb_fsls_phy_ll.h"
 #include "hal/usb_fsls_phy_hal.h"
 
-void usb_phy_hal_init(usb_phy_hal_context_t *hal)
+void usb_fsls_phy_hal_init(usb_fsls_phy_hal_context_t *hal)
 {
     hal->wrap_dev = &USB_WRAP;
 #if SOC_USB_SERIAL_JTAG_SUPPORTED
@@ -15,50 +15,50 @@ void usb_phy_hal_init(usb_phy_hal_context_t *hal)
 #endif
 }
 
-void usb_phy_hal_otg_conf(usb_phy_hal_context_t *hal, usb_phy_target_t phy_target)
+void usb_fsls_phy_hal_otg_conf(usb_fsls_phy_hal_context_t *hal, usb_phy_target_t phy_target)
 {
     if (phy_target == USB_PHY_TARGET_EXT) {
-        usb_phy_ll_ext_otg_enable(hal->wrap_dev);
+        usb_fsls_phy_ll_ext_otg_enable(hal->wrap_dev);
     } else if (phy_target == USB_PHY_TARGET_INT) {
-        usb_phy_ll_usb_wrap_pad_enable(hal->wrap_dev, true);
-        usb_phy_ll_int_otg_enable(hal->wrap_dev);
+        usb_fsls_phy_ll_usb_wrap_pad_enable(hal->wrap_dev, true);
+        usb_fsls_phy_ll_int_otg_enable(hal->wrap_dev);
     }
 }
 
 #if SOC_USB_SERIAL_JTAG_SUPPORTED
-void usb_phy_hal_jtag_conf(usb_phy_hal_context_t *hal, usb_phy_target_t phy_target)
+void usb_fsls_phy_hal_jtag_conf(usb_fsls_phy_hal_context_t *hal, usb_phy_target_t phy_target)
 {
     if (phy_target == USB_PHY_TARGET_EXT) {
-        usb_phy_ll_ext_jtag_enable(hal->jtag_dev);
+        usb_fsls_phy_ll_ext_jtag_enable(hal->jtag_dev);
     } else if (phy_target == USB_PHY_TARGET_INT) {
-        usb_phy_ll_int_jtag_enable(hal->jtag_dev);
+        usb_fsls_phy_ll_int_jtag_enable(hal->jtag_dev);
     }
 }
 #endif
 
-void usb_phy_hal_int_load_conf_host(usb_phy_hal_context_t *hal)
+void usb_fsls_phy_hal_int_load_conf_host(usb_fsls_phy_hal_context_t *hal)
 {
     // HOST - upstream: dp_pd = 1, dm_pd = 1
-    usb_phy_ll_int_load_conf(hal->wrap_dev, false, true, false, true);
+    usb_fsls_phy_ll_int_load_conf(hal->wrap_dev, false, true, false, true);
 }
 
-void usb_phy_hal_int_load_conf_dev(usb_phy_hal_context_t *hal, usb_phy_speed_t speed)
+void usb_fsls_phy_hal_int_load_conf_dev(usb_fsls_phy_hal_context_t *hal, usb_phy_speed_t speed)
 {
     // DEVICE - downstream
     if (speed == USB_PHY_SPEED_LOW) {
         // LS: dm_pu = 1
-        usb_phy_ll_int_load_conf(hal->wrap_dev, false, false, true, false);
+        usb_fsls_phy_ll_int_load_conf(hal->wrap_dev, false, false, true, false);
     } else {
         // FS: dp_pu = 1
-        usb_phy_ll_int_load_conf(hal->wrap_dev, true, false, false, false);
+        usb_fsls_phy_ll_int_load_conf(hal->wrap_dev, true, false, false, false);
     }
 }
 
-void usb_phy_hal_int_mimick_disconn(usb_phy_hal_context_t *hal, bool disconn)
+void usb_fsls_phy_hal_int_mimick_disconn(usb_fsls_phy_hal_context_t *hal, bool disconn)
 {
     /*
     We mimick a disconnect by enabling the internal PHY's test mode, then forcing the output_enable to HIGH. This will:
     A HIGH output_enable will cause the received VP and VM to be zero, thus mimicking a disconnection.
     */
-    usb_phy_ll_int_enable_test_mode(hal->wrap_dev, disconn);
+    usb_fsls_phy_ll_int_enable_test_mode(hal->wrap_dev, disconn);
 }
diff --git a/components/soc/esp32s2/include/soc/usb_wrap_struct.h b/components/soc/esp32s2/include/soc/usb_wrap_struct.h
index 1b89179774..0a01ebb0e1 100644
--- a/components/soc/esp32s2/include/soc/usb_wrap_struct.h
+++ b/components/soc/esp32s2/include/soc/usb_wrap_struct.h
@@ -153,7 +153,7 @@ typedef union {
          *  USB D- rx value in test.
          */
         uint32_t test_rx_dm:1;
-        uint32_t reserved:25;
+        uint32_t reserved_7:25;
     };
     uint32_t val;
 } usb_wrap_test_conf_reg_t;
diff --git a/components/soc/esp32s3/include/soc/usb_wrap_struct.h b/components/soc/esp32s3/include/soc/usb_wrap_struct.h
index ac0b871034..71013fe25f 100644
--- a/components/soc/esp32s3/include/soc/usb_wrap_struct.h
+++ b/components/soc/esp32s3/include/soc/usb_wrap_struct.h
@@ -154,7 +154,7 @@ typedef union {
          *  USB D- rx value in test.
          */
         uint32_t test_rx_dm:1;
-        uint32_t reserved7:25;
+        uint32_t reserved_7:25;
     };
     uint32_t val;
 } usb_wrap_test_conf_reg_t;
diff --git a/components/usb/usb_phy.c b/components/usb/usb_phy.c
index ecfa2d5e89..991bc4803d 100644
--- a/components/usb/usb_phy.c
+++ b/components/usb/usb_phy.c
@@ -33,7 +33,7 @@ struct phy_context_t {
     usb_otg_mode_t otg_mode;                      /**< USB OTG mode */
     usb_phy_speed_t otg_speed;                    /**< USB speed */
     usb_phy_ext_io_conf_t *iopins;                /**< external PHY I/O pins */
-    usb_phy_hal_context_t hal_context;            /**< USB_PHY hal context */
+    usb_fsls_phy_hal_context_t hal_context;            /**< USB_PHY hal context */
 };
 
 typedef struct {
@@ -120,7 +120,7 @@ esp_err_t usb_phy_otg_set_mode(usb_phy_handle_t handle, usb_otg_mode_t mode)
         esp_rom_gpio_connect_in_signal(GPIO_MATRIX_CONST_ONE_INPUT, USB_OTG_VBUSVALID_IN_IDX, false);  // receiving a valid Vbus from host
         esp_rom_gpio_connect_in_signal(GPIO_MATRIX_CONST_ONE_INPUT, USB_OTG_AVALID_IN_IDX, false);     // HIGH to force USB host mode
         if (handle->target == USB_PHY_TARGET_INT) {
-            usb_phy_hal_int_load_conf_host(&(handle->hal_context));
+            usb_fsls_phy_hal_int_load_conf_host(&(handle->hal_context));
         }
     } else if (mode == USB_OTG_MODE_DEVICE) {
         esp_rom_gpio_connect_in_signal(GPIO_MATRIX_CONST_ONE_INPUT, USB_OTG_IDDIG_IN_IDX, false);      // connected connector is mini-B side
@@ -141,7 +141,7 @@ esp_err_t usb_phy_otg_dev_set_speed(usb_phy_handle_t handle, usb_phy_speed_t spe
                         USBPHY_TAG, "set speed not supported");
 
     handle->otg_speed = speed;
-    usb_phy_hal_int_load_conf_dev(&(handle->hal_context), speed);
+    usb_fsls_phy_hal_int_load_conf_dev(&(handle->hal_context), speed);
     return ESP_OK;
 }
 
@@ -157,7 +157,7 @@ esp_err_t usb_phy_action(usb_phy_handle_t handle, usb_phy_action_t action)
     switch (action) {
     case USB_PHY_ACTION_HOST_ALLOW_CONN:
         if (handle->target == USB_PHY_TARGET_INT) {
-            usb_phy_hal_int_mimick_disconn(&(handle->hal_context), false);
+            usb_fsls_phy_hal_int_mimick_disconn(&(handle->hal_context), false);
         } else {
             if (!handle->iopins) {
                 ret = ESP_FAIL;
@@ -174,7 +174,7 @@ esp_err_t usb_phy_action(usb_phy_handle_t handle, usb_phy_action_t action)
 
     case USB_PHY_ACTION_HOST_FORCE_DISCONN:
         if (handle->target == USB_PHY_TARGET_INT) {
-            usb_phy_hal_int_mimick_disconn(&(handle->hal_context), true);
+            usb_fsls_phy_hal_int_mimick_disconn(&(handle->hal_context), true);
         } else {
             /*
             Disable connections on the external PHY by connecting the VP and VM signals to the constant LOW signal.
@@ -214,8 +214,8 @@ static esp_err_t usb_phy_install(void)
         portEXIT_CRITICAL(&phy_spinlock);
         goto cleanup;
     }
-    usb_phy_ll_usb_wrap_enable_bus_clock(true);
-    usb_phy_ll_usb_wrap_reset_register();
+    usb_fsls_phy_ll_usb_wrap_enable_bus_clock(true);
+    usb_fsls_phy_ll_usb_wrap_reset_register();
     // Enable USB peripheral and reset the register
     portEXIT_CRITICAL(&phy_spinlock);
     return ESP_OK;
@@ -255,13 +255,13 @@ esp_err_t usb_new_phy(const usb_phy_config_t *config, usb_phy_handle_t *handle_r
     phy_context->controller = config->controller;
     phy_context->status = USB_PHY_STATUS_IN_USE;
 
-    usb_phy_hal_init(&(phy_context->hal_context));
+    usb_fsls_phy_hal_init(&(phy_context->hal_context));
     if (config->controller == USB_PHY_CTRL_OTG) {
-        usb_phy_hal_otg_conf(&(phy_context->hal_context), config->target == USB_PHY_TARGET_EXT);
+        usb_fsls_phy_hal_otg_conf(&(phy_context->hal_context), config->target == USB_PHY_TARGET_EXT);
     }
 #if SOC_USB_SERIAL_JTAG_SUPPORTED
     else if (config->controller == USB_PHY_CTRL_SERIAL_JTAG) {
-        usb_phy_hal_jtag_conf(&(phy_context->hal_context), config->target == USB_PHY_TARGET_EXT);
+        usb_fsls_phy_hal_jtag_conf(&(phy_context->hal_context), config->target == USB_PHY_TARGET_EXT);
         phy_context->otg_mode = USB_OTG_MODE_DEVICE;
         phy_context->otg_speed = USB_PHY_SPEED_FULL;
     }
@@ -308,7 +308,7 @@ static void phy_uninstall(void)
         p_phy_ctrl_obj_free = p_phy_ctrl_obj;
         p_phy_ctrl_obj = NULL;
         // Disable USB peripheral without reset the module
-        usb_phy_ll_usb_wrap_enable_bus_clock(false);
+        usb_fsls_phy_ll_usb_wrap_enable_bus_clock(false);
     }
     portEXIT_CRITICAL(&phy_spinlock);
     free(p_phy_ctrl_obj_free);
@@ -324,8 +324,8 @@ esp_err_t usb_del_phy(usb_phy_handle_t handle)
         p_phy_ctrl_obj->external_phy = NULL;
     } else {
         // Clear pullup and pulldown loads on D+ / D-, and disable the pads
-        usb_phy_ll_int_load_conf(handle->hal_context.wrap_dev, false, false, false, false);
-        usb_phy_ll_usb_wrap_pad_enable(handle->hal_context.wrap_dev, false);
+        usb_fsls_phy_ll_int_load_conf(handle->hal_context.wrap_dev, false, false, false, false);
+        usb_fsls_phy_ll_usb_wrap_pad_enable(handle->hal_context.wrap_dev, false);
         p_phy_ctrl_obj->internal_phy = NULL;
     }
     portEXIT_CRITICAL(&phy_spinlock);