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sleep: fix sleep time inaccurate bug when select 8MD256 as rtc slow clock on ESP32

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Related to: https://github.com/espressif/esp-idf/issues/6687
This commit is contained in:
cje
2022-08-30 11:32:07 +08:00
committed by Xiao Xufeng
parent dc4c9c087f
commit d8fc054115
3 changed files with 7 additions and 2 deletions
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2
components/esp_hw_support/port/esp32/rtc_sleep.c
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@ -183,7 +183,6 @@ void rtc_sleep_init(rtc_sleep_config_t cfg)
CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BB_I2C_FORCE_PU);
} else {
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_PD_EN);
REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN, 0);
}
REG_SET_FIELD(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_XTL_FORCE_PU, cfg.xtal_fpu);
@ -202,6 +201,7 @@ void rtc_sleep_init(rtc_sleep_config_t cfg)
REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DBIAS_WAK, cfg.rtc_dbias_wak);
REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, cfg.dig_dbias_wak);
REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_SLP, cfg.dig_dbias_slp);
REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN, cfg.dbg_atten_slp);
}
void rtc_sleep_low_init(uint32_t slowclk_period)

6
components/soc/esp32/include/soc/rtc.h
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@ -514,6 +514,7 @@ typedef struct rtc_sleep_config_s {
uint32_t lslp_meminf_pd : 1; //!< remove all peripheral force power up flags
uint32_t vddsdio_pd_en : 1; //!< power down VDDSDIO regulator
uint32_t xtal_fpu : 1; //!< keep main XTAL powered up in sleep
uint32_t dbg_atten_slp : 2; //!< voltage parameter
} rtc_sleep_config_t;
/**
@ -547,7 +548,10 @@ typedef struct rtc_sleep_config_s {
: RTC_CNTL_DBIAS_0V90, \
.lslp_meminf_pd = 1, \
.vddsdio_pd_en = ((sleep_flags) & RTC_SLEEP_PD_VDDSDIO) ? 1 : 0, \
.xtal_fpu = ((sleep_flags) & RTC_SLEEP_PD_XTAL) ? 0 : 1 \
.xtal_fpu = ((sleep_flags) & RTC_SLEEP_PD_XTAL) ? 0 : 1, \
.dbg_atten_slp = !is_dslp(sleep_flags) ? RTC_CNTL_DBG_ATTEN_NODROP \
: !((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? RTC_CNTL_DBG_ATTEN_NODROP \
: RTC_CNTL_DBG_ATTEN_DEFAULT, \
};
#define RTC_SLEEP_PD_DIG BIT(0) //!< Deep sleep (power down digital domain)

1
components/soc/esp32/include/soc/rtc_cntl_reg.h
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@ -1070,6 +1070,7 @@
#define RTC_CNTL_DBG_ATTEN_V 0x3
#define RTC_CNTL_DBG_ATTEN_S 24
#define RTC_CNTL_DBG_ATTEN_DEFAULT 3
#define RTC_CNTL_DBG_ATTEN_NODROP 0
#define RTC_CNTL_REG (DR_REG_RTCCNTL_BASE + 0x7c)
/* RTC_CNTL_FORCE_PU : R/W ;bitpos:[31] ;default: 1'd1 ; */
/*description: RTC_REG force power up*/