mirror of
https://github.com/espressif/esp-idf.git
synced 2025-11-03 08:31:44 +01:00
feat(etm): add driver support for esp32c61
This commit is contained in:
morris
@@ -131,6 +131,10 @@ config SOC_REG_I2C_SUPPORTED
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bool
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default y
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config SOC_ETM_SUPPORTED
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bool
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default y
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config SOC_PAU_SUPPORTED
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bool
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default y
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@@ -267,6 +271,10 @@ config SOC_GDMA_PAIRS_PER_GROUP_MAX
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int
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default 2
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config SOC_GDMA_SUPPORT_ETM
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bool
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default y
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config SOC_GDMA_SUPPORT_SLEEP_RETENTION
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bool
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default y
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@@ -279,6 +287,10 @@ config SOC_ETM_CHANNELS_PER_GROUP
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int
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default 50
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config SOC_ETM_SUPPORT_SLEEP_RETENTION
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bool
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default y
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config SOC_GPIO_PORT
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int
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default 1
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@@ -295,6 +307,10 @@ config SOC_GPIO_SUPPORT_PIN_HYS_FILTER
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bool
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default y
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config SOC_GPIO_SUPPORT_ETM
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bool
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default y
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config SOC_GPIO_SUPPORT_RTC_INDEPENDENT
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bool
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default y
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@@ -655,6 +671,10 @@ config SOC_SYSTIMER_ALARM_MISS_COMPENSATE
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bool
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default y
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config SOC_SYSTIMER_SUPPORT_ETM
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bool
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default y
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config SOC_LP_TIMER_BIT_WIDTH_LO
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int
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default 32
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@@ -691,6 +711,10 @@ config SOC_TIMER_SUPPORT_SLEEP_RETENTION
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bool
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default y
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config SOC_TIMER_SUPPORT_ETM
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bool
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default y
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config SOC_MWDT_SUPPORT_SLEEP_RETENTION
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bool
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default y
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@@ -39,7 +39,7 @@ typedef union {
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*/
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uint32_t xpd_comp_0:1;
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/** mode_comp_0 : R/W; bitpos: [1]; default: 0;
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* Configures the reference voltage for analog PAD voltage comparater.. \\
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* Configures the reference voltage for analog PAD voltage comparator.. \\
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* 0: Reference voltage is the internal reference voltage, meanwhile GPIO8 PAD can be
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* used as a regular GPIO\\
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* 1: Reference voltage is the voltage on the GPIO8 PAD\\
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@@ -128,6 +128,15 @@ typedef union {
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uint32_t val;
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} gpio_ext_etm_event_chn_cfg_reg_t;
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/** Type of etm_task_pn_cfg register
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* GPIO selection register for ETM.
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* This register is an abstraction of the following registers:
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* gpio_ext_etm_task_p0_cfg_reg_t ~ gpio_ext_etm_task_p4_cfg_reg_t
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*/
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typedef union {
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uint32_t val;
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} gpio_ext_etm_task_pn_cfg_reg_t;
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/** Type of etm_task_p0_cfg register
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* GPIO selection register 0 for ETM
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*/
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@@ -659,6 +668,11 @@ typedef union {
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uint32_t val;
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} gpio_ext_version_reg_t;
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typedef struct gpio_etm_dev_t {
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volatile gpio_ext_etm_event_chn_cfg_reg_t etm_event_chn_cfg[8];
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uint32_t reserved_138[8];
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volatile gpio_ext_etm_task_pn_cfg_reg_t etm_task_pn_cfg[5];
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} gpio_etm_dev_t;
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typedef struct {
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volatile gpio_ext_clock_gate_reg_t clock_gate;
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@@ -666,13 +680,7 @@ typedef struct {
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volatile gpio_ext_pad_comp_config_0_reg_t pad_comp_config_0;
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volatile gpio_ext_pad_comp_filter_0_reg_t pad_comp_filter_0;
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uint32_t reserved_060[46];
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volatile gpio_ext_etm_event_chn_cfg_reg_t etm_event_chn_cfg[8];
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uint32_t reserved_138[8];
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volatile gpio_ext_etm_task_p0_cfg_reg_t etm_task_p0_cfg;
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volatile gpio_ext_etm_task_p1_cfg_reg_t etm_task_p1_cfg;
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volatile gpio_ext_etm_task_p2_cfg_reg_t etm_task_p2_cfg;
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volatile gpio_ext_etm_task_p3_cfg_reg_t etm_task_p3_cfg;
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volatile gpio_ext_etm_task_p4_cfg_reg_t etm_task_p4_cfg;
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volatile gpio_etm_dev_t etm;
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uint32_t reserved_16c[25];
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volatile gpio_ext_int_raw_reg_t int_raw;
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volatile gpio_ext_int_st_reg_t int_st;
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@@ -683,6 +691,8 @@ typedef struct {
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volatile gpio_ext_version_reg_t version;
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} gpio_ext_dev_t;
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extern gpio_etm_dev_t GPIO_ETM;
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extern gpio_ext_dev_t GPIO_EXT;
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#ifndef __cplusplus
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_Static_assert(sizeof(gpio_ext_dev_t) == 0x200, "Invalid size of gpio_ext_dev_t structure");
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@@ -56,7 +56,7 @@
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// \#define SOC_RNG_SUPPORTED 1 //TODO: [ESP32C61] IDF-9236
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#define SOC_MODEM_CLOCK_SUPPORTED 1
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#define SOC_REG_I2C_SUPPORTED 1
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// \#define SOC_ETM_SUPPORTED 0
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#define SOC_ETM_SUPPORTED 1
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// \#define SOC_SDIO_SLAVE_SUPPORTED 0
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#define SOC_PAU_SUPPORTED 1
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#define SOC_LIGHT_SLEEP_SUPPORTED 1
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@@ -148,13 +148,13 @@
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#define SOC_AHB_GDMA_VERSION 2U
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#define SOC_GDMA_NUM_GROUPS_MAX 1U
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#define SOC_GDMA_PAIRS_PER_GROUP_MAX 2
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// \#define SOC_GDMA_SUPPORT_ETM 1 // Support ETM submodule TODO: IDF-9964
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#define SOC_GDMA_SUPPORT_ETM 1 // Support ETM submodule
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#define SOC_GDMA_SUPPORT_SLEEP_RETENTION 1
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/*-------------------------- ETM CAPS --------------------------------------*/
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#define SOC_ETM_GROUPS 1U // Number of ETM groups
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#define SOC_ETM_CHANNELS_PER_GROUP 50 // Number of ETM channels in the group
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// #define SOC_ETM_SUPPORT_SLEEP_RETENTION 1 // Support sleep retention
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#define SOC_ETM_SUPPORT_SLEEP_RETENTION 1 // Support sleep retention
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/*-------------------------- GPIO CAPS ---------------------------------------*/
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// ESP32-C61 has 1 GPIO peripheral
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@@ -164,7 +164,7 @@
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#define SOC_GPIO_SUPPORT_PIN_HYS_FILTER 1
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// GPIO peripheral has the ETM extension
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// \#define SOC_GPIO_SUPPORT_ETM 1 //TODO: [ESP32C61] IDF-9318
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#define SOC_GPIO_SUPPORT_ETM 1
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// Target has the full LP IO subsystem
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// On ESP32-C61, Digital IOs have their own registers to control pullup/down capability, independent of LP registers.
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@@ -340,7 +340,7 @@
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#define SOC_SYSTIMER_SUPPORT_RC_FAST 1 // Systimer can use RC_FAST clock source
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#define SOC_SYSTIMER_INT_LEVEL 1 // Systimer peripheral uses level interrupt
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#define SOC_SYSTIMER_ALARM_MISS_COMPENSATE 1 // Systimer peripheral can generate interrupt immediately if t(target) > t(current)
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// #define SOC_SYSTIMER_SUPPORT_ETM 1 // Systimer comparator can generate ETM event
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#define SOC_SYSTIMER_SUPPORT_ETM 1 // Systimer comparator can generate ETM event
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/*-------------------------- LP_TIMER CAPS ----------------------------------*/
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#define SOC_LP_TIMER_BIT_WIDTH_LO 32 // Bit width of lp_timer low part
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@@ -354,7 +354,7 @@
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#define SOC_TIMER_GROUP_SUPPORT_XTAL (1)
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#define SOC_TIMER_GROUP_SUPPORT_RC_FAST (1)
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#define SOC_TIMER_SUPPORT_SLEEP_RETENTION (1)
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// #define SOC_TIMER_SUPPORT_ETM (1)
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#define SOC_TIMER_SUPPORT_ETM (1)
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/*--------------------------- WATCHDOG CAPS ---------------------------------------*/
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// #define SOC_MWDT_SUPPORT_XTAL (1)
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@@ -3161,113 +3161,17 @@ typedef union {
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} soc_etm_date_reg_t;
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typedef struct {
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typedef struct soc_etm_dev_t {
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volatile soc_etm_ch_ena_ad0_reg_t ch_ena_ad0;
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volatile soc_etm_ch_ena_ad0_set_reg_t ch_ena_ad0_set;
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volatile soc_etm_ch_ena_ad0_clr_reg_t ch_ena_ad0_clr;
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volatile soc_etm_ch_ena_ad1_reg_t ch_ena_ad1;
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volatile soc_etm_ch_ena_ad1_set_reg_t ch_ena_ad1_set;
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volatile soc_etm_ch_ena_ad1_clr_reg_t ch_ena_ad1_clr;
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volatile soc_etm_chn_evt_id_reg_t ch0_evt_id;
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volatile soc_etm_chn_task_id_reg_t ch0_task_id;
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volatile soc_etm_chn_evt_id_reg_t ch1_evt_id;
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volatile soc_etm_chn_task_id_reg_t ch1_task_id;
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volatile soc_etm_chn_evt_id_reg_t ch2_evt_id;
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volatile soc_etm_chn_task_id_reg_t ch2_task_id;
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volatile soc_etm_chn_evt_id_reg_t ch3_evt_id;
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volatile soc_etm_chn_task_id_reg_t ch3_task_id;
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volatile soc_etm_chn_evt_id_reg_t ch4_evt_id;
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volatile soc_etm_chn_task_id_reg_t ch4_task_id;
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volatile soc_etm_chn_evt_id_reg_t ch5_evt_id;
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volatile soc_etm_chn_task_id_reg_t ch5_task_id;
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volatile soc_etm_chn_evt_id_reg_t ch6_evt_id;
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volatile soc_etm_chn_task_id_reg_t ch6_task_id;
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volatile soc_etm_chn_evt_id_reg_t ch7_evt_id;
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volatile soc_etm_chn_task_id_reg_t ch7_task_id;
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volatile soc_etm_chn_evt_id_reg_t ch8_evt_id;
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volatile soc_etm_chn_task_id_reg_t ch8_task_id;
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volatile soc_etm_chn_evt_id_reg_t ch9_evt_id;
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volatile soc_etm_chn_task_id_reg_t ch9_task_id;
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volatile soc_etm_chn_evt_id_reg_t ch10_evt_id;
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volatile soc_etm_chn_task_id_reg_t ch10_task_id;
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volatile soc_etm_chn_evt_id_reg_t ch11_evt_id;
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volatile soc_etm_chn_task_id_reg_t ch11_task_id;
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volatile soc_etm_chn_evt_id_reg_t ch12_evt_id;
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volatile soc_etm_chn_task_id_reg_t ch12_task_id;
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volatile soc_etm_chn_evt_id_reg_t ch13_evt_id;
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volatile soc_etm_chn_task_id_reg_t ch13_task_id;
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volatile soc_etm_chn_evt_id_reg_t ch14_evt_id;
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volatile soc_etm_chn_task_id_reg_t ch14_task_id;
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volatile soc_etm_chn_evt_id_reg_t ch15_evt_id;
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volatile soc_etm_chn_task_id_reg_t ch15_task_id;
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volatile soc_etm_chn_evt_id_reg_t ch16_evt_id;
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volatile soc_etm_chn_task_id_reg_t ch16_task_id;
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volatile soc_etm_chn_evt_id_reg_t ch17_evt_id;
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volatile soc_etm_chn_task_id_reg_t ch17_task_id;
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volatile soc_etm_chn_evt_id_reg_t ch18_evt_id;
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volatile soc_etm_chn_task_id_reg_t ch18_task_id;
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volatile soc_etm_chn_evt_id_reg_t ch19_evt_id;
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volatile soc_etm_chn_task_id_reg_t ch19_task_id;
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volatile soc_etm_chn_evt_id_reg_t ch20_evt_id;
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volatile soc_etm_chn_task_id_reg_t ch20_task_id;
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volatile soc_etm_chn_evt_id_reg_t ch21_evt_id;
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volatile soc_etm_chn_task_id_reg_t ch21_task_id;
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volatile soc_etm_chn_evt_id_reg_t ch22_evt_id;
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volatile soc_etm_chn_task_id_reg_t ch22_task_id;
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volatile soc_etm_chn_evt_id_reg_t ch23_evt_id;
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volatile soc_etm_chn_task_id_reg_t ch23_task_id;
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volatile soc_etm_chn_evt_id_reg_t ch24_evt_id;
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volatile soc_etm_chn_task_id_reg_t ch24_task_id;
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volatile soc_etm_chn_evt_id_reg_t ch25_evt_id;
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volatile soc_etm_chn_task_id_reg_t ch25_task_id;
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volatile soc_etm_chn_evt_id_reg_t ch26_evt_id;
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volatile soc_etm_chn_task_id_reg_t ch26_task_id;
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volatile soc_etm_chn_evt_id_reg_t ch27_evt_id;
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volatile soc_etm_chn_task_id_reg_t ch27_task_id;
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volatile soc_etm_chn_evt_id_reg_t ch28_evt_id;
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volatile soc_etm_chn_task_id_reg_t ch28_task_id;
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volatile soc_etm_chn_evt_id_reg_t ch29_evt_id;
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volatile soc_etm_chn_task_id_reg_t ch29_task_id;
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volatile soc_etm_chn_evt_id_reg_t ch30_evt_id;
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volatile soc_etm_chn_task_id_reg_t ch30_task_id;
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volatile soc_etm_chn_evt_id_reg_t ch31_evt_id;
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volatile soc_etm_chn_task_id_reg_t ch31_task_id;
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volatile soc_etm_chn_evt_id_reg_t ch32_evt_id;
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volatile soc_etm_chn_task_id_reg_t ch32_task_id;
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volatile soc_etm_chn_evt_id_reg_t ch33_evt_id;
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volatile soc_etm_chn_task_id_reg_t ch33_task_id;
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volatile soc_etm_chn_evt_id_reg_t ch34_evt_id;
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volatile soc_etm_chn_task_id_reg_t ch34_task_id;
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volatile soc_etm_chn_evt_id_reg_t ch35_evt_id;
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volatile soc_etm_chn_task_id_reg_t ch35_task_id;
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volatile soc_etm_chn_evt_id_reg_t ch36_evt_id;
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volatile soc_etm_chn_task_id_reg_t ch36_task_id;
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volatile soc_etm_chn_evt_id_reg_t ch37_evt_id;
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volatile soc_etm_chn_task_id_reg_t ch37_task_id;
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volatile soc_etm_chn_evt_id_reg_t ch38_evt_id;
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volatile soc_etm_chn_task_id_reg_t ch38_task_id;
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volatile soc_etm_chn_evt_id_reg_t ch39_evt_id;
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volatile soc_etm_chn_task_id_reg_t ch39_task_id;
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volatile soc_etm_chn_evt_id_reg_t ch40_evt_id;
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volatile soc_etm_chn_task_id_reg_t ch40_task_id;
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volatile soc_etm_chn_evt_id_reg_t ch41_evt_id;
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volatile soc_etm_chn_task_id_reg_t ch41_task_id;
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volatile soc_etm_chn_evt_id_reg_t ch42_evt_id;
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volatile soc_etm_chn_task_id_reg_t ch42_task_id;
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volatile soc_etm_chn_evt_id_reg_t ch43_evt_id;
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volatile soc_etm_chn_task_id_reg_t ch43_task_id;
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volatile soc_etm_chn_evt_id_reg_t ch44_evt_id;
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volatile soc_etm_chn_task_id_reg_t ch44_task_id;
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volatile soc_etm_chn_evt_id_reg_t ch45_evt_id;
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volatile soc_etm_chn_task_id_reg_t ch45_task_id;
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volatile soc_etm_chn_evt_id_reg_t ch46_evt_id;
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volatile soc_etm_chn_task_id_reg_t ch46_task_id;
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volatile soc_etm_chn_evt_id_reg_t ch47_evt_id;
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volatile soc_etm_chn_task_id_reg_t ch47_task_id;
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volatile soc_etm_chn_evt_id_reg_t ch48_evt_id;
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volatile soc_etm_chn_task_id_reg_t ch48_task_id;
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volatile soc_etm_chn_evt_id_reg_t ch49_evt_id;
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volatile soc_etm_chn_task_id_reg_t ch49_task_id;
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volatile struct {
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soc_etm_chn_evt_id_reg_t eid;
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soc_etm_chn_task_id_reg_t tid;
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} channel[50];
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volatile soc_etm_evt_st0_reg_t evt_st0;
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volatile soc_etm_evt_st0_clr_reg_t evt_st0_clr;
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volatile soc_etm_evt_st1_reg_t evt_st1;
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@@ -29,6 +29,8 @@ PROVIDE ( ECC = 0x6008B000 );
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PROVIDE ( ECDSA = 0x6008E000 );
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PROVIDE ( IO_MUX = 0x60090000 );
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PROVIDE ( GPIO = 0x60091000 );
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PROVIDE ( GPIO_EXT = 0x60091e00 );
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PROVIDE ( GPIO_ETM = 0x60091f18 );
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PROVIDE ( TCM_MEM_MONITOR = 0x60092000 );
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PROVIDE ( PAU = 0x60093000 );
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PROVIDE ( HP_SYSTEM = 0x60095000 );
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