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feat(ble): add clk source freq change of ble slow clock on ESP32-C6

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This commit is contained in:
cjin
2025-08-07 14:17:54 +08:00
committed by BOT
parent 9d24716e28
commit d97781970f
1 changed files with 13 additions and 1 deletions
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12
components/bt/controller/esp32c6/bt.c
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@@ -918,8 +918,20 @@ static void ble_rtc_clk_init(esp_bt_controller_config_t *cfg)
#if CONFIG_RTC_CLK_SRC_INT_RC
s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_RC_SLOW;
#elif CONFIG_RTC_CLK_SRC_EXT_CRYS
uint32_t clk_freq = 0;
if (rtc_clk_slow_src_get() == SOC_RTC_SLOW_CLK_SRC_XTAL32K) {
if (!esp_clk_tree_src_get_freq_hz(SOC_MOD_CLK_XTAL32K, ESP_CLK_TREE_SRC_FREQ_PRECISION_EXACT, &clk_freq)) {
if (clk_freq > 32700 && clk_freq < 33800) {
s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_XTAL32K;
} else {
ESP_LOGW(NIMBLE_PORT_LOG_TAG, "32.768kHz XTAL detection error, switch to main XTAL as Bluetooth sleep clock");
s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL;
}
} else {
ESP_LOGW(NIMBLE_PORT_LOG_TAG, "32.768kHz XTAL detection error, switch to main XTAL as Bluetooth sleep clock");
s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL;
}
} else {
ESP_LOGW(NIMBLE_PORT_LOG_TAG, "32.768kHz XTAL not detected, fall back to main XTAL as Bluetooth sleep clock");
s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL;