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spi_flash: bringup for esp32c6

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This commit is contained in:
Cao Sen Miao
2022-10-20 13:59:08 +08:00
parent bdefd7fb6b
commit d9f01ed43c
18 changed files with 128 additions and 118 deletions
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2
components/spi_flash/.build-test-rules.yml
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@@ -4,7 +4,7 @@ components/spi_flash/test_apps/esp_flash:
disable:
- if: IDF_TARGET == "esp32c6"
temporary: true
reason: target esp32c6 is not supported yet
reason: target esp32c6 cannot pass atomic build
components/spi_flash/test_apps/flash_encryption:
disable_test:

4
components/spi_flash/esp32c6/flash_ops_esp32c6.c
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@@ -29,7 +29,6 @@ esp_err_t spi_flash_wrap_set(spi_flash_wrap_mode_t mode)
SPIFLASH.user.fwrite_dual = 0;
SPIFLASH.user.fwrite_qio = 1;
SPIFLASH.user.fwrite_quad = 0;
// SPIFLASH.ctrl.fcmd_dual = 0; // TODO: IDF-5333
SPIFLASH.ctrl.fcmd_quad = 0;
SPIFLASH.user.usr_dummy = 0;
SPIFLASH.user.usr_addr = 1;
@@ -53,7 +52,8 @@ esp_err_t spi_flash_wrap_set(spi_flash_wrap_mode_t mode)
esp_err_t spi_flash_enable_wrap(uint32_t wrap_size)
{
CLEAR_PERI_REG_MASK(SPI_MEM_CTRL2_REG(0), SPI_MEM_SPLIT_TRANS_EN_M); // TODO: IDF-5333 Newly added
// IDF-6198 TODO: support wrap on esp32-c6
CLEAR_PERI_REG_MASK(SPI_MEM_CTRL2_REG(0), SPI_MEM_SPLIT_TRANS_EN_M);
switch (wrap_size) {
case 8:
return spi_flash_wrap_set(FLASH_WRAP_MODE_8B);

21
components/spi_flash/test_apps/esp_flash/main/test_esp_flash_def.h
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@@ -80,6 +80,23 @@
#define FSPI_PIN_NUM_WP 5
#define FSPI_PIN_NUM_CS 10
// Just use the same pins for HSPI
#define HSPI_PIN_NUM_MOSI FSPI_PIN_NUM_MOSI
#define HSPI_PIN_NUM_MISO FSPI_PIN_NUM_MISO
#define HSPI_PIN_NUM_CLK FSPI_PIN_NUM_CLK
#define HSPI_PIN_NUM_HD FSPI_PIN_NUM_HD
#define HSPI_PIN_NUM_WP FSPI_PIN_NUM_WP
#define HSPI_PIN_NUM_CS FSPI_PIN_NUM_CS
#elif CONFIG_IDF_TARGET_ESP32C6
#define FSPI_PIN_NUM_MOSI 7
#define FSPI_PIN_NUM_MISO 2
#define FSPI_PIN_NUM_CLK 6
#define FSPI_PIN_NUM_HD 4
#define FSPI_PIN_NUM_WP 5
#define FSPI_PIN_NUM_CS 17
// Just use the same pins for HSPI
#define HSPI_PIN_NUM_MOSI FSPI_PIN_NUM_MOSI
#define HSPI_PIN_NUM_MISO FSPI_PIN_NUM_MISO
@@ -115,7 +132,7 @@ typedef void (*flash_test_func_t)(const esp_partition_t *part);
#define BYPASS_MULTIPLE_CHIP 1
#endif
#if CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3
#if CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C6
//chips without PSRAM
#define TEST_CHIP_NUM 2
#elif CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
@@ -223,7 +240,7 @@ flashtest_config_t config_list[] = {
.input_delay_ns = 0,
},
};
#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2
#elif CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6
flashtest_config_t config_list[] = {
/* No SPI1 CS1 flash on esp32c3 test */
{

2
components/spi_flash/test_apps/esp_flash/main/test_esp_flash_drv.c
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@@ -40,6 +40,8 @@
#include "esp32h2/rom/cache.h"
#elif CONFIG_IDF_TARGET_ESP32C2
#include "esp32c2/rom/cache.h"
#elif CONFIG_IDF_TARGET_ESP32C6
#include "esp32c2/rom/cache.h"
#endif
#define FUNC_SPI 1

2
components/spi_flash/test_apps/flash_mmap/main/test_mmap.c
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@@ -165,7 +165,7 @@ TEST_CASE("Can mmap into data address space", "[spi_flash][mmap]")
TEST_ASSERT_EQUAL_PTR(NULL, spi_flash_phys2cache(start, SPI_FLASH_MMAP_DATA));
}
#if !(CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2)
#if !(CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C6)
/* On S3/C3/C2 the cache is programmatically split between Icache and dcache and with the default setup we dont leave a lot pages
available for additional mmaps into instruction space. Disabling this test for now since any hypothetical use case for this
is no longer supported "out of the box"