From 88c123f805ecaa677642326801623234b57936ff Mon Sep 17 00:00:00 2001 From: wuzhenghui Date: Mon, 29 Aug 2022 11:52:59 +0800 Subject: [PATCH 1/3] esp_rom: add esp_rom_software_reset and esp_rom_software_reset_cpu interface --- components/esp_rom/esp32/ld/esp32.rom.api.ld | 3 +++ .../esp_rom/esp32c2/ld/esp32c2.rom.api.ld | 3 +++ .../esp_rom/esp32c3/ld/esp32c3.rom.api.ld | 3 +++ .../esp_rom/esp32c6/ld/esp32c6.rom.api.ld | 3 +++ .../esp_rom/esp32h2/ld/rev1/esp32h2.rom.api.ld | 3 +++ .../esp_rom/esp32h2/ld/rev2/esp32h2.rom.api.ld | 3 +++ .../esp_rom/esp32s2/ld/esp32s2.rom.api.ld | 3 +++ .../esp_rom/esp32s3/ld/esp32s3.rom.api.ld | 3 +++ components/esp_rom/include/esp_rom_sys.h | 18 ++++++++++++++++++ 9 files changed, 42 insertions(+) diff --git a/components/esp_rom/esp32/ld/esp32.rom.api.ld b/components/esp_rom/esp32/ld/esp32.rom.api.ld index 911cc17292..749977e845 100644 --- a/components/esp_rom/esp32/ld/esp32.rom.api.ld +++ b/components/esp_rom/esp32/ld/esp32.rom.api.ld @@ -33,6 +33,9 @@ PROVIDE ( esp_rom_md5_init = 0x4005da7c ); PROVIDE ( esp_rom_md5_update = 0x4005da9c ); PROVIDE ( esp_rom_md5_final = 0x4005db1c ); +PROVIDE ( esp_rom_software_reset_system = software_reset ); +PROVIDE ( esp_rom_software_reset_cpu = software_reset_cpu ); + PROVIDE ( esp_rom_printf = ets_printf ); PROVIDE ( esp_rom_delay_us = ets_delay_us ); PROVIDE ( esp_rom_install_uart_printf = ets_install_uart_printf ); diff --git a/components/esp_rom/esp32c2/ld/esp32c2.rom.api.ld b/components/esp_rom/esp32c2/ld/esp32c2.rom.api.ld index 4c39a51332..b214d50155 100644 --- a/components/esp_rom/esp32c2/ld/esp32c2.rom.api.ld +++ b/components/esp_rom/esp32c2/ld/esp32c2.rom.api.ld @@ -34,6 +34,9 @@ PROVIDE ( esp_rom_mbedtls_md5_starts_ret = mbedtls_md5_starts_ret ); PROVIDE ( esp_rom_mbedtls_md5_update_ret = mbedtls_md5_update_ret ); PROVIDE ( esp_rom_mbedtls_md5_finish_ret = mbedtls_md5_finish_ret ); +PROVIDE ( esp_rom_software_reset_system = software_reset ); +PROVIDE ( esp_rom_software_reset_cpu = software_reset_cpu ); + PROVIDE ( esp_rom_printf = ets_printf ); PROVIDE ( esp_rom_delay_us = ets_delay_us ); PROVIDE ( esp_rom_get_reset_reason = rtc_get_reset_reason ); diff --git a/components/esp_rom/esp32c3/ld/esp32c3.rom.api.ld b/components/esp_rom/esp32c3/ld/esp32c3.rom.api.ld index d223ff6a95..98888d17a4 100644 --- a/components/esp_rom/esp32c3/ld/esp32c3.rom.api.ld +++ b/components/esp_rom/esp32c3/ld/esp32c3.rom.api.ld @@ -32,6 +32,9 @@ PROVIDE ( esp_rom_md5_init = MD5Init ); PROVIDE ( esp_rom_md5_update = MD5Update ); PROVIDE ( esp_rom_md5_final = MD5Final ); +PROVIDE ( esp_rom_software_reset_system = software_reset ); +PROVIDE ( esp_rom_software_reset_cpu = software_reset_cpu ); + PROVIDE ( esp_rom_printf = ets_printf ); PROVIDE ( esp_rom_delay_us = ets_delay_us ); PROVIDE ( esp_rom_get_reset_reason = rtc_get_reset_reason ); diff --git a/components/esp_rom/esp32c6/ld/esp32c6.rom.api.ld b/components/esp_rom/esp32c6/ld/esp32c6.rom.api.ld index 27dde1adf2..4d26da2720 100644 --- a/components/esp_rom/esp32c6/ld/esp32c6.rom.api.ld +++ b/components/esp_rom/esp32c6/ld/esp32c6.rom.api.ld @@ -34,6 +34,9 @@ PROVIDE ( esp_rom_md5_init = MD5Init ); PROVIDE ( esp_rom_md5_update = MD5Update ); PROVIDE ( esp_rom_md5_final = MD5Final ); +PROVIDE ( esp_rom_software_reset_system = software_reset ); +PROVIDE ( esp_rom_software_reset_cpu = software_reset_cpu ); + PROVIDE ( esp_rom_printf = ets_printf ); PROVIDE ( esp_rom_install_uart_printf = ets_install_uart_printf ); PROVIDE ( esp_rom_delay_us = ets_delay_us ); diff --git a/components/esp_rom/esp32h2/ld/rev1/esp32h2.rom.api.ld b/components/esp_rom/esp32h2/ld/rev1/esp32h2.rom.api.ld index 7945722adc..96c5a68190 100644 --- a/components/esp_rom/esp32h2/ld/rev1/esp32h2.rom.api.ld +++ b/components/esp_rom/esp32h2/ld/rev1/esp32h2.rom.api.ld @@ -37,6 +37,9 @@ PROVIDE ( esp_rom_md5_init = MD5Init ); PROVIDE ( esp_rom_md5_update = MD5Update ); PROVIDE ( esp_rom_md5_final = MD5Final ); +PROVIDE ( esp_rom_software_reset_system = software_reset ); +PROVIDE ( esp_rom_software_reset_cpu = software_reset_cpu ); + PROVIDE ( esp_rom_printf = ets_printf ); PROVIDE ( esp_rom_delay_us = ets_delay_us ); PROVIDE ( esp_rom_get_reset_reason = rtc_get_reset_reason ); diff --git a/components/esp_rom/esp32h2/ld/rev2/esp32h2.rom.api.ld b/components/esp_rom/esp32h2/ld/rev2/esp32h2.rom.api.ld index 7945722adc..96c5a68190 100644 --- a/components/esp_rom/esp32h2/ld/rev2/esp32h2.rom.api.ld +++ b/components/esp_rom/esp32h2/ld/rev2/esp32h2.rom.api.ld @@ -37,6 +37,9 @@ PROVIDE ( esp_rom_md5_init = MD5Init ); PROVIDE ( esp_rom_md5_update = MD5Update ); PROVIDE ( esp_rom_md5_final = MD5Final ); +PROVIDE ( esp_rom_software_reset_system = software_reset ); +PROVIDE ( esp_rom_software_reset_cpu = software_reset_cpu ); + PROVIDE ( esp_rom_printf = ets_printf ); PROVIDE ( esp_rom_delay_us = ets_delay_us ); PROVIDE ( esp_rom_get_reset_reason = rtc_get_reset_reason ); diff --git a/components/esp_rom/esp32s2/ld/esp32s2.rom.api.ld b/components/esp_rom/esp32s2/ld/esp32s2.rom.api.ld index 078a648338..ca3488174c 100644 --- a/components/esp_rom/esp32s2/ld/esp32s2.rom.api.ld +++ b/components/esp_rom/esp32s2/ld/esp32s2.rom.api.ld @@ -34,6 +34,9 @@ PROVIDE ( esp_rom_md5_init = 0x4000526c ); PROVIDE ( esp_rom_md5_update = 0x4000528c ); PROVIDE ( esp_rom_md5_final = 0x4000530c ); +PROVIDE ( esp_rom_software_reset_system = software_reset ); +PROVIDE ( esp_rom_software_reset_cpu = software_reset_cpu ); + PROVIDE ( esp_rom_printf = ets_printf ); PROVIDE ( esp_rom_delay_us = ets_delay_us ); PROVIDE ( esp_rom_install_uart_printf = ets_install_uart_printf ); diff --git a/components/esp_rom/esp32s3/ld/esp32s3.rom.api.ld b/components/esp_rom/esp32s3/ld/esp32s3.rom.api.ld index 22425ce3bb..6355190a6c 100644 --- a/components/esp_rom/esp32s3/ld/esp32s3.rom.api.ld +++ b/components/esp_rom/esp32s3/ld/esp32s3.rom.api.ld @@ -33,6 +33,9 @@ PROVIDE ( esp_rom_md5_init = MD5Init ); PROVIDE ( esp_rom_md5_update = MD5Update ); PROVIDE ( esp_rom_md5_final = MD5Final ); +PROVIDE ( esp_rom_software_reset_system = software_reset ); +PROVIDE ( esp_rom_software_reset_cpu = software_reset_cpu ); + PROVIDE ( esp_rom_printf = ets_printf ); PROVIDE ( esp_rom_delay_us = ets_delay_us ); PROVIDE ( esp_rom_install_uart_printf = ets_install_uart_printf ); diff --git a/components/esp_rom/include/esp_rom_sys.h b/components/esp_rom/include/esp_rom_sys.h index 54ef25fe47..6d119edda6 100644 --- a/components/esp_rom/include/esp_rom_sys.h +++ b/components/esp_rom/include/esp_rom_sys.h @@ -13,6 +13,24 @@ extern "C" { #endif +/** + * @brief Software Reset digital core include RTC. + * + * It is not recommended to use this function in esp-idf, use + * esp_restart() instead. + */ +void esp_rom_software_reset_system(void); + +/** + * @brief Software Reset cpu core. + * + * It is not recommended to use this function in esp-idf, use + * esp_restart() instead. + * + * @param cpu_no : The CPU to reset, 0 for PRO CPU, 1 for APP CPU. + */ +void esp_rom_software_reset_cpu(int cpu_no); + /** * @brief Print formated string to console device * @note float and long long data are not supported! From 82ffe7e438d4d53360ff1a2f9f608c2ec34ab17c Mon Sep 17 00:00:00 2001 From: wuzhenghui Date: Mon, 29 Aug 2022 11:55:35 +0800 Subject: [PATCH 2/3] replacing reset by register operations with ROM interfaces to decouple the effects of register name changes --- components/bootloader_support/src/bootloader_utility.c | 2 +- components/esp_hw_support/include/esp_fault.h | 7 +++---- components/esp_system/esp_system.c | 3 ++- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/components/bootloader_support/src/bootloader_utility.c b/components/bootloader_support/src/bootloader_utility.c index b3c4ed1bf0..ba059f54b4 100644 --- a/components/bootloader_support/src/bootloader_utility.c +++ b/components/bootloader_support/src/bootloader_utility.c @@ -864,7 +864,7 @@ void bootloader_reset(void) #ifdef BOOTLOADER_BUILD bootloader_atexit(); esp_rom_delay_us(1000); /* Allow last byte to leave FIFO */ - REG_WRITE(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_SW_SYS_RST); + esp_rom_software_reset_system(); while (1) { } /* This line will never be reached, used to keep gcc happy */ #else abort(); /* This function should really not be called from application code */ diff --git a/components/esp_hw_support/include/esp_fault.h b/components/esp_hw_support/include/esp_fault.h index 910ba59d06..19b0a9e0cf 100644 --- a/components/esp_hw_support/include/esp_fault.h +++ b/components/esp_hw_support/include/esp_fault.h @@ -4,7 +4,6 @@ * SPDX-License-Identifier: Apache-2.0 */ #include "sdkconfig.h" -#include "soc/rtc_cntl_reg.h" #include "esp_rom_sys.h" #pragma once @@ -70,9 +69,9 @@ extern "C" { */ #ifndef ESP_FAULT_ASSERT_DEBUG -#define _ESP_FAULT_RESET() do { \ - REG_WRITE(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_SW_SYS_RST); \ - _ESP_FAULT_ILLEGAL_INSTRUCTION; \ +#define _ESP_FAULT_RESET() do { \ + esp_rom_software_reset_system(); \ + _ESP_FAULT_ILLEGAL_INSTRUCTION; \ } while(0) #else // ESP_FAULT_ASSERT_DEBUG diff --git a/components/esp_system/esp_system.c b/components/esp_system/esp_system.c index 0767a874fd..30f657871b 100644 --- a/components/esp_system/esp_system.c +++ b/components/esp_system/esp_system.c @@ -14,6 +14,7 @@ #include "soc/rtc_cntl_reg.h" #include "esp_private/panic_internal.h" #include "esp_rom_uart.h" +#include "esp_rom_sys.h" #if CONFIG_ESP_SYSTEM_MEMPROT_FEATURE #if CONFIG_IDF_TARGET_ESP32S2 #include "esp32s2/memprot.h" @@ -42,7 +43,7 @@ void IRAM_ATTR esp_restart_noos_dig(void) esp_cpu_unstall(PRO_CPU_NUM); #endif // reset the digital part - SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_SW_SYS_RST); + esp_rom_software_reset_system(); while (true) { ; } From c31aaeda2a412f4bc2ea5234cc5799bd844161dd Mon Sep 17 00:00:00 2001 From: wuzhenghui Date: Mon, 29 Aug 2022 20:14:23 +0800 Subject: [PATCH 3/3] ll: add reset interface to rtc_cntl_ll --- .../hal/esp32/include/hal/rtc_cntl_ll.h | 11 ++++++++ .../hal/esp32c2/include/hal/rtc_cntl_ll.h | 10 +++++++ .../hal/esp32c3/include/hal/rtc_cntl_ll.h | 28 ++++++++++--------- .../hal/esp32h2/include/hal/rtc_cntl_ll.h | 28 ++++++++++--------- .../hal/esp32s2/include/hal/rtc_cntl_ll.h | 10 +++++++ .../hal/esp32s3/include/hal/rtc_cntl_ll.h | 11 ++++++++ tools/ci/check_copyright_ignore.txt | 2 -- 7 files changed, 72 insertions(+), 28 deletions(-) diff --git a/components/hal/esp32/include/hal/rtc_cntl_ll.h b/components/hal/esp32/include/hal/rtc_cntl_ll.h index 19c12f69af..a4f6b3f7d8 100644 --- a/components/hal/esp32/include/hal/rtc_cntl_ll.h +++ b/components/hal/esp32/include/hal/rtc_cntl_ll.h @@ -52,6 +52,17 @@ static inline void rtc_cntl_ll_timer2_set_touch_wait_cycle(uint32_t wait_cycle) REG_SET_FIELD(RTC_CNTL_TIMER2_REG, RTC_CNTL_ULPCP_TOUCH_START_WAIT, wait_cycle); } +static inline void rtc_cntl_ll_reset_system(void) +{ + REG_WRITE(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_SW_SYS_RST); +} + +static inline void rtc_cntl_ll_reset_cpu(int cpu_no) +{ + uint32_t rtc_cntl_rst = (cpu_no == 0) ? RTC_CNTL_SW_PROCPU_RST : RTC_CNTL_SW_APPCPU_RST; + REG_WRITE(RTC_CNTL_OPTIONS0_REG, rtc_cntl_rst); +} + #ifdef __cplusplus } #endif diff --git a/components/hal/esp32c2/include/hal/rtc_cntl_ll.h b/components/hal/esp32c2/include/hal/rtc_cntl_ll.h index f98d7994eb..e7ee245713 100644 --- a/components/hal/esp32c2/include/hal/rtc_cntl_ll.h +++ b/components/hal/esp32c2/include/hal/rtc_cntl_ll.h @@ -54,6 +54,16 @@ static inline void rtc_cntl_ll_disable_cpu_retention(void) REG_CLR_BIT(RTC_CNTL_RETENTION_CTRL_REG, RTC_CNTL_RETENTION_EN); } +static inline void rtc_cntl_ll_reset_system(void) +{ + REG_WRITE(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_SW_SYS_RST); +} + +static inline void rtc_cntl_ll_reset_cpu(int cpu_no) +{ + REG_WRITE(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_SW_PROCPU_RST); +} + #ifdef __cplusplus } #endif diff --git a/components/hal/esp32c3/include/hal/rtc_cntl_ll.h b/components/hal/esp32c3/include/hal/rtc_cntl_ll.h index 9f298bbf09..7e1b553422 100644 --- a/components/hal/esp32c3/include/hal/rtc_cntl_ll.h +++ b/components/hal/esp32c3/include/hal/rtc_cntl_ll.h @@ -1,16 +1,8 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #pragma once @@ -68,6 +60,16 @@ static inline void rtc_cntl_ll_disable_cpu_retention(void) REG_CLR_BIT(RTC_CNTL_RETENTION_CTRL_REG, RTC_CNTL_RETENTION_EN); } +static inline void rtc_cntl_ll_reset_system(void) +{ + REG_WRITE(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_SW_SYS_RST); +} + +static inline void rtc_cntl_ll_reset_cpu(int cpu_no) +{ + REG_WRITE(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_SW_PROCPU_RST); +} + #ifdef __cplusplus } #endif diff --git a/components/hal/esp32h2/include/hal/rtc_cntl_ll.h b/components/hal/esp32h2/include/hal/rtc_cntl_ll.h index bff6c79390..750bc13333 100644 --- a/components/hal/esp32h2/include/hal/rtc_cntl_ll.h +++ b/components/hal/esp32h2/include/hal/rtc_cntl_ll.h @@ -1,16 +1,8 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #pragma once @@ -57,6 +49,16 @@ static inline void rtc_cntl_ll_disable_cpu_retention(void) // ESP32H2-TODO: IDF-3383 } +static inline void rtc_cntl_ll_reset_system(void) +{ + REG_WRITE(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_SW_SYS_RST); +} + +static inline void rtc_cntl_ll_reset_cpu(int cpu_no) +{ + REG_WRITE(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_SW_PROCPU_RST); +} + #ifdef __cplusplus } #endif diff --git a/components/hal/esp32s2/include/hal/rtc_cntl_ll.h b/components/hal/esp32s2/include/hal/rtc_cntl_ll.h index d70b997482..9ce2461517 100644 --- a/components/hal/esp32s2/include/hal/rtc_cntl_ll.h +++ b/components/hal/esp32s2/include/hal/rtc_cntl_ll.h @@ -52,6 +52,16 @@ static inline void rtc_cntl_ll_timer2_set_touch_wait_cycle(uint32_t wait_cycle) REG_SET_FIELD(RTC_CNTL_TIMER2_REG, RTC_CNTL_ULPCP_TOUCH_START_WAIT, wait_cycle); } +static inline void rtc_cntl_ll_reset_system(void) +{ + REG_WRITE(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_SW_SYS_RST); +} + +static inline void rtc_cntl_ll_reset_cpu(int cpu_no) +{ + REG_WRITE(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_SW_PROCPU_RST); +} + #ifdef __cplusplus } #endif diff --git a/components/hal/esp32s3/include/hal/rtc_cntl_ll.h b/components/hal/esp32s3/include/hal/rtc_cntl_ll.h index bdf20068cb..947f113668 100644 --- a/components/hal/esp32s3/include/hal/rtc_cntl_ll.h +++ b/components/hal/esp32s3/include/hal/rtc_cntl_ll.h @@ -132,6 +132,17 @@ static inline void rtc_cntl_ll_timer2_set_touch_wait_cycle(uint32_t wait_cycle) REG_SET_FIELD(RTC_CNTL_TIMER2_REG, RTC_CNTL_ULPCP_TOUCH_START_WAIT, wait_cycle); } +static inline void rtc_cntl_ll_reset_system(void) +{ + REG_WRITE(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_SW_SYS_RST); +} + +static inline void rtc_cntl_ll_reset_cpu(int cpu_no) +{ + uint32_t rtc_cntl_rst = (cpu_no == 0) ? RTC_CNTL_SW_PROCPU_RST : RTC_CNTL_SW_APPCPU_RST; + REG_WRITE(RTC_CNTL_OPTIONS0_REG, rtc_cntl_rst); +} + #ifdef __cplusplus } #endif diff --git a/tools/ci/check_copyright_ignore.txt b/tools/ci/check_copyright_ignore.txt index 5072f14120..0faa058673 100644 --- a/tools/ci/check_copyright_ignore.txt +++ b/tools/ci/check_copyright_ignore.txt @@ -708,7 +708,6 @@ components/hal/esp32c3/include/hal/ds_ll.h components/hal/esp32c3/include/hal/hmac_hal.h components/hal/esp32c3/include/hal/hmac_ll.h components/hal/esp32c3/include/hal/mpu_ll.h -components/hal/esp32c3/include/hal/rtc_cntl_ll.h components/hal/esp32c3/include/hal/sha_ll.h components/hal/esp32c3/include/hal/spi_flash_encrypted_ll.h components/hal/esp32c3/include/hal/uhci_ll.h @@ -720,7 +719,6 @@ components/hal/esp32h2/include/hal/ds_ll.h components/hal/esp32h2/include/hal/hmac_hal.h components/hal/esp32h2/include/hal/hmac_ll.h components/hal/esp32h2/include/hal/mpu_ll.h -components/hal/esp32h2/include/hal/rtc_cntl_ll.h components/hal/esp32h2/include/hal/sha_ll.h components/hal/esp32h2/include/hal/spi_flash_encrypted_ll.h components/hal/esp32h2/include/hal/uhci_ll.h