From f0518b3c16ec130eb9c81372ce711eed136961b5 Mon Sep 17 00:00:00 2001 From: Armando Date: Wed, 24 Jan 2024 13:28:15 +0800 Subject: [PATCH 1/6] feat(dma): advanced dma malloc helper --- components/driver/deprecated/i2s_legacy.c | 9 +- components/esp_driver_i2s/i2s_common.c | 30 ++- components/esp_hw_support/dma/esp_dma_utils.c | 210 +++++++++++++++--- components/esp_hw_support/dma/gdma.c | 33 ++- .../dma/include/esp_dma_utils.h | 119 +++++++--- .../dma/include/esp_private/gdma.h | 20 ++ .../test_apps/dma/main/CMakeLists.txt | 2 +- .../test_apps/dma/main/test_dma_utils.c | 155 +++++++++++++ components/esp_mm/esp_cache.c | 4 - components/hal/esp32c2/include/hal/gdma_ll.h | 2 + components/hal/esp32c3/include/hal/gdma_ll.h | 2 + components/hal/esp32c6/include/hal/gdma_ll.h | 2 + components/hal/esp32h2/include/hal/gdma_ll.h | 2 + components/hal/esp32p4/include/hal/gdma_ll.h | 3 + components/hal/esp32s3/include/hal/gdma_ll.h | 2 + components/hal/hal_utils.c | 19 -- components/hal/include/hal/hal_utils.h | 53 +++++ components/sdmmc/sdmmc_cmd.c | 24 +- components/sdmmc/sdmmc_common.c | 8 +- components/sdmmc/sdmmc_io.c | 18 +- components/sdmmc/sdmmc_mmc.c | 12 +- components/sdmmc/sdmmc_sd.c | 12 +- components/usb/hcd_dwc.c | 22 +- .../usb/test_apps/hcd/main/test_hcd_common.c | 10 +- components/usb/usb_private.c | 9 +- docs/en/api-reference/system/mm_sync.rst | 6 +- .../main/i80_controller_example_main.c | 14 +- 27 files changed, 672 insertions(+), 130 deletions(-) create mode 100644 components/esp_hw_support/test_apps/dma/main/test_dma_utils.c diff --git a/components/driver/deprecated/i2s_legacy.c b/components/driver/deprecated/i2s_legacy.c index 4c8c974cf6..103163c9a6 100644 --- a/components/driver/deprecated/i2s_legacy.c +++ b/components/driver/deprecated/i2s_legacy.c @@ -575,14 +575,19 @@ static esp_err_t i2s_alloc_dma_buffer(i2s_port_t i2s_num, i2s_dma_t *dma_obj) size_t desc_size = 0; for (int cnt = 0; cnt < buf_cnt; cnt++) { /* Allocate DMA buffer */ - esp_dma_calloc(1, sizeof(char) * dma_obj->buf_size, (MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA), (void **)&dma_obj->buf[cnt], NULL); + esp_dma_mem_info_t dma_mem_info = { + .heap_caps = MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA, + .dma_alignment = 4, + }; + esp_dma_capable_calloc(1, sizeof(char) * dma_obj->buf_size, &dma_mem_info, (void **)&dma_obj->buf[cnt], NULL); ESP_GOTO_ON_FALSE(dma_obj->buf[cnt], ESP_ERR_NO_MEM, err, TAG, "Error malloc dma buffer"); #if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE esp_cache_msync(dma_obj->buf[cnt], dma_obj->buf_size, ESP_CACHE_MSYNC_FLAG_DIR_C2M); #endif /* Allocate DMA descriptor */ - esp_dma_calloc(1, sizeof(lldesc_t), MALLOC_CAP_DEFAULT, (void **)&dma_obj->desc[cnt], &desc_size); + esp_dma_capable_calloc(1, sizeof(lldesc_t), &dma_mem_info, (void **)&dma_obj->desc[cnt], &desc_size); + // esp_dma_calloc(1, sizeof(lldesc_t), MALLOC_CAP_DEFAULT, (void **)&dma_obj->desc[cnt], &desc_size); ESP_GOTO_ON_FALSE(dma_obj->desc[cnt], ESP_ERR_NO_MEM, err, TAG, "Error malloc dma description entry"); } /* DMA descriptor must be initialize after all descriptor has been created, otherwise they can't be linked together as a chain */ diff --git a/components/esp_driver_i2s/i2s_common.c b/components/esp_driver_i2s/i2s_common.c index a211abf51a..b52f5be039 100644 --- a/components/esp_driver_i2s/i2s_common.c +++ b/components/esp_driver_i2s/i2s_common.c @@ -69,10 +69,32 @@ static const char *TAG = "i2s_common"; __attribute__((always_inline)) -inline void *i2s_dma_calloc(size_t num, size_t size, uint32_t caps, size_t *actual_size) +inline void *i2s_dma_calloc(i2s_chan_handle_t handle, size_t num, size_t size, bool is_desc, size_t *actual_size) { + esp_err_t ret = ESP_FAIL; void *ptr = NULL; - esp_dma_calloc(num, size, caps, &ptr, actual_size); + + size_t dma_alignment = 0; + void *gdma_chan_handle = NULL; +#if SOC_GDMA_SUPPORTED + gdma_chan_handle = handle->dma.dma_chan; +#endif + dma_alignment_info_t info = { + .is_desc = is_desc, + }; + ret = esp_dma_get_alignment(gdma_chan_handle, &info, &dma_alignment); + assert(ret == ESP_OK); + + esp_dma_mem_info_t dma_mem_info = { + .heap_caps = MALLOC_CAP_DMA, + .dma_alignment = 4, + }; + esp_dma_capable_calloc(num, size, &dma_mem_info, &ptr, actual_size); +#if CONFIG_IDF_TARGET_ESP32P4 + assert((int)ptr % 64 == 0); +#else + assert((int)ptr % 4 == 0); +#endif return ptr; } @@ -422,7 +444,7 @@ esp_err_t i2s_alloc_dma_desc(i2s_chan_handle_t handle, uint32_t num, uint32_t bu size_t desc_size = 0; for (int i = 0; i < num; i++) { /* Allocate DMA descriptor */ - handle->dma.desc[i] = (lldesc_t *) i2s_dma_calloc(1, sizeof(lldesc_t), I2S_DMA_ALLOC_CAPS, &desc_size); + handle->dma.desc[i] = (lldesc_t *) i2s_dma_calloc(handle, 1, sizeof(lldesc_t), true, &desc_size); ESP_GOTO_ON_FALSE(handle->dma.desc[i], ESP_ERR_NO_MEM, err, TAG, "allocate DMA description failed"); handle->dma.desc[i]->owner = 1; handle->dma.desc[i]->eof = 1; @@ -430,7 +452,7 @@ esp_err_t i2s_alloc_dma_desc(i2s_chan_handle_t handle, uint32_t num, uint32_t bu handle->dma.desc[i]->length = bufsize; handle->dma.desc[i]->size = bufsize; handle->dma.desc[i]->offset = 0; - handle->dma.bufs[i] = (uint8_t *) i2s_dma_calloc(1, bufsize * sizeof(uint8_t), I2S_DMA_ALLOC_CAPS, NULL); + handle->dma.bufs[i] = (uint8_t *) i2s_dma_calloc(handle, 1, bufsize * sizeof(uint8_t), false, NULL); ESP_GOTO_ON_FALSE(handle->dma.bufs[i], ESP_ERR_NO_MEM, err, TAG, "allocate DMA buffer failed"); #if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE esp_cache_msync(handle->dma.bufs[i], bufsize * sizeof(uint8_t), ESP_CACHE_MSYNC_FLAG_DIR_C2M); diff --git a/components/esp_hw_support/dma/esp_dma_utils.c b/components/esp_hw_support/dma/esp_dma_utils.c index 6dd01cf863..51079427b5 100644 --- a/components/esp_hw_support/dma/esp_dma_utils.c +++ b/components/esp_hw_support/dma/esp_dma_utils.c @@ -14,39 +14,163 @@ #include "esp_memory_utils.h" #include "esp_dma_utils.h" #include "esp_private/esp_cache_private.h" +#include "esp_private/gdma.h" #include "soc/soc_caps.h" +#include "hal/hal_utils.h" static const char *TAG = "dma_utils"; _Static_assert(ESP_DMA_MALLOC_FLAG_PSRAM == ESP_CACHE_MALLOC_FLAG_PSRAM); #define ALIGN_UP_BY(num, align) (((num) + ((align) - 1)) & ~((align) - 1)) +#define ALIGN_DOWN_BY(num, align) ((num) & (~((align) - 1))) - -esp_err_t esp_dma_malloc(size_t size, uint32_t flags, void **out_ptr, size_t *actual_size) +esp_err_t esp_dma_capable_malloc(size_t size, const esp_dma_mem_info_t *dma_mem_info, void **out_ptr, size_t *actual_size) { - ESP_RETURN_ON_FALSE_ISR(out_ptr, ESP_ERR_INVALID_ARG, TAG, "null pointer"); + ESP_RETURN_ON_FALSE_ISR(dma_mem_info && out_ptr, ESP_ERR_INVALID_ARG, TAG, "null pointer"); - esp_err_t ret = ESP_OK; + size_t alignment = 1; -#if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE - ret = esp_cache_aligned_malloc(size, flags | ESP_CACHE_MALLOC_FLAG_DMA, out_ptr, actual_size); -#else - if (flags & ESP_DMA_MALLOC_FLAG_PSRAM) { - ret = esp_cache_aligned_malloc(size, flags | ESP_CACHE_MALLOC_FLAG_DMA, out_ptr, actual_size); - } else { - size = ALIGN_UP_BY(size, 4); - void *ptr = heap_caps_aligned_alloc(4, size, MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL); - ESP_RETURN_ON_FALSE_ISR(ptr, ESP_ERR_NO_MEM, TAG, "no enough heap memory"); - *out_ptr = ptr; - if (actual_size) { - *actual_size = size; - } + //dma align + size_t dma_alignment = dma_mem_info->dma_alignment; + + //custom align + size_t custom_alignment = dma_mem_info->custom_alignment; + + //cache align + int cache_flags = 0; + size_t cache_alignment = 1; + if (dma_mem_info->heap_caps & MALLOC_CAP_SPIRAM) { + cache_flags |= ESP_DMA_MALLOC_FLAG_PSRAM; + } + esp_err_t ret = esp_cache_get_alignment(cache_flags, &cache_alignment); + assert(ret == ESP_OK); + + //lcm3 + alignment = _lcm_3(dma_alignment, cache_alignment, custom_alignment); + ESP_LOGD(TAG, "alignment: 0x%x", alignment); + + //malloc + size = ALIGN_UP_BY(size, alignment); + int heap_caps = dma_mem_info->heap_caps; + + void *ptr = heap_caps_aligned_alloc(alignment, size, heap_caps); + ESP_RETURN_ON_FALSE_ISR(ptr, ESP_ERR_NO_MEM, TAG, "no enough heap memory"); + + *out_ptr = ptr; + if (actual_size) { + *actual_size = size; + } + + return ESP_OK; +} + +esp_err_t esp_dma_capable_calloc(size_t n, size_t size, const esp_dma_mem_info_t *dma_mem_info, void **out_ptr, size_t *actual_size) +{ + esp_err_t ret = ESP_FAIL; + size_t size_bytes = 0; + bool ovf = false; + + ovf = __builtin_mul_overflow(n, size, &size_bytes); + ESP_RETURN_ON_FALSE_ISR(!ovf, ESP_ERR_INVALID_ARG, TAG, "wrong size, total size overflow"); + + void *ptr = NULL; + ret = esp_dma_capable_malloc(size_bytes, dma_mem_info, &ptr, actual_size); + if (ret == ESP_OK) { + memset(ptr, 0, size_bytes); + *out_ptr = ptr; } -#endif return ret; } +static bool s_buf_in_region(const void *ptr, size_t size, esp_dma_buf_location_t location) +{ + bool found = false; + if (location == ESP_DMA_BUF_LOCATION_INTERNAL) { + if (esp_ptr_dma_capable(ptr) && esp_ptr_dma_capable(ptr + size - 1)) { + found = true; + } + } else if (location == ESP_DMA_BUF_LOCATION_PSRAM) { +#if SOC_PSRAM_DMA_CAPABLE + if (esp_ptr_external_ram(ptr) && esp_ptr_external_ram(ptr + size - 1)) { + found = true; + } +#endif + } + return found; +} + +static inline bool s_is_buf_aligned(intptr_t ptr, size_t alignment) +{ + return (ptr % alignment == 0); +} + +bool esp_dma_is_buffer_alignment_satisfied(const void *ptr, size_t size, esp_dma_mem_info_t *dma_mem_info) +{ + assert(ptr); + + bool found = false; + for (int i = ESP_DMA_BUF_LOCATION_INTERNAL; i < ESP_DMA_BUF_LOCATION_AUTO; i++) { + if (s_buf_in_region(ptr, size, i)) { + found = true; + break; + } + } + if (!found) { + return false; + } + + size_t alignment = 1; + + //dma align + size_t dma_alignment = dma_mem_info->dma_alignment; + + //custom align + size_t custom_alignment = dma_mem_info->custom_alignment; + + //cache align + int cache_flags = 0; + size_t cache_alignment = 1; + if (dma_mem_info->heap_caps & MALLOC_CAP_SPIRAM) { + cache_flags |= ESP_DMA_MALLOC_FLAG_PSRAM; + } + esp_err_t ret = esp_cache_get_alignment(cache_flags, &cache_alignment); + assert(ret == ESP_OK); + + //lcm3 + alignment = _lcm_3(dma_alignment, cache_alignment, custom_alignment); + + bool is_aligned = s_is_buf_aligned((intptr_t)ptr, alignment) && s_is_buf_aligned((intptr_t)size, alignment); + return is_aligned; +} + + +//-----------------------Deprecated APIs-----------------------// +esp_err_t s_legacy_malloc(size_t size, uint32_t flags, void **out_ptr, size_t *actual_size) +{ + ESP_RETURN_ON_FALSE_ISR(out_ptr, ESP_ERR_INVALID_ARG, TAG, "null pointer"); + + int heap_caps = 0; + if (flags & ESP_DMA_MALLOC_FLAG_PSRAM) { + heap_caps |= MALLOC_CAP_SPIRAM; + } else { + heap_caps |= MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL; + } + + esp_dma_mem_info_t dma_mem_info = { + .heap_caps = heap_caps, + .dma_alignment = 4, //legacy API behaviour is only check max dma buffer alignment + }; + + ESP_RETURN_ON_ERROR_ISR(esp_dma_capable_malloc(size, &dma_mem_info, out_ptr, actual_size), TAG, "failed to do malloc"); + + return ESP_OK; +} + +esp_err_t esp_dma_malloc(size_t size, uint32_t flags, void **out_ptr, size_t *actual_size) +{ + return s_legacy_malloc(size, flags, out_ptr, actual_size); +} esp_err_t esp_dma_calloc(size_t n, size_t size, uint32_t flags, void **out_ptr, size_t *actual_size) { @@ -60,7 +184,7 @@ esp_err_t esp_dma_calloc(size_t n, size_t size, uint32_t flags, void **out_ptr, ESP_RETURN_ON_FALSE_ISR(!ovf, ESP_ERR_INVALID_ARG, TAG, "wrong size, total size overflow"); void *ptr = NULL; - ret = esp_dma_malloc(size_bytes, flags, &ptr, actual_size); + ret = s_legacy_malloc(size_bytes, flags, &ptr, actual_size); if (ret == ESP_OK) { memset(ptr, 0, size_bytes); *out_ptr = ptr; @@ -69,17 +193,18 @@ esp_err_t esp_dma_calloc(size_t n, size_t size, uint32_t flags, void **out_ptr, return ret; } -static bool s_buf_in_region(const void *ptr, size_t size, esp_dma_buf_location_t location, uint32_t *in_out_flags) +static bool s_buf_in_region_legacy(const void *ptr, size_t size, esp_dma_buf_location_t location, int *heap_caps) { bool found = false; if (location == ESP_DMA_BUF_LOCATION_INTERNAL) { if (esp_ptr_dma_capable(ptr) && esp_ptr_dma_capable(ptr + size - 1)) { + *heap_caps = MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL; found = true; } } else if (location == ESP_DMA_BUF_LOCATION_PSRAM) { #if SOC_PSRAM_DMA_CAPABLE if (esp_ptr_external_ram(ptr) && esp_ptr_external_ram(ptr + size - 1)) { - *in_out_flags |= ESP_DMA_MALLOC_FLAG_PSRAM; + *heap_caps = MALLOC_CAP_SPIRAM; found = true; } #endif @@ -90,33 +215,48 @@ static bool s_buf_in_region(const void *ptr, size_t size, esp_dma_buf_location_t bool esp_dma_is_buffer_aligned(const void *ptr, size_t size, esp_dma_buf_location_t location) { assert(ptr); - uint32_t flags = ESP_CACHE_MALLOC_FLAG_DMA; bool found = false; + int heap_caps = 0; if (location == ESP_DMA_BUF_LOCATION_AUTO) { for (int i = ESP_DMA_BUF_LOCATION_INTERNAL; i < ESP_DMA_BUF_LOCATION_AUTO; i++) { - if (s_buf_in_region(ptr, size, i, &flags)) { + if (s_buf_in_region_legacy(ptr, size, i, &heap_caps)) { found = true; break; } } } else if (location == ESP_DMA_BUF_LOCATION_INTERNAL) { - found = s_buf_in_region(ptr, size, ESP_DMA_BUF_LOCATION_INTERNAL, &flags); + found = s_buf_in_region_legacy(ptr, size, ESP_DMA_BUF_LOCATION_INTERNAL, &heap_caps); } else { - found = s_buf_in_region(ptr, size, ESP_DMA_BUF_LOCATION_PSRAM, &flags); + found = s_buf_in_region_legacy(ptr, size, ESP_DMA_BUF_LOCATION_PSRAM, &heap_caps); } if (!found) { return false; } - bool is_aligned = false; - size_t dma_alignment = 0; - size_t cache_alignment = 0; - size_t alignment = 0; - esp_err_t ret = esp_cache_get_alignment(flags, &cache_alignment); - assert(ret == ESP_OK); - alignment = MAX(dma_alignment, cache_alignment); - is_aligned = ((intptr_t)ptr % alignment == 0) && (size % alignment == 0); - - return is_aligned; + esp_dma_mem_info_t dma_mem_info = { + .heap_caps = heap_caps, + .dma_alignment = 4, //legacy API behaviour is only check max dma buffer alignment + }; + return esp_dma_is_buffer_alignment_satisfied(ptr, size, &dma_mem_info); +} + +esp_err_t esp_dma_get_alignment(void *gdma_chan_handle, const dma_alignment_info_t *info, size_t *alignment) +{ + ESP_RETURN_ON_FALSE(info && alignment, ESP_ERR_INVALID_ARG, TAG, "null pointer"); + +#if SOC_GDMA_SUPPORTED + if (gdma_chan_handle) { + gdma_channel_handle_t dma_chan = (gdma_channel_handle_t)gdma_chan_handle; + gdma_alignment_info_t gdma_info = {}; + memcpy(&gdma_info, info, sizeof(gdma_alignment_info_t)); + ESP_RETURN_ON_ERROR(gdma_get_alignment(dma_chan, &gdma_info, alignment), TAG, "failed to get gdma alignment"); + } else +#endif + { + //for esp32 and esp32s2 + *alignment = 4; + } + + return ESP_OK; } diff --git a/components/esp_hw_support/dma/gdma.c b/components/esp_hw_support/dma/gdma.c index a619205cb6..711e6e5980 100644 --- a/components/esp_hw_support/dma/gdma.c +++ b/components/esp_hw_support/dma/gdma.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -944,3 +944,34 @@ static esp_err_t gdma_install_tx_interrupt(gdma_tx_channel_t *tx_chan) err: return ret; } + +esp_err_t gdma_get_alignment(gdma_channel_handle_t dma_chan, const gdma_alignment_info_t *info, size_t *alignment) +{ + ESP_RETURN_ON_FALSE(dma_chan && info && alignment, ESP_ERR_INVALID_ARG, TAG, "null pointer"); + bool desc_on_psram = info->is_desc && info->on_psram; + ESP_RETURN_ON_FALSE(!desc_on_psram, ESP_ERR_INVALID_ARG, TAG, "should not place descriptor on psram"); + + if (info->is_desc) { + if (dma_chan->pair->group->bus_id == SOC_GDMA_BUS_AHB) { + *alignment = GDMA_LL_AHB_DESC_ALIGNMENT; + } +#if SOC_AXI_GDMA_SUPPORTED + else if (dma_chan->pair->group->bus_id == SOC_GDMA_BUS_AXI) { + *alignment = GDMA_LL_AXI_DESC_ALIGNMENT; + } +#endif + } else { + if (dma_chan->psram_alignment == 0 && dma_chan->sram_alignment == 0) { + ESP_LOGI(TAG, "gdma_set_transfer_ability isn't called before, use fallback alignment"); + *alignment = 4; + } else { + if (info->on_psram) { + *alignment = dma_chan->psram_alignment; + } else { + *alignment = dma_chan->sram_alignment; + } + } + } + + return ESP_OK; +} diff --git a/components/esp_hw_support/dma/include/esp_dma_utils.h b/components/esp_hw_support/dma/include/esp_dma_utils.h index c0b613495c..8f0d17f40c 100644 --- a/components/esp_hw_support/dma/include/esp_dma_utils.h +++ b/components/esp_hw_support/dma/include/esp_dma_utils.h @@ -9,11 +9,86 @@ #include #include #include "esp_err.h" +#include "esp_heap_caps.h" #ifdef __cplusplus extern "C" { #endif +/** + * @breif DMA Mem info + */ +typedef struct { + int heap_caps; ///< See heap caps + size_t dma_alignment; ///< DMA alignment + size_t custom_alignment; ///< Set this if you have custom alignment. E.g. if `psram_trans_align` is set when using GDMA driver, or you're using IP self DMA (e.g. SDMMC) +} esp_dma_mem_info_t; + +/** + * @brief Helper function for malloc a DMA capable memory buffer + * + * @param[in] size Size in bytes, the amount of memory to allocate + * @param[in] dma_mem_info DMA and memory info, see `esp_dma_mem_info_t` + * @param[out] out_ptr A pointer to the memory allocated successfully + * @param[out] actual_size Actual size for allocation in bytes, when the size you specified doesn't meet the DMA alignment requirements, this value might be bigger than the size you specified. Set null if you don't care this value. + * + * @return + * - ESP_OK: + * - ESP_ERR_INVALID_ARG: Invalid argument + * - ESP_ERR_NO_MEM: No enough memory for allocation + */ +esp_err_t esp_dma_capable_malloc(size_t size, const esp_dma_mem_info_t *dma_mem_info, void **out_ptr, size_t *actual_size); + +/** + * @brief Helper function for calloc a DMA capable memory buffer + * + * @param[in] size Size in bytes, the amount of memory to allocate + * @param[in] dma_mem_info DMA and memory info, see `esp_dma_mem_info_t` + * @param[out] out_ptr A pointer to the memory allocated successfully + * @param[out] actual_size Actual size for allocation in bytes, when the size you specified doesn't meet the DMA alignment requirements, this value might be bigger than the size you specified. Set null if you don't care this value. + * + * @return + * - ESP_OK: + * - ESP_ERR_INVALID_ARG: Invalid argument + * - ESP_ERR_NO_MEM: No enough memory for allocation + */ +esp_err_t esp_dma_capable_calloc(size_t n, size_t size, const esp_dma_mem_info_t *dma_mem_info, void **out_ptr, size_t *actual_size); + +/** + * @brief Helper function to check if a DMA buffer meets alignment requirements + * + * @param[in] ptr Pointer to the buffer + * @param[in] size Size of the buffer + * @param[in] dma_mem_info DMA and memory info, see `esp_dma_mem_info_t` + * + * @return + * - True: Buffer is aligned + * - False: Buffer is not aligned, or buffer is not DMA capable + */ +bool esp_dma_is_buffer_alignment_satisfied(const void *ptr, size_t size, esp_dma_mem_info_t *dma_mem_info); + +/** + * @brief Needed info to get GDMA alignment + */ +typedef struct { + bool is_desc; + bool on_psram; +} dma_alignment_info_t; + +/** + * @brief Helper to get DMA alignment + * + * @param[in] gdma_chan_handle GDMA channel handle, if no GDMA supported, set it to NULL + * @param[in] info DMA alignment info + * @param[out] alignment Alignment + * + * @return + * - ESP_OK + * - ESP_ERR_INVALID_ARG Invalid argument + */ +esp_err_t esp_dma_get_alignment(void *gdma_chan_handle, const dma_alignment_info_t *info, size_t *alignment); + +//-----------------------Deprecated APIs-----------------------// /** * DMA malloc flags */ @@ -23,35 +98,16 @@ extern "C" { #define ESP_DMA_MALLOC_FLAG_PSRAM BIT(0) /** - * @brief Helper function for malloc a DMA capable memory buffer - * - * @param[in] size Size in bytes, the amount of memory to allocate - * @param[in] flags Flags, see `ESP_DMA_MALLOC_FLAG_x` - * @param[out] out_ptr A pointer to the memory allocated successfully - * @param[out] actual_size Actual size for allocation in bytes, when the size you specified doesn't meet the DMA alignment requirements, this value might be bigger than the size you specified. Set null if you don't care this value. - * - * @return - * - ESP_OK: - * - ESP_ERR_INVALID_ARG: Invalid argument - * - ESP_ERR_NO_MEM: No enough memory for allocation + * @note This API will use MAX alignment requirement */ -esp_err_t esp_dma_malloc(size_t size, uint32_t flags, void **out_ptr, size_t *actual_size); +esp_err_t esp_dma_malloc(size_t size, uint32_t flags, void **out_ptr, size_t *actual_size) +__attribute__((deprecated("esp_dma_malloc is deprecated, please use esp_dma_capable_malloc"))); /** - * @brief Helper function for calloc a DMA capable memory buffer - * - * @param[in] n Number of continuing chunks of memory to allocate - * @param[in] size Size of one chunk, in bytes - * @param[in] flags Flags, see `ESP_DMA_MALLOC_FLAG_x` - * @param[out] out_ptr A pointer to the memory allocated successfully - * @param[out] actual_size Actual size for allocation in bytes, when the size you specified doesn't meet the cache alignment requirements, this value might be bigger than the size you specified. Set null if you don't care this value. - * - * @return - * - ESP_OK: - * - ESP_ERR_INVALID_ARG: Invalid argument - * - ESP_ERR_NO_MEM: No enough memory for allocation + * @note This API will use MAX alignment requirement */ -esp_err_t esp_dma_calloc(size_t n, size_t size, uint32_t flags, void **out_ptr, size_t *actual_size); +esp_err_t esp_dma_calloc(size_t n, size_t size, uint32_t flags, void **out_ptr, size_t *actual_size) +__attribute__((deprecated("esp_dma_calloc is deprecated, please use esp_dma_capable_calloc"))); /** * @brief DMA buffer location @@ -63,17 +119,10 @@ typedef enum { } esp_dma_buf_location_t; /** - * @brief Helper function to check if a buffer meets DMA alignment requirements - * - * @param[in] ptr Pointer to the buffer - * @param[in] size Size of the buffer - * @param[in] location Location of the DMA buffer, see `esp_dma_buf_location_t` - * - * @return - * - True: Buffer is aligned - * - False: Buffer is not aligned, or buffer is not DMA capable + * @note This API will use MAX alignment requirement */ -bool esp_dma_is_buffer_aligned(const void *ptr, size_t size, esp_dma_buf_location_t location); +bool esp_dma_is_buffer_aligned(const void *ptr, size_t size, esp_dma_buf_location_t location) +__attribute__((deprecated("esp_dma_is_buffer_aligned is deprecated, please use esp_dma_is_buffer_alignment_satisfied"))); #ifdef __cplusplus } diff --git a/components/esp_hw_support/dma/include/esp_private/gdma.h b/components/esp_hw_support/dma/include/esp_private/gdma.h index 2d61d531be..8dee53e7d8 100644 --- a/components/esp_hw_support/dma/include/esp_private/gdma.h +++ b/components/esp_hw_support/dma/include/esp_private/gdma.h @@ -457,6 +457,26 @@ esp_err_t gdma_config_crc_calculator(gdma_channel_handle_t dma_chan, const gdma_ esp_err_t gdma_crc_get_result(gdma_channel_handle_t dma_chan, uint32_t *result); #endif // SOC_GDMA_SUPPORT_CRC +/** + * @brief Needed info to get GDMA alignment + */ +typedef struct { + bool is_desc; + bool on_psram; +} gdma_alignment_info_t; + +/** + * @brief Get GDMA alignment from the channel handle + * + * @param[in] dma_chan GDMA channel handle + * @param[in] info GDMA alignment info + * @param[out] alignment Alignment + * + * @return + * - ESP_OK + * - ESP_ERR_INVALID_ARG Invalid argument + */ +esp_err_t gdma_get_alignment(gdma_channel_handle_t dma_chan, const gdma_alignment_info_t *info, size_t *alignment); #ifdef __cplusplus } #endif diff --git a/components/esp_hw_support/test_apps/dma/main/CMakeLists.txt b/components/esp_hw_support/test_apps/dma/main/CMakeLists.txt index b923e9882f..d7baeb0936 100644 --- a/components/esp_hw_support/test_apps/dma/main/CMakeLists.txt +++ b/components/esp_hw_support/test_apps/dma/main/CMakeLists.txt @@ -1,4 +1,4 @@ -set(srcs "test_app_main.c") +set(srcs "test_app_main.c" "test_dma_utils.c") if(CONFIG_SOC_ASYNC_MEMCPY_SUPPORTED) list(APPEND srcs "test_async_memcpy.c") diff --git a/components/esp_hw_support/test_apps/dma/main/test_dma_utils.c b/components/esp_hw_support/test_apps/dma/main/test_dma_utils.c new file mode 100644 index 0000000000..85420260c9 --- /dev/null +++ b/components/esp_hw_support/test_apps/dma/main/test_dma_utils.c @@ -0,0 +1,155 @@ +/* + * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include +#include +#include "sdkconfig.h" +#include "unity.h" +#include "esp_log.h" +#include "esp_dma_utils.h" +#include "esp_private/esp_cache_private.h" +#include "esp_private/gdma.h" +#include "soc/soc_caps.h" + +#define ALIGN_UP_BY(num, align) (((num) + ((align) - 1)) & ~((align) - 1)) + +static const char *TAG = "test_dma_utils"; + + +#if CONFIG_SPIRAM +/** + * To test the API logic is correct, here we simply use max value under default sdkconfig + */ +#if CONFIG_IDF_TARGET_ESP32P4 +#define TEST_BUFFER_PSRAM_ALIGNMENT 64 +#else +#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2 +#define TEST_BUFFER_PSRAM_ALIGNMENT 4 +#else +#define TEST_BUFFER_PSRAM_ALIGNMENT 32 +#endif +#endif + +TEST_CASE("test esp_dma_capable_malloc for PSRAM", "[dma_utils]") +{ + size_t test_size = 0; + void *test_ptr = NULL; + size_t actual_size = 0; + + esp_dma_mem_info_t dma_mem_info = { + .heap_caps = MALLOC_CAP_SPIRAM, + .dma_alignment = 4, + .custom_alignment = 4, + }; + + //------ psram ------// + //aligned + test_size = TEST_BUFFER_PSRAM_ALIGNMENT; + ESP_LOGI(TAG, "to alloc 0x%zx", test_size); + TEST_ESP_OK(esp_dma_capable_malloc(test_size, &dma_mem_info, &test_ptr, &actual_size)); + ESP_LOGI(TAG, "get test_ptr: %p, actual_size: 0x%zx", test_ptr, actual_size); + TEST_ASSERT((uint32_t)test_ptr % TEST_BUFFER_PSRAM_ALIGNMENT == 0); + TEST_ASSERT(test_size == actual_size); + free(test_ptr); + + //unaligned + test_size = TEST_BUFFER_PSRAM_ALIGNMENT + TEST_BUFFER_PSRAM_ALIGNMENT / 2; + ESP_LOGI(TAG, "to alloc 0x%zx", test_size); + TEST_ESP_OK(esp_dma_capable_malloc(test_size, &dma_mem_info, &test_ptr, &actual_size)); + ESP_LOGI(TAG, "get test_ptr: %p, actual_size: 0x%zx", test_ptr, actual_size); + TEST_ASSERT((uint32_t)test_ptr % TEST_BUFFER_PSRAM_ALIGNMENT == 0); + TEST_ASSERT(ALIGN_UP_BY(test_size, TEST_BUFFER_PSRAM_ALIGNMENT) == actual_size); + free(test_ptr); +} +#endif + +TEST_CASE("test custom alignment", "[dma_utils]") +{ + size_t test_size = 0; + void *test_ptr = NULL; + size_t actual_size = 0; + size_t custom_alignment = 512; + + esp_dma_mem_info_t dma_mem_info = { + .heap_caps = MALLOC_CAP_SPIRAM, + .dma_alignment = 4, + .custom_alignment = custom_alignment, + }; + test_size = custom_alignment + 3; + ESP_LOGI(TAG, "to alloc 0x%zx", test_size); + TEST_ESP_OK(esp_dma_capable_malloc(test_size, &dma_mem_info, &test_ptr, &actual_size)); + ESP_LOGI(TAG, "get test_ptr: %p, actual_size: 0x%zx", test_ptr, actual_size); + TEST_ASSERT((uint32_t)test_ptr % custom_alignment == 0); + TEST_ASSERT(ALIGN_UP_BY(test_size, custom_alignment) == actual_size); + free(test_ptr); +} + +TEST_CASE("test esp_dma_is_buffer_alignment_satisfied", "[dma_utils]") +{ + size_t test_size = 64; + void *test_ptr = NULL; + + esp_dma_mem_info_t dma_mem_info = { + .heap_caps = MALLOC_CAP_DMA, + .dma_alignment = 4, + }; + TEST_ESP_OK(esp_dma_capable_malloc(test_size, &dma_mem_info, &test_ptr, NULL)); + ESP_LOGI(TAG, "test_ptr %p", test_ptr); + bool is_aligned = esp_dma_is_buffer_alignment_satisfied(test_ptr, test_size, &dma_mem_info); + TEST_ASSERT(is_aligned); + is_aligned = esp_dma_is_buffer_alignment_satisfied(test_ptr + 3, test_size, &dma_mem_info); + TEST_ASSERT(!is_aligned); +} + + +#if CONFIG_IDF_TARGET_ESP32P4 +#define TEST_DMA_ALIGNMENT_INT 8 +#else +#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2 +#define TEST_DMA_ALIGNMENT_INT 4 +#else +#define TEST_DMA_ALIGNMENT_INT 8 +#endif +#endif + +TEST_CASE("test esp_dma_get_alignment", "[dma_utils]") +{ + size_t dma_alignment = 0; + gdma_channel_handle_t tx_channel = NULL; +#if SOC_GDMA_SUPPORTED + gdma_channel_alloc_config_t channel_config = {}; + channel_config.direction = GDMA_CHANNEL_DIRECTION_TX; + + TEST_ESP_OK(gdma_new_ahb_channel(&channel_config, &tx_channel)); + + gdma_transfer_ability_t ability = { + .psram_trans_align = 0, + .sram_trans_align = 8, + }; + TEST_ESP_OK(gdma_set_transfer_ability(tx_channel, &ability)); +#endif + + dma_alignment_info_t internal_info = {}; + + TEST_ESP_OK(esp_dma_get_alignment(tx_channel, &internal_info, &dma_alignment)); + ESP_LOGI(TAG, "dma_alignment: 0x%x", dma_alignment); + TEST_ASSERT(dma_alignment == TEST_DMA_ALIGNMENT_INT); +} + +#if SOC_GDMA_SUPPORTED +TEST_CASE("test esp_dma_get_alignment with no transfer ability set", "[dma_utils]") +{ + size_t dma_alignment = 0; + gdma_channel_handle_t tx_channel = NULL; + gdma_channel_alloc_config_t channel_config = {}; + channel_config.direction = GDMA_CHANNEL_DIRECTION_TX; + TEST_ESP_OK(gdma_new_ahb_channel(&channel_config, &tx_channel)); + + dma_alignment_info_t internal_info = {}; + TEST_ESP_OK(esp_dma_get_alignment(tx_channel, &internal_info, &dma_alignment)); + ESP_LOGI(TAG, "dma_alignment: 0x%x", dma_alignment); + TEST_ASSERT(dma_alignment == 4); +} +#endif diff --git a/components/esp_mm/esp_cache.c b/components/esp_mm/esp_cache.c index cc04ba42d6..825f77534b 100644 --- a/components/esp_mm/esp_cache.c +++ b/components/esp_mm/esp_cache.c @@ -218,10 +218,6 @@ esp_err_t esp_cache_get_alignment(uint32_t flags, size_t *out_alignment) } data_cache_line_size = cache_hal_get_cache_line_size(cache_level, CACHE_TYPE_DATA); - if (data_cache_line_size == 0) { - //default alignment - data_cache_line_size = 4; - } *out_alignment = data_cache_line_size; diff --git a/components/hal/esp32c2/include/hal/gdma_ll.h b/components/hal/esp32c2/include/hal/gdma_ll.h index 54a93d54cc..6bf41c6a50 100644 --- a/components/hal/esp32c2/include/hal/gdma_ll.h +++ b/components/hal/esp32c2/include/hal/gdma_ll.h @@ -47,6 +47,8 @@ extern "C" { #define GDMA_LL_AHB_PAIRS_PER_GROUP 1 // Number of GDMA pairs in each AHB group #define GDMA_LL_AHB_TX_RX_SHARE_INTERRUPT 1 // TX and RX channel in the same pair will share the same interrupt source number +#define GDMA_LL_AHB_DESC_ALIGNMENT 4 + ///////////////////////////////////// Common ///////////////////////////////////////// /** diff --git a/components/hal/esp32c3/include/hal/gdma_ll.h b/components/hal/esp32c3/include/hal/gdma_ll.h index deaf734889..a6cb889b7d 100644 --- a/components/hal/esp32c3/include/hal/gdma_ll.h +++ b/components/hal/esp32c3/include/hal/gdma_ll.h @@ -47,6 +47,8 @@ extern "C" { #define GDMA_LL_AHB_PAIRS_PER_GROUP 3 // Number of GDMA pairs in each AHB group #define GDMA_LL_AHB_TX_RX_SHARE_INTERRUPT 1 // TX and RX channel in the same pair will share the same interrupt source number +#define GDMA_LL_AHB_DESC_ALIGNMENT 4 + ///////////////////////////////////// Common ///////////////////////////////////////// /** diff --git a/components/hal/esp32c6/include/hal/gdma_ll.h b/components/hal/esp32c6/include/hal/gdma_ll.h index 310327aef1..78dd95c5c3 100644 --- a/components/hal/esp32c6/include/hal/gdma_ll.h +++ b/components/hal/esp32c6/include/hal/gdma_ll.h @@ -50,6 +50,8 @@ extern "C" { #define GDMA_LL_AHB_NUM_GROUPS 1 // Number of AHB GDMA groups #define GDMA_LL_AHB_PAIRS_PER_GROUP 3 // Number of GDMA pairs in each AHB group +#define GDMA_LL_AHB_DESC_ALIGNMENT 4 + #define GDMA_LL_TX_ETM_EVENT_TABLE(group, chan, event) \ (uint32_t[1][3][GDMA_ETM_EVENT_MAX]){{{ \ [GDMA_ETM_EVENT_EOF] = GDMA_EVT_OUT_EOF_CH0, \ diff --git a/components/hal/esp32h2/include/hal/gdma_ll.h b/components/hal/esp32h2/include/hal/gdma_ll.h index 310327aef1..78dd95c5c3 100644 --- a/components/hal/esp32h2/include/hal/gdma_ll.h +++ b/components/hal/esp32h2/include/hal/gdma_ll.h @@ -50,6 +50,8 @@ extern "C" { #define GDMA_LL_AHB_NUM_GROUPS 1 // Number of AHB GDMA groups #define GDMA_LL_AHB_PAIRS_PER_GROUP 3 // Number of GDMA pairs in each AHB group +#define GDMA_LL_AHB_DESC_ALIGNMENT 4 + #define GDMA_LL_TX_ETM_EVENT_TABLE(group, chan, event) \ (uint32_t[1][3][GDMA_ETM_EVENT_MAX]){{{ \ [GDMA_ETM_EVENT_EOF] = GDMA_EVT_OUT_EOF_CH0, \ diff --git a/components/hal/esp32p4/include/hal/gdma_ll.h b/components/hal/esp32p4/include/hal/gdma_ll.h index f7573cf1ac..f058a9af7c 100644 --- a/components/hal/esp32p4/include/hal/gdma_ll.h +++ b/components/hal/esp32p4/include/hal/gdma_ll.h @@ -45,6 +45,9 @@ #define GDMA_LL_AHB_MAX_CRC_BIT_WIDTH 32 // Max CRC bit width supported by AHB GDMA #define GDMA_LL_AXI_MAX_CRC_BIT_WIDTH 16 // Max CRC bit width supported by AXI GDMA +#define GDMA_LL_AHB_DESC_ALIGNMENT 4 +#define GDMA_LL_AXI_DESC_ALIGNMENT 8 + #define GDMA_LL_TX_ETM_EVENT_TABLE(group, chan, event) \ (uint32_t[2][GDMA_ETM_EVENT_MAX]){ \ { \ diff --git a/components/hal/esp32s3/include/hal/gdma_ll.h b/components/hal/esp32s3/include/hal/gdma_ll.h index c3f16bcbfb..fa151f0e73 100644 --- a/components/hal/esp32s3/include/hal/gdma_ll.h +++ b/components/hal/esp32s3/include/hal/gdma_ll.h @@ -60,6 +60,8 @@ extern "C" { #define GDMA_LL_AHB_NUM_GROUPS 1 // Number of AHB GDMA groups #define GDMA_LL_AHB_PAIRS_PER_GROUP 5 // Number of GDMA pairs in each AHB group +#define GDMA_LL_AHB_DESC_ALIGNMENT 4 + ///////////////////////////////////// Common ///////////////////////////////////////// /** diff --git a/components/hal/hal_utils.c b/components/hal/hal_utils.c index 1ef92ffe11..b214ce3cdf 100644 --- a/components/hal/hal_utils.c +++ b/components/hal/hal_utils.c @@ -7,25 +7,6 @@ #include "hal/hal_utils.h" #include "hal/assert.h" -/** - * @brief helper function, calculate the Greatest Common Divisor - * @note gcd(a, b) = gcd(b, a % b) - * @param a bigger value - * @param b smaller value - * @return result of gcd(a, b) - */ -__attribute__((always_inline)) -static inline uint32_t _gcd(uint32_t a, uint32_t b) -{ - uint32_t c = a % b; - while (c != 0) { - a = b; - b = c; - c = a % b; - } - return b; -} - __attribute__((always_inline)) static inline uint32_t _sub_abs(uint32_t a, uint32_t b) { diff --git a/components/hal/include/hal/hal_utils.h b/components/hal/include/hal/hal_utils.h index da8023c7a8..c5d7077470 100644 --- a/components/hal/include/hal/hal_utils.h +++ b/components/hal/include/hal/hal_utils.h @@ -102,6 +102,59 @@ static inline uint8_t hal_utils_bitwise_reverse8(uint8_t n) return n; } +/** + * @brief helper function, calculate the Greatest Common Divisor + * @note gcd(a, b) = gcd(b, a % b) + * @param a bigger value + * @param b smaller value + * @return result of gcd(a, b) + */ +__attribute__((always_inline)) +static inline uint32_t _gcd(uint32_t a, uint32_t b) +{ + uint32_t c = a % b; + while (c != 0) { + a = b; + b = c; + c = a % b; + } + return b; +} + +/** + * @brief Get the least common multiple of two integer + * + * @param[in] Integer A + * @param[in] Integer B + * + * @return LCM of A and B + */ +__attribute__((always_inline)) +static inline uint32_t _lcm(uint32_t a, uint32_t b) +{ + a = a == 0 ? 1 : a; + b = b == 0 ? 1 : b; + return (a * b / _gcd(a, b)); +} + +/** + * @brief Get the least common multiple of three integer + * + * @param[in] Integer A + * @param[in] Integer B + * @param[in] Integer C + * + * @return LCM of A, B and C + */ +__attribute__((always_inline)) +static inline uint32_t _lcm_3(uint32_t a, uint32_t b, uint32_t c) +{ + a = a == 0 ? 1 : a; + b = b == 0 ? 1 : b; + c = c == 0 ? 1 : c; + return _lcm(a, _lcm(b, c)); +} + #ifdef __cplusplus } #endif diff --git a/components/sdmmc/sdmmc_cmd.c b/components/sdmmc/sdmmc_cmd.c index 1a3e331d54..b0035c53dd 100644 --- a/components/sdmmc/sdmmc_cmd.c +++ b/components/sdmmc/sdmmc_cmd.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -328,7 +328,11 @@ esp_err_t sdmmc_send_cmd_send_scr(sdmmc_card_t* card, sdmmc_scr_t *out_scr) esp_err_t err = ESP_FAIL; uint32_t *buf = NULL; size_t actual_size = 0; - err = esp_dma_malloc(datalen, 0, (void *)&buf, &actual_size); + esp_dma_mem_info_t dma_mem_info = { + .heap_caps = MALLOC_CAP_DMA, + .custom_alignment = 4, + }; + err = esp_dma_capable_malloc(datalen, &dma_mem_info, (void *)&buf, &actual_size); if (err != ESP_OK) { return err; } @@ -401,7 +405,11 @@ esp_err_t sdmmc_write_sectors(sdmmc_card_t* card, const void* src, esp_err_t err = ESP_OK; size_t block_size = card->csd.sector_size; - if (esp_dma_is_buffer_aligned(src, block_size * block_count, ESP_DMA_BUF_LOCATION_INTERNAL)) { + esp_dma_mem_info_t dma_mem_info = { + .heap_caps = MALLOC_CAP_DMA, + .custom_alignment = 4, + }; + if (esp_dma_is_buffer_alignment_satisfied(src, block_size * block_count, &dma_mem_info)) { err = sdmmc_write_sectors_dma(card, src, start_block, block_count, block_size * block_count); } else { // SDMMC peripheral needs DMA-capable buffers. Split the write into @@ -409,7 +417,7 @@ esp_err_t sdmmc_write_sectors(sdmmc_card_t* card, const void* src, // DMA-capable buffer. void *tmp_buf = NULL; size_t actual_size = 0; - err = esp_dma_malloc(block_size, 0, &tmp_buf, &actual_size); + err = esp_dma_capable_malloc(block_size, &dma_mem_info, &tmp_buf, &actual_size); if (err != ESP_OK) { return err; } @@ -519,7 +527,11 @@ esp_err_t sdmmc_read_sectors(sdmmc_card_t* card, void* dst, esp_err_t err = ESP_OK; size_t block_size = card->csd.sector_size; - if (esp_dma_is_buffer_aligned(dst, block_size * block_count, ESP_DMA_BUF_LOCATION_INTERNAL)) { + esp_dma_mem_info_t dma_mem_info = { + .heap_caps = MALLOC_CAP_DMA, + .custom_alignment = 4, + }; + if (esp_dma_is_buffer_alignment_satisfied(dst, block_size * block_count, &dma_mem_info)) { err = sdmmc_read_sectors_dma(card, dst, start_block, block_count, block_size * block_count); } else { // SDMMC peripheral needs DMA-capable buffers. Split the read into @@ -527,7 +539,7 @@ esp_err_t sdmmc_read_sectors(sdmmc_card_t* card, void* dst, // DMA-capable buffer. void *tmp_buf = NULL; size_t actual_size = 0; - err = esp_dma_malloc(block_size, 0, &tmp_buf, &actual_size); + err = esp_dma_capable_malloc(block_size, &dma_mem_info, &tmp_buf, &actual_size); if (err != ESP_OK) { return err; } diff --git a/components/sdmmc/sdmmc_common.c b/components/sdmmc/sdmmc_common.c index 541710dc27..c264d41eba 100644 --- a/components/sdmmc/sdmmc_common.c +++ b/components/sdmmc/sdmmc_common.c @@ -340,7 +340,13 @@ esp_err_t sdmmc_allocate_aligned_buf(sdmmc_card_t* card) if (card->host.flags & SDMMC_HOST_FLAG_ALLOC_ALIGNED_BUF) { void* buf = NULL; size_t actual_size = 0; - esp_err_t ret = esp_dma_malloc(SDMMC_IO_BLOCK_SIZE, 0, &buf, &actual_size); + // esp_err_t ret = esp_dma_malloc(SDMMC_IO_BLOCK_SIZE, 0, &buf, &actual_size); + esp_dma_mem_info_t dma_mem_info = { + .heap_caps = MALLOC_CAP_DMA, + .custom_alignment = 4, + }; + esp_err_t ret = esp_dma_capable_malloc(SDMMC_IO_BLOCK_SIZE, &dma_mem_info, &buf, &actual_size); + if (ret != ESP_OK) { return ret; } diff --git a/components/sdmmc/sdmmc_io.c b/components/sdmmc/sdmmc_io.c index 5b7ef581db..7827844bc0 100644 --- a/components/sdmmc/sdmmc_io.c +++ b/components/sdmmc/sdmmc_io.c @@ -277,7 +277,11 @@ esp_err_t sdmmc_io_rw_extended(sdmmc_card_t* card, int func, .blklen = SDMMC_IO_BLOCK_SIZE /* TODO: read max block size from CIS */ }; - if (unlikely(datalen > 0 && !esp_dma_is_buffer_aligned(datap, buflen, ESP_DMA_BUF_LOCATION_AUTO))) { + esp_dma_mem_info_t dma_mem_info = { + .heap_caps = MALLOC_CAP_DMA, + .custom_alignment = 4, + }; + if (unlikely(datalen > 0 && !esp_dma_is_buffer_alignment_satisfied(datap, buflen, &dma_mem_info))) { if (datalen > SDMMC_IO_BLOCK_SIZE || card->host.dma_aligned_buffer == NULL) { // User gives unaligned buffer while `SDMMC_HOST_FLAG_ALLOC_ALIGNED_BUF` not set. return ESP_ERR_INVALID_ARG; @@ -386,7 +390,11 @@ esp_err_t sdmmc_io_write_bytes(sdmmc_card_t* card, uint32_t function, esp_err_t sdmmc_io_read_blocks(sdmmc_card_t* card, uint32_t function, uint32_t addr, void* dst, size_t size) { - if (unlikely(!esp_dma_is_buffer_aligned(dst, size, ESP_DMA_BUF_LOCATION_INTERNAL))) { + esp_dma_mem_info_t dma_mem_info = { + .heap_caps = MALLOC_CAP_DMA, + .custom_alignment = 4, + }; + if (unlikely(!esp_dma_is_buffer_alignment_satisfied(dst, size, &dma_mem_info))) { return ESP_ERR_INVALID_ARG; } return sdmmc_io_rw_extended(card, function, addr, @@ -397,7 +405,11 @@ esp_err_t sdmmc_io_read_blocks(sdmmc_card_t* card, uint32_t function, esp_err_t sdmmc_io_write_blocks(sdmmc_card_t* card, uint32_t function, uint32_t addr, const void* src, size_t size) { - if (unlikely(!esp_dma_is_buffer_aligned(src, size, ESP_DMA_BUF_LOCATION_INTERNAL))) { + esp_dma_mem_info_t dma_mem_info = { + .heap_caps = MALLOC_CAP_DMA, + .custom_alignment = 4, + }; + if (unlikely(!esp_dma_is_buffer_alignment_satisfied(src, size, &dma_mem_info))) { return ESP_ERR_INVALID_ARG; } return sdmmc_io_rw_extended(card, function, addr, diff --git a/components/sdmmc/sdmmc_mmc.c b/components/sdmmc/sdmmc_mmc.c index 4d0c756f0d..e44fa76630 100644 --- a/components/sdmmc/sdmmc_mmc.c +++ b/components/sdmmc/sdmmc_mmc.c @@ -28,7 +28,11 @@ esp_err_t sdmmc_init_mmc_read_ext_csd(sdmmc_card_t* card) esp_err_t err = ESP_OK; uint8_t* ext_csd = NULL; size_t actual_size = 0; - err = esp_dma_malloc(EXT_CSD_MMC_SIZE, 0, (void *)&ext_csd, &actual_size); + esp_dma_mem_info_t dma_mem_info = { + .heap_caps = MALLOC_CAP_DMA, + .custom_alignment = 4, + }; + err = esp_dma_capable_malloc(EXT_CSD_MMC_SIZE, &dma_mem_info, (void *)&ext_csd, &actual_size); if (err != ESP_OK) { ESP_LOGE(TAG, "%s: could not allocate ext_csd", __func__); return err; @@ -255,7 +259,11 @@ esp_err_t sdmmc_init_mmc_check_ext_csd(sdmmc_card_t* card) /* ensure EXT_CSD buffer is available before starting any SD-card operation */ uint8_t* ext_csd = NULL; size_t actual_size = 0; - esp_err_t err = esp_dma_malloc(EXT_CSD_MMC_SIZE, 0, (void *)&ext_csd, &actual_size); + esp_dma_mem_info_t dma_mem_info = { + .heap_caps = MALLOC_CAP_DMA, + .custom_alignment = 4, + }; + esp_err_t err = esp_dma_capable_malloc(EXT_CSD_MMC_SIZE, &dma_mem_info, (void *)&ext_csd, &actual_size); if (err != ESP_OK) { ESP_LOGE(TAG, "%s: could not allocate ext_csd", __func__); return err; diff --git a/components/sdmmc/sdmmc_sd.c b/components/sdmmc/sdmmc_sd.c index 464ab1362b..f4d0fe7ed2 100644 --- a/components/sdmmc/sdmmc_sd.c +++ b/components/sdmmc/sdmmc_sd.c @@ -91,7 +91,11 @@ esp_err_t sdmmc_init_sd_ssr(sdmmc_card_t* card) */ uint32_t* sd_ssr = NULL; size_t actual_size = 0; - err = esp_dma_calloc(1, SD_SSR_SIZE, 0, (void *)&sd_ssr, &actual_size); + esp_dma_mem_info_t dma_mem_info = { + .heap_caps = MALLOC_CAP_DMA, + .custom_alignment = 4, + }; + err = esp_dma_capable_calloc(1, SD_SSR_SIZE, &dma_mem_info, (void *)&sd_ssr, &actual_size); if (err != ESP_OK) { ESP_LOGE(TAG, "%s: could not allocate sd_ssr", __func__); return err; @@ -239,7 +243,11 @@ esp_err_t sdmmc_enable_hs_mode(sdmmc_card_t* card) size_t actual_size = 0; sdmmc_switch_func_rsp_t *response = NULL; - esp_err_t err = esp_dma_malloc(sizeof(*response), 0, (void *)&response, &actual_size); + esp_dma_mem_info_t dma_mem_info = { + .heap_caps = MALLOC_CAP_DMA, + .custom_alignment = 4, + }; + esp_err_t err = esp_dma_capable_malloc(sizeof(*response), &dma_mem_info, (void *)&response, &actual_size); assert(actual_size == sizeof(*response)); if (err != ESP_OK) { return err; diff --git a/components/usb/hcd_dwc.c b/components/usb/hcd_dwc.c index 574dc0cace..1ec3de6771 100644 --- a/components/usb/hcd_dwc.c +++ b/components/usb/hcd_dwc.c @@ -1040,11 +1040,18 @@ static void port_obj_free(port_t *port) void *frame_list_alloc(size_t frame_list_len) { - void *frame_list = heap_caps_aligned_calloc(USB_DWC_FRAME_LIST_MEM_ALIGN, frame_list_len, sizeof(uint32_t), MALLOC_CAP_DMA); + esp_err_t ret = ESP_FAIL; + void *frame_list = NULL; + esp_dma_mem_info_t dma_mem_info = { + .heap_caps = MALLOC_CAP_DMA, + .custom_alignment = USB_DWC_FRAME_LIST_MEM_ALIGN, + }; + ret = esp_dma_capable_calloc(frame_list_len, sizeof(uint32_t), &dma_mem_info, &frame_list, NULL); + assert(ret != ESP_ERR_INVALID_ARG); // Both Frame List start address and size should be already cache aligned so this is only a sanity check if (frame_list) { - if (!esp_dma_is_buffer_aligned(frame_list, frame_list_len * sizeof(uint32_t), ESP_DMA_BUF_LOCATION_AUTO)) { + if (!esp_dma_is_buffer_alignment_satisfied(frame_list, frame_list_len * sizeof(uint32_t), &dma_mem_info)) { // This should never happen heap_caps_free(frame_list); frame_list = NULL; @@ -1065,10 +1072,17 @@ void *transfer_descriptor_list_alloc(size_t list_len, size_t *list_len_bytes_out *list_len_bytes_out = list_len * sizeof(usb_dwc_ll_dma_qtd_t); #endif // SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE - void *qtd_list = heap_caps_aligned_calloc(USB_DWC_QTD_LIST_MEM_ALIGN, *list_len_bytes_out, 1, MALLOC_CAP_DMA); + esp_err_t ret = ESP_FAIL; + void *qtd_list = NULL; + esp_dma_mem_info_t dma_mem_info = { + .heap_caps = MALLOC_CAP_DMA, + .custom_alignment = USB_DWC_QTD_LIST_MEM_ALIGN, + }; + ret = esp_dma_capable_calloc(*list_len_bytes_out, 1, &dma_mem_info, &qtd_list, NULL); + assert(ret != ESP_ERR_INVALID_ARG); if (qtd_list) { - if (!esp_dma_is_buffer_aligned(qtd_list, *list_len_bytes_out * sizeof(usb_dwc_ll_dma_qtd_t), ESP_DMA_BUF_LOCATION_AUTO)) { + if (!esp_dma_is_buffer_alignment_satisfied(qtd_list, *list_len_bytes_out * sizeof(usb_dwc_ll_dma_qtd_t), &dma_mem_info)) { // This should never happen heap_caps_free(qtd_list); qtd_list = NULL; diff --git a/components/usb/test_apps/hcd/main/test_hcd_common.c b/components/usb/test_apps/hcd/main/test_hcd_common.c index 25145c3f24..80f4e5c275 100644 --- a/components/usb/test_apps/hcd/main/test_hcd_common.c +++ b/components/usb/test_apps/hcd/main/test_hcd_common.c @@ -266,8 +266,14 @@ urb_t *test_hcd_alloc_urb(int num_isoc_packets, size_t data_buffer_size) urb_t *urb = heap_caps_calloc(1, sizeof(urb_t) + (sizeof(usb_isoc_packet_desc_t) * num_isoc_packets), MALLOC_CAP_DEFAULT); void *data_buffer; size_t real_size; - esp_dma_malloc(data_buffer_size, 0, &data_buffer, &real_size); - + esp_dma_mem_info_t dma_mem_info = { + .dma_type = ESP_DMA_OTHERS, + .mem_flags = { + .dir = ESP_DMA_MEM_DIR_DONT_CARE, + }, + .custom_alignment = 4, + }; + esp_dma_capable_malloc(data_buffer_size, &dma_mem_info, &data_buffer, &real_size); TEST_ASSERT_NOT_NULL_MESSAGE(urb, "Failed to allocate URB"); TEST_ASSERT_NOT_NULL_MESSAGE(data_buffer, "Failed to allocate transfer buffer"); diff --git a/components/usb/usb_private.c b/components/usb/usb_private.c index 17a2220e86..323bc916f9 100644 --- a/components/usb/usb_private.c +++ b/components/usb/usb_private.c @@ -14,7 +14,14 @@ urb_t *urb_alloc(size_t data_buffer_size, int num_isoc_packets) urb_t *urb = heap_caps_calloc(1, sizeof(urb_t) + (sizeof(usb_isoc_packet_desc_t) * num_isoc_packets), MALLOC_CAP_DEFAULT); void *data_buffer; size_t real_size; - esp_dma_malloc(data_buffer_size, 0, &data_buffer, &real_size); + esp_dma_mem_info_t dma_mem_info = { + .dma_type = ESP_DMA_OTHERS, + .mem_flags = { + .dir = ESP_DMA_MEM_DIR_DONT_CARE, + }, + .custom_alignment = 4, + }; + esp_dma_capable_malloc(data_buffer_size, &dma_mem_info, &data_buffer, &real_size); if (urb == NULL || data_buffer == NULL) { goto err; } diff --git a/docs/en/api-reference/system/mm_sync.rst b/docs/en/api-reference/system/mm_sync.rst index 6aa0ec3819..3a86ae06d1 100644 --- a/docs/en/api-reference/system/mm_sync.rst +++ b/docs/en/api-reference/system/mm_sync.rst @@ -106,10 +106,10 @@ Memory Allocation Helper cache memory synchronization is usually considered when DMA is involved. ESP-IDF provides an API to do memory allocation that can meet the alignment requirement from both the cache and the DMA. -- :cpp:func:`esp_dma_malloc`, this API allocates a chunk of memory that meets the alignment requirement from both the cache and the DMA. -- :cpp:func:`esp_dma_calloc`, this API allocates a chunk of memory that meets the alignment requirement from both the cache and the DMA. The initialized value in the memory is set to zero. +- :cpp:func:`esp_dma_capable_malloc`, this API allocates a chunk of memory that meets the alignment requirement from both the cache and the DMA. +- :cpp:func:`esp_dma_capable_calloc`, this API allocates a chunk of memory that meets the alignment requirement from both the cache and the DMA. The initialized value in the memory is set to zero. -You can also use :c:macro:`ESP_DMA_MALLOC_FLAG_PSRAM` to allocate from the PSRAM. +You can also use :cpp:member:`esp_dma_mem_info_t::on_psram` to allocate from the PSRAM. Warning for Address Alignment Requirement diff --git a/examples/peripherals/lcd/i80_controller/main/i80_controller_example_main.c b/examples/peripherals/lcd/i80_controller/main/i80_controller_example_main.c index 9f063d8782..745fb6b4ad 100644 --- a/examples/peripherals/lcd/i80_controller/main/i80_controller_example_main.c +++ b/examples/peripherals/lcd/i80_controller/main/i80_controller_example_main.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: CC0-1.0 */ @@ -447,12 +447,16 @@ void app_main(void) // it's recommended to choose the size of the draw buffer(s) to be at least 1/10 screen sized lv_color_t *buf1 = NULL; lv_color_t *buf2 = NULL; - uint32_t malloc_flags = 0; + esp_dma_mem_info_t dma_mem_info = { + .dma_alignment = 4, #if CONFIG_EXAMPLE_LCD_I80_COLOR_IN_PSRAM - malloc_flags |= ESP_DMA_MALLOC_FLAG_PSRAM; + .heap_caps = MALLOC_CAP_SPIRAM, +#else + .heap_caps = MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL, #endif // CONFIG_EXAMPLE_LCD_I80_COLOR_IN_PSRAM - ESP_ERROR_CHECK(esp_dma_malloc(EXAMPLE_LCD_H_RES * 100 * sizeof(lv_color_t), malloc_flags, (void *)&buf1, NULL)); - ESP_ERROR_CHECK(esp_dma_malloc(EXAMPLE_LCD_H_RES * 100 * sizeof(lv_color_t), malloc_flags, (void *)&buf2, NULL)); + }; + ESP_ERROR_CHECK(esp_dma_capable_malloc(EXAMPLE_LCD_H_RES * 100 * sizeof(lv_color_t), &dma_mem_info, (void *)&buf1, NULL)); + ESP_ERROR_CHECK(esp_dma_capable_malloc(EXAMPLE_LCD_H_RES * 100 * sizeof(lv_color_t), &dma_mem_info, (void *)&buf2, NULL)); assert(buf1); assert(buf2); ESP_LOGI(TAG, "buf1@%p, buf2@%p", buf1, buf2); From 78f96c4466ef3304bbc7005ae0dc1cb6a52ba99b Mon Sep 17 00:00:00 2001 From: Armando Date: Wed, 24 Jan 2024 19:08:41 +0800 Subject: [PATCH 2/6] change(eth): use new esp_dma_calloc --- components/esp_eth/src/esp_eth_mac_esp_dma.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/components/esp_eth/src/esp_eth_mac_esp_dma.c b/components/esp_eth/src/esp_eth_mac_esp_dma.c index 7730c795b9..4a888715e0 100644 --- a/components/esp_eth/src/esp_eth_mac_esp_dma.c +++ b/components/esp_eth/src/esp_eth_mac_esp_dma.c @@ -531,15 +531,20 @@ esp_err_t emac_esp_new_dma(const emac_esp_dma_config_t* config, emac_esp_dma_han /* alloc memory for ethernet dma descriptor */ uint32_t desc_size = CONFIG_ETH_DMA_RX_BUFFER_NUM * sizeof(eth_dma_rx_descriptor_t) + CONFIG_ETH_DMA_TX_BUFFER_NUM * sizeof(eth_dma_tx_descriptor_t); - esp_dma_calloc(1, desc_size, 0, (void*)&emac_esp_dma->descriptors, NULL); + esp_dma_mem_info_t dma_mem_info = { + .heap_caps = MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA, + .dma_alignment = 4, + }; + esp_dma_capable_calloc(1, desc_size, &dma_mem_info, (void*)&emac_esp_dma->descriptors, NULL); + ESP_GOTO_ON_FALSE(emac_esp_dma->descriptors, ESP_ERR_NO_MEM, err, TAG, "no mem for descriptors"); /* alloc memory for ethernet dma buffer */ for (int i = 0; i < CONFIG_ETH_DMA_RX_BUFFER_NUM; i++) { - esp_dma_calloc(1, CONFIG_ETH_DMA_BUFFER_SIZE, 0, (void*)&emac_esp_dma->rx_buf[i], NULL); + esp_dma_capable_calloc(1, CONFIG_ETH_DMA_BUFFER_SIZE, &dma_mem_info, (void*)&emac_esp_dma->rx_buf[i], NULL); ESP_GOTO_ON_FALSE(emac_esp_dma->rx_buf[i], ESP_ERR_NO_MEM, err, TAG, "no mem for RX DMA buffers"); } for (int i = 0; i < CONFIG_ETH_DMA_TX_BUFFER_NUM; i++) { - esp_dma_calloc(1, CONFIG_ETH_DMA_BUFFER_SIZE, 0, (void*)&emac_esp_dma->tx_buf[i], NULL); + esp_dma_capable_calloc(1, CONFIG_ETH_DMA_BUFFER_SIZE, &dma_mem_info, (void*)&emac_esp_dma->tx_buf[i], NULL); ESP_GOTO_ON_FALSE(emac_esp_dma->tx_buf[i], ESP_ERR_NO_MEM, err, TAG, "no mem for TX DMA buffers"); } emac_hal_init(&emac_esp_dma->hal); From 40f38bea6fbc33b45da02aeea3f261f7e8137f0a Mon Sep 17 00:00:00 2001 From: gaoxu Date: Fri, 29 Mar 2024 11:36:27 +0800 Subject: [PATCH 3/6] feat(dma): refactor dma calloc function --- .codespellrc | 2 +- components/driver/deprecated/i2s_legacy.c | 6 +- components/esp_driver_i2s/i2s_common.c | 29 ++----- components/esp_driver_jpeg/jpeg_decode.c | 6 +- .../include/driver/sdmmc_default_configs.h | 1 + .../include/driver/sdmmc_host.h | 13 ++- components/esp_driver_sdmmc/src/sdmmc_host.c | 10 +++ .../include/driver/sdspi_host.h | 16 +++- components/esp_driver_sdspi/src/sdspi_host.c | 10 ++- components/esp_eth/src/esp_eth_mac_esp_dma.c | 6 +- components/esp_hw_support/dma/esp_dma_utils.c | 86 +++++++------------ components/esp_hw_support/dma/gdma.c | 31 ------- .../dma/include/esp_dma_utils.h | 35 +++----- .../dma/include/esp_private/gdma.h | 20 ----- .../test_apps/dma/main/test_dma_utils.c | 84 ++---------------- components/hal/esp32c5/include/hal/gdma_ll.h | 2 + components/hal/hal_utils.c | 2 +- components/hal/include/hal/hal_utils.h | 63 ++++++-------- .../mbedtls/port/aes/dma/esp_aes_dma_core.c | 13 ++- components/sdmmc/include/sd_protocol_types.h | 4 +- components/sdmmc/sdmmc_cmd.c | 26 +++--- components/sdmmc/sdmmc_common.c | 7 +- components/sdmmc/sdmmc_io.c | 26 +++--- components/sdmmc/sdmmc_mmc.c | 12 +-- components/sdmmc/sdmmc_sd.c | 12 +-- components/usb/hcd_dwc.c | 24 +++--- .../usb/test_apps/hcd/main/test_hcd_common.c | 6 +- components/usb/usb_private.c | 7 +- docs/en/api-reference/system/mm_sync.rst | 2 +- .../main/i80_controller_example_main.c | 6 +- 30 files changed, 204 insertions(+), 363 deletions(-) diff --git a/.codespellrc b/.codespellrc index 34d7b2674e..4ecd7ca7a6 100644 --- a/.codespellrc +++ b/.codespellrc @@ -1,4 +1,4 @@ [codespell] skip = build,*.yuv,components/fatfs/src/*,alice.txt,*.rgb -ignore-words-list = ser,dout,rsource,fram,inout +ignore-words-list = ser,dout,rsource,fram,inout,shs write-changes = true diff --git a/components/driver/deprecated/i2s_legacy.c b/components/driver/deprecated/i2s_legacy.c index 103163c9a6..d36b2e2945 100644 --- a/components/driver/deprecated/i2s_legacy.c +++ b/components/driver/deprecated/i2s_legacy.c @@ -576,9 +576,10 @@ static esp_err_t i2s_alloc_dma_buffer(i2s_port_t i2s_num, i2s_dma_t *dma_obj) for (int cnt = 0; cnt < buf_cnt; cnt++) { /* Allocate DMA buffer */ esp_dma_mem_info_t dma_mem_info = { - .heap_caps = MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA, - .dma_alignment = 4, + .extra_heap_caps = MALLOC_CAP_INTERNAL, + .dma_alignment_bytes = 4, }; + //TODO: IDF-9636 esp_dma_capable_calloc(1, sizeof(char) * dma_obj->buf_size, &dma_mem_info, (void **)&dma_obj->buf[cnt], NULL); ESP_GOTO_ON_FALSE(dma_obj->buf[cnt], ESP_ERR_NO_MEM, err, TAG, "Error malloc dma buffer"); #if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE @@ -587,7 +588,6 @@ static esp_err_t i2s_alloc_dma_buffer(i2s_port_t i2s_num, i2s_dma_t *dma_obj) /* Allocate DMA descriptor */ esp_dma_capable_calloc(1, sizeof(lldesc_t), &dma_mem_info, (void **)&dma_obj->desc[cnt], &desc_size); - // esp_dma_calloc(1, sizeof(lldesc_t), MALLOC_CAP_DEFAULT, (void **)&dma_obj->desc[cnt], &desc_size); ESP_GOTO_ON_FALSE(dma_obj->desc[cnt], ESP_ERR_NO_MEM, err, TAG, "Error malloc dma description entry"); } /* DMA descriptor must be initialize after all descriptor has been created, otherwise they can't be linked together as a chain */ diff --git a/components/esp_driver_i2s/i2s_common.c b/components/esp_driver_i2s/i2s_common.c index b52f5be039..e3042695f2 100644 --- a/components/esp_driver_i2s/i2s_common.c +++ b/components/esp_driver_i2s/i2s_common.c @@ -69,32 +69,15 @@ static const char *TAG = "i2s_common"; __attribute__((always_inline)) -inline void *i2s_dma_calloc(i2s_chan_handle_t handle, size_t num, size_t size, bool is_desc, size_t *actual_size) +inline void *i2s_dma_calloc(i2s_chan_handle_t handle, size_t num, size_t size, size_t *actual_size) { - esp_err_t ret = ESP_FAIL; void *ptr = NULL; - - size_t dma_alignment = 0; - void *gdma_chan_handle = NULL; -#if SOC_GDMA_SUPPORTED - gdma_chan_handle = handle->dma.dma_chan; -#endif - dma_alignment_info_t info = { - .is_desc = is_desc, - }; - ret = esp_dma_get_alignment(gdma_chan_handle, &info, &dma_alignment); - assert(ret == ESP_OK); - esp_dma_mem_info_t dma_mem_info = { - .heap_caps = MALLOC_CAP_DMA, - .dma_alignment = 4, + .extra_heap_caps = I2S_DMA_ALLOC_CAPS, + .dma_alignment_bytes = 4, }; + //TODO: IDF-9636 esp_dma_capable_calloc(num, size, &dma_mem_info, &ptr, actual_size); -#if CONFIG_IDF_TARGET_ESP32P4 - assert((int)ptr % 64 == 0); -#else - assert((int)ptr % 4 == 0); -#endif return ptr; } @@ -444,7 +427,7 @@ esp_err_t i2s_alloc_dma_desc(i2s_chan_handle_t handle, uint32_t num, uint32_t bu size_t desc_size = 0; for (int i = 0; i < num; i++) { /* Allocate DMA descriptor */ - handle->dma.desc[i] = (lldesc_t *) i2s_dma_calloc(handle, 1, sizeof(lldesc_t), true, &desc_size); + handle->dma.desc[i] = (lldesc_t *) i2s_dma_calloc(handle, 1, sizeof(lldesc_t), &desc_size); ESP_GOTO_ON_FALSE(handle->dma.desc[i], ESP_ERR_NO_MEM, err, TAG, "allocate DMA description failed"); handle->dma.desc[i]->owner = 1; handle->dma.desc[i]->eof = 1; @@ -452,7 +435,7 @@ esp_err_t i2s_alloc_dma_desc(i2s_chan_handle_t handle, uint32_t num, uint32_t bu handle->dma.desc[i]->length = bufsize; handle->dma.desc[i]->size = bufsize; handle->dma.desc[i]->offset = 0; - handle->dma.bufs[i] = (uint8_t *) i2s_dma_calloc(handle, 1, bufsize * sizeof(uint8_t), false, NULL); + handle->dma.bufs[i] = (uint8_t *) i2s_dma_calloc(handle, 1, bufsize * sizeof(uint8_t), NULL); ESP_GOTO_ON_FALSE(handle->dma.bufs[i], ESP_ERR_NO_MEM, err, TAG, "allocate DMA buffer failed"); #if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE esp_cache_msync(handle->dma.bufs[i], bufsize * sizeof(uint8_t), ESP_CACHE_MSYNC_FLAG_DIR_C2M); diff --git a/components/esp_driver_jpeg/jpeg_decode.c b/components/esp_driver_jpeg/jpeg_decode.c index 767c1d1693..7ccf3e5155 100644 --- a/components/esp_driver_jpeg/jpeg_decode.c +++ b/components/esp_driver_jpeg/jpeg_decode.c @@ -176,7 +176,11 @@ esp_err_t jpeg_decoder_process(jpeg_decoder_handle_t decoder_engine, const jpeg_ ESP_RETURN_ON_FALSE(decoder_engine, ESP_ERR_INVALID_ARG, TAG, "jpeg decode handle is null"); ESP_RETURN_ON_FALSE(decode_cfg, ESP_ERR_INVALID_ARG, TAG, "jpeg decode config is null"); ESP_RETURN_ON_FALSE(decode_outbuf, ESP_ERR_INVALID_ARG, TAG, "jpeg decode picture buffer is null"); - ESP_RETURN_ON_FALSE(esp_dma_is_buffer_aligned(decode_outbuf, outbuf_size, ESP_DMA_BUF_LOCATION_PSRAM), ESP_ERR_INVALID_ARG, TAG, "jpeg decode decode_outbuf or out_buffer size is not aligned, please use jpeg_alloc_decoder_mem to malloc your buffer"); + esp_dma_mem_info_t dma_mem_info = { + .dma_alignment_bytes = 4, + }; + //TODO: IDF-9637 + ESP_RETURN_ON_FALSE(esp_dma_is_buffer_alignment_satisfied(decode_outbuf, outbuf_size, dma_mem_info), ESP_ERR_INVALID_ARG, TAG, "jpeg decode decode_outbuf or out_buffer size is not aligned, please use jpeg_alloc_decoder_mem to malloc your buffer"); esp_err_t ret = ESP_OK; diff --git a/components/esp_driver_sdmmc/include/driver/sdmmc_default_configs.h b/components/esp_driver_sdmmc/include/driver/sdmmc_default_configs.h index ff400fbd13..add6c4c859 100644 --- a/components/esp_driver_sdmmc/include/driver/sdmmc_default_configs.h +++ b/components/esp_driver_sdmmc/include/driver/sdmmc_default_configs.h @@ -46,6 +46,7 @@ extern "C" { .set_input_delay = &sdmmc_host_set_input_delay, \ .dma_aligned_buffer = NULL, \ .pwr_ctrl_handle = NULL, \ + .get_dma_info = &sdmmc_host_get_dma_info, \ } #define SDMMC_SLOT_NO_CD GPIO_NUM_NC ///< indicates that card detect line is not used diff --git a/components/esp_driver_sdmmc/include/driver/sdmmc_host.h b/components/esp_driver_sdmmc/include/driver/sdmmc_host.h index 94080760b2..e596835005 100644 --- a/components/esp_driver_sdmmc/include/driver/sdmmc_host.h +++ b/components/esp_driver_sdmmc/include/driver/sdmmc_host.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -247,6 +247,17 @@ esp_err_t sdmmc_host_get_real_freq(int slot, int* real_freq_khz); */ esp_err_t sdmmc_host_set_input_delay(int slot, sdmmc_delay_phase_t delay_phase); +/** + * @brief Get the DMA memory information for the host driver + * + * @param[in] slot slot number (SDMMC_HOST_SLOT_0 or SDMMC_HOST_SLOT_1) + * @param[out] dma_mem_info DMA memory information structure + * @return + * - ESP_OK: ON success. + * - ESP_ERR_INVALID_ARG: Invalid argument. + */ +esp_err_t sdmmc_host_get_dma_info(int slot, esp_dma_mem_info_t *dma_mem_info); + #ifdef __cplusplus } #endif diff --git a/components/esp_driver_sdmmc/src/sdmmc_host.c b/components/esp_driver_sdmmc/src/sdmmc_host.c index c6a552eb37..2a2e4c9cc0 100644 --- a/components/esp_driver_sdmmc/src/sdmmc_host.c +++ b/components/esp_driver_sdmmc/src/sdmmc_host.c @@ -921,3 +921,13 @@ static esp_err_t sdmmc_host_pullup_en_internal(int slot, int width) } return ESP_OK; } + +esp_err_t sdmmc_host_get_dma_info(int slot, esp_dma_mem_info_t *dma_mem_info) +{ + if (!(slot == 0 || slot == 1)) { + return ESP_ERR_INVALID_ARG; + } + dma_mem_info->extra_heap_caps = MALLOC_CAP_DMA; + dma_mem_info->dma_alignment_bytes = 4; + return ESP_OK; +} diff --git a/components/esp_driver_sdspi/include/driver/sdspi_host.h b/components/esp_driver_sdspi/include/driver/sdspi_host.h index a8a793e17e..85657a3ccb 100644 --- a/components/esp_driver_sdspi/include/driver/sdspi_host.h +++ b/components/esp_driver_sdspi/include/driver/sdspi_host.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -53,7 +53,8 @@ typedef int sdspi_dev_handle_t; .command_timeout_ms = 0, \ .get_real_freq = &sdspi_host_get_real_freq, \ .input_delay_phase = SDMMC_DELAY_PHASE_0, \ - .set_input_delay = NULL \ + .set_input_delay = NULL, \ + .get_dma_info = &sdspi_host_get_dma_info, \ } /** @@ -209,6 +210,17 @@ esp_err_t sdspi_host_io_int_enable(sdspi_dev_handle_t handle); */ esp_err_t sdspi_host_io_int_wait(sdspi_dev_handle_t handle, TickType_t timeout_ticks); +/** + * @brief Get the DMA memory information for the host driver + * + * @param[in] slot Not used + * @param[out] dma_mem_info DMA memory information structure + * @return + * - ESP_OK: ON success. + * - ESP_ERR_INVALID_ARG: Invalid argument. + */ +esp_err_t sdspi_host_get_dma_info(int slot, esp_dma_mem_info_t *dma_mem_info); + #ifdef __cplusplus } #endif diff --git a/components/esp_driver_sdspi/src/sdspi_host.c b/components/esp_driver_sdspi/src/sdspi_host.c index 7877c3133f..98100b0b5b 100644 --- a/components/esp_driver_sdspi/src/sdspi_host.c +++ b/components/esp_driver_sdspi/src/sdspi_host.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -998,3 +998,11 @@ esp_err_t sdspi_host_io_int_wait(sdspi_dev_handle_t handle, TickType_t timeout_t } return ESP_OK; } + +esp_err_t sdspi_host_get_dma_info(int slot, esp_dma_mem_info_t *dma_mem_info) +{ + (void)slot; + dma_mem_info->extra_heap_caps = MALLOC_CAP_DMA; + dma_mem_info->dma_alignment_bytes = 4; + return ESP_OK; +} diff --git a/components/esp_eth/src/esp_eth_mac_esp_dma.c b/components/esp_eth/src/esp_eth_mac_esp_dma.c index 4a888715e0..b885fe0cee 100644 --- a/components/esp_eth/src/esp_eth_mac_esp_dma.c +++ b/components/esp_eth/src/esp_eth_mac_esp_dma.c @@ -385,7 +385,7 @@ uint8_t *emac_esp_dma_alloc_recv_buf(emac_esp_dma_handle_t emac_esp_dma, uint32_ buf = malloc(copy_len); if (buf != NULL) { emac_esp_dma_auto_buf_info_t *buff_info = (emac_esp_dma_auto_buf_info_t *)buf; - /* no need to check allocated buffer min lenght prior writing since we know that EMAC DMA is configured to + /* no need to check allocated buffer min length prior writing since we know that EMAC DMA is configured to not forward erroneous or undersized frames (less than 64B) on ESP32, see emac_hal_init_dma_default */ #ifndef NDEBUG buff_info->magic_id = EMAC_HAL_BUF_MAGIC_ID; @@ -532,8 +532,8 @@ esp_err_t emac_esp_new_dma(const emac_esp_dma_config_t* config, emac_esp_dma_han uint32_t desc_size = CONFIG_ETH_DMA_RX_BUFFER_NUM * sizeof(eth_dma_rx_descriptor_t) + CONFIG_ETH_DMA_TX_BUFFER_NUM * sizeof(eth_dma_tx_descriptor_t); esp_dma_mem_info_t dma_mem_info = { - .heap_caps = MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA, - .dma_alignment = 4, + .extra_heap_caps = MALLOC_CAP_INTERNAL, + .dma_alignment_bytes = 4, }; esp_dma_capable_calloc(1, desc_size, &dma_mem_info, (void*)&emac_esp_dma->descriptors, NULL); diff --git a/components/esp_hw_support/dma/esp_dma_utils.c b/components/esp_hw_support/dma/esp_dma_utils.c index 51079427b5..41fbe0503e 100644 --- a/components/esp_hw_support/dma/esp_dma_utils.c +++ b/components/esp_hw_support/dma/esp_dma_utils.c @@ -14,7 +14,6 @@ #include "esp_memory_utils.h" #include "esp_dma_utils.h" #include "esp_private/esp_cache_private.h" -#include "esp_private/gdma.h" #include "soc/soc_caps.h" #include "hal/hal_utils.h" @@ -28,33 +27,31 @@ esp_err_t esp_dma_capable_malloc(size_t size, const esp_dma_mem_info_t *dma_mem_ { ESP_RETURN_ON_FALSE_ISR(dma_mem_info && out_ptr, ESP_ERR_INVALID_ARG, TAG, "null pointer"); - size_t alignment = 1; + size_t alignment_bytes = 0; //dma align - size_t dma_alignment = dma_mem_info->dma_alignment; - - //custom align - size_t custom_alignment = dma_mem_info->custom_alignment; + size_t dma_alignment_bytes = dma_mem_info->dma_alignment_bytes; //cache align int cache_flags = 0; - size_t cache_alignment = 1; - if (dma_mem_info->heap_caps & MALLOC_CAP_SPIRAM) { + size_t cache_alignment_bytes = 0; + + int heap_caps = dma_mem_info->extra_heap_caps | MALLOC_CAP_DMA; + if (dma_mem_info->extra_heap_caps & MALLOC_CAP_SPIRAM) { cache_flags |= ESP_DMA_MALLOC_FLAG_PSRAM; + heap_caps = dma_mem_info->extra_heap_caps | MALLOC_CAP_SPIRAM; } - esp_err_t ret = esp_cache_get_alignment(cache_flags, &cache_alignment); + + esp_err_t ret = esp_cache_get_alignment(cache_flags, &cache_alignment_bytes); assert(ret == ESP_OK); - //lcm3 - alignment = _lcm_3(dma_alignment, cache_alignment, custom_alignment); - ESP_LOGD(TAG, "alignment: 0x%x", alignment); + //Get the least common multiple of two alignment + alignment_bytes = hal_utils_calc_lcm(dma_alignment_bytes, cache_alignment_bytes); //malloc - size = ALIGN_UP_BY(size, alignment); - int heap_caps = dma_mem_info->heap_caps; - - void *ptr = heap_caps_aligned_alloc(alignment, size, heap_caps); - ESP_RETURN_ON_FALSE_ISR(ptr, ESP_ERR_NO_MEM, TAG, "no enough heap memory"); + size = ALIGN_UP_BY(size, alignment_bytes); + void *ptr = heap_caps_aligned_alloc(alignment_bytes, size, heap_caps); + ESP_RETURN_ON_FALSE_ISR(ptr, ESP_ERR_NO_MEM, TAG, "Not enough heap memory"); *out_ptr = ptr; if (actual_size) { @@ -64,13 +61,13 @@ esp_err_t esp_dma_capable_malloc(size_t size, const esp_dma_mem_info_t *dma_mem_ return ESP_OK; } -esp_err_t esp_dma_capable_calloc(size_t n, size_t size, const esp_dma_mem_info_t *dma_mem_info, void **out_ptr, size_t *actual_size) +esp_err_t esp_dma_capable_calloc(size_t calloc_num, size_t size, const esp_dma_mem_info_t *dma_mem_info, void **out_ptr, size_t *actual_size) { esp_err_t ret = ESP_FAIL; size_t size_bytes = 0; bool ovf = false; - ovf = __builtin_mul_overflow(n, size, &size_bytes); + ovf = __builtin_mul_overflow(calloc_num, size, &size_bytes); ESP_RETURN_ON_FALSE_ISR(!ovf, ESP_ERR_INVALID_ARG, TAG, "wrong size, total size overflow"); void *ptr = NULL; @@ -105,7 +102,7 @@ static inline bool s_is_buf_aligned(intptr_t ptr, size_t alignment) return (ptr % alignment == 0); } -bool esp_dma_is_buffer_alignment_satisfied(const void *ptr, size_t size, esp_dma_mem_info_t *dma_mem_info) +bool esp_dma_is_buffer_alignment_satisfied(const void *ptr, size_t size, esp_dma_mem_info_t dma_mem_info) { assert(ptr); @@ -120,27 +117,24 @@ bool esp_dma_is_buffer_alignment_satisfied(const void *ptr, size_t size, esp_dma return false; } - size_t alignment = 1; + size_t alignment_bytes = 0; //dma align - size_t dma_alignment = dma_mem_info->dma_alignment; - - //custom align - size_t custom_alignment = dma_mem_info->custom_alignment; + size_t dma_alignment_bytes = dma_mem_info.dma_alignment_bytes; //cache align int cache_flags = 0; - size_t cache_alignment = 1; - if (dma_mem_info->heap_caps & MALLOC_CAP_SPIRAM) { + size_t cache_alignment_bytes = 0; + if (esp_ptr_external_ram(ptr)) { cache_flags |= ESP_DMA_MALLOC_FLAG_PSRAM; } - esp_err_t ret = esp_cache_get_alignment(cache_flags, &cache_alignment); + esp_err_t ret = esp_cache_get_alignment(cache_flags, &cache_alignment_bytes); assert(ret == ESP_OK); - //lcm3 - alignment = _lcm_3(dma_alignment, cache_alignment, custom_alignment); + //Get the least common multiple of two alignment + alignment_bytes = hal_utils_calc_lcm(dma_alignment_bytes, cache_alignment_bytes); - bool is_aligned = s_is_buf_aligned((intptr_t)ptr, alignment) && s_is_buf_aligned((intptr_t)size, alignment); + bool is_aligned = s_is_buf_aligned((intptr_t)ptr, alignment_bytes) && s_is_buf_aligned((intptr_t)size, alignment_bytes); return is_aligned; } @@ -158,8 +152,8 @@ esp_err_t s_legacy_malloc(size_t size, uint32_t flags, void **out_ptr, size_t *a } esp_dma_mem_info_t dma_mem_info = { - .heap_caps = heap_caps, - .dma_alignment = 4, //legacy API behaviour is only check max dma buffer alignment + .extra_heap_caps = heap_caps, + .dma_alignment_bytes = 4, //legacy API behaviour is only check max dma buffer alignment }; ESP_RETURN_ON_ERROR_ISR(esp_dma_capable_malloc(size, &dma_mem_info, out_ptr, actual_size), TAG, "failed to do malloc"); @@ -235,28 +229,8 @@ bool esp_dma_is_buffer_aligned(const void *ptr, size_t size, esp_dma_buf_locatio } esp_dma_mem_info_t dma_mem_info = { - .heap_caps = heap_caps, - .dma_alignment = 4, //legacy API behaviour is only check max dma buffer alignment + .extra_heap_caps = heap_caps, + .dma_alignment_bytes = 4, //legacy API behaviour is only check max dma buffer alignment }; - return esp_dma_is_buffer_alignment_satisfied(ptr, size, &dma_mem_info); -} - -esp_err_t esp_dma_get_alignment(void *gdma_chan_handle, const dma_alignment_info_t *info, size_t *alignment) -{ - ESP_RETURN_ON_FALSE(info && alignment, ESP_ERR_INVALID_ARG, TAG, "null pointer"); - -#if SOC_GDMA_SUPPORTED - if (gdma_chan_handle) { - gdma_channel_handle_t dma_chan = (gdma_channel_handle_t)gdma_chan_handle; - gdma_alignment_info_t gdma_info = {}; - memcpy(&gdma_info, info, sizeof(gdma_alignment_info_t)); - ESP_RETURN_ON_ERROR(gdma_get_alignment(dma_chan, &gdma_info, alignment), TAG, "failed to get gdma alignment"); - } else -#endif - { - //for esp32 and esp32s2 - *alignment = 4; - } - - return ESP_OK; + return esp_dma_is_buffer_alignment_satisfied(ptr, size, dma_mem_info); } diff --git a/components/esp_hw_support/dma/gdma.c b/components/esp_hw_support/dma/gdma.c index 711e6e5980..c283a30bd0 100644 --- a/components/esp_hw_support/dma/gdma.c +++ b/components/esp_hw_support/dma/gdma.c @@ -944,34 +944,3 @@ static esp_err_t gdma_install_tx_interrupt(gdma_tx_channel_t *tx_chan) err: return ret; } - -esp_err_t gdma_get_alignment(gdma_channel_handle_t dma_chan, const gdma_alignment_info_t *info, size_t *alignment) -{ - ESP_RETURN_ON_FALSE(dma_chan && info && alignment, ESP_ERR_INVALID_ARG, TAG, "null pointer"); - bool desc_on_psram = info->is_desc && info->on_psram; - ESP_RETURN_ON_FALSE(!desc_on_psram, ESP_ERR_INVALID_ARG, TAG, "should not place descriptor on psram"); - - if (info->is_desc) { - if (dma_chan->pair->group->bus_id == SOC_GDMA_BUS_AHB) { - *alignment = GDMA_LL_AHB_DESC_ALIGNMENT; - } -#if SOC_AXI_GDMA_SUPPORTED - else if (dma_chan->pair->group->bus_id == SOC_GDMA_BUS_AXI) { - *alignment = GDMA_LL_AXI_DESC_ALIGNMENT; - } -#endif - } else { - if (dma_chan->psram_alignment == 0 && dma_chan->sram_alignment == 0) { - ESP_LOGI(TAG, "gdma_set_transfer_ability isn't called before, use fallback alignment"); - *alignment = 4; - } else { - if (info->on_psram) { - *alignment = dma_chan->psram_alignment; - } else { - *alignment = dma_chan->sram_alignment; - } - } - } - - return ESP_OK; -} diff --git a/components/esp_hw_support/dma/include/esp_dma_utils.h b/components/esp_hw_support/dma/include/esp_dma_utils.h index 8f0d17f40c..5e3a426e93 100644 --- a/components/esp_hw_support/dma/include/esp_dma_utils.h +++ b/components/esp_hw_support/dma/include/esp_dma_utils.h @@ -16,17 +16,20 @@ extern "C" { #endif /** - * @breif DMA Mem info + * @brief DMA Mem info */ typedef struct { - int heap_caps; ///< See heap caps - size_t dma_alignment; ///< DMA alignment - size_t custom_alignment; ///< Set this if you have custom alignment. E.g. if `psram_trans_align` is set when using GDMA driver, or you're using IP self DMA (e.g. SDMMC) + int extra_heap_caps; ///< extra heap caps based on MALLOC_CAP_DMA + size_t dma_alignment_bytes; ///< DMA alignment } esp_dma_mem_info_t; /** * @brief Helper function for malloc a DMA capable memory buffer * + * @note This API will take care of the cache alignment internally, + * you will need to set `esp_dma_mem_info_t: dma_alignment_bytes` + * with either the custom alignment or DMA alignment of used peripheral driver. + * * @param[in] size Size in bytes, the amount of memory to allocate * @param[in] dma_mem_info DMA and memory info, see `esp_dma_mem_info_t` * @param[out] out_ptr A pointer to the memory allocated successfully @@ -42,6 +45,7 @@ esp_err_t esp_dma_capable_malloc(size_t size, const esp_dma_mem_info_t *dma_mem_ /** * @brief Helper function for calloc a DMA capable memory buffer * + * @param[in] calloc_num Number of elements to allocate * @param[in] size Size in bytes, the amount of memory to allocate * @param[in] dma_mem_info DMA and memory info, see `esp_dma_mem_info_t` * @param[out] out_ptr A pointer to the memory allocated successfully @@ -52,10 +56,10 @@ esp_err_t esp_dma_capable_malloc(size_t size, const esp_dma_mem_info_t *dma_mem_ * - ESP_ERR_INVALID_ARG: Invalid argument * - ESP_ERR_NO_MEM: No enough memory for allocation */ -esp_err_t esp_dma_capable_calloc(size_t n, size_t size, const esp_dma_mem_info_t *dma_mem_info, void **out_ptr, size_t *actual_size); +esp_err_t esp_dma_capable_calloc(size_t calloc_num, size_t size, const esp_dma_mem_info_t *dma_mem_info, void **out_ptr, size_t *actual_size); /** - * @brief Helper function to check if a DMA buffer meets alignment requirements + * @brief Helper function to check if a DMA buffer pointer and size meet both hardware alignment requirements and custom alignment requirements * * @param[in] ptr Pointer to the buffer * @param[in] size Size of the buffer @@ -65,29 +69,16 @@ esp_err_t esp_dma_capable_calloc(size_t n, size_t size, const esp_dma_mem_info_t * - True: Buffer is aligned * - False: Buffer is not aligned, or buffer is not DMA capable */ -bool esp_dma_is_buffer_alignment_satisfied(const void *ptr, size_t size, esp_dma_mem_info_t *dma_mem_info); +bool esp_dma_is_buffer_alignment_satisfied(const void *ptr, size_t size, esp_dma_mem_info_t dma_mem_info); /** * @brief Needed info to get GDMA alignment */ typedef struct { - bool is_desc; - bool on_psram; + bool is_desc; ///< allocate DMA descriptor + bool on_psram; ///< allocate DMA from the PSRAM } dma_alignment_info_t; -/** - * @brief Helper to get DMA alignment - * - * @param[in] gdma_chan_handle GDMA channel handle, if no GDMA supported, set it to NULL - * @param[in] info DMA alignment info - * @param[out] alignment Alignment - * - * @return - * - ESP_OK - * - ESP_ERR_INVALID_ARG Invalid argument - */ -esp_err_t esp_dma_get_alignment(void *gdma_chan_handle, const dma_alignment_info_t *info, size_t *alignment); - //-----------------------Deprecated APIs-----------------------// /** * DMA malloc flags diff --git a/components/esp_hw_support/dma/include/esp_private/gdma.h b/components/esp_hw_support/dma/include/esp_private/gdma.h index 8dee53e7d8..2d61d531be 100644 --- a/components/esp_hw_support/dma/include/esp_private/gdma.h +++ b/components/esp_hw_support/dma/include/esp_private/gdma.h @@ -457,26 +457,6 @@ esp_err_t gdma_config_crc_calculator(gdma_channel_handle_t dma_chan, const gdma_ esp_err_t gdma_crc_get_result(gdma_channel_handle_t dma_chan, uint32_t *result); #endif // SOC_GDMA_SUPPORT_CRC -/** - * @brief Needed info to get GDMA alignment - */ -typedef struct { - bool is_desc; - bool on_psram; -} gdma_alignment_info_t; - -/** - * @brief Get GDMA alignment from the channel handle - * - * @param[in] dma_chan GDMA channel handle - * @param[in] info GDMA alignment info - * @param[out] alignment Alignment - * - * @return - * - ESP_OK - * - ESP_ERR_INVALID_ARG Invalid argument - */ -esp_err_t gdma_get_alignment(gdma_channel_handle_t dma_chan, const gdma_alignment_info_t *info, size_t *alignment); #ifdef __cplusplus } #endif diff --git a/components/esp_hw_support/test_apps/dma/main/test_dma_utils.c b/components/esp_hw_support/test_apps/dma/main/test_dma_utils.c index 85420260c9..ec23a20ce3 100644 --- a/components/esp_hw_support/test_apps/dma/main/test_dma_utils.c +++ b/components/esp_hw_support/test_apps/dma/main/test_dma_utils.c @@ -39,9 +39,8 @@ TEST_CASE("test esp_dma_capable_malloc for PSRAM", "[dma_utils]") size_t actual_size = 0; esp_dma_mem_info_t dma_mem_info = { - .heap_caps = MALLOC_CAP_SPIRAM, - .dma_alignment = 4, - .custom_alignment = 4, + .extra_heap_caps = MALLOC_CAP_SPIRAM, + .dma_alignment_bytes = 4, }; //------ psram ------// @@ -65,91 +64,18 @@ TEST_CASE("test esp_dma_capable_malloc for PSRAM", "[dma_utils]") } #endif -TEST_CASE("test custom alignment", "[dma_utils]") -{ - size_t test_size = 0; - void *test_ptr = NULL; - size_t actual_size = 0; - size_t custom_alignment = 512; - - esp_dma_mem_info_t dma_mem_info = { - .heap_caps = MALLOC_CAP_SPIRAM, - .dma_alignment = 4, - .custom_alignment = custom_alignment, - }; - test_size = custom_alignment + 3; - ESP_LOGI(TAG, "to alloc 0x%zx", test_size); - TEST_ESP_OK(esp_dma_capable_malloc(test_size, &dma_mem_info, &test_ptr, &actual_size)); - ESP_LOGI(TAG, "get test_ptr: %p, actual_size: 0x%zx", test_ptr, actual_size); - TEST_ASSERT((uint32_t)test_ptr % custom_alignment == 0); - TEST_ASSERT(ALIGN_UP_BY(test_size, custom_alignment) == actual_size); - free(test_ptr); -} - TEST_CASE("test esp_dma_is_buffer_alignment_satisfied", "[dma_utils]") { size_t test_size = 64; void *test_ptr = NULL; esp_dma_mem_info_t dma_mem_info = { - .heap_caps = MALLOC_CAP_DMA, - .dma_alignment = 4, + .dma_alignment_bytes = 4, }; TEST_ESP_OK(esp_dma_capable_malloc(test_size, &dma_mem_info, &test_ptr, NULL)); ESP_LOGI(TAG, "test_ptr %p", test_ptr); - bool is_aligned = esp_dma_is_buffer_alignment_satisfied(test_ptr, test_size, &dma_mem_info); + bool is_aligned = esp_dma_is_buffer_alignment_satisfied(test_ptr, test_size, dma_mem_info); TEST_ASSERT(is_aligned); - is_aligned = esp_dma_is_buffer_alignment_satisfied(test_ptr + 3, test_size, &dma_mem_info); + is_aligned = esp_dma_is_buffer_alignment_satisfied(test_ptr + 3, test_size, dma_mem_info); TEST_ASSERT(!is_aligned); } - - -#if CONFIG_IDF_TARGET_ESP32P4 -#define TEST_DMA_ALIGNMENT_INT 8 -#else -#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2 -#define TEST_DMA_ALIGNMENT_INT 4 -#else -#define TEST_DMA_ALIGNMENT_INT 8 -#endif -#endif - -TEST_CASE("test esp_dma_get_alignment", "[dma_utils]") -{ - size_t dma_alignment = 0; - gdma_channel_handle_t tx_channel = NULL; -#if SOC_GDMA_SUPPORTED - gdma_channel_alloc_config_t channel_config = {}; - channel_config.direction = GDMA_CHANNEL_DIRECTION_TX; - - TEST_ESP_OK(gdma_new_ahb_channel(&channel_config, &tx_channel)); - - gdma_transfer_ability_t ability = { - .psram_trans_align = 0, - .sram_trans_align = 8, - }; - TEST_ESP_OK(gdma_set_transfer_ability(tx_channel, &ability)); -#endif - - dma_alignment_info_t internal_info = {}; - - TEST_ESP_OK(esp_dma_get_alignment(tx_channel, &internal_info, &dma_alignment)); - ESP_LOGI(TAG, "dma_alignment: 0x%x", dma_alignment); - TEST_ASSERT(dma_alignment == TEST_DMA_ALIGNMENT_INT); -} - -#if SOC_GDMA_SUPPORTED -TEST_CASE("test esp_dma_get_alignment with no transfer ability set", "[dma_utils]") -{ - size_t dma_alignment = 0; - gdma_channel_handle_t tx_channel = NULL; - gdma_channel_alloc_config_t channel_config = {}; - channel_config.direction = GDMA_CHANNEL_DIRECTION_TX; - TEST_ESP_OK(gdma_new_ahb_channel(&channel_config, &tx_channel)); - - dma_alignment_info_t internal_info = {}; - TEST_ESP_OK(esp_dma_get_alignment(tx_channel, &internal_info, &dma_alignment)); - ESP_LOGI(TAG, "dma_alignment: 0x%x", dma_alignment); - TEST_ASSERT(dma_alignment == 4); -} -#endif diff --git a/components/hal/esp32c5/include/hal/gdma_ll.h b/components/hal/esp32c5/include/hal/gdma_ll.h index 7b1147d27b..55c89bb81f 100644 --- a/components/hal/esp32c5/include/hal/gdma_ll.h +++ b/components/hal/esp32c5/include/hal/gdma_ll.h @@ -99,6 +99,8 @@ extern "C" { // TODO: Workaround for C5-beta3 only. C5-mp can still vectorized channels into an array in gdma_struct.h #define GDMA_LL_CHANNEL_GET_REG_ADDR(dev, ch) ((volatile gdma_chn_reg_t*[]){&dev->channel0, &dev->channel1, &dev->channel2}[(ch)]) +#define GDMA_LL_AHB_DESC_ALIGNMENT 4 + ///////////////////////////////////// Common ///////////////////////////////////////// /** diff --git a/components/hal/hal_utils.c b/components/hal/hal_utils.c index b214ce3cdf..68ea4bb60a 100644 --- a/components/hal/hal_utils.c +++ b/components/hal/hal_utils.c @@ -26,7 +26,7 @@ uint32_t hal_utils_calc_clk_div_frac_fast(const hal_utils_clk_info_t *clk_info, // Carry bit if the decimal is greater than 1.0 - 1.0 / ((max_fract - 1) * 2) if (freq_error < clk_info->exp_freq_hz - clk_info->exp_freq_hz / (clk_info->max_fract - 1) * 2) { // Calculate the Greatest Common Divisor, time complexity O(log n) - uint32_t gcd = _gcd(clk_info->exp_freq_hz, freq_error); + uint32_t gcd = hal_utils_gcd(clk_info->exp_freq_hz, freq_error); // divide by the Greatest Common Divisor to get the accurate fraction before normalization div_denom = clk_info->exp_freq_hz / gcd; div_numer = freq_error / gcd; diff --git a/components/hal/include/hal/hal_utils.h b/components/hal/include/hal/hal_utils.h index c5d7077470..b95931c252 100644 --- a/components/hal/include/hal/hal_utils.h +++ b/components/hal/include/hal/hal_utils.h @@ -23,7 +23,7 @@ typedef enum { } hal_utils_div_round_opt_t; /** - * @brief Clock infomation + * @brief Clock information * */ typedef struct { @@ -53,7 +53,7 @@ typedef struct { * @note Speed first algorithm, Time complexity O(log n). * About 8~10 times faster than the accurate algorithm * - * @param[in] clk_info The clock infomation + * @param[in] clk_info The clock information * @param[out] clk_div The clock division with integral and fractal part * @return * - 0: Failed to get the result because the division is out of range @@ -66,7 +66,7 @@ uint32_t hal_utils_calc_clk_div_frac_fast(const hal_utils_clk_info_t *clk_info, * @note Accuracy first algorithm, Time complexity O(n). * About 1~hundreds times more accurate than the fast algorithm * - * @param[in] clk_info The clock infomation + * @param[in] clk_info The clock information * @param[out] clk_div The clock division with integral and fractal part * @return * - 0: Failed to get the result because the division is out of range @@ -77,12 +77,12 @@ uint32_t hal_utils_calc_clk_div_frac_accurate(const hal_utils_clk_info_t *clk_in /** * @brief Calculate the clock division without fractal part * - * @param[in] clk_info The clock infomation + * @param[in] clk_info The clock information * @param[out] int_div The clock integral division * @return * - 0: Failed to get the result because the division is out of range, * but parameter `int_div` will still be assigned to min/max division that given in `clk_info`, - * incase the caller still want to use the min/max division in this case. + * in case the caller still want to use the min/max division in this case. * - others: The real output clock frequency */ uint32_t hal_utils_calc_clk_div_integer(const hal_utils_clk_info_t *clk_info, uint32_t *int_div); @@ -103,20 +103,31 @@ static inline uint8_t hal_utils_bitwise_reverse8(uint8_t n) } /** - * @brief helper function, calculate the Greatest Common Divisor - * @note gcd(a, b) = gcd(b, a % b) - * @param a bigger value - * @param b smaller value - * @return result of gcd(a, b) + * @brief Helper function to calculate the GCD between two numbers using the Euclidean algorithm. + * Calculate the Greatest Common Divisor (GDC) of two unsigned numbers + * + * @param num_1 First number + * @param num_2 Second number + * @return GCD of 'a' and 'b' */ __attribute__((always_inline)) -static inline uint32_t _gcd(uint32_t a, uint32_t b) +static inline uint32_t hal_utils_gcd(uint32_t num_1, uint32_t num_2) { - uint32_t c = a % b; - while (c != 0) { + uint32_t a, b, rem; + // Always mod larger number by smaller number + if (num_1 > num_2) { + a = num_1; + b = num_2; + } else { + b = num_2; + a = num_1; + } + + rem = a % b; + while (rem != 0) { a = b; - b = c; - c = a % b; + b = rem; + rem = a % b; } return b; } @@ -130,29 +141,11 @@ static inline uint32_t _gcd(uint32_t a, uint32_t b) * @return LCM of A and B */ __attribute__((always_inline)) -static inline uint32_t _lcm(uint32_t a, uint32_t b) +static inline uint32_t hal_utils_calc_lcm(uint32_t a, uint32_t b) { a = a == 0 ? 1 : a; b = b == 0 ? 1 : b; - return (a * b / _gcd(a, b)); -} - -/** - * @brief Get the least common multiple of three integer - * - * @param[in] Integer A - * @param[in] Integer B - * @param[in] Integer C - * - * @return LCM of A, B and C - */ -__attribute__((always_inline)) -static inline uint32_t _lcm_3(uint32_t a, uint32_t b, uint32_t c) -{ - a = a == 0 ? 1 : a; - b = b == 0 ? 1 : b; - c = c == 0 ? 1 : c; - return _lcm(a, _lcm(b, c)); + return (a * b / hal_utils_gcd(a, b)); } #ifdef __cplusplus diff --git a/components/mbedtls/port/aes/dma/esp_aes_dma_core.c b/components/mbedtls/port/aes/dma/esp_aes_dma_core.c index 87ab2c0bf5..728bd0ea6c 100644 --- a/components/mbedtls/port/aes/dma/esp_aes_dma_core.c +++ b/components/mbedtls/port/aes/dma/esp_aes_dma_core.c @@ -46,7 +46,7 @@ #define AES_DMA_INTR_TRIG_LEN 2000 /* With buffers in PSRAM (worst condition) we still achieve a speed of 4 MB/s - thus a 2 second timeout value should be suffient for even very large buffers. + thus a 2 second timeout value should be sufficient for even very large buffers. */ #define AES_WAIT_INTR_TIMEOUT_MS 2000 @@ -98,7 +98,7 @@ void esp_aes_intr_alloc(void) static StaticSemaphore_t op_sem_buf; op_complete_sem = xSemaphoreCreateBinaryStatic(&op_sem_buf); - // Static semaphore creation is unlikley to fail but still basic sanity + // Static semaphore creation is unlikely to fail but still basic sanity assert(op_complete_sem != NULL); } } @@ -164,7 +164,7 @@ static int esp_aes_dma_wait_complete(bool use_intr, crypto_dma_desc_t *output_de } -/* Output buffers in external ram needs to be 16-byte aligned and DMA cant access input in the iCache mem range, +/* Output buffers in external ram needs to be 16-byte aligned and DMA can't access input in the iCache mem range, reallocate them into internal memory and encrypt in chunks to avoid having to malloc too big of a buffer @@ -276,7 +276,12 @@ static inline void dma_desc_append(crypto_dma_desc_t **head, crypto_dma_desc_t * static inline void *aes_dma_calloc(size_t num, size_t size, uint32_t caps, size_t *actual_size) { void *ptr = NULL; - esp_dma_calloc(num, size, caps, &ptr, actual_size); + esp_dma_mem_info_t dma_mem_info = { + .extra_heap_caps = caps, + .dma_alignment_bytes = 4, + }; + //TODO: IDF-9638 + esp_dma_capable_calloc(num, size, &dma_mem_info, &ptr, actual_size); return ptr; } diff --git a/components/sdmmc/include/sd_protocol_types.h b/components/sdmmc/include/sd_protocol_types.h index 7ba1769016..effe3b4a0f 100644 --- a/components/sdmmc/include/sd_protocol_types.h +++ b/components/sdmmc/include/sd_protocol_types.h @@ -28,6 +28,7 @@ #include "esp_err.h" #include "freertos/FreeRTOS.h" #include "sd_pwr_ctrl.h" +#include "esp_dma_utils.h" #ifdef __cplusplus extern "C" { @@ -79,7 +80,7 @@ typedef struct { uint32_t erase_size_au: 16; /*!< Erase size for the purpose of timeout calculation, in multiples of allocation unit */ uint32_t cur_bus_width: 2; /*!< SD current bus width */ uint32_t discard_support: 1; /*!< SD discard feature support */ - uint32_t fule_support: 1; /*!< SD FULE (Full User Area Logical Erase) feature support */ + uint32_t fule_support: 1; /*!< SD FILE (Full User Area Logical Erase) feature support */ uint32_t erase_timeout: 6; /*!< Timeout (in seconds) for erase of a single allocation unit */ uint32_t erase_offset: 2; /*!< Constant timeout offset (in seconds) for any erase operation */ uint32_t reserved: 20; /*!< reserved for future expansion */ @@ -209,6 +210,7 @@ typedef struct { esp_err_t (*set_input_delay)(int slot, sdmmc_delay_phase_t delay_phase); /*!< set input delay phase */ void* dma_aligned_buffer; /*!< Leave it NULL. Reserved for cache aligned buffers for SDIO mode */ sd_pwr_ctrl_handle_t pwr_ctrl_handle; /*!< Power control handle */ + esp_err_t (*get_dma_info)(int slot, esp_dma_mem_info_t *dma_mem_info); /*!< host function to dma memory information*/ } sdmmc_host_t; /** diff --git a/components/sdmmc/sdmmc_cmd.c b/components/sdmmc/sdmmc_cmd.c index b0035c53dd..6f2c6e8e57 100644 --- a/components/sdmmc/sdmmc_cmd.c +++ b/components/sdmmc/sdmmc_cmd.c @@ -326,13 +326,11 @@ esp_err_t sdmmc_send_cmd_send_scr(sdmmc_card_t* card, sdmmc_scr_t *out_scr) { size_t datalen = 8; esp_err_t err = ESP_FAIL; - uint32_t *buf = NULL; + void *buf = NULL; size_t actual_size = 0; - esp_dma_mem_info_t dma_mem_info = { - .heap_caps = MALLOC_CAP_DMA, - .custom_alignment = 4, - }; - err = esp_dma_capable_malloc(datalen, &dma_mem_info, (void *)&buf, &actual_size); + esp_dma_mem_info_t dma_mem_info; + card->host.get_dma_info(card->host.slot, &dma_mem_info); + err = esp_dma_capable_malloc(datalen, &dma_mem_info, &buf, &actual_size); if (err != ESP_OK) { return err; } @@ -405,11 +403,9 @@ esp_err_t sdmmc_write_sectors(sdmmc_card_t* card, const void* src, esp_err_t err = ESP_OK; size_t block_size = card->csd.sector_size; - esp_dma_mem_info_t dma_mem_info = { - .heap_caps = MALLOC_CAP_DMA, - .custom_alignment = 4, - }; - if (esp_dma_is_buffer_alignment_satisfied(src, block_size * block_count, &dma_mem_info)) { + esp_dma_mem_info_t dma_mem_info; + card->host.get_dma_info(card->host.slot, &dma_mem_info); + if (esp_dma_is_buffer_alignment_satisfied(src, block_size * block_count, dma_mem_info)) { err = sdmmc_write_sectors_dma(card, src, start_block, block_count, block_size * block_count); } else { // SDMMC peripheral needs DMA-capable buffers. Split the write into @@ -527,11 +523,9 @@ esp_err_t sdmmc_read_sectors(sdmmc_card_t* card, void* dst, esp_err_t err = ESP_OK; size_t block_size = card->csd.sector_size; - esp_dma_mem_info_t dma_mem_info = { - .heap_caps = MALLOC_CAP_DMA, - .custom_alignment = 4, - }; - if (esp_dma_is_buffer_alignment_satisfied(dst, block_size * block_count, &dma_mem_info)) { + esp_dma_mem_info_t dma_mem_info; + card->host.get_dma_info(card->host.slot, &dma_mem_info); + if (esp_dma_is_buffer_alignment_satisfied(dst, block_size * block_count, dma_mem_info)) { err = sdmmc_read_sectors_dma(card, dst, start_block, block_count, block_size * block_count); } else { // SDMMC peripheral needs DMA-capable buffers. Split the read into diff --git a/components/sdmmc/sdmmc_common.c b/components/sdmmc/sdmmc_common.c index c264d41eba..8135e593e2 100644 --- a/components/sdmmc/sdmmc_common.c +++ b/components/sdmmc/sdmmc_common.c @@ -340,11 +340,8 @@ esp_err_t sdmmc_allocate_aligned_buf(sdmmc_card_t* card) if (card->host.flags & SDMMC_HOST_FLAG_ALLOC_ALIGNED_BUF) { void* buf = NULL; size_t actual_size = 0; - // esp_err_t ret = esp_dma_malloc(SDMMC_IO_BLOCK_SIZE, 0, &buf, &actual_size); - esp_dma_mem_info_t dma_mem_info = { - .heap_caps = MALLOC_CAP_DMA, - .custom_alignment = 4, - }; + esp_dma_mem_info_t dma_mem_info; + card->host.get_dma_info(card->host.slot, &dma_mem_info); esp_err_t ret = esp_dma_capable_malloc(SDMMC_IO_BLOCK_SIZE, &dma_mem_info, &buf, &actual_size); if (ret != ESP_OK) { diff --git a/components/sdmmc/sdmmc_io.c b/components/sdmmc/sdmmc_io.c index 7827844bc0..80a3cc26c9 100644 --- a/components/sdmmc/sdmmc_io.c +++ b/components/sdmmc/sdmmc_io.c @@ -277,11 +277,9 @@ esp_err_t sdmmc_io_rw_extended(sdmmc_card_t* card, int func, .blklen = SDMMC_IO_BLOCK_SIZE /* TODO: read max block size from CIS */ }; - esp_dma_mem_info_t dma_mem_info = { - .heap_caps = MALLOC_CAP_DMA, - .custom_alignment = 4, - }; - if (unlikely(datalen > 0 && !esp_dma_is_buffer_alignment_satisfied(datap, buflen, &dma_mem_info))) { + esp_dma_mem_info_t dma_mem_info; + card->host.get_dma_info(card->host.slot, &dma_mem_info); + if (unlikely(datalen > 0 && !esp_dma_is_buffer_alignment_satisfied(datap, buflen, dma_mem_info))) { if (datalen > SDMMC_IO_BLOCK_SIZE || card->host.dma_aligned_buffer == NULL) { // User gives unaligned buffer while `SDMMC_HOST_FLAG_ALLOC_ALIGNED_BUF` not set. return ESP_ERR_INVALID_ARG; @@ -304,7 +302,7 @@ esp_err_t sdmmc_io_rw_extended(sdmmc_card_t* card, int func, return ESP_ERR_INVALID_SIZE; } if (datalen == SDMMC_IO_BLOCK_SIZE) { - count = 0; // See 5.3.1 SDIO simplifed spec + count = 0; // See 5.3.1 SDIO simplified spec } else { count = datalen; } @@ -390,11 +388,9 @@ esp_err_t sdmmc_io_write_bytes(sdmmc_card_t* card, uint32_t function, esp_err_t sdmmc_io_read_blocks(sdmmc_card_t* card, uint32_t function, uint32_t addr, void* dst, size_t size) { - esp_dma_mem_info_t dma_mem_info = { - .heap_caps = MALLOC_CAP_DMA, - .custom_alignment = 4, - }; - if (unlikely(!esp_dma_is_buffer_alignment_satisfied(dst, size, &dma_mem_info))) { + esp_dma_mem_info_t dma_mem_info; + card->host.get_dma_info(card->host.slot, &dma_mem_info); + if (unlikely(!esp_dma_is_buffer_alignment_satisfied(dst, size, dma_mem_info))) { return ESP_ERR_INVALID_ARG; } return sdmmc_io_rw_extended(card, function, addr, @@ -405,11 +401,9 @@ esp_err_t sdmmc_io_read_blocks(sdmmc_card_t* card, uint32_t function, esp_err_t sdmmc_io_write_blocks(sdmmc_card_t* card, uint32_t function, uint32_t addr, const void* src, size_t size) { - esp_dma_mem_info_t dma_mem_info = { - .heap_caps = MALLOC_CAP_DMA, - .custom_alignment = 4, - }; - if (unlikely(!esp_dma_is_buffer_alignment_satisfied(src, size, &dma_mem_info))) { + esp_dma_mem_info_t dma_mem_info; + card->host.get_dma_info(card->host.slot, &dma_mem_info); + if (unlikely(!esp_dma_is_buffer_alignment_satisfied(src, size, dma_mem_info))) { return ESP_ERR_INVALID_ARG; } return sdmmc_io_rw_extended(card, function, addr, diff --git a/components/sdmmc/sdmmc_mmc.c b/components/sdmmc/sdmmc_mmc.c index e44fa76630..e3f44bc865 100644 --- a/components/sdmmc/sdmmc_mmc.c +++ b/components/sdmmc/sdmmc_mmc.c @@ -28,10 +28,8 @@ esp_err_t sdmmc_init_mmc_read_ext_csd(sdmmc_card_t* card) esp_err_t err = ESP_OK; uint8_t* ext_csd = NULL; size_t actual_size = 0; - esp_dma_mem_info_t dma_mem_info = { - .heap_caps = MALLOC_CAP_DMA, - .custom_alignment = 4, - }; + esp_dma_mem_info_t dma_mem_info; + card->host.get_dma_info(card->host.slot, &dma_mem_info); err = esp_dma_capable_malloc(EXT_CSD_MMC_SIZE, &dma_mem_info, (void *)&ext_csd, &actual_size); if (err != ESP_OK) { ESP_LOGE(TAG, "%s: could not allocate ext_csd", __func__); @@ -259,10 +257,8 @@ esp_err_t sdmmc_init_mmc_check_ext_csd(sdmmc_card_t* card) /* ensure EXT_CSD buffer is available before starting any SD-card operation */ uint8_t* ext_csd = NULL; size_t actual_size = 0; - esp_dma_mem_info_t dma_mem_info = { - .heap_caps = MALLOC_CAP_DMA, - .custom_alignment = 4, - }; + esp_dma_mem_info_t dma_mem_info; + card->host.get_dma_info(card->host.slot, &dma_mem_info); esp_err_t err = esp_dma_capable_malloc(EXT_CSD_MMC_SIZE, &dma_mem_info, (void *)&ext_csd, &actual_size); if (err != ESP_OK) { ESP_LOGE(TAG, "%s: could not allocate ext_csd", __func__); diff --git a/components/sdmmc/sdmmc_sd.c b/components/sdmmc/sdmmc_sd.c index f4d0fe7ed2..2b208cf9ab 100644 --- a/components/sdmmc/sdmmc_sd.c +++ b/components/sdmmc/sdmmc_sd.c @@ -91,10 +91,8 @@ esp_err_t sdmmc_init_sd_ssr(sdmmc_card_t* card) */ uint32_t* sd_ssr = NULL; size_t actual_size = 0; - esp_dma_mem_info_t dma_mem_info = { - .heap_caps = MALLOC_CAP_DMA, - .custom_alignment = 4, - }; + esp_dma_mem_info_t dma_mem_info; + card->host.get_dma_info(card->host.slot, &dma_mem_info); err = esp_dma_capable_calloc(1, SD_SSR_SIZE, &dma_mem_info, (void *)&sd_ssr, &actual_size); if (err != ESP_OK) { ESP_LOGE(TAG, "%s: could not allocate sd_ssr", __func__); @@ -243,10 +241,8 @@ esp_err_t sdmmc_enable_hs_mode(sdmmc_card_t* card) size_t actual_size = 0; sdmmc_switch_func_rsp_t *response = NULL; - esp_dma_mem_info_t dma_mem_info = { - .heap_caps = MALLOC_CAP_DMA, - .custom_alignment = 4, - }; + esp_dma_mem_info_t dma_mem_info; + card->host.get_dma_info(card->host.slot, &dma_mem_info); esp_err_t err = esp_dma_capable_malloc(sizeof(*response), &dma_mem_info, (void *)&response, &actual_size); assert(actual_size == sizeof(*response)); if (err != ESP_OK) { diff --git a/components/usb/hcd_dwc.c b/components/usb/hcd_dwc.c index 1ec3de6771..9d668fb79b 100644 --- a/components/usb/hcd_dwc.c +++ b/components/usb/hcd_dwc.c @@ -1040,18 +1040,18 @@ static void port_obj_free(port_t *port) void *frame_list_alloc(size_t frame_list_len) { - esp_err_t ret = ESP_FAIL; + esp_err_t ret; void *frame_list = NULL; + size_t actual_size = 0; esp_dma_mem_info_t dma_mem_info = { - .heap_caps = MALLOC_CAP_DMA, - .custom_alignment = USB_DWC_FRAME_LIST_MEM_ALIGN, + .dma_alignment_bytes = USB_DWC_FRAME_LIST_MEM_ALIGN, }; - ret = esp_dma_capable_calloc(frame_list_len, sizeof(uint32_t), &dma_mem_info, &frame_list, NULL); - assert(ret != ESP_ERR_INVALID_ARG); + ret = esp_dma_capable_calloc(frame_list_len, sizeof(uint32_t), &dma_mem_info, &frame_list, &actual_size); + assert(ret == ESP_OK); // Both Frame List start address and size should be already cache aligned so this is only a sanity check if (frame_list) { - if (!esp_dma_is_buffer_alignment_satisfied(frame_list, frame_list_len * sizeof(uint32_t), &dma_mem_info)) { + if (!esp_dma_is_buffer_alignment_satisfied(frame_list, actual_size, dma_mem_info)) { // This should never happen heap_caps_free(frame_list); frame_list = NULL; @@ -1072,17 +1072,17 @@ void *transfer_descriptor_list_alloc(size_t list_len, size_t *list_len_bytes_out *list_len_bytes_out = list_len * sizeof(usb_dwc_ll_dma_qtd_t); #endif // SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE - esp_err_t ret = ESP_FAIL; + esp_err_t ret; void *qtd_list = NULL; + size_t actual_size = 0; esp_dma_mem_info_t dma_mem_info = { - .heap_caps = MALLOC_CAP_DMA, - .custom_alignment = USB_DWC_QTD_LIST_MEM_ALIGN, + .dma_alignment_bytes = USB_DWC_QTD_LIST_MEM_ALIGN, }; - ret = esp_dma_capable_calloc(*list_len_bytes_out, 1, &dma_mem_info, &qtd_list, NULL); - assert(ret != ESP_ERR_INVALID_ARG); + ret = esp_dma_capable_calloc(*list_len_bytes_out, 1, &dma_mem_info, &qtd_list, &actual_size); + assert(ret == ESP_OK); if (qtd_list) { - if (!esp_dma_is_buffer_alignment_satisfied(qtd_list, *list_len_bytes_out * sizeof(usb_dwc_ll_dma_qtd_t), &dma_mem_info)) { + if (!esp_dma_is_buffer_alignment_satisfied(qtd_list, actual_size, dma_mem_info)) { // This should never happen heap_caps_free(qtd_list); qtd_list = NULL; diff --git a/components/usb/test_apps/hcd/main/test_hcd_common.c b/components/usb/test_apps/hcd/main/test_hcd_common.c index 80f4e5c275..b2147b5ad1 100644 --- a/components/usb/test_apps/hcd/main/test_hcd_common.c +++ b/components/usb/test_apps/hcd/main/test_hcd_common.c @@ -267,11 +267,7 @@ urb_t *test_hcd_alloc_urb(int num_isoc_packets, size_t data_buffer_size) void *data_buffer; size_t real_size; esp_dma_mem_info_t dma_mem_info = { - .dma_type = ESP_DMA_OTHERS, - .mem_flags = { - .dir = ESP_DMA_MEM_DIR_DONT_CARE, - }, - .custom_alignment = 4, + .dma_alignment_bytes = 4, }; esp_dma_capable_malloc(data_buffer_size, &dma_mem_info, &data_buffer, &real_size); TEST_ASSERT_NOT_NULL_MESSAGE(urb, "Failed to allocate URB"); diff --git a/components/usb/usb_private.c b/components/usb/usb_private.c index 323bc916f9..e5ab2d3da8 100644 --- a/components/usb/usb_private.c +++ b/components/usb/usb_private.c @@ -15,12 +15,9 @@ urb_t *urb_alloc(size_t data_buffer_size, int num_isoc_packets) void *data_buffer; size_t real_size; esp_dma_mem_info_t dma_mem_info = { - .dma_type = ESP_DMA_OTHERS, - .mem_flags = { - .dir = ESP_DMA_MEM_DIR_DONT_CARE, - }, - .custom_alignment = 4, + .dma_alignment_bytes = 4, }; + //TODO: IDF-9639 esp_dma_capable_malloc(data_buffer_size, &dma_mem_info, &data_buffer, &real_size); if (urb == NULL || data_buffer == NULL) { goto err; diff --git a/docs/en/api-reference/system/mm_sync.rst b/docs/en/api-reference/system/mm_sync.rst index 3a86ae06d1..55fb9932d1 100644 --- a/docs/en/api-reference/system/mm_sync.rst +++ b/docs/en/api-reference/system/mm_sync.rst @@ -109,7 +109,7 @@ cache memory synchronization is usually considered when DMA is involved. ESP-IDF - :cpp:func:`esp_dma_capable_malloc`, this API allocates a chunk of memory that meets the alignment requirement from both the cache and the DMA. - :cpp:func:`esp_dma_capable_calloc`, this API allocates a chunk of memory that meets the alignment requirement from both the cache and the DMA. The initialized value in the memory is set to zero. -You can also use :cpp:member:`esp_dma_mem_info_t::on_psram` to allocate from the PSRAM. +You can also use :c:macro:`ESP_DMA_MALLOC_FLAG_PSRAM` to allocate from the PSRAM. Warning for Address Alignment Requirement diff --git a/examples/peripherals/lcd/i80_controller/main/i80_controller_example_main.c b/examples/peripherals/lcd/i80_controller/main/i80_controller_example_main.c index 745fb6b4ad..86e8ce2b41 100644 --- a/examples/peripherals/lcd/i80_controller/main/i80_controller_example_main.c +++ b/examples/peripherals/lcd/i80_controller/main/i80_controller_example_main.c @@ -448,11 +448,11 @@ void app_main(void) lv_color_t *buf1 = NULL; lv_color_t *buf2 = NULL; esp_dma_mem_info_t dma_mem_info = { - .dma_alignment = 4, + .dma_alignment_bytes = 4, #if CONFIG_EXAMPLE_LCD_I80_COLOR_IN_PSRAM - .heap_caps = MALLOC_CAP_SPIRAM, + .extra_heap_caps = MALLOC_CAP_SPIRAM, #else - .heap_caps = MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL, + .extra_heap_caps = MALLOC_CAP_INTERNAL, #endif // CONFIG_EXAMPLE_LCD_I80_COLOR_IN_PSRAM }; ESP_ERROR_CHECK(esp_dma_capable_malloc(EXAMPLE_LCD_H_RES * 100 * sizeof(lv_color_t), &dma_mem_info, (void *)&buf1, NULL)); From 8e9b1501c00c09c6fbfb35ce4d7fbfff3b2a3d1e Mon Sep 17 00:00:00 2001 From: gaoxu Date: Tue, 2 Apr 2024 10:02:41 +0800 Subject: [PATCH 4/6] fix(dma): fix s3 dma reg spell error --- components/hal/esp32s3/include/hal/gdma_ll.h | 4 +- components/soc/esp32s3/include/soc/gdma_reg.h | 559 +++++++++--------- .../soc/esp32s3/include/soc/gdma_struct.h | 4 +- 3 files changed, 283 insertions(+), 284 deletions(-) diff --git a/components/hal/esp32s3/include/hal/gdma_ll.h b/components/hal/esp32s3/include/hal/gdma_ll.h index fa151f0e73..951145e85f 100644 --- a/components/hal/esp32s3/include/hal/gdma_ll.h +++ b/components/hal/esp32s3/include/hal/gdma_ll.h @@ -338,7 +338,7 @@ static inline uint32_t gdma_ll_rx_get_prefetched_desc_addr(gdma_dev_t *dev, uint */ static inline void gdma_ll_rx_set_weight(gdma_dev_t *dev, uint32_t channel, uint32_t weight) { - dev->channel[channel].in.wight.rx_weight = weight; + dev->channel[channel].in.weight.rx_weight = weight; } /** @@ -597,7 +597,7 @@ static inline uint32_t gdma_ll_tx_get_prefetched_desc_addr(gdma_dev_t *dev, uint */ static inline void gdma_ll_tx_set_weight(gdma_dev_t *dev, uint32_t channel, uint32_t weight) { - dev->channel[channel].out.wight.tx_weight = weight; + dev->channel[channel].out.weight.tx_weight = weight; } /** diff --git a/components/soc/esp32s3/include/soc/gdma_reg.h b/components/soc/esp32s3/include/soc/gdma_reg.h index 62b3402947..53e76bdc6f 100644 --- a/components/soc/esp32s3/include/soc/gdma_reg.h +++ b/components/soc/esp32s3/include/soc/gdma_reg.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -14,8 +14,7 @@ extern "C" { #define GDMA_IN_CONF0_CH0_REG (DR_REG_GDMA_BASE + 0x0) /* GDMA_MEM_TRANS_EN_CH0 : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: Set this bit 1 to enable automatic transmitting data from memory to memory via D -MA..*/ +/*description: Set this bit 1 to enable automatic transmitting data from memory to memory via DMA..*/ #define GDMA_MEM_TRANS_EN_CH0 (BIT(4)) #define GDMA_MEM_TRANS_EN_CH0_M (BIT(4)) #define GDMA_MEM_TRANS_EN_CH0_V 0x1 @@ -28,8 +27,8 @@ when accessing internal SRAM. .*/ #define GDMA_IN_DATA_BURST_EN_CH0_V 0x1 #define GDMA_IN_DATA_BURST_EN_CH0_S 3 /* GDMA_INDSCR_BURST_EN_CH0 : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link de -scriptor when accessing internal SRAM. .*/ +/*description: Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link +descriptor when accessing internal SRAM. .*/ #define GDMA_INDSCR_BURST_EN_CH0 (BIT(2)) #define GDMA_INDSCR_BURST_EN_CH0_M (BIT(2)) #define GDMA_INDSCR_BURST_EN_CH0_V 0x1 @@ -62,8 +61,8 @@ scriptor when accessing internal SRAM. .*/ #define GDMA_IN_CHECK_OWNER_CH0_V 0x1 #define GDMA_IN_CHECK_OWNER_CH0_S 12 /* GDMA_DMA_INFIFO_FULL_THRS_CH0 : R/W ;bitpos:[11:0] ;default: 12'hc ; */ -/*description: This register is used to generate the INFIFO_FULL_WM_INT interrupt when Rx chann -el 0 received byte number in Rx FIFO is up to the value of the register..*/ +/*description: This register is used to generate the INFIFO_FULL_WM_INT interrupt when Rx +channel 0 received byte number in Rx FIFO is up to the value of the register..*/ #define GDMA_DMA_INFIFO_FULL_THRS_CH0 0x00000FFF #define GDMA_DMA_INFIFO_FULL_THRS_CH0_M ((GDMA_DMA_INFIFO_FULL_THRS_CH0_V)<<(GDMA_DMA_INFIFO_FULL_THRS_CH0_S)) #define GDMA_DMA_INFIFO_FULL_THRS_CH0_V 0xFFF @@ -99,15 +98,15 @@ overflow. .*/ #define GDMA_INFIFO_OVF_L1_CH0_INT_RAW_V 0x1 #define GDMA_INFIFO_OVF_L1_CH0_INT_RAW_S 6 /* GDMA_INFIFO_FULL_WM_CH0_INT_RAW : R/WTC/SS ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when received data byte number is up t -o threshold configured by REG_DMA_INFIFO_FULL_THRS_CH0 in Rx FIFO of channel 0..*/ +/*description: The raw interrupt bit turns to high level when received data byte number is up +to threshold configured by REG_DMA_INFIFO_FULL_THRS_CH0 in Rx FIFO of channel 0..*/ #define GDMA_INFIFO_FULL_WM_CH0_INT_RAW (BIT(5)) #define GDMA_INFIFO_FULL_WM_CH0_INT_RAW_M (BIT(5)) #define GDMA_INFIFO_FULL_WM_CH0_INT_RAW_V 0x1 #define GDMA_INFIFO_FULL_WM_CH0_INT_RAW_S 5 /* GDMA_IN_DSCR_EMPTY_CH0_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when Rx buffer pointed by inlink is fu -ll and receiving data is not completed, but there is no more inlink for Rx chann +/*description: The raw interrupt bit turns to high level when Rx buffer pointed by inlink is +full and receiving data is not completed, but there is no more inlink for Rx chann el 0..*/ #define GDMA_IN_DSCR_EMPTY_CH0_INT_RAW (BIT(4)) #define GDMA_IN_DSCR_EMPTY_CH0_INT_RAW_M (BIT(4)) @@ -115,23 +114,23 @@ el 0..*/ #define GDMA_IN_DSCR_EMPTY_CH0_INT_RAW_S 4 /* GDMA_IN_DSCR_ERR_CH0_INT_RAW : R/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */ /*description: The raw interrupt bit turns to high level when detecting inlink descriptor error -, including owner error, the second and third word error of inlink descriptor fo -r Rx channel 0..*/ +, including owner error, the second and third word error of inlink descriptor +for Rx channel 0..*/ #define GDMA_IN_DSCR_ERR_CH0_INT_RAW (BIT(3)) #define GDMA_IN_DSCR_ERR_CH0_INT_RAW_M (BIT(3)) #define GDMA_IN_DSCR_ERR_CH0_INT_RAW_V 0x1 #define GDMA_IN_DSCR_ERR_CH0_INT_RAW_S 3 /* GDMA_IN_ERR_EOF_CH0_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when data error is detected only in th -e case that the peripheral is UHCI0 for Rx channel 0. For other peripherals, thi -s raw interrupt is reserved..*/ +/*description: The raw interrupt bit turns to high level when data error is detected only in +the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals, +this raw interrupt is reserved..*/ #define GDMA_IN_ERR_EOF_CH0_INT_RAW (BIT(2)) #define GDMA_IN_ERR_EOF_CH0_INT_RAW_M (BIT(2)) #define GDMA_IN_ERR_EOF_CH0_INT_RAW_V 0x1 #define GDMA_IN_ERR_EOF_CH0_INT_RAW_S 2 /* GDMA_IN_SUC_EOF_CH0_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when the last data pointed by one inli -nk descriptor has been received for Rx channel 0. For UHCI0, the raw interrupt b +/*description: The raw interrupt bit turns to high level when the last data pointed by +oneinlink descriptor has been received for Rx channel 0. For UHCI0, the raw interrupt b it turns to high level when the last data pointed by one inlink descriptor has b een received and no data error is detected for Rx channel 0..*/ #define GDMA_IN_SUC_EOF_CH0_INT_RAW (BIT(1)) @@ -139,8 +138,8 @@ een received and no data error is detected for Rx channel 0..*/ #define GDMA_IN_SUC_EOF_CH0_INT_RAW_V 0x1 #define GDMA_IN_SUC_EOF_CH0_INT_RAW_S 1 /* GDMA_IN_DONE_CH0_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when the last data pointed by one inli -nk descriptor has been received for Rx channel 0..*/ +/*description: The raw interrupt bit turns to high level when the last data pointed by one +inlink descriptor has been received for Rx channel 0..*/ #define GDMA_IN_DONE_CH0_INT_RAW (BIT(0)) #define GDMA_IN_DONE_CH0_INT_RAW_M (BIT(0)) #define GDMA_IN_DONE_CH0_INT_RAW_V 0x1 @@ -459,15 +458,15 @@ nk descriptor has been received for Rx channel 0..*/ #define GDMA_INLINK_STOP_CH0_V 0x1 #define GDMA_INLINK_STOP_CH0_S 21 /* GDMA_INLINK_AUTO_RET_CH0 : R/W ;bitpos:[20] ;default: 1'b1 ; */ -/*description: Set this bit to return to current inlink descriptor's address, when there are so -me errors in current receiving data..*/ +/*description: Set this bit to return to current inlink descriptor's address, when there are +some errors in current receiving data..*/ #define GDMA_INLINK_AUTO_RET_CH0 (BIT(20)) #define GDMA_INLINK_AUTO_RET_CH0_M (BIT(20)) #define GDMA_INLINK_AUTO_RET_CH0_V 0x1 #define GDMA_INLINK_AUTO_RET_CH0_S 20 /* GDMA_INLINK_ADDR_CH0 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ -/*description: This register stores the 20 least significant bits of the first inlink descripto -r's address..*/ +/*description: This register stores the 20 least significant bits of the first inlink +descriptor's address..*/ #define GDMA_INLINK_ADDR_CH0 0x000FFFFF #define GDMA_INLINK_ADDR_CH0_M ((GDMA_INLINK_ADDR_CH0_V)<<(GDMA_INLINK_ADDR_CH0_S)) #define GDMA_INLINK_ADDR_CH0_V 0xFFFFF @@ -495,8 +494,8 @@ r's address..*/ #define GDMA_IN_SUC_EOF_DES_ADDR_CH0_REG (DR_REG_GDMA_BASE + 0x28) /* GDMA_IN_SUC_EOF_DES_ADDR_CH0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: This register stores the address of the inlink descriptor when the EOF bit in th -is descriptor is 1..*/ +/*description: This register stores the address of the inlink descriptor when the EOF bit in +this descriptor is 1..*/ #define GDMA_IN_SUC_EOF_DES_ADDR_CH0 0xFFFFFFFF #define GDMA_IN_SUC_EOF_DES_ADDR_CH0_M ((GDMA_IN_SUC_EOF_DES_ADDR_CH0_V)<<(GDMA_IN_SUC_EOF_DES_ADDR_CH0_S)) #define GDMA_IN_SUC_EOF_DES_ADDR_CH0_V 0xFFFFFFFF @@ -504,8 +503,8 @@ is descriptor is 1..*/ #define GDMA_IN_ERR_EOF_DES_ADDR_CH0_REG (DR_REG_GDMA_BASE + 0x2C) /* GDMA_IN_ERR_EOF_DES_ADDR_CH0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: This register stores the address of the inlink descriptor when there are some er -rors in current receiving data. Only used when peripheral is UHCI0..*/ +/*description: This register stores the address of the inlink descriptor when there are some +errors in current receiving data. Only used when peripheral is UHCI0..*/ #define GDMA_IN_ERR_EOF_DES_ADDR_CH0 0xFFFFFFFF #define GDMA_IN_ERR_EOF_DES_ADDR_CH0_M ((GDMA_IN_ERR_EOF_DES_ADDR_CH0_V)<<(GDMA_IN_ERR_EOF_DES_ADDR_CH0_S)) #define GDMA_IN_ERR_EOF_DES_ADDR_CH0_V 0xFFFFFFFF @@ -535,7 +534,7 @@ rors in current receiving data. Only used when peripheral is UHCI0..*/ #define GDMA_INLINK_DSCR_BF1_CH0_V 0xFFFFFFFF #define GDMA_INLINK_DSCR_BF1_CH0_S 0 -#define GDMA_IN_WIGHT_CH0_REG (DR_REG_GDMA_BASE + 0x3C) +#define GDMA_IN_WEIGHT_CH0_REG (DR_REG_GDMA_BASE + 0x3C) /* GDMA_RX_WEIGHT_CH0 : R/W ;bitpos:[11:8] ;default: 4'hf ; */ /*description: The weight of Rx channel 0. .*/ #define GDMA_RX_WEIGHT_CH0 0x0000000F @@ -545,8 +544,8 @@ rors in current receiving data. Only used when peripheral is UHCI0..*/ #define GDMA_IN_PRI_CH0_REG (DR_REG_GDMA_BASE + 0x44) /* GDMA_RX_PRI_CH0 : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ -/*description: The priority of Rx channel 0. The larger of the value, the higher of the priorit -y..*/ +/*description: The priority of Rx channel 0. The larger of the value, the higher of the +priority..*/ #define GDMA_RX_PRI_CH0 0x0000000F #define GDMA_RX_PRI_CH0_M ((GDMA_RX_PRI_CH0_V)<<(GDMA_RX_PRI_CH0_S)) #define GDMA_RX_PRI_CH0_V 0xF @@ -563,15 +562,15 @@ y..*/ #define GDMA_OUT_CONF0_CH0_REG (DR_REG_GDMA_BASE + 0x60) /* GDMA_OUT_DATA_BURST_EN_CH0 : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting da -ta when accessing internal SRAM. .*/ +/*description: Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting +data when accessing internal SRAM. .*/ #define GDMA_OUT_DATA_BURST_EN_CH0 (BIT(5)) #define GDMA_OUT_DATA_BURST_EN_CH0_M (BIT(5)) #define GDMA_OUT_DATA_BURST_EN_CH0_V 0x1 #define GDMA_OUT_DATA_BURST_EN_CH0_S 5 /* GDMA_OUTDSCR_BURST_EN_CH0 : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link de -scriptor when accessing internal SRAM. .*/ +/*description: Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link +descriptor when accessing internal SRAM. .*/ #define GDMA_OUTDSCR_BURST_EN_CH0 (BIT(4)) #define GDMA_OUTDSCR_BURST_EN_CH0_M (BIT(4)) #define GDMA_OUTDSCR_BURST_EN_CH0_V 0x1 @@ -584,8 +583,8 @@ scriptor when accessing internal SRAM. .*/ #define GDMA_OUT_EOF_MODE_CH0_V 0x1 #define GDMA_OUT_EOF_MODE_CH0_S 3 /* GDMA_OUT_AUTO_WRBACK_CH0 : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: Set this bit to enable automatic outlink-writeback when all the data in tx buffe -r has been transmitted..*/ +/*description: Set this bit to enable automatic outlink-writeback when all the data in tx +buffer has been transmitted..*/ #define GDMA_OUT_AUTO_WRBACK_CH0 (BIT(2)) #define GDMA_OUT_AUTO_WRBACK_CH0_M (BIT(2)) #define GDMA_OUT_AUTO_WRBACK_CH0_V 0x1 @@ -648,31 +647,31 @@ overflow. .*/ #define GDMA_OUTFIFO_OVF_L1_CH0_INT_RAW_V 0x1 #define GDMA_OUTFIFO_OVF_L1_CH0_INT_RAW_S 4 /* GDMA_OUT_TOTAL_EOF_CH0_INT_RAW : R/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when data corresponding a outlink (inc -ludes one link descriptor or few link descriptors) is transmitted out for Tx cha +/*description: The raw interrupt bit turns to high level when data corresponding a outlink +(includes one link descriptor or few link descriptors) is transmitted out for Tx cha nnel 0..*/ #define GDMA_OUT_TOTAL_EOF_CH0_INT_RAW (BIT(3)) #define GDMA_OUT_TOTAL_EOF_CH0_INT_RAW_M (BIT(3)) #define GDMA_OUT_TOTAL_EOF_CH0_INT_RAW_V 0x1 #define GDMA_OUT_TOTAL_EOF_CH0_INT_RAW_S 3 /* GDMA_OUT_DSCR_ERR_CH0_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when detecting outlink descriptor erro -r, including owner error, the second and third word error of outlink descriptor +/*description: The raw interrupt bit turns to high level when detecting outlink descriptor +error, including owner error, the second and third word error of outlink descriptor for Tx channel 0..*/ #define GDMA_OUT_DSCR_ERR_CH0_INT_RAW (BIT(2)) #define GDMA_OUT_DSCR_ERR_CH0_INT_RAW_M (BIT(2)) #define GDMA_OUT_DSCR_ERR_CH0_INT_RAW_V 0x1 #define GDMA_OUT_DSCR_ERR_CH0_INT_RAW_S 2 /* GDMA_OUT_EOF_CH0_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when the last data pointed by one outl -ink descriptor has been read from memory for Tx channel 0. .*/ +/*description: The raw interrupt bit turns to high level when the last data pointed by one +outlink descriptor has been read from memory for Tx channel 0. .*/ #define GDMA_OUT_EOF_CH0_INT_RAW (BIT(1)) #define GDMA_OUT_EOF_CH0_INT_RAW_M (BIT(1)) #define GDMA_OUT_EOF_CH0_INT_RAW_V 0x1 #define GDMA_OUT_EOF_CH0_INT_RAW_S 1 /* GDMA_OUT_DONE_CH0_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when the last data pointed by one outl -ink descriptor has been transmitted to peripherals for Tx channel 0..*/ +/*description: The raw interrupt bit turns to high level when the last data pointed by one +outlink descriptor has been transmitted to peripherals for Tx channel 0..*/ #define GDMA_OUT_DONE_CH0_INT_RAW (BIT(0)) #define GDMA_OUT_DONE_CH0_INT_RAW_M (BIT(0)) #define GDMA_OUT_DONE_CH0_INT_RAW_V 0x1 @@ -924,8 +923,8 @@ ink descriptor has been transmitted to peripherals for Tx channel 0..*/ #define GDMA_OUT_LINK_CH0_REG (DR_REG_GDMA_BASE + 0x80) /* GDMA_OUTLINK_PARK_CH0 : RO ;bitpos:[23] ;default: 1'h1 ; */ -/*description: 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's F -SM is working..*/ +/*description: 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's +FSM is working..*/ #define GDMA_OUTLINK_PARK_CH0 (BIT(23)) #define GDMA_OUTLINK_PARK_CH0_M (BIT(23)) #define GDMA_OUTLINK_PARK_CH0_V 0x1 @@ -949,8 +948,8 @@ SM is working..*/ #define GDMA_OUTLINK_STOP_CH0_V 0x1 #define GDMA_OUTLINK_STOP_CH0_S 20 /* GDMA_OUTLINK_ADDR_CH0 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ -/*description: This register stores the 20 least significant bits of the first outlink descript -or's address..*/ +/*description: This register stores the 20 least significant bits of the first outlink +descriptor's address..*/ #define GDMA_OUTLINK_ADDR_CH0 0x000FFFFF #define GDMA_OUTLINK_ADDR_CH0_M ((GDMA_OUTLINK_ADDR_CH0_V)<<(GDMA_OUTLINK_ADDR_CH0_S)) #define GDMA_OUTLINK_ADDR_CH0_V 0xFFFFF @@ -978,8 +977,8 @@ or's address..*/ #define GDMA_OUT_EOF_DES_ADDR_CH0_REG (DR_REG_GDMA_BASE + 0x88) /* GDMA_OUT_EOF_DES_ADDR_CH0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: This register stores the address of the outlink descriptor when the EOF bit in t -his descriptor is 1..*/ +/*description: This register stores the address of the outlink descriptor when the EOF bit in +this descriptor is 1..*/ #define GDMA_OUT_EOF_DES_ADDR_CH0 0xFFFFFFFF #define GDMA_OUT_EOF_DES_ADDR_CH0_M ((GDMA_OUT_EOF_DES_ADDR_CH0_V)<<(GDMA_OUT_EOF_DES_ADDR_CH0_S)) #define GDMA_OUT_EOF_DES_ADDR_CH0_V 0xFFFFFFFF @@ -987,8 +986,8 @@ his descriptor is 1..*/ #define GDMA_OUT_EOF_BFR_DES_ADDR_CH0_REG (DR_REG_GDMA_BASE + 0x8C) /* GDMA_OUT_EOF_BFR_DES_ADDR_CH0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: This register stores the address of the outlink descriptor before the last outli -nk descriptor..*/ +/*description: This register stores the address of the outlink descriptor before the last +outlink descriptor..*/ #define GDMA_OUT_EOF_BFR_DES_ADDR_CH0 0xFFFFFFFF #define GDMA_OUT_EOF_BFR_DES_ADDR_CH0_M ((GDMA_OUT_EOF_BFR_DES_ADDR_CH0_V)<<(GDMA_OUT_EOF_BFR_DES_ADDR_CH0_S)) #define GDMA_OUT_EOF_BFR_DES_ADDR_CH0_V 0xFFFFFFFF @@ -1018,7 +1017,7 @@ nk descriptor..*/ #define GDMA_OUTLINK_DSCR_BF1_CH0_V 0xFFFFFFFF #define GDMA_OUTLINK_DSCR_BF1_CH0_S 0 -#define GDMA_OUT_WIGHT_CH0_REG (DR_REG_GDMA_BASE + 0x9C) +#define GDMA_OUT_WEIGHT_CH0_REG (DR_REG_GDMA_BASE + 0x9C) /* GDMA_TX_WEIGHT_CH0 : R/W ;bitpos:[11:8] ;default: 4'hf ; */ /*description: The weight of Tx channel 0. .*/ #define GDMA_TX_WEIGHT_CH0 0x0000000F @@ -1047,8 +1046,8 @@ S. 8: SHA. 9: ADC_DAC..*/ #define GDMA_IN_CONF0_CH1_REG (DR_REG_GDMA_BASE + 0xC0) /* GDMA_MEM_TRANS_EN_CH1 : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: Set this bit 1 to enable automatic transmitting data from memory to memory via D -MA..*/ +/*description: Set this bit 1 to enable automatic transmitting data from memory to memory via +DMA..*/ #define GDMA_MEM_TRANS_EN_CH1 (BIT(4)) #define GDMA_MEM_TRANS_EN_CH1_M (BIT(4)) #define GDMA_MEM_TRANS_EN_CH1_V 0x1 @@ -1061,8 +1060,8 @@ when accessing internal SRAM. .*/ #define GDMA_IN_DATA_BURST_EN_CH1_V 0x1 #define GDMA_IN_DATA_BURST_EN_CH1_S 3 /* GDMA_INDSCR_BURST_EN_CH1 : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: Set this bit to 1 to enable INCR burst transfer for Rx channel 1 reading link de -scriptor when accessing internal SRAM. .*/ +/*description: Set this bit to 1 to enable INCR burst transfer for Rx channel 1 reading link +descriptor when accessing internal SRAM. .*/ #define GDMA_INDSCR_BURST_EN_CH1 (BIT(2)) #define GDMA_INDSCR_BURST_EN_CH1_M (BIT(2)) #define GDMA_INDSCR_BURST_EN_CH1_V 0x1 @@ -1095,8 +1094,8 @@ scriptor when accessing internal SRAM. .*/ #define GDMA_IN_CHECK_OWNER_CH1_V 0x1 #define GDMA_IN_CHECK_OWNER_CH1_S 12 /* GDMA_DMA_INFIFO_FULL_THRS_CH1 : R/W ;bitpos:[11:0] ;default: 12'hc ; */ -/*description: This register is used to generate the INFIFO_FULL_WM_INT interrupt when Rx chann -el 0 received byte number in Rx FIFO is up to the value of the register..*/ +/*description: This register is used to generate the INFIFO_FULL_WM_INT interrupt when Rx +channel 0 received byte number in Rx FIFO is up to the value of the register..*/ #define GDMA_DMA_INFIFO_FULL_THRS_CH1 0x00000FFF #define GDMA_DMA_INFIFO_FULL_THRS_CH1_M ((GDMA_DMA_INFIFO_FULL_THRS_CH1_V)<<(GDMA_DMA_INFIFO_FULL_THRS_CH1_S)) #define GDMA_DMA_INFIFO_FULL_THRS_CH1_V 0xFFF @@ -1132,15 +1131,15 @@ overflow. .*/ #define GDMA_INFIFO_OVF_L1_CH1_INT_RAW_V 0x1 #define GDMA_INFIFO_OVF_L1_CH1_INT_RAW_S 6 /* GDMA_INFIFO_FULL_WM_CH1_INT_RAW : R/WTC/SS ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when received data byte number is up t -o threshold configured by REG_DMA_INFIFO_FULL_THRS_CH0 in Rx FIFO of channel 1..*/ +/*description: The raw interrupt bit turns to high level when received data byte number is up +to threshold configured by REG_DMA_INFIFO_FULL_THRS_CH0 in Rx FIFO of channel 1..*/ #define GDMA_INFIFO_FULL_WM_CH1_INT_RAW (BIT(5)) #define GDMA_INFIFO_FULL_WM_CH1_INT_RAW_M (BIT(5)) #define GDMA_INFIFO_FULL_WM_CH1_INT_RAW_V 0x1 #define GDMA_INFIFO_FULL_WM_CH1_INT_RAW_S 5 /* GDMA_IN_DSCR_EMPTY_CH1_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when Rx buffer pointed by inlink is fu -ll and receiving data is not completed, but there is no more inlink for Rx chann +/*description: The raw interrupt bit turns to high level when Rx buffer pointed by inlink is +full and receiving data is not completed, but there is no more inlink for Rx chann el 1..*/ #define GDMA_IN_DSCR_EMPTY_CH1_INT_RAW (BIT(4)) #define GDMA_IN_DSCR_EMPTY_CH1_INT_RAW_M (BIT(4)) @@ -1148,32 +1147,32 @@ el 1..*/ #define GDMA_IN_DSCR_EMPTY_CH1_INT_RAW_S 4 /* GDMA_IN_DSCR_ERR_CH1_INT_RAW : R/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */ /*description: The raw interrupt bit turns to high level when detecting inlink descriptor error -, including owner error, the second and third word error of inlink descriptor fo -r Rx channel 1..*/ +, including owner error, the second and third word error of inlink descriptor +for Rx channel 1..*/ #define GDMA_IN_DSCR_ERR_CH1_INT_RAW (BIT(3)) #define GDMA_IN_DSCR_ERR_CH1_INT_RAW_M (BIT(3)) #define GDMA_IN_DSCR_ERR_CH1_INT_RAW_V 0x1 #define GDMA_IN_DSCR_ERR_CH1_INT_RAW_S 3 /* GDMA_IN_ERR_EOF_CH1_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when data error is detected only in th -e case that the peripheral is UHCI0 for Rx channel 1. For other peripherals, thi -s raw interrupt is reserved..*/ +/*description: The raw interrupt bit turns to high level when data error is detected only in +the case that the peripheral is UHCI0 for Rx channel 1. For other peripherals, +this raw interrupt is reserved..*/ #define GDMA_IN_ERR_EOF_CH1_INT_RAW (BIT(2)) #define GDMA_IN_ERR_EOF_CH1_INT_RAW_M (BIT(2)) #define GDMA_IN_ERR_EOF_CH1_INT_RAW_V 0x1 #define GDMA_IN_ERR_EOF_CH1_INT_RAW_S 2 /* GDMA_IN_SUC_EOF_CH1_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when the last data pointed by one inli -nk descriptor has been received for Rx channel 1. For UHCI0, the raw interrupt b -it turns to high level when the last data pointed by one inlink descriptor has b -een received and no data error is detected for Rx channel 0..*/ +/*description: The raw interrupt bit turns to high level when the last data pointed by one +inlink descriptor has been received for Rx channel 1. For UHCI0, the raw interrupt +bit turns to high level when the last data pointed by one inlink descriptor has +been received and no data error is detected for Rx channel 0..*/ #define GDMA_IN_SUC_EOF_CH1_INT_RAW (BIT(1)) #define GDMA_IN_SUC_EOF_CH1_INT_RAW_M (BIT(1)) #define GDMA_IN_SUC_EOF_CH1_INT_RAW_V 0x1 #define GDMA_IN_SUC_EOF_CH1_INT_RAW_S 1 /* GDMA_IN_DONE_CH1_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when the last data pointed by one inli -nk descriptor has been received for Rx channel 1..*/ +/*description: The raw interrupt bit turns to high level when the last data pointed by one +inlink descriptor has been received for Rx channel 1..*/ #define GDMA_IN_DONE_CH1_INT_RAW (BIT(0)) #define GDMA_IN_DONE_CH1_INT_RAW_M (BIT(0)) #define GDMA_IN_DONE_CH1_INT_RAW_V 0x1 @@ -1492,15 +1491,15 @@ nk descriptor has been received for Rx channel 1..*/ #define GDMA_INLINK_STOP_CH1_V 0x1 #define GDMA_INLINK_STOP_CH1_S 21 /* GDMA_INLINK_AUTO_RET_CH1 : R/W ;bitpos:[20] ;default: 1'b1 ; */ -/*description: Set this bit to return to current inlink descriptor's address, when there are so -me errors in current receiving data..*/ +/*description: Set this bit to return to current inlink descriptor's address, when there are +some errors in current receiving data..*/ #define GDMA_INLINK_AUTO_RET_CH1 (BIT(20)) #define GDMA_INLINK_AUTO_RET_CH1_M (BIT(20)) #define GDMA_INLINK_AUTO_RET_CH1_V 0x1 #define GDMA_INLINK_AUTO_RET_CH1_S 20 /* GDMA_INLINK_ADDR_CH1 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ -/*description: This register stores the 20 least significant bits of the first inlink descripto -r's address..*/ +/*description: This register stores the 20 least significant bits of the first inlink +descriptor's address..*/ #define GDMA_INLINK_ADDR_CH1 0x000FFFFF #define GDMA_INLINK_ADDR_CH1_M ((GDMA_INLINK_ADDR_CH1_V)<<(GDMA_INLINK_ADDR_CH1_S)) #define GDMA_INLINK_ADDR_CH1_V 0xFFFFF @@ -1528,8 +1527,8 @@ r's address..*/ #define GDMA_IN_SUC_EOF_DES_ADDR_CH1_REG (DR_REG_GDMA_BASE + 0xE8) /* GDMA_IN_SUC_EOF_DES_ADDR_CH1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: This register stores the address of the inlink descriptor when the EOF bit in th -is descriptor is 1..*/ +/*description: This register stores the address of the inlink descriptor when the EOF bit in +this descriptor is 1..*/ #define GDMA_IN_SUC_EOF_DES_ADDR_CH1 0xFFFFFFFF #define GDMA_IN_SUC_EOF_DES_ADDR_CH1_M ((GDMA_IN_SUC_EOF_DES_ADDR_CH1_V)<<(GDMA_IN_SUC_EOF_DES_ADDR_CH1_S)) #define GDMA_IN_SUC_EOF_DES_ADDR_CH1_V 0xFFFFFFFF @@ -1537,8 +1536,8 @@ is descriptor is 1..*/ #define GDMA_IN_ERR_EOF_DES_ADDR_CH1_REG (DR_REG_GDMA_BASE + 0xEC) /* GDMA_IN_ERR_EOF_DES_ADDR_CH1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: This register stores the address of the inlink descriptor when there are some er -rors in current receiving data. Only used when peripheral is UHCI0..*/ +/*description: This register stores the address of the inlink descriptor when there are some +errors in current receiving data. Only used when peripheral is UHCI0..*/ #define GDMA_IN_ERR_EOF_DES_ADDR_CH1 0xFFFFFFFF #define GDMA_IN_ERR_EOF_DES_ADDR_CH1_M ((GDMA_IN_ERR_EOF_DES_ADDR_CH1_V)<<(GDMA_IN_ERR_EOF_DES_ADDR_CH1_S)) #define GDMA_IN_ERR_EOF_DES_ADDR_CH1_V 0xFFFFFFFF @@ -1568,7 +1567,7 @@ rors in current receiving data. Only used when peripheral is UHCI0..*/ #define GDMA_INLINK_DSCR_BF1_CH1_V 0xFFFFFFFF #define GDMA_INLINK_DSCR_BF1_CH1_S 0 -#define GDMA_IN_WIGHT_CH1_REG (DR_REG_GDMA_BASE + 0xFC) +#define GDMA_IN_WEIGHT_CH1_REG (DR_REG_GDMA_BASE + 0xFC) /* GDMA_RX_WEIGHT_CH1 : R/W ;bitpos:[11:8] ;default: 4'hf ; */ /*description: The weight of Rx channel 1. .*/ #define GDMA_RX_WEIGHT_CH1 0x0000000F @@ -1578,8 +1577,8 @@ rors in current receiving data. Only used when peripheral is UHCI0..*/ #define GDMA_IN_PRI_CH1_REG (DR_REG_GDMA_BASE + 0x104) /* GDMA_RX_PRI_CH1 : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ -/*description: The priority of Rx channel 1. The larger of the value, the higher of the priorit -y..*/ +/*description: The priority of Rx channel 1. The larger of the value, the higher of the +priority..*/ #define GDMA_RX_PRI_CH1 0x0000000F #define GDMA_RX_PRI_CH1_M ((GDMA_RX_PRI_CH1_V)<<(GDMA_RX_PRI_CH1_S)) #define GDMA_RX_PRI_CH1_V 0xF @@ -1596,15 +1595,15 @@ y..*/ #define GDMA_OUT_CONF0_CH1_REG (DR_REG_GDMA_BASE + 0x120) /* GDMA_OUT_DATA_BURST_EN_CH1 : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: Set this bit to 1 to enable INCR burst transfer for Tx channel 1 transmitting da -ta when accessing internal SRAM. .*/ +/*description: Set this bit to 1 to enable INCR burst transfer for Tx channel 1 transmitting +data when accessing internal SRAM. .*/ #define GDMA_OUT_DATA_BURST_EN_CH1 (BIT(5)) #define GDMA_OUT_DATA_BURST_EN_CH1_M (BIT(5)) #define GDMA_OUT_DATA_BURST_EN_CH1_V 0x1 #define GDMA_OUT_DATA_BURST_EN_CH1_S 5 /* GDMA_OUTDSCR_BURST_EN_CH1 : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: Set this bit to 1 to enable INCR burst transfer for Tx channel 1 reading link de -scriptor when accessing internal SRAM. .*/ +/*description: Set this bit to 1 to enable INCR burst transfer for Tx channel 1 reading link +descriptor when accessing internal SRAM. .*/ #define GDMA_OUTDSCR_BURST_EN_CH1 (BIT(4)) #define GDMA_OUTDSCR_BURST_EN_CH1_M (BIT(4)) #define GDMA_OUTDSCR_BURST_EN_CH1_V 0x1 @@ -1617,8 +1616,8 @@ scriptor when accessing internal SRAM. .*/ #define GDMA_OUT_EOF_MODE_CH1_V 0x1 #define GDMA_OUT_EOF_MODE_CH1_S 3 /* GDMA_OUT_AUTO_WRBACK_CH1 : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: Set this bit to enable automatic outlink-writeback when all the data in tx buffe -r has been transmitted..*/ +/*description: Set this bit to enable automatic outlink-writeback when all the data in tx +buffer has been transmitted..*/ #define GDMA_OUT_AUTO_WRBACK_CH1 (BIT(2)) #define GDMA_OUT_AUTO_WRBACK_CH1_M (BIT(2)) #define GDMA_OUT_AUTO_WRBACK_CH1_V 0x1 @@ -1681,31 +1680,31 @@ overflow. .*/ #define GDMA_OUTFIFO_OVF_L1_CH1_INT_RAW_V 0x1 #define GDMA_OUTFIFO_OVF_L1_CH1_INT_RAW_S 4 /* GDMA_OUT_TOTAL_EOF_CH1_INT_RAW : R/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when data corresponding a outlink (inc -ludes one link descriptor or few link descriptors) is transmitted out for Tx cha +/*description: The raw interrupt bit turns to high level when data corresponding a outlink ' +(includes one link descriptor or few link descriptors) is transmitted out for Tx cha nnel 1..*/ #define GDMA_OUT_TOTAL_EOF_CH1_INT_RAW (BIT(3)) #define GDMA_OUT_TOTAL_EOF_CH1_INT_RAW_M (BIT(3)) #define GDMA_OUT_TOTAL_EOF_CH1_INT_RAW_V 0x1 #define GDMA_OUT_TOTAL_EOF_CH1_INT_RAW_S 3 /* GDMA_OUT_DSCR_ERR_CH1_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when detecting outlink descriptor erro -r, including owner error, the second and third word error of outlink descriptor +/*description: The raw interrupt bit turns to high level when detecting outlink descriptor +error, including owner error, the second and third word error of outlink descriptor for Tx channel 1..*/ #define GDMA_OUT_DSCR_ERR_CH1_INT_RAW (BIT(2)) #define GDMA_OUT_DSCR_ERR_CH1_INT_RAW_M (BIT(2)) #define GDMA_OUT_DSCR_ERR_CH1_INT_RAW_V 0x1 #define GDMA_OUT_DSCR_ERR_CH1_INT_RAW_S 2 /* GDMA_OUT_EOF_CH1_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when the last data pointed by one outl -ink descriptor has been read from memory for Tx channel 1. .*/ +/*description: The raw interrupt bit turns to high level when the last data pointed by one +outlink descriptor has been read from memory for Tx channel 1. .*/ #define GDMA_OUT_EOF_CH1_INT_RAW (BIT(1)) #define GDMA_OUT_EOF_CH1_INT_RAW_M (BIT(1)) #define GDMA_OUT_EOF_CH1_INT_RAW_V 0x1 #define GDMA_OUT_EOF_CH1_INT_RAW_S 1 /* GDMA_OUT_DONE_CH1_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when the last data pointed by one outl -ink descriptor has been transmitted to peripherals for Tx channel 1..*/ +/*description: The raw interrupt bit turns to high level when the last data pointed by one +ouink descriptor has been transmitted to peripherals for Tx channel 1..*/ #define GDMA_OUT_DONE_CH1_INT_RAW (BIT(0)) #define GDMA_OUT_DONE_CH1_INT_RAW_M (BIT(0)) #define GDMA_OUT_DONE_CH1_INT_RAW_V 0x1 @@ -1957,8 +1956,8 @@ ink descriptor has been transmitted to peripherals for Tx channel 1..*/ #define GDMA_OUT_LINK_CH1_REG (DR_REG_GDMA_BASE + 0x140) /* GDMA_OUTLINK_PARK_CH1 : RO ;bitpos:[23] ;default: 1'h1 ; */ -/*description: 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's F -SM is working..*/ +/*description: 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's +FSM is working..*/ #define GDMA_OUTLINK_PARK_CH1 (BIT(23)) #define GDMA_OUTLINK_PARK_CH1_M (BIT(23)) #define GDMA_OUTLINK_PARK_CH1_V 0x1 @@ -1982,8 +1981,8 @@ SM is working..*/ #define GDMA_OUTLINK_STOP_CH1_V 0x1 #define GDMA_OUTLINK_STOP_CH1_S 20 /* GDMA_OUTLINK_ADDR_CH1 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ -/*description: This register stores the 20 least significant bits of the first outlink descript -or's address..*/ +/*description: This register stores the 20 least significant bits of the first outlink +descriptor's address..*/ #define GDMA_OUTLINK_ADDR_CH1 0x000FFFFF #define GDMA_OUTLINK_ADDR_CH1_M ((GDMA_OUTLINK_ADDR_CH1_V)<<(GDMA_OUTLINK_ADDR_CH1_S)) #define GDMA_OUTLINK_ADDR_CH1_V 0xFFFFF @@ -2011,8 +2010,8 @@ or's address..*/ #define GDMA_OUT_EOF_DES_ADDR_CH1_REG (DR_REG_GDMA_BASE + 0x148) /* GDMA_OUT_EOF_DES_ADDR_CH1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: This register stores the address of the outlink descriptor when the EOF bit in t -his descriptor is 1..*/ +/*description: This register stores the address of the outlink descriptor when the EOF bit in +this descriptor is 1..*/ #define GDMA_OUT_EOF_DES_ADDR_CH1 0xFFFFFFFF #define GDMA_OUT_EOF_DES_ADDR_CH1_M ((GDMA_OUT_EOF_DES_ADDR_CH1_V)<<(GDMA_OUT_EOF_DES_ADDR_CH1_S)) #define GDMA_OUT_EOF_DES_ADDR_CH1_V 0xFFFFFFFF @@ -2020,8 +2019,8 @@ his descriptor is 1..*/ #define GDMA_OUT_EOF_BFR_DES_ADDR_CH1_REG (DR_REG_GDMA_BASE + 0x14C) /* GDMA_OUT_EOF_BFR_DES_ADDR_CH1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: This register stores the address of the outlink descriptor before the last outli -nk descriptor..*/ +/*description: This register stores the address of the outlink descriptor before the last +outlink descriptor..*/ #define GDMA_OUT_EOF_BFR_DES_ADDR_CH1 0xFFFFFFFF #define GDMA_OUT_EOF_BFR_DES_ADDR_CH1_M ((GDMA_OUT_EOF_BFR_DES_ADDR_CH1_V)<<(GDMA_OUT_EOF_BFR_DES_ADDR_CH1_S)) #define GDMA_OUT_EOF_BFR_DES_ADDR_CH1_V 0xFFFFFFFF @@ -2051,7 +2050,7 @@ nk descriptor..*/ #define GDMA_OUTLINK_DSCR_BF1_CH1_V 0xFFFFFFFF #define GDMA_OUTLINK_DSCR_BF1_CH1_S 0 -#define GDMA_OUT_WIGHT_CH1_REG (DR_REG_GDMA_BASE + 0x15C) +#define GDMA_OUT_WEIGHT_CH1_REG (DR_REG_GDMA_BASE + 0x15C) /* GDMA_TX_WEIGHT_CH1 : R/W ;bitpos:[11:8] ;default: 4'hf ; */ /*description: The weight of Tx channel 1. .*/ #define GDMA_TX_WEIGHT_CH1 0x0000000F @@ -2061,8 +2060,8 @@ nk descriptor..*/ #define GDMA_OUT_PRI_CH1_REG (DR_REG_GDMA_BASE + 0x164) /* GDMA_TX_PRI_CH1 : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ -/*description: The priority of Tx channel 1. The larger of the value, the higher of the priorit -y..*/ +/*description: The priority of Tx channel 1. The larger of the value, the higher of the +priority..*/ #define GDMA_TX_PRI_CH1 0x0000000F #define GDMA_TX_PRI_CH1_M ((GDMA_TX_PRI_CH1_V)<<(GDMA_TX_PRI_CH1_S)) #define GDMA_TX_PRI_CH1_V 0xF @@ -2080,8 +2079,8 @@ S. 8: SHA. 9: ADC_DAC..*/ #define GDMA_IN_CONF0_CH2_REG (DR_REG_GDMA_BASE + 0x180) /* GDMA_MEM_TRANS_EN_CH2 : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: Set this bit 1 to enable automatic transmitting data from memory to memory via D -MA..*/ +/*description: Set this bit 1 to enable automatic transmitting data from memory to memory via +DMA..*/ #define GDMA_MEM_TRANS_EN_CH2 (BIT(4)) #define GDMA_MEM_TRANS_EN_CH2_M (BIT(4)) #define GDMA_MEM_TRANS_EN_CH2_V 0x1 @@ -2094,8 +2093,8 @@ when accessing internal SRAM. .*/ #define GDMA_IN_DATA_BURST_EN_CH2_V 0x1 #define GDMA_IN_DATA_BURST_EN_CH2_S 3 /* GDMA_INDSCR_BURST_EN_CH2 : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: Set this bit to 1 to enable INCR burst transfer for Rx channel 2 reading link de -scriptor when accessing internal SRAM. .*/ +/*description: Set this bit to 1 to enable INCR burst transfer for Rx channel 2 reading link +descriptor when accessing internal SRAM. .*/ #define GDMA_INDSCR_BURST_EN_CH2 (BIT(2)) #define GDMA_INDSCR_BURST_EN_CH2_M (BIT(2)) #define GDMA_INDSCR_BURST_EN_CH2_V 0x1 @@ -2128,8 +2127,8 @@ scriptor when accessing internal SRAM. .*/ #define GDMA_IN_CHECK_OWNER_CH2_V 0x1 #define GDMA_IN_CHECK_OWNER_CH2_S 12 /* GDMA_DMA_INFIFO_FULL_THRS_CH2 : R/W ;bitpos:[11:0] ;default: 12'hc ; */ -/*description: This register is used to generate the INFIFO_FULL_WM_INT interrupt when Rx chann -el 2 received byte number in Rx FIFO is up to the value of the register..*/ +/*description: This register is used to generate the INFIFO_FULL_WM_INT interrupt when Rx +channel 2 received byte number in Rx FIFO is up to the value of the register..*/ #define GDMA_DMA_INFIFO_FULL_THRS_CH2 0x00000FFF #define GDMA_DMA_INFIFO_FULL_THRS_CH2_M ((GDMA_DMA_INFIFO_FULL_THRS_CH2_V)<<(GDMA_DMA_INFIFO_FULL_THRS_CH2_S)) #define GDMA_DMA_INFIFO_FULL_THRS_CH2_V 0xFFF @@ -2165,15 +2164,15 @@ overflow. .*/ #define GDMA_INFIFO_OVF_L1_CH2_INT_RAW_V 0x1 #define GDMA_INFIFO_OVF_L1_CH2_INT_RAW_S 6 /* GDMA_INFIFO_FULL_WM_CH2_INT_RAW : R/WTC/SS ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when received data byte number is up t -o threshold configured by REG_DMA_INFIFO_FULL_THRS_CH0 in Rx FIFO of channel 2..*/ +/*description: The raw interrupt bit turns to high level when received data byte number is up +to threshold configured by REG_DMA_INFIFO_FULL_THRS_CH0 in Rx FIFO of channel 2..*/ #define GDMA_INFIFO_FULL_WM_CH2_INT_RAW (BIT(5)) #define GDMA_INFIFO_FULL_WM_CH2_INT_RAW_M (BIT(5)) #define GDMA_INFIFO_FULL_WM_CH2_INT_RAW_V 0x1 #define GDMA_INFIFO_FULL_WM_CH2_INT_RAW_S 5 /* GDMA_IN_DSCR_EMPTY_CH2_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when Rx buffer pointed by inlink is fu -ll and receiving data is not completed, but there is no more inlink for Rx chann +/*description: The raw interrupt bit turns to high level when Rx buffer pointed by inlink is +full and receiving data is not completed, but there is no more inlink for Rx chann el 2..*/ #define GDMA_IN_DSCR_EMPTY_CH2_INT_RAW (BIT(4)) #define GDMA_IN_DSCR_EMPTY_CH2_INT_RAW_M (BIT(4)) @@ -2181,16 +2180,16 @@ el 2..*/ #define GDMA_IN_DSCR_EMPTY_CH2_INT_RAW_S 4 /* GDMA_IN_DSCR_ERR_CH2_INT_RAW : R/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */ /*description: The raw interrupt bit turns to high level when detecting inlink descriptor error -, including owner error, the second and third word error of inlink descriptor fo -r Rx channel 2..*/ +, including owner error, the second and third word error of inlink descriptor +for Rx channel 2..*/ #define GDMA_IN_DSCR_ERR_CH2_INT_RAW (BIT(3)) #define GDMA_IN_DSCR_ERR_CH2_INT_RAW_M (BIT(3)) #define GDMA_IN_DSCR_ERR_CH2_INT_RAW_V 0x1 #define GDMA_IN_DSCR_ERR_CH2_INT_RAW_S 3 /* GDMA_IN_ERR_EOF_CH2_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when data error is detected only in th -e case that the peripheral is UHCI0 for Rx channel 2. For other peripherals, thi -s raw interrupt is reserved..*/ +/*description: The raw interrupt bit turns to high level when data error is detected only in +the case that the peripheral is UHCI0 for Rx channel 2. For other peripherals, +this raw interrupt is reserved..*/ #define GDMA_IN_ERR_EOF_CH2_INT_RAW (BIT(2)) #define GDMA_IN_ERR_EOF_CH2_INT_RAW_M (BIT(2)) #define GDMA_IN_ERR_EOF_CH2_INT_RAW_V 0x1 @@ -2525,14 +2524,14 @@ nk descriptor has been received for Rx channel 2..*/ #define GDMA_INLINK_STOP_CH2_V 0x1 #define GDMA_INLINK_STOP_CH2_S 21 /* GDMA_INLINK_AUTO_RET_CH2 : R/W ;bitpos:[20] ;default: 1'b1 ; */ -/*description: Set this bit to return to current inlink descriptor's address, when there are so -me errors in current receiving data..*/ +/*description: Set this bit to return to current inlink descriptor's address, when there are +some errors in current receiving data..*/ #define GDMA_INLINK_AUTO_RET_CH2 (BIT(20)) #define GDMA_INLINK_AUTO_RET_CH2_M (BIT(20)) #define GDMA_INLINK_AUTO_RET_CH2_V 0x1 #define GDMA_INLINK_AUTO_RET_CH2_S 20 /* GDMA_INLINK_ADDR_CH2 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ -/*description: This register stores the 20 least significant bits of the first inlink descripto +/*description: This register stores the 20 least significant bits of the first inlink descriptor r's address..*/ #define GDMA_INLINK_ADDR_CH2 0x000FFFFF #define GDMA_INLINK_ADDR_CH2_M ((GDMA_INLINK_ADDR_CH2_V)<<(GDMA_INLINK_ADDR_CH2_S)) @@ -2561,8 +2560,8 @@ r's address..*/ #define GDMA_IN_SUC_EOF_DES_ADDR_CH2_REG (DR_REG_GDMA_BASE + 0x1A8) /* GDMA_IN_SUC_EOF_DES_ADDR_CH2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: This register stores the address of the inlink descriptor when the EOF bit in th -is descriptor is 1..*/ +/*description: This register stores the address of the inlink descriptor when the EOF bit in +this descriptor is 1..*/ #define GDMA_IN_SUC_EOF_DES_ADDR_CH2 0xFFFFFFFF #define GDMA_IN_SUC_EOF_DES_ADDR_CH2_M ((GDMA_IN_SUC_EOF_DES_ADDR_CH2_V)<<(GDMA_IN_SUC_EOF_DES_ADDR_CH2_S)) #define GDMA_IN_SUC_EOF_DES_ADDR_CH2_V 0xFFFFFFFF @@ -2570,8 +2569,8 @@ is descriptor is 1..*/ #define GDMA_IN_ERR_EOF_DES_ADDR_CH2_REG (DR_REG_GDMA_BASE + 0x1AC) /* GDMA_IN_ERR_EOF_DES_ADDR_CH2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: This register stores the address of the inlink descriptor when there are some er -rors in current receiving data. Only used when peripheral is UHCI0..*/ +/*description: This register stores the address of the inlink descriptor when there are some +errors in current receiving data. Only used when peripheral is UHCI0..*/ #define GDMA_IN_ERR_EOF_DES_ADDR_CH2 0xFFFFFFFF #define GDMA_IN_ERR_EOF_DES_ADDR_CH2_M ((GDMA_IN_ERR_EOF_DES_ADDR_CH2_V)<<(GDMA_IN_ERR_EOF_DES_ADDR_CH2_S)) #define GDMA_IN_ERR_EOF_DES_ADDR_CH2_V 0xFFFFFFFF @@ -2601,7 +2600,7 @@ rors in current receiving data. Only used when peripheral is UHCI0..*/ #define GDMA_INLINK_DSCR_BF1_CH2_V 0xFFFFFFFF #define GDMA_INLINK_DSCR_BF1_CH2_S 0 -#define GDMA_IN_WIGHT_CH2_REG (DR_REG_GDMA_BASE + 0x1BC) +#define GDMA_IN_WEIGHT_CH2_REG (DR_REG_GDMA_BASE + 0x1BC) /* GDMA_RX_WEIGHT_CH2 : R/W ;bitpos:[11:8] ;default: 4'hf ; */ /*description: The weight of Rx channel 2. .*/ #define GDMA_RX_WEIGHT_CH2 0x0000000F @@ -2611,8 +2610,8 @@ rors in current receiving data. Only used when peripheral is UHCI0..*/ #define GDMA_IN_PRI_CH2_REG (DR_REG_GDMA_BASE + 0x1C4) /* GDMA_RX_PRI_CH2 : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ -/*description: The priority of Rx channel 2. The larger of the value, the higher of the priorit -y..*/ +/*description: The priority of Rx channel 2. The larger of the value, the higher of the +priority..*/ #define GDMA_RX_PRI_CH2 0x0000000F #define GDMA_RX_PRI_CH2_M ((GDMA_RX_PRI_CH2_V)<<(GDMA_RX_PRI_CH2_S)) #define GDMA_RX_PRI_CH2_V 0xF @@ -2629,15 +2628,15 @@ y..*/ #define GDMA_OUT_CONF0_CH2_REG (DR_REG_GDMA_BASE + 0x1E0) /* GDMA_OUT_DATA_BURST_EN_CH2 : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: Set this bit to 1 to enable INCR burst transfer for Tx channel 2 transmitting da -ta when accessing internal SRAM. .*/ +/*description: Set this bit to 1 to enable INCR burst transfer for Tx channel 2 transmitting +data when accessing internal SRAM. .*/ #define GDMA_OUT_DATA_BURST_EN_CH2 (BIT(5)) #define GDMA_OUT_DATA_BURST_EN_CH2_M (BIT(5)) #define GDMA_OUT_DATA_BURST_EN_CH2_V 0x1 #define GDMA_OUT_DATA_BURST_EN_CH2_S 5 /* GDMA_OUTDSCR_BURST_EN_CH2 : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: Set this bit to 1 to enable INCR burst transfer for Tx channel 2 reading link de -scriptor when accessing internal SRAM. .*/ +/*description: Set this bit to 1 to enable INCR burst transfer for Tx channel 2 reading link +descriptor when accessing internal SRAM. .*/ #define GDMA_OUTDSCR_BURST_EN_CH2 (BIT(4)) #define GDMA_OUTDSCR_BURST_EN_CH2_M (BIT(4)) #define GDMA_OUTDSCR_BURST_EN_CH2_V 0x1 @@ -2650,8 +2649,8 @@ scriptor when accessing internal SRAM. .*/ #define GDMA_OUT_EOF_MODE_CH2_V 0x1 #define GDMA_OUT_EOF_MODE_CH2_S 3 /* GDMA_OUT_AUTO_WRBACK_CH2 : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: Set this bit to enable automatic outlink-writeback when all the data in tx buffe -r has been transmitted..*/ +/*description: Set this bit to enable automatic outlink-writeback when all the data in tx +buffer has been transmitted..*/ #define GDMA_OUT_AUTO_WRBACK_CH2 (BIT(2)) #define GDMA_OUT_AUTO_WRBACK_CH2_M (BIT(2)) #define GDMA_OUT_AUTO_WRBACK_CH2_V 0x1 @@ -2714,31 +2713,31 @@ overflow. .*/ #define GDMA_OUTFIFO_OVF_L1_CH2_INT_RAW_V 0x1 #define GDMA_OUTFIFO_OVF_L1_CH2_INT_RAW_S 4 /* GDMA_OUT_TOTAL_EOF_CH2_INT_RAW : R/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when data corresponding a outlink (inc -ludes one link descriptor or few link descriptors) is transmitted out for Tx cha +/*description: The raw interrupt bit turns to high level when data corresponding a outlink +(includes one link descriptor or few link descriptors) is transmitted out for Tx cha nnel 2..*/ #define GDMA_OUT_TOTAL_EOF_CH2_INT_RAW (BIT(3)) #define GDMA_OUT_TOTAL_EOF_CH2_INT_RAW_M (BIT(3)) #define GDMA_OUT_TOTAL_EOF_CH2_INT_RAW_V 0x1 #define GDMA_OUT_TOTAL_EOF_CH2_INT_RAW_S 3 /* GDMA_OUT_DSCR_ERR_CH2_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when detecting outlink descriptor erro -r, including owner error, the second and third word error of outlink descriptor +/*description: The raw interrupt bit turns to high level when detecting outlink descriptor +error, including owner error, the second and third word error of outlink descriptor for Tx channel 2..*/ #define GDMA_OUT_DSCR_ERR_CH2_INT_RAW (BIT(2)) #define GDMA_OUT_DSCR_ERR_CH2_INT_RAW_M (BIT(2)) #define GDMA_OUT_DSCR_ERR_CH2_INT_RAW_V 0x1 #define GDMA_OUT_DSCR_ERR_CH2_INT_RAW_S 2 /* GDMA_OUT_EOF_CH2_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when the last data pointed by one outl -ink descriptor has been read from memory for Tx channel 2. .*/ +/*description: The raw interrupt bit turns to high level when the last data pointed by one +outlink descriptor has been read from memory for Tx channel 2. .*/ #define GDMA_OUT_EOF_CH2_INT_RAW (BIT(1)) #define GDMA_OUT_EOF_CH2_INT_RAW_M (BIT(1)) #define GDMA_OUT_EOF_CH2_INT_RAW_V 0x1 #define GDMA_OUT_EOF_CH2_INT_RAW_S 1 /* GDMA_OUT_DONE_CH2_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when the last data pointed by one outl -ink descriptor has been transmitted to peripherals for Tx channel 2..*/ +/*description: The raw interrupt bit turns to high level when the last data pointed by one +outlink descriptor has been transmitted to peripherals for Tx channel 2..*/ #define GDMA_OUT_DONE_CH2_INT_RAW (BIT(0)) #define GDMA_OUT_DONE_CH2_INT_RAW_M (BIT(0)) #define GDMA_OUT_DONE_CH2_INT_RAW_V 0x1 @@ -2990,8 +2989,8 @@ ink descriptor has been transmitted to peripherals for Tx channel 2..*/ #define GDMA_OUT_LINK_CH2_REG (DR_REG_GDMA_BASE + 0x200) /* GDMA_OUTLINK_PARK_CH2 : RO ;bitpos:[23] ;default: 1'h1 ; */ -/*description: 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's F -SM is working..*/ +/*description: 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's +FSM is working..*/ #define GDMA_OUTLINK_PARK_CH2 (BIT(23)) #define GDMA_OUTLINK_PARK_CH2_M (BIT(23)) #define GDMA_OUTLINK_PARK_CH2_V 0x1 @@ -3015,8 +3014,8 @@ SM is working..*/ #define GDMA_OUTLINK_STOP_CH2_V 0x1 #define GDMA_OUTLINK_STOP_CH2_S 20 /* GDMA_OUTLINK_ADDR_CH2 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ -/*description: This register stores the 20 least significant bits of the first outlink descript -or's address..*/ +/*description: This register stores the 20 least significant bits of the first outlink +descriptor's address..*/ #define GDMA_OUTLINK_ADDR_CH2 0x000FFFFF #define GDMA_OUTLINK_ADDR_CH2_M ((GDMA_OUTLINK_ADDR_CH2_V)<<(GDMA_OUTLINK_ADDR_CH2_S)) #define GDMA_OUTLINK_ADDR_CH2_V 0xFFFFF @@ -3044,8 +3043,8 @@ or's address..*/ #define GDMA_OUT_EOF_DES_ADDR_CH2_REG (DR_REG_GDMA_BASE + 0x208) /* GDMA_OUT_EOF_DES_ADDR_CH2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: This register stores the address of the outlink descriptor when the EOF bit in t -his descriptor is 1..*/ +/*description: This register stores the address of the outlink descriptor when the EOF bit in +this descriptor is 1..*/ #define GDMA_OUT_EOF_DES_ADDR_CH2 0xFFFFFFFF #define GDMA_OUT_EOF_DES_ADDR_CH2_M ((GDMA_OUT_EOF_DES_ADDR_CH2_V)<<(GDMA_OUT_EOF_DES_ADDR_CH2_S)) #define GDMA_OUT_EOF_DES_ADDR_CH2_V 0xFFFFFFFF @@ -3053,8 +3052,8 @@ his descriptor is 1..*/ #define GDMA_OUT_EOF_BFR_DES_ADDR_CH2_REG (DR_REG_GDMA_BASE + 0x20C) /* GDMA_OUT_EOF_BFR_DES_ADDR_CH2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: This register stores the address of the outlink descriptor before the last outli -nk descriptor..*/ +/*description: This register stores the address of the outlink descriptor before the last +outlink descriptor..*/ #define GDMA_OUT_EOF_BFR_DES_ADDR_CH2 0xFFFFFFFF #define GDMA_OUT_EOF_BFR_DES_ADDR_CH2_M ((GDMA_OUT_EOF_BFR_DES_ADDR_CH2_V)<<(GDMA_OUT_EOF_BFR_DES_ADDR_CH2_S)) #define GDMA_OUT_EOF_BFR_DES_ADDR_CH2_V 0xFFFFFFFF @@ -3084,7 +3083,7 @@ nk descriptor..*/ #define GDMA_OUTLINK_DSCR_BF1_CH2_V 0xFFFFFFFF #define GDMA_OUTLINK_DSCR_BF1_CH2_S 0 -#define GDMA_OUT_WIGHT_CH2_REG (DR_REG_GDMA_BASE + 0x21C) +#define GDMA_OUT_WEIGHT_CH2_REG (DR_REG_GDMA_BASE + 0x21C) /* GDMA_TX_WEIGHT_CH2 : R/W ;bitpos:[11:8] ;default: 4'hf ; */ /*description: The weight of Tx channel 2. .*/ #define GDMA_TX_WEIGHT_CH2 0x0000000F @@ -3094,8 +3093,8 @@ nk descriptor..*/ #define GDMA_OUT_PRI_CH2_REG (DR_REG_GDMA_BASE + 0x224) /* GDMA_TX_PRI_CH2 : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ -/*description: The priority of Tx channel 2. The larger of the value, the higher of the priorit -y..*/ +/*description: The priority of Tx channel 2. The larger of the value, the higher of the +priority..*/ #define GDMA_TX_PRI_CH2 0x0000000F #define GDMA_TX_PRI_CH2_M ((GDMA_TX_PRI_CH2_V)<<(GDMA_TX_PRI_CH2_S)) #define GDMA_TX_PRI_CH2_V 0xF @@ -3113,8 +3112,8 @@ S. 8: SHA. 9: ADC_DAC..*/ #define GDMA_IN_CONF0_CH3_REG (DR_REG_GDMA_BASE + 0x240) /* GDMA_MEM_TRANS_EN_CH3 : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: Set this bit 1 to enable automatic transmitting data from memory to memory via D -MA..*/ +/*description: Set this bit 1 to enable automatic transmitting data from memory to memory via +DMA..*/ #define GDMA_MEM_TRANS_EN_CH3 (BIT(4)) #define GDMA_MEM_TRANS_EN_CH3_M (BIT(4)) #define GDMA_MEM_TRANS_EN_CH3_V 0x1 @@ -3127,8 +3126,8 @@ when accessing internal SRAM. .*/ #define GDMA_IN_DATA_BURST_EN_CH3_V 0x1 #define GDMA_IN_DATA_BURST_EN_CH3_S 3 /* GDMA_INDSCR_BURST_EN_CH3 : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: Set this bit to 1 to enable INCR burst transfer for Rx channel 2 reading link de -scriptor when accessing internal SRAM. .*/ +/*description: Set this bit to 1 to enable INCR burst transfer for Rx channel 2 reading link +descriptor when accessing internal SRAM. .*/ #define GDMA_INDSCR_BURST_EN_CH3 (BIT(2)) #define GDMA_INDSCR_BURST_EN_CH3_M (BIT(2)) #define GDMA_INDSCR_BURST_EN_CH3_V 0x1 @@ -3161,8 +3160,8 @@ scriptor when accessing internal SRAM. .*/ #define GDMA_IN_CHECK_OWNER_CH3_V 0x1 #define GDMA_IN_CHECK_OWNER_CH3_S 12 /* GDMA_DMA_INFIFO_FULL_THRS_CH3 : R/W ;bitpos:[11:0] ;default: 12'hc ; */ -/*description: This register is used to generate the INFIFO_FULL_WM_INT interrupt when Rx chann -el 3 received byte number in Rx FIFO is up to the value of the register..*/ +/*description: This register is used to generate the INFIFO_FULL_WM_INT interrupt when Rx +channel 3 received byte number in Rx FIFO is up to the value of the register..*/ #define GDMA_DMA_INFIFO_FULL_THRS_CH3 0x00000FFF #define GDMA_DMA_INFIFO_FULL_THRS_CH3_M ((GDMA_DMA_INFIFO_FULL_THRS_CH3_V)<<(GDMA_DMA_INFIFO_FULL_THRS_CH3_S)) #define GDMA_DMA_INFIFO_FULL_THRS_CH3_V 0xFFF @@ -3198,15 +3197,15 @@ overflow. .*/ #define GDMA_INFIFO_OVF_L1_CH3_INT_RAW_V 0x1 #define GDMA_INFIFO_OVF_L1_CH3_INT_RAW_S 6 /* GDMA_INFIFO_FULL_WM_CH3_INT_RAW : R/WTC/SS ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when received data byte number is up t -o threshold configured by REG_DMA_INFIFO_FULL_THRS_CH0 in Rx FIFO of channel 3..*/ +/*description: The raw interrupt bit turns to high level when received data byte number is up +to threshold configured by REG_DMA_INFIFO_FULL_THRS_CH0 in Rx FIFO of channel 3..*/ #define GDMA_INFIFO_FULL_WM_CH3_INT_RAW (BIT(5)) #define GDMA_INFIFO_FULL_WM_CH3_INT_RAW_M (BIT(5)) #define GDMA_INFIFO_FULL_WM_CH3_INT_RAW_V 0x1 #define GDMA_INFIFO_FULL_WM_CH3_INT_RAW_S 5 /* GDMA_IN_DSCR_EMPTY_CH3_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when Rx buffer pointed by inlink is fu -ll and receiving data is not completed, but there is no more inlink for Rx chann +/*description: The raw interrupt bit turns to high level when Rx buffer pointed by inlink is +full and receiving data is not completed, but there is no more inlink for Rx chann el 3..*/ #define GDMA_IN_DSCR_EMPTY_CH3_INT_RAW (BIT(4)) #define GDMA_IN_DSCR_EMPTY_CH3_INT_RAW_M (BIT(4)) @@ -3214,32 +3213,32 @@ el 3..*/ #define GDMA_IN_DSCR_EMPTY_CH3_INT_RAW_S 4 /* GDMA_IN_DSCR_ERR_CH3_INT_RAW : R/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */ /*description: The raw interrupt bit turns to high level when detecting inlink descriptor error -, including owner error, the second and third word error of inlink descriptor fo -r Rx channel 3..*/ +, including owner error, the second and third word error of inlink descriptor +for Rx channel 3..*/ #define GDMA_IN_DSCR_ERR_CH3_INT_RAW (BIT(3)) #define GDMA_IN_DSCR_ERR_CH3_INT_RAW_M (BIT(3)) #define GDMA_IN_DSCR_ERR_CH3_INT_RAW_V 0x1 #define GDMA_IN_DSCR_ERR_CH3_INT_RAW_S 3 /* GDMA_IN_ERR_EOF_CH3_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when data error is detected only in th -e case that the peripheral is UHCI0 for Rx channel 3. For other peripherals, thi -s raw interrupt is reserved..*/ +/*description: The raw interrupt bit turns to high level when data error is detected only in +the case that the peripheral is UHCI0 for Rx channel 3. For other peripherals, +this raw interrupt is reserved..*/ #define GDMA_IN_ERR_EOF_CH3_INT_RAW (BIT(2)) #define GDMA_IN_ERR_EOF_CH3_INT_RAW_M (BIT(2)) #define GDMA_IN_ERR_EOF_CH3_INT_RAW_V 0x1 #define GDMA_IN_ERR_EOF_CH3_INT_RAW_S 2 /* GDMA_IN_SUC_EOF_CH3_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when the last data pointed by one inli -nk descriptor has been received for Rx channel 3. For UHCI0, the raw interrupt b -it turns to high level when the last data pointed by one inlink descriptor has b -een received and no data error is detected for Rx channel 0..*/ +/*description: The raw interrupt bit turns to high level when the last data pointed by one +inlink descriptor has been received for Rx channel 3. For UHCI0, the raw interrupt +bit turns to high level when the last data pointed by one inlink descriptor has +been received and no data error is detected for Rx channel 0..*/ #define GDMA_IN_SUC_EOF_CH3_INT_RAW (BIT(1)) #define GDMA_IN_SUC_EOF_CH3_INT_RAW_M (BIT(1)) #define GDMA_IN_SUC_EOF_CH3_INT_RAW_V 0x1 #define GDMA_IN_SUC_EOF_CH3_INT_RAW_S 1 /* GDMA_IN_DONE_CH3_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when the last data pointed by one inli -nk descriptor has been received for Rx channel 3..*/ +/*description: The raw interrupt bit turns to high level when the last data pointed by one +inlink descriptor has been received for Rx channel 3..*/ #define GDMA_IN_DONE_CH3_INT_RAW (BIT(0)) #define GDMA_IN_DONE_CH3_INT_RAW_M (BIT(0)) #define GDMA_IN_DONE_CH3_INT_RAW_V 0x1 @@ -3558,15 +3557,15 @@ nk descriptor has been received for Rx channel 3..*/ #define GDMA_INLINK_STOP_CH3_V 0x1 #define GDMA_INLINK_STOP_CH3_S 21 /* GDMA_INLINK_AUTO_RET_CH3 : R/W ;bitpos:[20] ;default: 1'b1 ; */ -/*description: Set this bit to return to current inlink descriptor's address, when there are so -me errors in current receiving data..*/ +/*description: Set this bit to return to current inlink descriptor's address, when there are +some errors in current receiving data..*/ #define GDMA_INLINK_AUTO_RET_CH3 (BIT(20)) #define GDMA_INLINK_AUTO_RET_CH3_M (BIT(20)) #define GDMA_INLINK_AUTO_RET_CH3_V 0x1 #define GDMA_INLINK_AUTO_RET_CH3_S 20 /* GDMA_INLINK_ADDR_CH3 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ -/*description: This register stores the 20 least significant bits of the first inlink descripto -r's address..*/ +/*description: This register stores the 20 least significant bits of the first inlink +descriptor's address..*/ #define GDMA_INLINK_ADDR_CH3 0x000FFFFF #define GDMA_INLINK_ADDR_CH3_M ((GDMA_INLINK_ADDR_CH3_V)<<(GDMA_INLINK_ADDR_CH3_S)) #define GDMA_INLINK_ADDR_CH3_V 0xFFFFF @@ -3594,8 +3593,8 @@ r's address..*/ #define GDMA_IN_SUC_EOF_DES_ADDR_CH3_REG (DR_REG_GDMA_BASE + 0x268) /* GDMA_IN_SUC_EOF_DES_ADDR_CH3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: This register stores the address of the inlink descriptor when the EOF bit in th -is descriptor is 1..*/ +/*description: This register stores the address of the inlink descriptor when the EOF bit in +this descriptor is 1..*/ #define GDMA_IN_SUC_EOF_DES_ADDR_CH3 0xFFFFFFFF #define GDMA_IN_SUC_EOF_DES_ADDR_CH3_M ((GDMA_IN_SUC_EOF_DES_ADDR_CH3_V)<<(GDMA_IN_SUC_EOF_DES_ADDR_CH3_S)) #define GDMA_IN_SUC_EOF_DES_ADDR_CH3_V 0xFFFFFFFF @@ -3603,8 +3602,8 @@ is descriptor is 1..*/ #define GDMA_IN_ERR_EOF_DES_ADDR_CH3_REG (DR_REG_GDMA_BASE + 0x26C) /* GDMA_IN_ERR_EOF_DES_ADDR_CH3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: This register stores the address of the inlink descriptor when there are some er -rors in current receiving data. Only used when peripheral is UHCI0..*/ +/*description: This register stores the address of the inlink descriptor when there are some +errors in current receiving data. Only used when peripheral is UHCI0..*/ #define GDMA_IN_ERR_EOF_DES_ADDR_CH3 0xFFFFFFFF #define GDMA_IN_ERR_EOF_DES_ADDR_CH3_M ((GDMA_IN_ERR_EOF_DES_ADDR_CH3_V)<<(GDMA_IN_ERR_EOF_DES_ADDR_CH3_S)) #define GDMA_IN_ERR_EOF_DES_ADDR_CH3_V 0xFFFFFFFF @@ -3634,7 +3633,7 @@ rors in current receiving data. Only used when peripheral is UHCI0..*/ #define GDMA_INLINK_DSCR_BF1_CH3_V 0xFFFFFFFF #define GDMA_INLINK_DSCR_BF1_CH3_S 0 -#define GDMA_IN_WIGHT_CH3_REG (DR_REG_GDMA_BASE + 0x27C) +#define GDMA_IN_WEIGHT_CH3_REG (DR_REG_GDMA_BASE + 0x27C) /* GDMA_RX_WEIGHT_CH3 : R/W ;bitpos:[11:8] ;default: 4'hf ; */ /*description: The weight of Rx channel 3. .*/ #define GDMA_RX_WEIGHT_CH3 0x0000000F @@ -3644,8 +3643,8 @@ rors in current receiving data. Only used when peripheral is UHCI0..*/ #define GDMA_IN_PRI_CH3_REG (DR_REG_GDMA_BASE + 0x284) /* GDMA_RX_PRI_CH3 : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ -/*description: The priority of Rx channel 3. The larger of the value, the higher of the priorit -y..*/ +/*description: The priority of Rx channel 3. The larger of the value, the higher of the +priority..*/ #define GDMA_RX_PRI_CH3 0x0000000F #define GDMA_RX_PRI_CH3_M ((GDMA_RX_PRI_CH3_V)<<(GDMA_RX_PRI_CH3_S)) #define GDMA_RX_PRI_CH3_V 0xF @@ -3662,15 +3661,15 @@ y..*/ #define GDMA_OUT_CONF0_CH3_REG (DR_REG_GDMA_BASE + 0x2A0) /* GDMA_OUT_DATA_BURST_EN_CH3 : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: Set this bit to 1 to enable INCR burst transfer for Tx channel 3 transmitting da -ta when accessing internal SRAM. .*/ +/*description: Set this bit to 1 to enable INCR burst transfer for Tx channel 3 transmitting +data when accessing internal SRAM. .*/ #define GDMA_OUT_DATA_BURST_EN_CH3 (BIT(5)) #define GDMA_OUT_DATA_BURST_EN_CH3_M (BIT(5)) #define GDMA_OUT_DATA_BURST_EN_CH3_V 0x1 #define GDMA_OUT_DATA_BURST_EN_CH3_S 5 /* GDMA_OUTDSCR_BURST_EN_CH3 : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: Set this bit to 1 to enable INCR burst transfer for Tx channel 3 reading link de -scriptor when accessing internal SRAM. .*/ +/*description: Set this bit to 1 to enable INCR burst transfer for Tx channel 3 reading link +descriptor when accessing internal SRAM. .*/ #define GDMA_OUTDSCR_BURST_EN_CH3 (BIT(4)) #define GDMA_OUTDSCR_BURST_EN_CH3_M (BIT(4)) #define GDMA_OUTDSCR_BURST_EN_CH3_V 0x1 @@ -3683,8 +3682,8 @@ scriptor when accessing internal SRAM. .*/ #define GDMA_OUT_EOF_MODE_CH3_V 0x1 #define GDMA_OUT_EOF_MODE_CH3_S 3 /* GDMA_OUT_AUTO_WRBACK_CH3 : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: Set this bit to enable automatic outlink-writeback when all the data in tx buffe -r has been transmitted..*/ +/*description: Set this bit to enable automatic outlink-writeback when all the data in tx +buffer has been transmitted..*/ #define GDMA_OUT_AUTO_WRBACK_CH3 (BIT(2)) #define GDMA_OUT_AUTO_WRBACK_CH3_M (BIT(2)) #define GDMA_OUT_AUTO_WRBACK_CH3_V 0x1 @@ -3747,15 +3746,15 @@ overflow. .*/ #define GDMA_OUTFIFO_OVF_L1_CH3_INT_RAW_V 0x1 #define GDMA_OUTFIFO_OVF_L1_CH3_INT_RAW_S 4 /* GDMA_OUT_TOTAL_EOF_CH3_INT_RAW : R/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when data corresponding a outlink (inc -ludes one link descriptor or few link descriptors) is transmitted out for Tx cha +/*description: The raw interrupt bit turns to high level when data corresponding a outlink +(includes one link descriptor or few link descriptors) is transmitted out for Tx cha nnel 3..*/ #define GDMA_OUT_TOTAL_EOF_CH3_INT_RAW (BIT(3)) #define GDMA_OUT_TOTAL_EOF_CH3_INT_RAW_M (BIT(3)) #define GDMA_OUT_TOTAL_EOF_CH3_INT_RAW_V 0x1 #define GDMA_OUT_TOTAL_EOF_CH3_INT_RAW_S 3 /* GDMA_OUT_DSCR_ERR_CH3_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when detecting outlink descriptor erro +/*description: The raw interrupt bit turns to high level when detecting outlink descriptor error r, including owner error, the second and third word error of outlink descriptor for Tx channel 3..*/ #define GDMA_OUT_DSCR_ERR_CH3_INT_RAW (BIT(2)) @@ -3763,15 +3762,15 @@ for Tx channel 3..*/ #define GDMA_OUT_DSCR_ERR_CH3_INT_RAW_V 0x1 #define GDMA_OUT_DSCR_ERR_CH3_INT_RAW_S 2 /* GDMA_OUT_EOF_CH3_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when the last data pointed by one outl -ink descriptor has been read from memory for Tx channel 3. .*/ +/*description: The raw interrupt bit turns to high level when the last data pointed by one +outlink descriptor has been read from memory for Tx channel 3. .*/ #define GDMA_OUT_EOF_CH3_INT_RAW (BIT(1)) #define GDMA_OUT_EOF_CH3_INT_RAW_M (BIT(1)) #define GDMA_OUT_EOF_CH3_INT_RAW_V 0x1 #define GDMA_OUT_EOF_CH3_INT_RAW_S 1 /* GDMA_OUT_DONE_CH3_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when the last data pointed by one outl -ink descriptor has been transmitted to peripherals for Tx channel 3..*/ +/*description: The raw interrupt bit turns to high level when the last data pointed by one +outlink descriptor has been transmitted to peripherals for Tx channel 3..*/ #define GDMA_OUT_DONE_CH3_INT_RAW (BIT(0)) #define GDMA_OUT_DONE_CH3_INT_RAW_M (BIT(0)) #define GDMA_OUT_DONE_CH3_INT_RAW_V 0x1 @@ -4023,8 +4022,8 @@ ink descriptor has been transmitted to peripherals for Tx channel 3..*/ #define GDMA_OUT_LINK_CH3_REG (DR_REG_GDMA_BASE + 0x2C0) /* GDMA_OUTLINK_PARK_CH3 : RO ;bitpos:[23] ;default: 1'h1 ; */ -/*description: 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's F -SM is working..*/ +/*description: 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's +FSM is working..*/ #define GDMA_OUTLINK_PARK_CH3 (BIT(23)) #define GDMA_OUTLINK_PARK_CH3_M (BIT(23)) #define GDMA_OUTLINK_PARK_CH3_V 0x1 @@ -4048,8 +4047,8 @@ SM is working..*/ #define GDMA_OUTLINK_STOP_CH3_V 0x1 #define GDMA_OUTLINK_STOP_CH3_S 20 /* GDMA_OUTLINK_ADDR_CH3 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ -/*description: This register stores the 20 least significant bits of the first outlink descript -or's address..*/ +/*description: This register stores the 20 least significant bits of the first outlink +descriptor's address..*/ #define GDMA_OUTLINK_ADDR_CH3 0x000FFFFF #define GDMA_OUTLINK_ADDR_CH3_M ((GDMA_OUTLINK_ADDR_CH3_V)<<(GDMA_OUTLINK_ADDR_CH3_S)) #define GDMA_OUTLINK_ADDR_CH3_V 0xFFFFF @@ -4077,8 +4076,8 @@ or's address..*/ #define GDMA_OUT_EOF_DES_ADDR_CH3_REG (DR_REG_GDMA_BASE + 0x2C8) /* GDMA_OUT_EOF_DES_ADDR_CH3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: This register stores the address of the outlink descriptor when the EOF bit in t -his descriptor is 1..*/ +/*description: This register stores the address of the outlink descriptor when the EOF bit in +this descriptor is 1..*/ #define GDMA_OUT_EOF_DES_ADDR_CH3 0xFFFFFFFF #define GDMA_OUT_EOF_DES_ADDR_CH3_M ((GDMA_OUT_EOF_DES_ADDR_CH3_V)<<(GDMA_OUT_EOF_DES_ADDR_CH3_S)) #define GDMA_OUT_EOF_DES_ADDR_CH3_V 0xFFFFFFFF @@ -4086,8 +4085,8 @@ his descriptor is 1..*/ #define GDMA_OUT_EOF_BFR_DES_ADDR_CH3_REG (DR_REG_GDMA_BASE + 0x2CC) /* GDMA_OUT_EOF_BFR_DES_ADDR_CH3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: This register stores the address of the outlink descriptor before the last outli -nk descriptor..*/ +/*description: This register stores the address of the outlink descriptor before the last +outlink descriptor..*/ #define GDMA_OUT_EOF_BFR_DES_ADDR_CH3 0xFFFFFFFF #define GDMA_OUT_EOF_BFR_DES_ADDR_CH3_M ((GDMA_OUT_EOF_BFR_DES_ADDR_CH3_V)<<(GDMA_OUT_EOF_BFR_DES_ADDR_CH3_S)) #define GDMA_OUT_EOF_BFR_DES_ADDR_CH3_V 0xFFFFFFFF @@ -4117,7 +4116,7 @@ nk descriptor..*/ #define GDMA_OUTLINK_DSCR_BF1_CH3_V 0xFFFFFFFF #define GDMA_OUTLINK_DSCR_BF1_CH3_S 0 -#define GDMA_OUT_WIGHT_CH3_REG (DR_REG_GDMA_BASE + 0x2DC) +#define GDMA_OUT_WEIGHT_CH3_REG (DR_REG_GDMA_BASE + 0x2DC) /* GDMA_TX_WEIGHT_CH3 : R/W ;bitpos:[11:8] ;default: 4'hf ; */ /*description: The weight of Tx channel 3. .*/ #define GDMA_TX_WEIGHT_CH3 0x0000000F @@ -4127,8 +4126,8 @@ nk descriptor..*/ #define GDMA_OUT_PRI_CH3_REG (DR_REG_GDMA_BASE + 0x2E4) /* GDMA_TX_PRI_CH3 : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ -/*description: The priority of Tx channel 3. The larger of the value, the higher of the priorit -y..*/ +/*description: The priority of Tx channel 3. The larger of the value, the higher of the +priority..*/ #define GDMA_TX_PRI_CH3 0x0000000F #define GDMA_TX_PRI_CH3_M ((GDMA_TX_PRI_CH3_V)<<(GDMA_TX_PRI_CH3_S)) #define GDMA_TX_PRI_CH3_V 0xF @@ -4146,8 +4145,8 @@ S. 8: SHA. 9: ADC_DAC..*/ #define GDMA_IN_CONF0_CH4_REG (DR_REG_GDMA_BASE + 0x300) /* GDMA_MEM_TRANS_EN_CH4 : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: Set this bit 1 to enable automatic transmitting data from memory to memory via D -MA..*/ +/*description: Set this bit 1 to enable automatic transmitting data from memory to memory via +DMA..*/ #define GDMA_MEM_TRANS_EN_CH4 (BIT(4)) #define GDMA_MEM_TRANS_EN_CH4_M (BIT(4)) #define GDMA_MEM_TRANS_EN_CH4_V 0x1 @@ -4160,8 +4159,8 @@ when accessing internal SRAM. .*/ #define GDMA_IN_DATA_BURST_EN_CH4_V 0x1 #define GDMA_IN_DATA_BURST_EN_CH4_S 3 /* GDMA_INDSCR_BURST_EN_CH4 : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: Set this bit to 1 to enable INCR burst transfer for Rx channel 2 reading link de -scriptor when accessing internal SRAM. .*/ +/*description: Set this bit to 1 to enable INCR burst transfer for Rx channel 2 reading link +descriptor when accessing internal SRAM. .*/ #define GDMA_INDSCR_BURST_EN_CH4 (BIT(2)) #define GDMA_INDSCR_BURST_EN_CH4_M (BIT(2)) #define GDMA_INDSCR_BURST_EN_CH4_V 0x1 @@ -4194,8 +4193,8 @@ scriptor when accessing internal SRAM. .*/ #define GDMA_IN_CHECK_OWNER_CH4_V 0x1 #define GDMA_IN_CHECK_OWNER_CH4_S 12 /* GDMA_DMA_INFIFO_FULL_THRS_CH4 : R/W ;bitpos:[11:0] ;default: 12'hc ; */ -/*description: This register is used to generate the INFIFO_FULL_WM_INT interrupt when Rx chann -el 4 received byte number in Rx FIFO is up to the value of the register..*/ +/*description: This register is used to generate the INFIFO_FULL_WM_INT interrupt when Rx +channel 4 received byte number in Rx FIFO is up to the value of the register..*/ #define GDMA_DMA_INFIFO_FULL_THRS_CH4 0x00000FFF #define GDMA_DMA_INFIFO_FULL_THRS_CH4_M ((GDMA_DMA_INFIFO_FULL_THRS_CH4_V)<<(GDMA_DMA_INFIFO_FULL_THRS_CH4_S)) #define GDMA_DMA_INFIFO_FULL_THRS_CH4_V 0xFFF @@ -4231,48 +4230,48 @@ overflow. .*/ #define GDMA_INFIFO_OVF_L1_CH4_INT_RAW_V 0x1 #define GDMA_INFIFO_OVF_L1_CH4_INT_RAW_S 6 /* GDMA_INFIFO_FULL_WM_CH4_INT_RAW : R/WTC/SS ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when received data byte number is up t -o threshold configured by REG_DMA_INFIFO_FULL_THRS_CH0 in Rx FIFO of channel 4..*/ +/*description: The raw interrupt bit turns to high level when received data byte number is up +to threshold configured by REG_DMA_INFIFO_FULL_THRS_CH0 in Rx FIFO of channel 4..*/ #define GDMA_INFIFO_FULL_WM_CH4_INT_RAW (BIT(5)) #define GDMA_INFIFO_FULL_WM_CH4_INT_RAW_M (BIT(5)) #define GDMA_INFIFO_FULL_WM_CH4_INT_RAW_V 0x1 #define GDMA_INFIFO_FULL_WM_CH4_INT_RAW_S 5 /* GDMA_IN_DSCR_EMPTY_CH4_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when Rx buffer pointed by inlink is fu -ll and receiving data is not completed, but there is no more inlink for Rx chann -el 4..*/ +/*description: The raw interrupt bit turns to high level when Rx buffer pointed by inlink is +full and receiving data is not completed, but there is no more inlink for Rx +channel 4..*/ #define GDMA_IN_DSCR_EMPTY_CH4_INT_RAW (BIT(4)) #define GDMA_IN_DSCR_EMPTY_CH4_INT_RAW_M (BIT(4)) #define GDMA_IN_DSCR_EMPTY_CH4_INT_RAW_V 0x1 #define GDMA_IN_DSCR_EMPTY_CH4_INT_RAW_S 4 /* GDMA_IN_DSCR_ERR_CH4_INT_RAW : R/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */ /*description: The raw interrupt bit turns to high level when detecting inlink descriptor error -, including owner error, the second and third word error of inlink descriptor fo -r Rx channel 4..*/ +, including owner error, the second and third word error of inlink descriptor +for Rx channel 4..*/ #define GDMA_IN_DSCR_ERR_CH4_INT_RAW (BIT(3)) #define GDMA_IN_DSCR_ERR_CH4_INT_RAW_M (BIT(3)) #define GDMA_IN_DSCR_ERR_CH4_INT_RAW_V 0x1 #define GDMA_IN_DSCR_ERR_CH4_INT_RAW_S 3 /* GDMA_IN_ERR_EOF_CH4_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when data error is detected only in th -e case that the peripheral is UHCI0 for Rx channel 4. For other peripherals, thi -s raw interrupt is reserved..*/ +/*description: The raw interrupt bit turns to high level when data error is detected only in +the case that the peripheral is UHCI0 for Rx channel 4. For other peripherals, +this raw interrupt is reserved..*/ #define GDMA_IN_ERR_EOF_CH4_INT_RAW (BIT(2)) #define GDMA_IN_ERR_EOF_CH4_INT_RAW_M (BIT(2)) #define GDMA_IN_ERR_EOF_CH4_INT_RAW_V 0x1 #define GDMA_IN_ERR_EOF_CH4_INT_RAW_S 2 /* GDMA_IN_SUC_EOF_CH4_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when the last data pointed by one inli -nk descriptor has been received for Rx channel 4. For UHCI0, the raw interrupt b -it turns to high level when the last data pointed by one inlink descriptor has b -een received and no data error is detected for Rx channel 0..*/ +/*description: The raw interrupt bit turns to high level when the last data pointed by one +inlink descriptor has been received for Rx channel 4. For UHCI0, the raw interrupt +bit turns to high level when the last data pointed by one inlink descriptor has +been received and no data error is detected for Rx channel 0..*/ #define GDMA_IN_SUC_EOF_CH4_INT_RAW (BIT(1)) #define GDMA_IN_SUC_EOF_CH4_INT_RAW_M (BIT(1)) #define GDMA_IN_SUC_EOF_CH4_INT_RAW_V 0x1 #define GDMA_IN_SUC_EOF_CH4_INT_RAW_S 1 /* GDMA_IN_DONE_CH4_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when the last data pointed by one inli -nk descriptor has been received for Rx channel 4..*/ +/*description: The raw interrupt bit turns to high level when the last data pointed by one +inlink descriptor has been received for Rx channel 4..*/ #define GDMA_IN_DONE_CH4_INT_RAW (BIT(0)) #define GDMA_IN_DONE_CH4_INT_RAW_M (BIT(0)) #define GDMA_IN_DONE_CH4_INT_RAW_V 0x1 @@ -4591,15 +4590,15 @@ nk descriptor has been received for Rx channel 4..*/ #define GDMA_INLINK_STOP_CH4_V 0x1 #define GDMA_INLINK_STOP_CH4_S 21 /* GDMA_INLINK_AUTO_RET_CH4 : R/W ;bitpos:[20] ;default: 1'b1 ; */ -/*description: Set this bit to return to current inlink descriptor's address, when there are so -me errors in current receiving data..*/ +/*description: Set this bit to return to current inlink descriptor's address, when there are +some errors in current receiving data..*/ #define GDMA_INLINK_AUTO_RET_CH4 (BIT(20)) #define GDMA_INLINK_AUTO_RET_CH4_M (BIT(20)) #define GDMA_INLINK_AUTO_RET_CH4_V 0x1 #define GDMA_INLINK_AUTO_RET_CH4_S 20 /* GDMA_INLINK_ADDR_CH4 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ -/*description: This register stores the 20 least significant bits of the first inlink descripto -r's address..*/ +/*description: This register stores the 20 least significant bits of the first inlink +descriptor's address..*/ #define GDMA_INLINK_ADDR_CH4 0x000FFFFF #define GDMA_INLINK_ADDR_CH4_M ((GDMA_INLINK_ADDR_CH4_V)<<(GDMA_INLINK_ADDR_CH4_S)) #define GDMA_INLINK_ADDR_CH4_V 0xFFFFF @@ -4627,8 +4626,8 @@ r's address..*/ #define GDMA_IN_SUC_EOF_DES_ADDR_CH4_REG (DR_REG_GDMA_BASE + 0x328) /* GDMA_IN_SUC_EOF_DES_ADDR_CH4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: This register stores the address of the inlink descriptor when the EOF bit in th -is descriptor is 1..*/ +/*description: This register stores the address of the inlink descriptor when the EOF bit in +this descriptor is 1..*/ #define GDMA_IN_SUC_EOF_DES_ADDR_CH4 0xFFFFFFFF #define GDMA_IN_SUC_EOF_DES_ADDR_CH4_M ((GDMA_IN_SUC_EOF_DES_ADDR_CH4_V)<<(GDMA_IN_SUC_EOF_DES_ADDR_CH4_S)) #define GDMA_IN_SUC_EOF_DES_ADDR_CH4_V 0xFFFFFFFF @@ -4636,8 +4635,8 @@ is descriptor is 1..*/ #define GDMA_IN_ERR_EOF_DES_ADDR_CH4_REG (DR_REG_GDMA_BASE + 0x32C) /* GDMA_IN_ERR_EOF_DES_ADDR_CH4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: This register stores the address of the inlink descriptor when there are some er -rors in current receiving data. Only used when peripheral is UHCI0..*/ +/*description: This register stores the address of the inlink descriptor when there are some +errors in current receiving data. Only used when peripheral is UHCI0..*/ #define GDMA_IN_ERR_EOF_DES_ADDR_CH4 0xFFFFFFFF #define GDMA_IN_ERR_EOF_DES_ADDR_CH4_M ((GDMA_IN_ERR_EOF_DES_ADDR_CH4_V)<<(GDMA_IN_ERR_EOF_DES_ADDR_CH4_S)) #define GDMA_IN_ERR_EOF_DES_ADDR_CH4_V 0xFFFFFFFF @@ -4667,7 +4666,7 @@ rors in current receiving data. Only used when peripheral is UHCI0..*/ #define GDMA_INLINK_DSCR_BF1_CH4_V 0xFFFFFFFF #define GDMA_INLINK_DSCR_BF1_CH4_S 0 -#define GDMA_IN_WIGHT_CH4_REG (DR_REG_GDMA_BASE + 0x33C) +#define GDMA_IN_WEIGHT_CH4_REG (DR_REG_GDMA_BASE + 0x33C) /* GDMA_RX_WEIGHT_CH4 : R/W ;bitpos:[11:8] ;default: 4'hf ; */ /*description: The weight of Rx channel 4. .*/ #define GDMA_RX_WEIGHT_CH4 0x0000000F @@ -4695,15 +4694,15 @@ y..*/ #define GDMA_OUT_CONF0_CH4_REG (DR_REG_GDMA_BASE + 0x360) /* GDMA_OUT_DATA_BURST_EN_CH4 : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: Set this bit to 1 to enable INCR burst transfer for Tx channel 4 transmitting da -ta when accessing internal SRAM. .*/ +/*description: Set this bit to 1 to enable INCR burst transfer for Tx channel 4 transmitting +data when accessing internal SRAM. .*/ #define GDMA_OUT_DATA_BURST_EN_CH4 (BIT(5)) #define GDMA_OUT_DATA_BURST_EN_CH4_M (BIT(5)) #define GDMA_OUT_DATA_BURST_EN_CH4_V 0x1 #define GDMA_OUT_DATA_BURST_EN_CH4_S 5 /* GDMA_OUTDSCR_BURST_EN_CH4 : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: Set this bit to 1 to enable INCR burst transfer for Tx channel 4 reading link de -scriptor when accessing internal SRAM. .*/ +/*description: Set this bit to 1 to enable INCR burst transfer for Tx channel 4 reading link +descriptor when accessing internal SRAM. .*/ #define GDMA_OUTDSCR_BURST_EN_CH4 (BIT(4)) #define GDMA_OUTDSCR_BURST_EN_CH4_M (BIT(4)) #define GDMA_OUTDSCR_BURST_EN_CH4_V 0x1 @@ -4716,8 +4715,8 @@ scriptor when accessing internal SRAM. .*/ #define GDMA_OUT_EOF_MODE_CH4_V 0x1 #define GDMA_OUT_EOF_MODE_CH4_S 3 /* GDMA_OUT_AUTO_WRBACK_CH4 : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: Set this bit to enable automatic outlink-writeback when all the data in tx buffe -r has been transmitted..*/ +/*description: Set this bit to enable automatic outlink-writeback when all the data in tx +buffer has been transmitted..*/ #define GDMA_OUT_AUTO_WRBACK_CH4 (BIT(2)) #define GDMA_OUT_AUTO_WRBACK_CH4_M (BIT(2)) #define GDMA_OUT_AUTO_WRBACK_CH4_V 0x1 @@ -4780,15 +4779,15 @@ overflow. .*/ #define GDMA_OUTFIFO_OVF_L1_CH4_INT_RAW_V 0x1 #define GDMA_OUTFIFO_OVF_L1_CH4_INT_RAW_S 4 /* GDMA_OUT_TOTAL_EOF_CH4_INT_RAW : R/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when data corresponding a outlink (inc -ludes one link descriptor or few link descriptors) is transmitted out for Tx cha +/*description: The raw interrupt bit turns to high level when data corresponding a outlink +(includes one link descriptor or few link descriptors) is transmitted out for Tx cha nnel 4..*/ #define GDMA_OUT_TOTAL_EOF_CH4_INT_RAW (BIT(3)) #define GDMA_OUT_TOTAL_EOF_CH4_INT_RAW_M (BIT(3)) #define GDMA_OUT_TOTAL_EOF_CH4_INT_RAW_V 0x1 #define GDMA_OUT_TOTAL_EOF_CH4_INT_RAW_S 3 /* GDMA_OUT_DSCR_ERR_CH4_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when detecting outlink descriptor erro +/*description: The raw interrupt bit turns to high level when detecting outlink descriptor error r, including owner error, the second and third word error of outlink descriptor for Tx channel 4..*/ #define GDMA_OUT_DSCR_ERR_CH4_INT_RAW (BIT(2)) @@ -4796,15 +4795,15 @@ for Tx channel 4..*/ #define GDMA_OUT_DSCR_ERR_CH4_INT_RAW_V 0x1 #define GDMA_OUT_DSCR_ERR_CH4_INT_RAW_S 2 /* GDMA_OUT_EOF_CH4_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when the last data pointed by one outl -ink descriptor has been read from memory for Tx channel 4. .*/ +/*description: The raw interrupt bit turns to high level when the last data pointed by one +outlink descriptor has been read from memory for Tx channel 4. .*/ #define GDMA_OUT_EOF_CH4_INT_RAW (BIT(1)) #define GDMA_OUT_EOF_CH4_INT_RAW_M (BIT(1)) #define GDMA_OUT_EOF_CH4_INT_RAW_V 0x1 #define GDMA_OUT_EOF_CH4_INT_RAW_S 1 /* GDMA_OUT_DONE_CH4_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when the last data pointed by one outl -ink descriptor has been transmitted to peripherals for Tx channel 4..*/ +/*description: The raw interrupt bit turns to high level when the last data pointed by one +outlink descriptor has been transmitted to peripherals for Tx channel 4..*/ #define GDMA_OUT_DONE_CH4_INT_RAW (BIT(0)) #define GDMA_OUT_DONE_CH4_INT_RAW_M (BIT(0)) #define GDMA_OUT_DONE_CH4_INT_RAW_V 0x1 @@ -5056,8 +5055,8 @@ ink descriptor has been transmitted to peripherals for Tx channel 4..*/ #define GDMA_OUT_LINK_CH4_REG (DR_REG_GDMA_BASE + 0x380) /* GDMA_OUTLINK_PARK_CH4 : RO ;bitpos:[23] ;default: 1'h1 ; */ -/*description: 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's F -SM is working..*/ +/*description: 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's +FSM is working..*/ #define GDMA_OUTLINK_PARK_CH4 (BIT(23)) #define GDMA_OUTLINK_PARK_CH4_M (BIT(23)) #define GDMA_OUTLINK_PARK_CH4_V 0x1 @@ -5081,8 +5080,8 @@ SM is working..*/ #define GDMA_OUTLINK_STOP_CH4_V 0x1 #define GDMA_OUTLINK_STOP_CH4_S 20 /* GDMA_OUTLINK_ADDR_CH4 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ -/*description: This register stores the 20 least significant bits of the first outlink descript -or's address..*/ +/*description: This register stores the 20 least significant bits of the first outlink +descriptor's address..*/ #define GDMA_OUTLINK_ADDR_CH4 0x000FFFFF #define GDMA_OUTLINK_ADDR_CH4_M ((GDMA_OUTLINK_ADDR_CH4_V)<<(GDMA_OUTLINK_ADDR_CH4_S)) #define GDMA_OUTLINK_ADDR_CH4_V 0xFFFFF @@ -5110,8 +5109,8 @@ or's address..*/ #define GDMA_OUT_EOF_DES_ADDR_CH4_REG (DR_REG_GDMA_BASE + 0x388) /* GDMA_OUT_EOF_DES_ADDR_CH4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: This register stores the address of the outlink descriptor when the EOF bit in t -his descriptor is 1..*/ +/*description: This register stores the address of the outlink descriptor when the EOF bit in +this descriptor is 1..*/ #define GDMA_OUT_EOF_DES_ADDR_CH4 0xFFFFFFFF #define GDMA_OUT_EOF_DES_ADDR_CH4_M ((GDMA_OUT_EOF_DES_ADDR_CH4_V)<<(GDMA_OUT_EOF_DES_ADDR_CH4_S)) #define GDMA_OUT_EOF_DES_ADDR_CH4_V 0xFFFFFFFF @@ -5119,8 +5118,8 @@ his descriptor is 1..*/ #define GDMA_OUT_EOF_BFR_DES_ADDR_CH4_REG (DR_REG_GDMA_BASE + 0x38C) /* GDMA_OUT_EOF_BFR_DES_ADDR_CH4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ -/*description: This register stores the address of the outlink descriptor before the last outli -nk descriptor..*/ +/*description: This register stores the address of the outlink descriptor before the last +outlink descriptor..*/ #define GDMA_OUT_EOF_BFR_DES_ADDR_CH4 0xFFFFFFFF #define GDMA_OUT_EOF_BFR_DES_ADDR_CH4_M ((GDMA_OUT_EOF_BFR_DES_ADDR_CH4_V)<<(GDMA_OUT_EOF_BFR_DES_ADDR_CH4_S)) #define GDMA_OUT_EOF_BFR_DES_ADDR_CH4_V 0xFFFFFFFF @@ -5150,7 +5149,7 @@ nk descriptor..*/ #define GDMA_OUTLINK_DSCR_BF1_CH4_V 0xFFFFFFFF #define GDMA_OUTLINK_DSCR_BF1_CH4_S 0 -#define GDMA_OUT_WIGHT_CH4_REG (DR_REG_GDMA_BASE + 0x39C) +#define GDMA_OUT_WEIGHT_CH4_REG (DR_REG_GDMA_BASE + 0x39C) /* GDMA_TX_WEIGHT_CH4 : R/W ;bitpos:[11:8] ;default: 4'hf ; */ /*description: The weight of Tx channel 4. .*/ #define GDMA_TX_WEIGHT_CH4 0x0000000F @@ -5160,8 +5159,8 @@ nk descriptor..*/ #define GDMA_OUT_PRI_CH4_REG (DR_REG_GDMA_BASE + 0x3A4) /* GDMA_TX_PRI_CH4 : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ -/*description: The priority of Tx channel 4. The larger of the value, the higher of the priorit -y..*/ +/*description: The priority of Tx channel 4. The larger of the value, the higher of the +priority..*/ #define GDMA_TX_PRI_CH4 0x0000000F #define GDMA_TX_PRI_CH4_M ((GDMA_TX_PRI_CH4_V)<<(GDMA_TX_PRI_CH4_S)) #define GDMA_TX_PRI_CH4_V 0xF @@ -5193,8 +5192,8 @@ S. 8: SHA. 9: ADC_DAC..*/ #define GDMA_PD_CONF_REG (DR_REG_GDMA_BASE + 0x3C4) /* GDMA_DMA_RAM_CLK_FO : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: 1: Force to open the clock and bypass the gate-clock when accessing the RAM in D -MA. 0: A gate-clock will be used when accessing the RAM in DMA..*/ +/*description: 1: Force to open the clock and bypass the gate-clock when accessing the RAM in +DMA. 0: A gate-clock will be used when accessing the RAM in DMA..*/ #define GDMA_DMA_RAM_CLK_FO (BIT(6)) #define GDMA_DMA_RAM_CLK_FO_M (BIT(6)) #define GDMA_DMA_RAM_CLK_FO_V 0x1 @@ -5340,8 +5339,8 @@ s. 7: 72 bytes. 8: 80 bytes..*/ #define GDMA_EXTMEM_REJECT_ADDR_REG (DR_REG_GDMA_BASE + 0x3F4) /* GDMA_EXTMEM_REJECT_ADDR : RO ;bitpos:[31:0] ;default: 32'd0 ; */ -/*description: This register store the first address rejected by permission control when access -ing external RAM..*/ +/*description: This register store the first address rejected by permission control when +accessing external RAM..*/ #define GDMA_EXTMEM_REJECT_ADDR 0xFFFFFFFF #define GDMA_EXTMEM_REJECT_ADDR_M ((GDMA_EXTMEM_REJECT_ADDR_V)<<(GDMA_EXTMEM_REJECT_ADDR_S)) #define GDMA_EXTMEM_REJECT_ADDR_V 0xFFFFFFFF @@ -5361,8 +5360,8 @@ ing external RAM..*/ #define GDMA_EXTMEM_REJECT_CHANNEL_NUM_V 0xF #define GDMA_EXTMEM_REJECT_CHANNEL_NUM_S 2 /* GDMA_EXTMEM_REJECT_ATTR : RO ;bitpos:[1:0] ;default: 2'b0 ; */ -/*description: The reject accessing. Bit 0: if this bit is 1, the rejected accessing is READ. B -it 1: if this bit is 1, the rejected accessing is WRITE..*/ +/*description: The reject accessing. Bit 0: if this bit is 1, the rejected accessing is READ. +Bit 1: if this bit is 1, the rejected accessing is WRITE..*/ #define GDMA_EXTMEM_REJECT_ATTR 0x00000003 #define GDMA_EXTMEM_REJECT_ATTR_M ((GDMA_EXTMEM_REJECT_ATTR_V)<<(GDMA_EXTMEM_REJECT_ATTR_S)) #define GDMA_EXTMEM_REJECT_ATTR_V 0x3 @@ -5370,8 +5369,8 @@ it 1: if this bit is 1, the rejected accessing is WRITE..*/ #define GDMA_EXTMEM_REJECT_INT_RAW_REG (DR_REG_GDMA_BASE + 0x3FC) /* GDMA_EXTMEM_REJECT_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The raw interrupt bit turns to high level when accessing external RAM is rejecte -d by permission control..*/ +/*description: The raw interrupt bit turns to high level when accessing external RAM is +rejected by permission control..*/ #define GDMA_EXTMEM_REJECT_INT_RAW (BIT(0)) #define GDMA_EXTMEM_REJECT_INT_RAW_M (BIT(0)) #define GDMA_EXTMEM_REJECT_INT_RAW_V 0x1 diff --git a/components/soc/esp32s3/include/soc/gdma_struct.h b/components/soc/esp32s3/include/soc/gdma_struct.h index 1a9b3ccf91..680a1cccf1 100644 --- a/components/soc/esp32s3/include/soc/gdma_struct.h +++ b/components/soc/esp32s3/include/soc/gdma_struct.h @@ -161,7 +161,7 @@ typedef volatile struct gdma_dev_s { uint32_t reserved12 : 20; }; uint32_t val; - } wight; + } weight; uint32_t reserved_40; union { struct { @@ -321,7 +321,7 @@ typedef volatile struct gdma_dev_s { uint32_t reserved12 : 20; }; uint32_t val; - } wight; + } weight; uint32_t reserved_a0; union { struct { From e383616503720876a9cfe8c002c9d2b7fd188e69 Mon Sep 17 00:00:00 2001 From: "harshal.patil" Date: Fri, 29 Mar 2024 12:02:55 +0530 Subject: [PATCH 5/6] fix(mbedtls/aes): Fix incorrect dma alignment size --- components/mbedtls/port/aes/dma/esp_aes_dma_core.c | 3 +-- components/mbedtls/port/include/esp_crypto_dma.h | 11 +++++++---- 2 files changed, 8 insertions(+), 6 deletions(-) diff --git a/components/mbedtls/port/aes/dma/esp_aes_dma_core.c b/components/mbedtls/port/aes/dma/esp_aes_dma_core.c index 728bd0ea6c..cc64191490 100644 --- a/components/mbedtls/port/aes/dma/esp_aes_dma_core.c +++ b/components/mbedtls/port/aes/dma/esp_aes_dma_core.c @@ -278,9 +278,8 @@ static inline void *aes_dma_calloc(size_t num, size_t size, uint32_t caps, size_ void *ptr = NULL; esp_dma_mem_info_t dma_mem_info = { .extra_heap_caps = caps, - .dma_alignment_bytes = 4, + .dma_alignment_bytes = DMA_DESC_MEM_ALIGN_SIZE, }; - //TODO: IDF-9638 esp_dma_capable_calloc(num, size, &dma_mem_info, &ptr, actual_size); return ptr; } diff --git a/components/mbedtls/port/include/esp_crypto_dma.h b/components/mbedtls/port/include/esp_crypto_dma.h index 03cbf84ccd..f273cbd31a 100644 --- a/components/mbedtls/port/include/esp_crypto_dma.h +++ b/components/mbedtls/port/include/esp_crypto_dma.h @@ -7,9 +7,12 @@ #pragma once #include "hal/dma_types.h" -#include "soc/gdma_channel.h" #include "soc/soc_caps.h" +#if SOC_GDMA_SUPPORTED +#include "soc/gdma_channel.h" +#include "hal/gdma_ll.h" +#endif /* SOC_GDMA_SUPPORTED */ #ifdef __cplusplus extern "C" @@ -22,17 +25,17 @@ extern "C" #if (SOC_AES_GDMA) || (SOC_SHA_GDMA) #if (SOC_GDMA_TRIG_PERIPH_AES0_BUS == SOC_GDMA_BUS_AHB) || (SOC_GDMA_TRIG_PERIPH_SHA0_BUS == SOC_GDMA_BUS_AHB) -#define DMA_DESC_MEM_ALIGN_SIZE 4 +#define DMA_DESC_MEM_ALIGN_SIZE GDMA_LL_AHB_DESC_ALIGNMENT typedef dma_descriptor_align4_t crypto_dma_desc_t; #elif (SOC_GDMA_TRIG_PERIPH_AES0_BUS == SOC_GDMA_BUS_AXI) || (SOC_GDMA_TRIG_PERIPH_SHA0_BUS == SOC_GDMA_BUS_AXI) -#define DMA_DESC_MEM_ALIGN_SIZE 8 +#define DMA_DESC_MEM_ALIGN_SIZE GDMA_LL_AXI_DESC_ALIGNMENT typedef dma_descriptor_align8_t crypto_dma_desc_t; #else #error "As we support a shared crypto GDMA layer for the AES and the SHA peripheral, both the peripherals must use the same GDMA bus" #endif /* (SOC_GDMA_TRIG_PERIPH_AES0_BUS == SOC_GDMA_BUS_AHB) || (SOC_GDMA_TRIG_PERIPH_AES0_BUS == SOC_GDMA_BUS_AHB) */ #elif (SOC_AES_CRYPTO_DMA) || (SOC_SHA_CRYPTO_DMA) -#define DMA_DESC_MEM_ALIGN_SIZE 4 +#define DMA_DESC_MEM_ALIGN_SIZE GDMA_LL_AHB_DESC_ALIGNMENT typedef dma_descriptor_align4_t crypto_dma_desc_t; #endif /* (SOC_AES_GDMA) && (SOC_SHA_GDMA) */ From c3303c0096ee265d907d553e1413a8624157c3ea Mon Sep 17 00:00:00 2001 From: gaoxu Date: Tue, 2 Apr 2024 16:17:10 +0800 Subject: [PATCH 6/6] fix(eth): fix defaultip101 tests error on ci --- components/esp_eth/include/esp_eth_mac.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/components/esp_eth/include/esp_eth_mac.h b/components/esp_eth/include/esp_eth_mac.h index 35f88e8857..c10b813709 100644 --- a/components/esp_eth/include/esp_eth_mac.h +++ b/components/esp_eth/include/esp_eth_mac.h @@ -451,7 +451,7 @@ typedef struct { #define ETH_MAC_DEFAULT_CONFIG() \ { \ .sw_reset_timeout_ms = 100, \ - .rx_task_stack_size = 2048, \ + .rx_task_stack_size = 4096, \ .rx_task_prio = 15, \ .flags = 0, \ }