From dd62e32137522c8151a7b2e6729e1731e71f7a88 Mon Sep 17 00:00:00 2001 From: cjin Date: Thu, 14 Aug 2025 20:25:01 +0800 Subject: [PATCH] feat(ble): add clk source freq change of ble slow clock on ESP32-H2 --- components/bt/controller/esp32h2/bt.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/components/bt/controller/esp32h2/bt.c b/components/bt/controller/esp32h2/bt.c index bdd0dffed1..0a1cf93ae1 100644 --- a/components/bt/controller/esp32h2/bt.c +++ b/components/bt/controller/esp32h2/bt.c @@ -846,8 +846,20 @@ static void ble_rtc_clk_init(esp_bt_controller_config_t *cfg) #if CONFIG_RTC_CLK_SRC_INT_RC s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_RC_SLOW; #elif CONFIG_RTC_CLK_SRC_EXT_CRYS + uint32_t clk_freq = 0; + if (rtc_clk_slow_src_get() == SOC_RTC_SLOW_CLK_SRC_XTAL32K) { - s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_XTAL32K; + if (!esp_clk_tree_src_get_freq_hz(SOC_MOD_CLK_XTAL32K, ESP_CLK_TREE_SRC_FREQ_PRECISION_EXACT, &clk_freq)) { + if (clk_freq > 32700 && clk_freq < 33800) { + s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_XTAL32K; + } else { + ESP_LOGW(NIMBLE_PORT_LOG_TAG, "32.768kHz XTAL detection error, switch to main XTAL as Bluetooth sleep clock"); + s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL; + } + } else { + ESP_LOGW(NIMBLE_PORT_LOG_TAG, "32.768kHz XTAL detection error, switch to main XTAL as Bluetooth sleep clock"); + s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL; + } } else { ESP_LOGW(NIMBLE_PORT_LOG_TAG, "32.768kHz XTAL not detected, fall back to main XTAL as Bluetooth sleep clock"); s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL;