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change(soc): added SOC_ prefix to mmu defs

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This commit is contained in:
Armando
2023-08-31 12:28:04 +08:00
parent a9e3f963c2
commit de77ab3061
44 changed files with 550 additions and 621 deletions
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components/esp_mm/port/esp32s2/ext_mem_layout.c
+5 -5
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@@ -18,7 +18,7 @@ const mmu_mem_region_t g_mmu_mem_regions[SOC_MMU_LINEAR_ADDRESS_REGION_NUM] = {
[0] = {
.start = SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW,
.end = SOC_MMU_IRAM0_LINEAR_ADDRESS_HIGH,
.size = BUS_SIZE(SOC_MMU_IRAM0_LINEAR),
.size = SOC_BUS_SIZE(SOC_MMU_IRAM0_LINEAR),
.bus_id = CACHE_BUS_IBUS0,
.targets = MMU_TARGET_FLASH0 | MMU_TARGET_PSRAM0,
.caps = MMU_MEM_CAP_EXEC | MMU_MEM_CAP_32BIT,
@@ -26,7 +26,7 @@ const mmu_mem_region_t g_mmu_mem_regions[SOC_MMU_LINEAR_ADDRESS_REGION_NUM] = {
[1] = {
.start = SOC_MMU_DROM0_LINEAR_ADDRESS_LOW,
.end = SOC_MMU_DROM0_LINEAR_ADDRESS_HIGH,
.size = BUS_SIZE(SOC_MMU_DROM0_LINEAR),
.size = SOC_BUS_SIZE(SOC_MMU_DROM0_LINEAR),
.bus_id = CACHE_BUS_IBUS2,
.targets = MMU_TARGET_FLASH0 | MMU_TARGET_PSRAM0,
.caps = MMU_MEM_CAP_READ | MMU_MEM_CAP_32BIT | MMU_MEM_CAP_8BIT,
@@ -34,7 +34,7 @@ const mmu_mem_region_t g_mmu_mem_regions[SOC_MMU_LINEAR_ADDRESS_REGION_NUM] = {
[2] = {
.start = SOC_MMU_DPORT_LINEAR_ADDRESS_LOW,
.end = SOC_MMU_DPORT_LINEAR_ADDRESS_HIGH,
.size = BUS_SIZE(SOC_MMU_DPORT_LINEAR),
.size = SOC_BUS_SIZE(SOC_MMU_DPORT_LINEAR),
.bus_id = CACHE_BUS_DBUS2,
.targets = MMU_TARGET_FLASH0 | MMU_TARGET_PSRAM0,
.caps = MMU_MEM_CAP_READ | MMU_MEM_CAP_WRITE | MMU_MEM_CAP_32BIT,
@@ -42,7 +42,7 @@ const mmu_mem_region_t g_mmu_mem_regions[SOC_MMU_LINEAR_ADDRESS_REGION_NUM] = {
[3] = {
.start = SOC_MMU_DRAM1_LINEAR_ADDRESS_LOW,
.end = SOC_MMU_DRAM1_LINEAR_ADDRESS_HIGH,
.size = BUS_SIZE(SOC_MMU_DRAM1_LINEAR),
.size = SOC_BUS_SIZE(SOC_MMU_DRAM1_LINEAR),
.bus_id = CACHE_BUS_DBUS1,
.targets = MMU_TARGET_FLASH0 | MMU_TARGET_PSRAM0,
.caps = MMU_MEM_CAP_READ | MMU_MEM_CAP_WRITE | MMU_MEM_CAP_32BIT | MMU_MEM_CAP_8BIT,
@@ -50,7 +50,7 @@ const mmu_mem_region_t g_mmu_mem_regions[SOC_MMU_LINEAR_ADDRESS_REGION_NUM] = {
[4] = {
.start = SOC_MMU_DRAM0_LINEAR_ADDRESS_LOW,
.end = SOC_MMU_DRAM0_LINEAR_ADDRESS_HIGH,
.size = BUS_SIZE(SOC_MMU_DRAM0_LINEAR),
.size = SOC_BUS_SIZE(SOC_MMU_DRAM0_LINEAR),
.bus_id = CACHE_BUS_DBUS0,
.targets = MMU_TARGET_FLASH0 | MMU_TARGET_PSRAM0,
.caps = MMU_MEM_CAP_READ | MMU_MEM_CAP_WRITE | MMU_MEM_CAP_32BIT | MMU_MEM_CAP_8BIT,