diff --git a/components/bootloader/subproject/main/ld/esp32c3/bootloader.ld b/components/bootloader/subproject/main/ld/esp32c3/bootloader.ld index 680335aa73..84faa88e42 100644 --- a/components/bootloader/subproject/main/ld/esp32c3/bootloader.ld +++ b/components/bootloader/subproject/main/ld/esp32c3/bootloader.ld @@ -3,7 +3,7 @@ * * ESP32-C3 ROM static data usage is as follows: * - 0x3fccae00 - 0x3fcdc710: Shared buffers, used in UART/USB/SPI download mode only - * - 0x3fcdc710 - 0x3fcde710: APP CPU stack, can be reclaimed as heap after RTOS startup + * - 0x3fcdc710 - 0x3fcde710: PRO CPU stack, can be reclaimed as heap after RTOS startup * - 0x3fcde710 - 0x3fce0000: ROM .bss and .data (not easily reclaimable) * * The 2nd stage bootloader can take space up to the end of ROM shared diff --git a/components/bootloader/subproject/main/ld/esp32h2/bootloader.ld b/components/bootloader/subproject/main/ld/esp32h2/bootloader.ld index 560fee4fe9..6719e17cff 100644 --- a/components/bootloader/subproject/main/ld/esp32h2/bootloader.ld +++ b/components/bootloader/subproject/main/ld/esp32h2/bootloader.ld @@ -3,7 +3,7 @@ * * ESP32-H2 ROM static data usage is as follows: * - 0x3fccb900 - 0x3fcdd210: Shared buffers, used in UART/USB/SPI download mode only - * - 0x3fcdd210 - 0x3fcdf210: APP CPU stack, can be reclaimed as heap after RTOS startup + * - 0x3fcdd210 - 0x3fcdf210: PRO CPU stack, can be reclaimed as heap after RTOS startup * - 0x3fcdf210 - 0x3fce0000: ROM .bss and .data (not easily reclaimable) * * The 2nd stage bootloader can take space up to the end of ROM shared diff --git a/components/heap/port/esp32c3/memory_layout.c b/components/heap/port/esp32c3/memory_layout.c index 110c3861db..1f3825e41f 100644 --- a/components/heap/port/esp32c3/memory_layout.c +++ b/components/heap/port/esp32c3/memory_layout.c @@ -33,22 +33,26 @@ * - Most other malloc caps only fit in one region anyway. * */ -const soc_memory_type_desc_t soc_memory_types[] = { - // Type 0: DRAM - { "DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, 0 }, false, false}, - // Type 1: DRAM used for startup stacks - { "STACK/DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_EXEC | MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, MALLOC_CAP_RETENTION }, false, true}, - // Type 2: DRAM which has an alias on the I-port - { "D/IRAM", { 0, MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL | MALLOC_CAP_DEFAULT, MALLOC_CAP_32BIT | MALLOC_CAP_EXEC }, true, false}, - // Type 3: RTCRAM - { "RTCRAM", { MALLOC_CAP_RTCRAM, MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_32BIT }, false, false}, -}; /* Index of memory in `soc_memory_types[]` */ -#define SOC_MEMORY_TYPE_DRAM 0 -#define SOC_MEMORY_TYPE_STACK_DRAM 1 -#define SOC_MEMORY_TYPE_DIRAM 2 -#define SOC_MEMORY_TYPE_RTCRAM 3 +enum { + SOC_MEMORY_TYPE_DRAM = 0, + SOC_MEMORY_TYPE_STACK_DRAM = 1, + SOC_MEMORY_TYPE_DIRAM = 2, + SOC_MEMORY_TYPE_RTCRAM = 3, + SOC_MEMORY_TYPE_NUM, +}; + +const soc_memory_type_desc_t soc_memory_types[SOC_MEMORY_TYPE_NUM] = { + // Type 0: DRAM + [SOC_MEMORY_TYPE_DRAM] = { "DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, 0 }, false, false}, + // Type 1: DRAM used for startup stacks + [SOC_MEMORY_TYPE_STACK_DRAM] = { "STACK/DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_EXEC | MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, MALLOC_CAP_RETENTION }, false, true}, + // Type 2: DRAM which has an alias on the I-port + [SOC_MEMORY_TYPE_DIRAM] = { "D/IRAM", { 0, MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL | MALLOC_CAP_DEFAULT, MALLOC_CAP_32BIT | MALLOC_CAP_EXEC }, true, false}, + // Type 3: RTCRAM + [SOC_MEMORY_TYPE_RTCRAM] = { "RTCRAM", { MALLOC_CAP_RTCRAM, MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_32BIT }, false, false}, +}; #ifdef CONFIG_ESP_SYSTEM_MEMPROT_FEATURE #define SOC_MEMORY_TYPE_DEFAULT SOC_MEMORY_TYPE_DRAM diff --git a/components/heap/port/esp32h2/memory_layout.c b/components/heap/port/esp32h2/memory_layout.c index c3def826d2..1da96453d4 100644 --- a/components/heap/port/esp32h2/memory_layout.c +++ b/components/heap/port/esp32h2/memory_layout.c @@ -33,22 +33,25 @@ * - Most other malloc caps only fit in one region anyway. * */ -const soc_memory_type_desc_t soc_memory_types[] = { - // Type 0: DRAM - { "DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, 0 }, false, false}, - // Type 1: DRAM used for startup stacks - { "STACK/DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, MALLOC_CAP_RETENTION }, false, true}, - // Type 2: DRAM which has an alias on the I-port - { "D/IRAM", { 0, MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL | MALLOC_CAP_DEFAULT, MALLOC_CAP_32BIT | MALLOC_CAP_EXEC }, true, false}, - // Type 3: RTCRAM - { "RTCRAM", { MALLOC_CAP_RTCRAM, MALLOC_CAP_8BIT|MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL|MALLOC_CAP_32BIT }, false, false}, +/* Index of memory in `soc_memory_types[]` */ +enum { + SOC_MEMORY_TYPE_DRAM = 0, + SOC_MEMORY_TYPE_STACK_DRAM = 1, + SOC_MEMORY_TYPE_DIRAM = 2, + SOC_MEMORY_TYPE_RTCRAM = 3, + SOC_MEMORY_TYPE_NUM, }; -/* Index of memory in `soc_memory_types[]` */ -#define SOC_MEMORY_TYPE_DRAM 0 -#define SOC_MEMORY_TYPE_STACK_DRAM 1 -#define SOC_MEMORY_TYPE_DIRAM 2 -#define SOC_MEMORY_TYPE_RTCRAM 3 +const soc_memory_type_desc_t soc_memory_types[SOC_MEMORY_TYPE_NUM] = { + // Type 0: DRAM + [SOC_MEMORY_TYPE_DRAM] = { "DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, 0 }, false, false}, + // Type 1: DRAM used for startup stacks + [SOC_MEMORY_TYPE_STACK_DRAM] = { "STACK/DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, MALLOC_CAP_RETENTION }, false, true}, + // Type 2: DRAM which has an alias on the I-port + [SOC_MEMORY_TYPE_DIRAM] = { "D/IRAM", { 0, MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL | MALLOC_CAP_DEFAULT, MALLOC_CAP_32BIT | MALLOC_CAP_EXEC }, true, false}, + // Type 3: RTCRAM + [SOC_MEMORY_TYPE_RTCRAM] = { "RTCRAM", { MALLOC_CAP_RTCRAM, MALLOC_CAP_8BIT|MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL|MALLOC_CAP_32BIT }, false, false}, +}; #ifdef CONFIG_ESP_SYSTEM_MEMPROT_FEATURE #define SOC_MEMORY_TYPE_DEFAULT SOC_MEMORY_TYPE_DRAM diff --git a/components/heap/port/esp32s3/memory_layout.c b/components/heap/port/esp32s3/memory_layout.c index 5b25b17824..8010346f4e 100644 --- a/components/heap/port/esp32s3/memory_layout.c +++ b/components/heap/port/esp32s3/memory_layout.c @@ -28,21 +28,34 @@ * - Most other malloc caps only fit in one region anyway. * */ -const soc_memory_type_desc_t soc_memory_types[] = { + +/* Index of memory in `soc_memory_types[]` */ +enum { + SOC_MEMORY_TYPE_DRAM = 0, + SOC_MEMORY_TYPE_STACK_DRAM = 1, + SOC_MEMORY_TYPE_DIRAM = 2, + SOC_MEMORY_TYPE_IRAM = 3, + SOC_MEMORY_TYPE_SPIRAM = 4, + SOC_MEMORY_TYPE_NODMARAM = 5, + SOC_MEMORY_TYPE_RTCRAM = 6, + SOC_MEMORY_TYPE_NUM, +}; + +const soc_memory_type_desc_t soc_memory_types[SOC_MEMORY_TYPE_NUM] = { // Type 0: DRAM - { "DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, 0 }, false, false}, + [SOC_MEMORY_TYPE_DRAM] = { "DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, 0 }, false, false}, // Type 1: DRAM used for startup stacks - { "STACK/DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_EXEC | MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, 0 }, false, true}, + [SOC_MEMORY_TYPE_STACK_DRAM] = { "STACK/DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_EXEC | MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA | MALLOC_CAP_32BIT, 0 }, false, true}, // Type 2: DRAM which has an alias on the I-port - { "D/IRAM", { 0, MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL | MALLOC_CAP_DEFAULT, MALLOC_CAP_32BIT | MALLOC_CAP_EXEC }, true, false}, + [SOC_MEMORY_TYPE_DIRAM] = { "D/IRAM", { 0, MALLOC_CAP_DMA | MALLOC_CAP_8BIT | MALLOC_CAP_INTERNAL | MALLOC_CAP_DEFAULT, MALLOC_CAP_32BIT | MALLOC_CAP_EXEC }, true, false}, // Type 3: IRAM - { "IRAM", { MALLOC_CAP_EXEC | MALLOC_CAP_32BIT | MALLOC_CAP_INTERNAL, 0, 0 }, false, false}, + [SOC_MEMORY_TYPE_IRAM] = { "IRAM", { MALLOC_CAP_EXEC | MALLOC_CAP_32BIT | MALLOC_CAP_INTERNAL, 0, 0 }, false, false}, // Type 4: SPI SRAM data - { "SPIRAM", { MALLOC_CAP_SPIRAM | MALLOC_CAP_DEFAULT, 0, MALLOC_CAP_8BIT | MALLOC_CAP_32BIT}, false, false}, + [SOC_MEMORY_TYPE_SPIRAM] = { "SPIRAM", { MALLOC_CAP_SPIRAM | MALLOC_CAP_DEFAULT, 0, MALLOC_CAP_8BIT | MALLOC_CAP_32BIT}, false, false}, // Type 5: DRAM which is not DMA accesible - { "NON_DMA_DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_32BIT, 0 }, false, false}, + [SOC_MEMORY_TYPE_NODMARAM] = { "NON_DMA_DRAM", { MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_32BIT, 0 }, false, false}, // Type 6: RTC Fast RAM - { "RTCRAM", { MALLOC_CAP_RTCRAM, MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_32BIT }, false, false}, + [SOC_MEMORY_TYPE_RTCRAM] = { "RTCRAM", { MALLOC_CAP_RTCRAM, MALLOC_CAP_8BIT | MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL | MALLOC_CAP_32BIT }, false, false}, }; const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memory_type_desc_t); @@ -62,27 +75,27 @@ const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memor const soc_memory_region_t soc_memory_regions[] = { #ifdef CONFIG_SPIRAM - { SOC_EXTRAM_DATA_LOW, SOC_EXTRAM_DATA_SIZE, 4, 0}, //SPI SRAM, if available + { SOC_EXTRAM_DATA_LOW, SOC_EXTRAM_DATA_SIZE, SOC_MEMORY_TYPE_SPIRAM, 0}, //SPI SRAM, if available #endif #if CONFIG_ESP32S3_INSTRUCTION_CACHE_16KB - { 0x40374000, 0x4000, 3, 0}, //Level 1, IRAM + { 0x40374000, 0x4000, SOC_MEMORY_TYPE_IRAM, 0}, //Level 1, IRAM #endif - { 0x3FC88000, 0x8000, 2, 0x40378000}, //Level 2, IDRAM, can be used as trace memroy - { 0x3FC90000, 0x10000, 2, 0x40380000}, //Level 3, IDRAM, can be used as trace memroy - { 0x3FCA0000, 0x10000, 2, 0x40390000}, //Level 4, IDRAM, can be used as trace memroy - { 0x3FCB0000, 0x10000, 2, 0x403A0000}, //Level 5, IDRAM, can be used as trace memroy - { 0x3FCC0000, 0x10000, 2, 0x403B0000}, //Level 6, IDRAM, can be used as trace memroy - { 0x3FCD0000, 0x10000, 2, 0x403C0000}, //Level 7, IDRAM, can be used as trace memroy - { 0x3FCE0000, (APP_USABLE_DRAM_END-0x3FCE0000), 2, 0x403D0000}, //Level 8, IDRAM, can be used as trace memroy, - { APP_USABLE_DRAM_END, (SOC_DIRAM_DRAM_HIGH-APP_USABLE_DRAM_END), 1, MAP_DRAM_TO_IRAM(APP_USABLE_DRAM_END)}, //Level 8, IDRAM, can be used as trace memroy, ROM reserved area, recycled by heap allocator in app_main task + { 0x3FC88000, 0x8000, SOC_MEMORY_TYPE_DIRAM, 0x40378000}, //Level 2, IDRAM, can be used as trace memroy + { 0x3FC90000, 0x10000, SOC_MEMORY_TYPE_DIRAM, 0x40380000}, //Level 3, IDRAM, can be used as trace memroy + { 0x3FCA0000, 0x10000, SOC_MEMORY_TYPE_DIRAM, 0x40390000}, //Level 4, IDRAM, can be used as trace memroy + { 0x3FCB0000, 0x10000, SOC_MEMORY_TYPE_DIRAM, 0x403A0000}, //Level 5, IDRAM, can be used as trace memroy + { 0x3FCC0000, 0x10000, SOC_MEMORY_TYPE_DIRAM, 0x403B0000}, //Level 6, IDRAM, can be used as trace memroy + { 0x3FCD0000, 0x10000, SOC_MEMORY_TYPE_DIRAM, 0x403C0000}, //Level 7, IDRAM, can be used as trace memroy + { 0x3FCE0000, (APP_USABLE_DRAM_END-0x3FCE0000), SOC_MEMORY_TYPE_DIRAM, 0x403D0000}, //Level 8, IDRAM, can be used as trace memroy, + { APP_USABLE_DRAM_END, (SOC_DIRAM_DRAM_HIGH-APP_USABLE_DRAM_END), SOC_MEMORY_TYPE_STACK_DRAM, MAP_DRAM_TO_IRAM(APP_USABLE_DRAM_END)}, //Level 8, IDRAM, can be used as trace memroy, ROM reserved area, recycled by heap allocator in app_main task #if CONFIG_ESP32S3_DATA_CACHE_16KB || CONFIG_ESP32S3_DATA_CACHE_32KB - { 0x3FCF0000, 0x8000, 0, 0}, //Level 9, DRAM + { 0x3FCF0000, 0x8000, SOC_MEMORY_TYPE_DRAM, 0}, //Level 9, DRAM #endif #if CONFIG_ESP32S3_DATA_CACHE_16KB - { 0x3C000000, 0x4000, 5, 0}, + { 0x3C000000, 0x4000, SOC_MEMORY_TYPE_NODMARAM, 0}, #endif #ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP - { 0x600fe000, 0x2000, 6, 0}, //Fast RTC memory + { 0x600fe000, 0x2000, SOC_MEMORY_TYPE_RTCRAM, 0}, //Fast RTC memory #endif };