From dfbe76e988ab663ae854de9177dc6a003056c8fd Mon Sep 17 00:00:00 2001 From: laokaiyao Date: Tue, 7 Sep 2021 21:09:52 +0800 Subject: [PATCH] i2s: fix return value when failed to register i2s --- components/driver/i2s.c | 5 +- components/driver/include/driver/i2s.h | 2 +- components/driver/test/test_i2s.c | 68 +++++++++++++++++++- components/esp_lcd/test/test_i80_lcd_panel.c | 2 +- 4 files changed, 71 insertions(+), 6 deletions(-) diff --git a/components/driver/i2s.c b/components/driver/i2s.c index 0d79241ae9..0eb50e4738 100644 --- a/components/driver/i2s.c +++ b/components/driver/i2s.c @@ -1194,7 +1194,7 @@ static esp_err_t i2s_calculate_common_clock(int i2s_num, i2s_hal_clock_cfg_t *cl * Here use 'SOC_I2S_SUPPORTS_TDM' to differentialize other chips with ESP32 and ESP32S2. */ #if SOC_I2S_SUPPORTS_TDM - multi = clk_cfg->sclk / rate; + multi = I2S_LL_BASE_CLK / rate; #else multi = 64 * chan_bit; #endif @@ -1906,6 +1906,7 @@ static esp_err_t i2s_dma_object_init(i2s_port_t i2s_num) * - ESP_OK Success * - ESP_ERR_INVALID_ARG Parameter error * - ESP_ERR_NO_MEM Out of memory + * - ESP_ERR_INVALID_STATE Current I2S port is in use */ esp_err_t i2s_driver_install(i2s_port_t i2s_num, const i2s_config_t *i2s_config, int queue_size, void *i2s_queue) { @@ -1926,7 +1927,7 @@ esp_err_t i2s_driver_install(i2s_port_t i2s_num, const i2s_config_t *i2s_config, if (ret != ESP_OK) { free(pre_alloc_i2s_obj); ESP_LOGE(TAG, "register I2S object to platform failed"); - return ret; + return ESP_ERR_INVALID_STATE; } /* Step 3: Initialize I2S object, assign configarations */ diff --git a/components/driver/include/driver/i2s.h b/components/driver/include/driver/i2s.h index 6fffd9311e..aa649ed479 100644 --- a/components/driver/include/driver/i2s.h +++ b/components/driver/include/driver/i2s.h @@ -221,7 +221,7 @@ esp_err_t i2s_set_pdm_tx_up_sample(i2s_port_t i2s_num, const i2s_pdm_tx_upsample * - ESP_OK Success * - ESP_ERR_INVALID_ARG Parameter error * - ESP_ERR_NO_MEM Out of memory - * - ESP_ERR_NOT_FOUND I2S port is not found or has been installed by others (e.g. LCD i80) + * - ESP_ERR_INVALID_STATE Current I2S port is in use */ esp_err_t i2s_driver_install(i2s_port_t i2s_num, const i2s_config_t *i2s_config, int queue_size, void *i2s_queue); diff --git a/components/driver/test/test_i2s.c b/components/driver/test/test_i2s.c index 5a0e79755d..7234164cc5 100644 --- a/components/driver/test/test_i2s.c +++ b/components/driver/test/test_i2s.c @@ -145,6 +145,14 @@ TEST_CASE("I2S basic driver install, uninstall, set pin test", "[i2s]") .dma_buf_len = 60, .use_apll = 0, .intr_alloc_flags = ESP_INTR_FLAG_LEVEL1, +#if SOC_I2S_SUPPORTS_TDM + .chan_mask = I2S_TDM_ACTIVE_CH0 | I2S_TDM_ACTIVE_CH1, + .total_chan = 2, + .left_align = false, + .big_edin = false, + .bit_order_msb = false, + .skip_msk = false +#endif }; // normal i2s @@ -181,6 +189,14 @@ TEST_CASE("I2S Loopback test(master tx and rx)", "[i2s]") .dma_buf_len = 100, .use_apll = 0, .intr_alloc_flags = ESP_INTR_FLAG_LEVEL1, +#if SOC_I2S_SUPPORTS_TDM + .chan_mask = I2S_TDM_ACTIVE_CH0 | I2S_TDM_ACTIVE_CH1, + .total_chan = 2, + .left_align = false, + .big_edin = false, + .bit_order_msb = false, + .skip_msk = false +#endif }; i2s_pin_config_t master_pin_config = { .bck_io_num = MASTER_BCK_IO, @@ -246,6 +262,14 @@ TEST_CASE("I2S write and read test(master tx and slave rx)", "[i2s]") .dma_buf_len = 100, .use_apll = 0, .intr_alloc_flags = ESP_INTR_FLAG_LEVEL1, +#if SOC_I2S_SUPPORTS_TDM + .chan_mask = I2S_TDM_ACTIVE_CH0 | I2S_TDM_ACTIVE_CH1, + .total_chan = 2, + .left_align = false, + .big_edin = false, + .bit_order_msb = false, + .skip_msk = false +#endif }; i2s_pin_config_t master_pin_config = { .bck_io_num = MASTER_BCK_IO, @@ -268,6 +292,14 @@ TEST_CASE("I2S write and read test(master tx and slave rx)", "[i2s]") .dma_buf_len = 100, .use_apll = 0, .intr_alloc_flags = ESP_INTR_FLAG_LEVEL1, +#if SOC_I2S_SUPPORTS_TDM + .chan_mask = I2S_TDM_ACTIVE_CH0 | I2S_TDM_ACTIVE_CH1, + .total_chan = 2, + .left_align = false, + .big_edin = false, + .bit_order_msb = false, + .skip_msk = false +#endif }; i2s_pin_config_t slave_pin_config = { .bck_io_num = SLAVE_BCK_IO, @@ -332,6 +364,14 @@ TEST_CASE("I2S write and read test(master rx and slave tx)", "[i2s]") .dma_buf_len = 100, .use_apll = 1, .intr_alloc_flags = ESP_INTR_FLAG_LEVEL1, +#if SOC_I2S_SUPPORTS_TDM + .chan_mask = I2S_TDM_ACTIVE_CH0 | I2S_TDM_ACTIVE_CH1, + .total_chan = 2, + .left_align = false, + .big_edin = false, + .bit_order_msb = false, + .skip_msk = false +#endif }; i2s_pin_config_t master_pin_config = { .bck_io_num = MASTER_BCK_IO, @@ -354,6 +394,14 @@ TEST_CASE("I2S write and read test(master rx and slave tx)", "[i2s]") .dma_buf_len = 100, .use_apll = 1, .intr_alloc_flags = ESP_INTR_FLAG_LEVEL1, +#if SOC_I2S_SUPPORTS_TDM + .chan_mask = I2S_TDM_ACTIVE_CH0 | I2S_TDM_ACTIVE_CH1, + .total_chan = 2, + .left_align = false, + .big_edin = false, + .bit_order_msb = false, + .skip_msk = false +#endif }; i2s_pin_config_t slave_pin_config = { .bck_io_num = SLAVE_BCK_IO, @@ -419,6 +467,14 @@ TEST_CASE("I2S memory leaking test", "[i2s]") .dma_buf_len = 100, .use_apll = 0, .intr_alloc_flags = ESP_INTR_FLAG_LEVEL1, +#if SOC_I2S_SUPPORTS_TDM + .chan_mask = I2S_TDM_ACTIVE_CH0 | I2S_TDM_ACTIVE_CH1, + .total_chan = 2, + .left_align = false, + .big_edin = false, + .bit_order_msb = false, + .skip_msk = false +#endif }; i2s_pin_config_t master_pin_config = { .bck_io_num = MASTER_BCK_IO, @@ -442,6 +498,7 @@ TEST_CASE("I2S memory leaking test", "[i2s]") TEST_ASSERT(initial_size == esp_get_free_heap_size()); } +#if SOC_I2S_SUPPORTS_APLL /* * The I2S APLL clock variation test used to test the difference between the different sample rates, different bits per sample * and the APLL clock generate for it. The TEST_CASE passes PERCENT_DIFF variation from the provided sample rate in APLL generated clock @@ -464,10 +521,16 @@ TEST_CASE("I2S APLL clock variation test", "[i2s]") .communication_format = I2S_COMM_FORMAT_STAND_I2S, .dma_buf_count = 6, .dma_buf_len = 60, -#if SOC_I2S_SUPPORTS_APLL .use_apll = true, -#endif .intr_alloc_flags = 0, +#if SOC_I2S_SUPPORTS_TDM + .chan_mask = I2S_TDM_ACTIVE_CH0 | I2S_TDM_ACTIVE_CH1, + .total_chan = 2, + .left_align = false, + .big_edin = false, + .bit_order_msb = false, + .skip_msk = false +#endif }; TEST_ESP_OK(i2s_driver_install(I2S_NUM_0, &i2s_config, 0, NULL)); @@ -494,6 +557,7 @@ TEST_CASE("I2S APLL clock variation test", "[i2s]") vTaskDelay(100 / portTICK_PERIOD_MS); TEST_ASSERT(initial_size == esp_get_free_heap_size()); } +#endif #if SOC_I2S_SUPPORTS_ADC /* Only ESP32 need I2S adc/dac test */ diff --git a/components/esp_lcd/test/test_i80_lcd_panel.c b/components/esp_lcd/test/test_i80_lcd_panel.c index fc07add0c2..89f94d818e 100644 --- a/components/esp_lcd/test/test_i80_lcd_panel.c +++ b/components/esp_lcd/test/test_i80_lcd_panel.c @@ -560,7 +560,7 @@ TEST_CASE("i80 and i2s driver coexistance", "[lcd][i2s]") .dma_buf_len = 60, }; // I2S driver won't be installed as the same I2S port has been used by LCD - TEST_ASSERT_EQUAL(ESP_ERR_NOT_FOUND, i2s_driver_install(0, &i2s_config, 0, NULL)); + TEST_ASSERT_EQUAL(ESP_ERR_INVALID_STATE, i2s_driver_install(0, &i2s_config, 0, NULL)); TEST_ESP_OK(esp_lcd_del_i80_bus(i80_bus)); } #endif // SOC_I2S_LCD_I80_VARIANT