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Revert "fix(esp_pm): Constrains the minimum frequency of APB_MAX when the modem is working"

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This reverts commit 9158cba846.
This commit is contained in:
wuzhenghui
2023-07-25 13:51:37 +08:00
parent c64231564a
commit e0e4642ff8
9 changed files with 11 additions and 13 deletions
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13
components/esp_pm/pm_impl.c
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@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2016-2023 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2016-2022 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -266,14 +266,15 @@ esp_err_t esp_pm_configure(const void* vconfig)
*/ */
apb_max_freq = 80; apb_max_freq = 80;
} }
#else #elif CONFIG_IDF_TARGET_ESP32C6
/* Maximum SOC APB clock frequency is 40 MHz, maximum Modem (WiFi, /* Maximum SOC APB clock frequency is 40 MHz, maximum Modem (WiFi,
* Bluetooth, etc..) APB clock frequency is 80 MHz */ * Bluetooth, etc..) APB clock frequency is 80 MHz */
int apb_clk_freq = esp_clk_apb_freq() / MHZ; const int soc_apb_clk_freq = esp_clk_apb_freq() / MHZ;
#if CONFIG_ESP_WIFI_ENABLED || CONFIG_BT_ENABLED || CONFIG_IEEE802154_ENABLED const int modem_apb_clk_freq = MODEM_APB_CLK_FREQ / MHZ;
apb_clk_freq = MAX(apb_clk_freq, MODEM_REQUIRED_MIN_APB_CLK_FREQ / MHZ); const int apb_clk_freq = MAX(soc_apb_clk_freq, modem_apb_clk_freq);
#endif
int apb_max_freq = MIN(max_freq_mhz, apb_clk_freq); /* CPU frequency in APB_MAX mode */ int apb_max_freq = MIN(max_freq_mhz, apb_clk_freq); /* CPU frequency in APB_MAX mode */
#else
int apb_max_freq = MIN(max_freq_mhz, APB_CLK_FREQ / MHZ); /* CPU frequency in APB_MAX mode */
#endif #endif
apb_max_freq = MAX(apb_max_freq, min_freq_mhz); apb_max_freq = MAX(apb_max_freq, min_freq_mhz);

3
components/esp_wifi/src/wifi_init.c
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@@ -325,6 +325,9 @@ void wifi_apb80m_request(void)
{ {
assert(s_wifi_modem_sleep_lock); assert(s_wifi_modem_sleep_lock);
esp_pm_lock_acquire(s_wifi_modem_sleep_lock); esp_pm_lock_acquire(s_wifi_modem_sleep_lock);
if (esp_clk_apb_freq() != APB_CLK_FREQ) {
ESP_LOGE(__func__, "WiFi needs 80MHz APB frequency to work, but got %dHz", esp_clk_apb_freq());
}
} }
void wifi_apb80m_release(void) void wifi_apb80m_release(void)

1
components/soc/esp32/include/soc/soc.h
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@@ -159,7 +159,6 @@
#define CPU_CLK_FREQ_MHZ_BTLD (80) // The cpu clock frequency (in MHz) to set at 2nd stage bootloader system clock configuration #define CPU_CLK_FREQ_MHZ_BTLD (80) // The cpu clock frequency (in MHz) to set at 2nd stage bootloader system clock configuration
#define CPU_CLK_FREQ APB_CLK_FREQ //this may be incorrect, please refer to ESP_DEFAULT_CPU_FREQ_MHZ #define CPU_CLK_FREQ APB_CLK_FREQ //this may be incorrect, please refer to ESP_DEFAULT_CPU_FREQ_MHZ
#define APB_CLK_FREQ ( 80*1000000 ) //unit: Hz #define APB_CLK_FREQ ( 80*1000000 ) //unit: Hz
#define MODEM_REQUIRED_MIN_APB_CLK_FREQ ( 80*1000000 )
#define REF_CLK_FREQ ( 1000000 ) #define REF_CLK_FREQ ( 1000000 )
#define UART_CLK_FREQ APB_CLK_FREQ #define UART_CLK_FREQ APB_CLK_FREQ
#define WDT_CLK_FREQ APB_CLK_FREQ #define WDT_CLK_FREQ APB_CLK_FREQ

1
components/soc/esp32c2/include/soc/soc.h
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@@ -146,7 +146,6 @@
#define CPU_CLK_FREQ_MHZ_BTLD (80) // The cpu clock frequency (in MHz) to set at 2nd stage bootloader system clock configuration #define CPU_CLK_FREQ_MHZ_BTLD (80) // The cpu clock frequency (in MHz) to set at 2nd stage bootloader system clock configuration
#define CPU_CLK_FREQ APB_CLK_FREQ #define CPU_CLK_FREQ APB_CLK_FREQ
#define APB_CLK_FREQ ( 40*1000000 ) #define APB_CLK_FREQ ( 40*1000000 )
#define MODEM_REQUIRED_MIN_APB_CLK_FREQ ( 80*1000000 )
#define REF_CLK_FREQ ( 1000000 ) #define REF_CLK_FREQ ( 1000000 )
#define UART_CLK_FREQ APB_CLK_FREQ #define UART_CLK_FREQ APB_CLK_FREQ
#define WDT_CLK_FREQ APB_CLK_FREQ #define WDT_CLK_FREQ APB_CLK_FREQ

1
components/soc/esp32c3/include/soc/soc.h
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@@ -139,7 +139,6 @@
#define CPU_CLK_FREQ_MHZ_BTLD (80) // The cpu clock frequency (in MHz) to set at 2nd stage bootloader system clock configuration #define CPU_CLK_FREQ_MHZ_BTLD (80) // The cpu clock frequency (in MHz) to set at 2nd stage bootloader system clock configuration
#define CPU_CLK_FREQ APB_CLK_FREQ #define CPU_CLK_FREQ APB_CLK_FREQ
#define APB_CLK_FREQ ( 80*1000000 ) #define APB_CLK_FREQ ( 80*1000000 )
#define MODEM_REQUIRED_MIN_APB_CLK_FREQ ( 80*1000000 )
#define REF_CLK_FREQ ( 1000000 ) #define REF_CLK_FREQ ( 1000000 )
#define XTAL_CLK_FREQ (40*1000000) #define XTAL_CLK_FREQ (40*1000000)
#define UART_CLK_FREQ APB_CLK_FREQ #define UART_CLK_FREQ APB_CLK_FREQ

2
components/soc/esp32c6/include/soc/soc.h
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@@ -142,7 +142,7 @@
#define CPU_CLK_FREQ_MHZ_BTLD (80) // The cpu clock frequency (in MHz) to set at 2nd stage bootloader system clock configuration #define CPU_CLK_FREQ_MHZ_BTLD (80) // The cpu clock frequency (in MHz) to set at 2nd stage bootloader system clock configuration
#define CPU_CLK_FREQ APB_CLK_FREQ #define CPU_CLK_FREQ APB_CLK_FREQ
#define APB_CLK_FREQ ( 40*1000000 ) #define APB_CLK_FREQ ( 40*1000000 )
#define MODEM_REQUIRED_MIN_APB_CLK_FREQ ( 80*1000000 ) #define MODEM_APB_CLK_FREQ ( 80*1000000 )
#define REF_CLK_FREQ ( 1000000 ) #define REF_CLK_FREQ ( 1000000 )
#define XTAL_CLK_FREQ (40*1000000) #define XTAL_CLK_FREQ (40*1000000)
#define GPIO_MATRIX_DELAY_NS 0 #define GPIO_MATRIX_DELAY_NS 0

1
components/soc/esp32h2/include/soc/soc.h
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@@ -140,7 +140,6 @@
#define CPU_CLK_FREQ_MHZ_BTLD (96) // The cpu clock frequency (in MHz) to set at 2nd stage bootloader system clock configuration #define CPU_CLK_FREQ_MHZ_BTLD (96) // The cpu clock frequency (in MHz) to set at 2nd stage bootloader system clock configuration
#define CPU_CLK_FREQ APB_CLK_FREQ #define CPU_CLK_FREQ APB_CLK_FREQ
#define APB_CLK_FREQ ( 32*1000000 ) #define APB_CLK_FREQ ( 32*1000000 )
#define MODEM_REQUIRED_MIN_APB_CLK_FREQ ( 32*1000000 )
#define REF_CLK_FREQ ( 1000000 ) #define REF_CLK_FREQ ( 1000000 )
#define XTAL_CLK_FREQ (32*1000000) #define XTAL_CLK_FREQ (32*1000000)
#define GPIO_MATRIX_DELAY_NS 0 #define GPIO_MATRIX_DELAY_NS 0

1
components/soc/esp32s2/include/soc/soc.h
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@@ -145,7 +145,6 @@
#define CPU_CLK_FREQ_MHZ_BTLD (80) // The cpu clock frequency (in MHz) to set at 2nd stage bootloader system clock configuration #define CPU_CLK_FREQ_MHZ_BTLD (80) // The cpu clock frequency (in MHz) to set at 2nd stage bootloader system clock configuration
#define CPU_CLK_FREQ APB_CLK_FREQ #define CPU_CLK_FREQ APB_CLK_FREQ
#define APB_CLK_FREQ ( 80*1000000 ) //unit: Hz #define APB_CLK_FREQ ( 80*1000000 ) //unit: Hz
#define MODEM_REQUIRED_MIN_APB_CLK_FREQ ( 80*1000000 )
#define REF_CLK_FREQ ( 1000000 ) #define REF_CLK_FREQ ( 1000000 )
#define UART_CLK_FREQ APB_CLK_FREQ #define UART_CLK_FREQ APB_CLK_FREQ
#define WDT_CLK_FREQ APB_CLK_FREQ #define WDT_CLK_FREQ APB_CLK_FREQ

1
components/soc/esp32s3/include/soc/soc.h
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@@ -155,7 +155,6 @@
#define CPU_CLK_FREQ_MHZ_BTLD (80) // The cpu clock frequency (in MHz) to set at 2nd stage bootloader system clock configuration #define CPU_CLK_FREQ_MHZ_BTLD (80) // The cpu clock frequency (in MHz) to set at 2nd stage bootloader system clock configuration
#define CPU_CLK_FREQ APB_CLK_FREQ #define CPU_CLK_FREQ APB_CLK_FREQ
#define APB_CLK_FREQ (80*1000000) #define APB_CLK_FREQ (80*1000000)
#define MODEM_REQUIRED_MIN_APB_CLK_FREQ (80*1000000)
#define REF_CLK_FREQ (1000000) #define REF_CLK_FREQ (1000000)
#define XTAL_CLK_FREQ (40*1000000) #define XTAL_CLK_FREQ (40*1000000)
#define UART_CLK_FREQ APB_CLK_FREQ #define UART_CLK_FREQ APB_CLK_FREQ