feat(adc): add always inline for adc ll functions called by bootloader

components/hal/esp32c5/include/hal/adc_ll.h

@@ -139,6 +139,7 @@ static inline void adc_ll_set_sample_cycle(uint32_t sample_cycle)
  *
  * @param div Division factor.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_set_clk_div(uint32_t div)
 {
     /* ADC clock divided from digital controller clock clk */
@@ -188,6 +189,7 @@ static inline void adc_ll_digi_set_convert_mode(adc_ll_digi_convert_mode_t mode)
  * @param adc_n ADC unit.
  * @param patt_len Items range: 1 ~ 8.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_set_pattern_table_len(adc_unit_t adc_n, uint32_t patt_len)
 {
     APB_SARADC.saradc_ctrl.saradc_saradc_sar_patt_len = patt_len - 1;
@@ -203,6 +205,7 @@ static inline void adc_ll_digi_set_pattern_table_len(adc_unit_t adc_n, uint32_t
  * @param pattern_index Items index. Range: 0 ~ 7.
  * @param pattern Stored conversion rules.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_set_pattern_table(adc_unit_t adc_n, uint32_t pattern_index, adc_digi_pattern_config_t table)
 {
     uint32_t tab;
@@ -275,6 +278,7 @@ static inline void adc_ll_digi_output_invert(adc_unit_t adc_n, bool inv_en)
  * @note The trigger interval should not be smaller than the sampling time of the SAR ADC.
  * @param cycle The clock cycle (trigger interval) of the measurement. Range: 30 ~ 4095.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_set_trigger_interval(uint32_t cycle)
 {
     APB_SARADC.saradc_ctrl2.saradc_saradc_timer_target = cycle;
@@ -283,6 +287,7 @@ static inline void adc_ll_digi_set_trigger_interval(uint32_t cycle)
 /**
  * Enable digital controller timer to trigger the measurement.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_trigger_enable(void)
 {
     APB_SARADC.saradc_ctrl2.saradc_saradc_timer_en = 1;
@@ -291,6 +296,7 @@ static inline void adc_ll_digi_trigger_enable(void)
 /**
  * Disable digital controller timer to trigger the measurement.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_trigger_disable(void)
 {
     APB_SARADC.saradc_ctrl2.saradc_saradc_timer_en = 0;
@@ -304,6 +310,7 @@ static inline void adc_ll_digi_trigger_disable(void)
  * @param div_b Division factor. Range: 1 ~ 63.
  * @param div_a Division factor. Range: 0 ~ 63.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_controller_clk_div(uint32_t div_num, uint32_t div_b, uint32_t div_a)
 {
     HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.saradc_clkm_conf, saradc_clkm_div_num, div_num);
@@ -316,6 +323,7 @@ static inline void adc_ll_digi_controller_clk_div(uint32_t div_num, uint32_t div
  *
  * @param clk_src clock source for ADC digital controller.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_clk_sel(adc_continuous_clk_src_t clk_src)
 {
     switch (clk_src) {
@@ -570,6 +578,7 @@ static inline uint32_t adc_ll_pwdet_get_cct(void)
  * @brief Enable the ADC APB clock
  * @param enable true to enable, false to disable
  */
+__attribute__((always_inline))
 static inline void adc_ll_enable_bus_clock(bool enable)
 {
     PCR.saradc_conf.saradc_reg_clk_en = enable;
@@ -579,6 +588,7 @@ static inline void adc_ll_enable_bus_clock(bool enable)
  * @brief Enable the ADC function clock
  * @param enable true to enable, false to disable
  */
+__attribute__((always_inline))
 static inline void adc_ll_enable_func_clock(bool enable)
 {
     PCR.saradc_clkm_conf.saradc_clkm_en = enable;
@@ -587,6 +597,7 @@ static inline void adc_ll_enable_func_clock(bool enable)
 /**
  * @brief Reset ADC module
  */
+__attribute__((always_inline))
 static inline void adc_ll_reset_register(void)
 {
     PCR.saradc_conf.saradc_rst_en = 1;

components/hal/esp32c6/include/hal/adc_ll.h

@@ -138,6 +138,7 @@ static inline void adc_ll_set_sample_cycle(uint32_t sample_cycle)
  *
  * @param div Division factor.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_set_clk_div(uint32_t div)
 {
     /* ADC clock divided from digital controller clock clk */
@@ -187,6 +188,7 @@ static inline void adc_ll_digi_set_convert_mode(adc_ll_digi_convert_mode_t mode)
  * @param adc_n ADC unit.
  * @param patt_len Items range: 1 ~ 8.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_set_pattern_table_len(adc_unit_t adc_n, uint32_t patt_len)
 {
     APB_SARADC.saradc_ctrl.saradc_saradc_sar_patt_len = patt_len - 1;
@@ -202,6 +204,7 @@ static inline void adc_ll_digi_set_pattern_table_len(adc_unit_t adc_n, uint32_t
  * @param pattern_index Items index. Range: 0 ~ 7.
  * @param pattern Stored conversion rules.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_set_pattern_table(adc_unit_t adc_n, uint32_t pattern_index, adc_digi_pattern_config_t table)
 {
     uint32_t tab;
@@ -274,6 +277,7 @@ static inline void adc_ll_digi_output_invert(adc_unit_t adc_n, bool inv_en)
  * @note The trigger interval should not be smaller than the sampling time of the SAR ADC.
  * @param cycle The clock cycle (trigger interval) of the measurement. Range: 30 ~ 4095.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_set_trigger_interval(uint32_t cycle)
 {
     APB_SARADC.saradc_ctrl2.saradc_saradc_timer_target = cycle;
@@ -282,6 +286,7 @@ static inline void adc_ll_digi_set_trigger_interval(uint32_t cycle)
 /**
  * Enable digital controller timer to trigger the measurement.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_trigger_enable(void)
 {
     APB_SARADC.saradc_ctrl2.saradc_saradc_timer_en = 1;
@@ -290,6 +295,7 @@ static inline void adc_ll_digi_trigger_enable(void)
 /**
  * Disable digital controller timer to trigger the measurement.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_trigger_disable(void)
 {
     APB_SARADC.saradc_ctrl2.saradc_saradc_timer_en = 0;
@@ -303,6 +309,7 @@ static inline void adc_ll_digi_trigger_disable(void)
  * @param div_b Division factor. Range: 1 ~ 63.
  * @param div_a Division factor. Range: 0 ~ 63.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_controller_clk_div(uint32_t div_num, uint32_t div_b, uint32_t div_a)
 {
     HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.saradc_clkm_conf, saradc_clkm_div_num, div_num);
@@ -315,6 +322,7 @@ static inline void adc_ll_digi_controller_clk_div(uint32_t div_num, uint32_t div
  *
  * @param clk_src clock source for ADC digital controller.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_clk_sel(adc_continuous_clk_src_t clk_src)
 {
     switch (clk_src) {
@@ -569,6 +577,7 @@ static inline uint32_t adc_ll_pwdet_get_cct(void)
  * @brief Enable the ADC clock
  * @param enable true to enable, false to disable
  */
+__attribute__((always_inline))
 static inline void adc_ll_enable_bus_clock(bool enable)
 {
     PCR.saradc_conf.saradc_reg_clk_en = enable;
@@ -578,6 +587,7 @@ static inline void adc_ll_enable_bus_clock(bool enable)
  * @brief Enable the ADC function clock
  * @param enable true to enable, false to disable
  */
+__attribute__((always_inline))
 static inline void adc_ll_enable_func_clock(bool enable)
 {
     PCR.saradc_clkm_conf.saradc_clkm_en = enable;
@@ -586,6 +596,7 @@ static inline void adc_ll_enable_func_clock(bool enable)
 /**
  * @brief Reset ADC module
  */
+__attribute__((always_inline))
 static inline void adc_ll_reset_register(void)
 {
     PCR.saradc_conf.saradc_rst_en = 1;

components/hal/esp32c61/include/hal/adc_ll.h

@@ -139,6 +139,7 @@ static inline void adc_ll_set_sample_cycle(uint32_t sample_cycle)
  *
  * @param div Division factor.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_set_clk_div(uint32_t div)
 {
     /* ADC clock divided from digital controller clock clk */
@@ -188,6 +189,7 @@ static inline void adc_ll_digi_set_convert_mode(adc_ll_digi_convert_mode_t mode)
  * @param adc_n ADC unit.
  * @param patt_len Items range: 1 ~ 8.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_set_pattern_table_len(adc_unit_t adc_n, uint32_t patt_len)
 {
     ADC.saradc_ctrl.saradc_sar_patt_len = patt_len - 1;
@@ -203,6 +205,7 @@ static inline void adc_ll_digi_set_pattern_table_len(adc_unit_t adc_n, uint32_t
  * @param pattern_index Items index. Range: 0 ~ 7.
  * @param pattern Stored conversion rules.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_set_pattern_table(adc_unit_t adc_n, uint32_t pattern_index, adc_digi_pattern_config_t table)
 {
     uint32_t tab;
@@ -277,6 +280,7 @@ static inline void adc_ll_digi_output_invert(adc_unit_t adc_n, bool inv_en)
  * @note The trigger interval should not be smaller than the sampling time of the SAR ADC.
  * @param cycle The clock cycle (trigger interval) of the measurement. Range: 30 ~ 4095.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_set_trigger_interval(uint32_t cycle)
 {
     ADC.saradc_ctrl2.saradc_timer_target = cycle;
@@ -285,6 +289,7 @@ static inline void adc_ll_digi_set_trigger_interval(uint32_t cycle)
 /**
  * Enable digital controller timer to trigger the measurement.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_trigger_enable(void)
 {
     ADC.saradc_ctrl2.saradc_timer_en = 1;
@@ -293,6 +298,7 @@ static inline void adc_ll_digi_trigger_enable(void)
 /**
  * Disable digital controller timer to trigger the measurement.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_trigger_disable(void)
 {
     ADC.saradc_ctrl2.saradc_timer_en = 0;
@@ -306,6 +312,7 @@ static inline void adc_ll_digi_trigger_disable(void)
  * @param div_b Division factor. Range: 1 ~ 63.
  * @param div_a Division factor. Range: 0 ~ 63.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_controller_clk_div(uint32_t div_num, uint32_t div_b, uint32_t div_a)
 {
     HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.saradc_clkm_conf, saradc_clkm_div_num, div_num);
@@ -318,6 +325,7 @@ static inline void adc_ll_digi_controller_clk_div(uint32_t div_num, uint32_t div
  *
  * @param clk_src clock source for ADC digital controller.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_clk_sel(adc_continuous_clk_src_t clk_src)
 {
     switch (clk_src) {
@@ -572,6 +580,7 @@ static inline uint32_t adc_ll_pwdet_get_cct(void)
  * @brief Enable the ADC APB clock
  * @param enable true to enable, false to disable
  */
+__attribute__((always_inline))
 static inline void adc_ll_enable_bus_clock(bool enable)
 {
     PCR.saradc_conf.saradc_reg_clk_en = enable;
@@ -581,6 +590,7 @@ static inline void adc_ll_enable_bus_clock(bool enable)
  * @brief Enable the ADC function clock
  * @param enable true to enable, false to disable
  */
+__attribute__((always_inline))
 static inline void adc_ll_enable_func_clock(bool enable)
 {
     PCR.saradc_clkm_conf.saradc_clkm_en = enable;
@@ -589,6 +599,7 @@ static inline void adc_ll_enable_func_clock(bool enable)
 /**
  * @brief Reset ADC module
  */
+__attribute__((always_inline))
 static inline void adc_ll_reset_register(void)
 {
     PCR.saradc_conf.saradc_rst_en = 1;

components/hal/esp32h2/include/hal/adc_ll.h

@@ -139,6 +139,7 @@ static inline void adc_ll_set_sample_cycle(uint32_t sample_cycle)
  *
  * @param div Division factor.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_set_clk_div(uint32_t div)
 {
     /* ADC clock divided from digital controller clock clk */
@@ -188,6 +189,7 @@ static inline void adc_ll_digi_set_convert_mode(adc_ll_digi_convert_mode_t mode)
  * @param adc_n ADC unit.
  * @param patt_len Items range: 1 ~ 8.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_set_pattern_table_len(adc_unit_t adc_n, uint32_t patt_len)
 {
     APB_SARADC.saradc_ctrl.saradc_saradc_sar_patt_len = patt_len - 1;
@@ -203,6 +205,7 @@ static inline void adc_ll_digi_set_pattern_table_len(adc_unit_t adc_n, uint32_t
  * @param pattern_index Items index. Range: 0 ~ 7.
  * @param pattern Stored conversion rules.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_set_pattern_table(adc_unit_t adc_n, uint32_t pattern_index, adc_digi_pattern_config_t table)
 {
     uint32_t tab;
@@ -275,6 +278,7 @@ static inline void adc_ll_digi_output_invert(adc_unit_t adc_n, bool inv_en)
  * @note The trigger interval should not be smaller than the sampling time of the SAR ADC.
  * @param cycle The clock cycle (trigger interval) of the measurement. Range: 30 ~ 4095.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_set_trigger_interval(uint32_t cycle)
 {
     APB_SARADC.saradc_ctrl2.saradc_saradc_timer_target = cycle;
@@ -283,6 +287,7 @@ static inline void adc_ll_digi_set_trigger_interval(uint32_t cycle)
 /**
  * Enable digital controller timer to trigger the measurement.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_trigger_enable(void)
 {
     APB_SARADC.saradc_ctrl2.saradc_saradc_timer_en = 1;
@@ -291,6 +296,7 @@ static inline void adc_ll_digi_trigger_enable(void)
 /**
  * Disable digital controller timer to trigger the measurement.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_trigger_disable(void)
 {
     APB_SARADC.saradc_ctrl2.saradc_saradc_timer_en = 0;
@@ -304,6 +310,7 @@ static inline void adc_ll_digi_trigger_disable(void)
  * @param div_b Division factor. Range: 1 ~ 63.
  * @param div_a Division factor. Range: 0 ~ 63.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_controller_clk_div(uint32_t div_num, uint32_t div_b, uint32_t div_a)
 {
     HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.saradc_clkm_conf, saradc_clkm_div_num, div_num);
@@ -316,6 +323,7 @@ static inline void adc_ll_digi_controller_clk_div(uint32_t div_num, uint32_t div
  *
  * @param clk_src clock source for ADC digital controller.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_clk_sel(adc_continuous_clk_src_t clk_src)
 {
     switch (clk_src) {
@@ -570,6 +578,7 @@ static inline uint32_t adc_ll_pwdet_get_cct(void)
  * @brief Enable the ADC clock
  * @param enable true to enable, false to disable
  */
+__attribute__((always_inline))
 static inline void adc_ll_enable_bus_clock(bool enable)
 {
     PCR.saradc_conf.saradc_reg_clk_en = enable;
@@ -579,6 +588,7 @@ static inline void adc_ll_enable_bus_clock(bool enable)
  * @brief Enable the ADC function clock
  * @param enable true to enable, false to disable
  */
+__attribute__((always_inline))
 static inline void adc_ll_enable_func_clock(bool enable)
 {
     PCR.saradc_clkm_conf.saradc_clkm_en = enable;
@@ -587,6 +597,7 @@ static inline void adc_ll_enable_func_clock(bool enable)
 /**
  * @brief Reset ADC module
  */
+__attribute__((always_inline))
 static inline void adc_ll_reset_register(void)
 {
     PCR.saradc_conf.saradc_rst_en = 1;

components/hal/esp32p4/include/hal/adc_ll.h

@@ -145,6 +145,7 @@ static inline void adc_ll_set_sample_cycle(uint32_t sample_cycle)
  *
  * @param div Division factor.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_set_clk_div(uint32_t div)
 {
     /* ADC clock divided from digital controller clock clk */
@@ -202,6 +203,7 @@ static inline void adc_ll_digi_set_convert_mode(adc_ll_digi_convert_mode_t mode)
  * @param div_b Division factor. Range: 1 ~ 63.
  * @param div_a Division factor. Range: 0 ~ 63.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_controller_clk_div(uint32_t div_num, uint32_t div_b, uint32_t div_a)
 {
     HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl23, reg_adc_clk_div_num, div_num);
@@ -214,6 +216,7 @@ static inline void adc_ll_digi_controller_clk_div(uint32_t div_num, uint32_t div
  *
  * @param clk_src clock source for ADC digital controller.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_clk_sel(adc_continuous_clk_src_t clk_src)
 {
     switch (clk_src) {
@@ -326,6 +329,7 @@ static inline void adc_ll_digi_filter_enable(adc_digi_iir_filter_t idx, adc_unit
  * @param adc_n ADC unit.
  * @param patt_len Items range: 1 ~ 16.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_set_pattern_table_len(adc_unit_t adc_n, uint32_t patt_len)
 {
     if (adc_n == ADC_UNIT_1) {
@@ -345,6 +349,7 @@ static inline void adc_ll_digi_set_pattern_table_len(adc_unit_t adc_n, uint32_t
  * @param pattern_index Items index. Range: 0 ~ 11.
  * @param pattern Stored conversion rules.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_set_pattern_table(adc_unit_t adc_n, uint32_t pattern_index, adc_digi_pattern_config_t table)
 {
     uint32_t tab;
@@ -416,6 +421,7 @@ static inline void adc_ll_digi_output_invert(adc_unit_t adc_n, bool inv_en)
  * @note The trigger interval should not be smaller than the sampling time of the SAR ADC.
  * @param cycle The clock cycle (trigger interval) of the measurement. Range: 30 ~ 4095.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_set_trigger_interval(uint32_t cycle)
 {
     ADC.ctrl2.timer_target = cycle;
@@ -460,6 +466,7 @@ static inline void adc_ll_digi_reset(void)
 /**
  * Enable digital controller timer to trigger the measurement.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_trigger_enable(void)
 {
     ADC.ctrl2.timer_sel = 1;
@@ -469,6 +476,7 @@ static inline void adc_ll_digi_trigger_enable(void)
 /**
  * Disable digital controller timer to trigger the measurement.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_trigger_disable(void)
 {
     ADC.ctrl2.timer_en = 0;
@@ -526,6 +534,7 @@ static inline void _adc_ll_sar2_clock_force_en(bool enable)
  * @brief Enable the ADC clock
  * @param enable true to enable, false to disable
  */
+__attribute__((always_inline))
 static inline void _adc_ll_enable_bus_clock(bool enable)
 {
     HP_SYS_CLKRST.soc_clk_ctrl2.reg_adc_apb_clk_en = enable;
@@ -537,6 +546,7 @@ static inline void _adc_ll_enable_bus_clock(bool enable)
 /**
  * @brief Reset ADC module
  */
+__attribute__((always_inline))
 static inline void _adc_ll_reset_register(void)
 {
     HP_SYS_CLKRST.hp_rst_en2.reg_rst_en_adc = 1;
@@ -553,6 +563,7 @@ static inline void _adc_ll_reset_register(void)
  * @param adc_n ADC unit.
  * @param manage Set ADC power status.
  */
+__attribute__((always_inline))
 static inline void adc_ll_digi_set_power_manage(adc_unit_t adc_n, adc_ll_power_t manage)
 {
     if (adc_n == ADC_UNIT_1) {