diff --git a/components/esp_rom/esp32p4/esp_rom_caps.h b/components/esp_rom/esp32p4/esp_rom_caps.h
index 92536eedfd..437fa7bdd7 100644
--- a/components/esp_rom/esp32p4/esp_rom_caps.h
+++ b/components/esp_rom/esp32p4/esp_rom_caps.h
@@ -25,6 +25,6 @@
 #define ESP_ROM_HAS_NEWLIB_NANO_FORMAT      (1) // ROM has the newlib nano version of formatting functions
 #define ESP_ROM_HAS_NEWLIB_NANO_PRINTF_FLOAT_BUG  (1) // ROM has the printf float bug with newlib nano version
 #define ESP_ROM_HAS_VERSION                 (1) // ROM has version/eco information
-#define ESP_ROM_CLIC_INT_TYPE_PATCH         (1) // ROM api esprv_intc_int_set_type configuring edge type interrupt is invalid TODO: IDF-13409
+#define ESP_ROM_CLIC_INT_TYPE_PATCH         (1) // ROM api esprv_intc_int_set_type configuring edge type interrupt (old revisions)
 #define ESP_ROM_HAS_OUTPUT_PUTC_FUNC        (1) // ROM has esp_rom_output_putc (or ets_write_char_uart)
 #define ESP_ROM_HAS_SUBOPTIMAL_NEWLIB_ON_MISALIGNED_MEMORY  (1) // ROM mem/str functions are not optimized well for misaligned memory access.
diff --git a/components/esp_rom/patches/esp_rom_clic.c b/components/esp_rom/patches/esp_rom_clic.c
index d4643e3ef5..85656d2222 100644
--- a/components/esp_rom/patches/esp_rom_clic.c
+++ b/components/esp_rom/patches/esp_rom_clic.c
@@ -1,14 +1,15 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
+#include "sdkconfig.h"
 #include "esp_rom_caps.h"
 #include "soc/clic_reg.h"
 #include "riscv/interrupt.h"
 
-#if ESP_ROM_CLIC_INT_TYPE_PATCH
+#if ESP_ROM_CLIC_INT_TYPE_PATCH && CONFIG_ESP32P4_SELECTS_REV_LESS_V3
 
 /* Rom api esprv_intc_int_set_type, if the configured interrupt type is INTR_TYPE_EDGE,
  * the actual configured type is still INTR_TYPE_LEVEL. So the patch is to solve this issue.
diff --git a/components/riscv/vectors.S b/components/riscv/vectors.S
index 56542f2505..114f83a41c 100644
--- a/components/riscv/vectors.S
+++ b/components/riscv/vectors.S
@@ -278,7 +278,8 @@ hwlp_not_used:
      * For example, bit 1 can be set and bit 0 won't, even if the reason is an FPU instruction. */
     andi  a1, a0, EXT_ILL_RSN_FPU
     bnez  a1, rtos_save_fpu_coproc
-#if SOC_CPU_HAS_FPU_EXT_ILL_BUG
+    /* The FPU_EXT_ILL bug was fixed on revision 3.0 and higher */
+#if SOC_CPU_HAS_FPU_EXT_ILL_BUG && CONFIG_ESP32P4_SELECTS_REV_LESS_V3
     /* If the SOC present the hardware EXT_ILL CSR bug, it doesn't support FPU load/store detection
      * so we have to check the instruction's opcode (in `mtval` = `t0`) */
     andi  a0, t0, 0b1011111