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Merge branch 'bugfix/rtc_8md256_deepsleep_time_esp32_v4.4' into 'release/v4.4'

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pm: Fixed sleep time inaccurate bug when select 8MD256 as rtc slow clock on ESP32 (v4.4)

See merge request espressif/esp-idf!21822
This commit is contained in:
morris
2023-02-06 11:13:52 +08:00
parent 3ecf906721 5998130eb9
commit e1e9e10d3b
3 changed files with 5 additions and 1 deletions
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4
components/esp_hw_support/port/esp32/rtc_sleep.c
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@ -108,11 +108,13 @@ void rtc_sleep_get_default_config(uint32_t sleep_flags, rtc_sleep_config_t *out_
out_config->dig_dbias_slp = RTC_CNTL_DBIAS_0V90; out_config->dig_dbias_slp = RTC_CNTL_DBIAS_0V90;
out_config->rtc_dbias_wak = RTC_CNTL_DBIAS_1V10; out_config->rtc_dbias_wak = RTC_CNTL_DBIAS_1V10;
out_config->rtc_dbias_slp = RTC_CNTL_DBIAS_0V90; out_config->rtc_dbias_slp = RTC_CNTL_DBIAS_0V90;
out_config->dbg_atten_slp = !(sleep_flags & RTC_SLEEP_PD_INT_8M) ? RTC_CNTL_DBG_ATTEN_NODROP : RTC_CNTL_DBG_ATTEN_DEFAULT;
} else { } else {
out_config->dig_dbias_wak = RTC_CNTL_DBIAS_1V10; out_config->dig_dbias_wak = RTC_CNTL_DBIAS_1V10;
out_config->dig_dbias_slp = !((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? RTC_CNTL_DBIAS_1V10 : RTC_CNTL_DBIAS_0V90; out_config->dig_dbias_slp = !((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? RTC_CNTL_DBIAS_1V10 : RTC_CNTL_DBIAS_0V90;
out_config->rtc_dbias_wak = RTC_CNTL_DBIAS_1V10; out_config->rtc_dbias_wak = RTC_CNTL_DBIAS_1V10;
out_config->rtc_dbias_slp = !((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? RTC_CNTL_DBIAS_1V10 : RTC_CNTL_DBIAS_0V90; out_config->rtc_dbias_slp = !((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? RTC_CNTL_DBIAS_1V10 : RTC_CNTL_DBIAS_0V90;
out_config->dbg_atten_slp = RTC_CNTL_DBG_ATTEN_NODROP;
} }
} }
@ -207,7 +209,6 @@ void rtc_sleep_init(rtc_sleep_config_t cfg)
CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BB_I2C_FORCE_PU); CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BB_I2C_FORCE_PU);
} else { } else {
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_PD_EN); CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_PD_EN);
REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN, 0);
} }
REG_SET_FIELD(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_XTL_FORCE_PU, cfg.xtal_fpu); REG_SET_FIELD(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_XTL_FORCE_PU, cfg.xtal_fpu);
@ -226,6 +227,7 @@ void rtc_sleep_init(rtc_sleep_config_t cfg)
REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DBIAS_WAK, cfg.rtc_dbias_wak); REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DBIAS_WAK, cfg.rtc_dbias_wak);
REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, cfg.dig_dbias_wak); REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, cfg.dig_dbias_wak);
REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_SLP, cfg.dig_dbias_slp); REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_SLP, cfg.dig_dbias_slp);
REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN, cfg.dbg_atten_slp);
} }
void rtc_sleep_low_init(uint32_t slowclk_period) void rtc_sleep_low_init(uint32_t slowclk_period)

1
components/soc/esp32/include/soc/rtc.h
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@ -514,6 +514,7 @@ typedef struct rtc_sleep_config_s {
uint32_t lslp_meminf_pd : 1; //!< remove all peripheral force power up flags uint32_t lslp_meminf_pd : 1; //!< remove all peripheral force power up flags
uint32_t vddsdio_pd_en : 1; //!< power down VDDSDIO regulator uint32_t vddsdio_pd_en : 1; //!< power down VDDSDIO regulator
uint32_t xtal_fpu : 1; //!< keep main XTAL powered up in sleep uint32_t xtal_fpu : 1; //!< keep main XTAL powered up in sleep
uint32_t dbg_atten_slp : 2; //!< voltage parameter
} rtc_sleep_config_t; } rtc_sleep_config_t;
#define RTC_SLEEP_PD_DIG BIT(0) //!< Deep sleep (power down digital domain) #define RTC_SLEEP_PD_DIG BIT(0) //!< Deep sleep (power down digital domain)

1
components/soc/esp32/include/soc/rtc_cntl_reg.h
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@ -1070,6 +1070,7 @@
#define RTC_CNTL_DBG_ATTEN_V 0x3 #define RTC_CNTL_DBG_ATTEN_V 0x3
#define RTC_CNTL_DBG_ATTEN_S 24 #define RTC_CNTL_DBG_ATTEN_S 24
#define RTC_CNTL_DBG_ATTEN_DEFAULT 3 #define RTC_CNTL_DBG_ATTEN_DEFAULT 3
#define RTC_CNTL_DBG_ATTEN_NODROP 0
#define RTC_CNTL_REG (DR_REG_RTCCNTL_BASE + 0x7c) #define RTC_CNTL_REG (DR_REG_RTCCNTL_BASE + 0x7c)
/* RTC_CNTL_FORCE_PU : R/W ;bitpos:[31] ;default: 1'd1 ; */ /* RTC_CNTL_FORCE_PU : R/W ;bitpos:[31] ;default: 1'd1 ; */
/*description: RTC_REG force power up*/ /*description: RTC_REG force power up*/