From 77eb6b1397990582632855e3efd28cddc1ce8e2e Mon Sep 17 00:00:00 2001 From: Marius Vikhammer Date: Tue, 29 Dec 2020 11:28:27 +0800 Subject: [PATCH 1/9] System: add C3 root kconfig settings --- Kconfig | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/Kconfig b/Kconfig index 9b230774b6..0646ca29d2 100644 --- a/Kconfig +++ b/Kconfig @@ -58,11 +58,18 @@ mainmenu "Espressif IoT Development Framework Configuration" prompt "ESP32-S3 beta2" endchoice + config IDF_TARGET_ESP32C3 + bool + default "y" if IDF_TARGET="esp32c3" + select FREERTOS_UNICORE + select IDF_TARGET_ARCH_RISCV + config IDF_FIRMWARE_CHIP_ID hex default 0x0000 if IDF_TARGET_ESP32 default 0x0002 if IDF_TARGET_ESP32S2 default 0x0004 if IDF_TARGET_ESP32S3 + default 0x0005 if IDF_TARGET_ESP32C3 default 0xFFFF menu "SDK tool configuration" @@ -71,6 +78,8 @@ mainmenu "Espressif IoT Development Framework Configuration" default "xtensa-esp32-elf-" if IDF_TARGET_ESP32 default "xtensa-esp32s2-elf-" if IDF_TARGET_ESP32S2 default "xtensa-esp32s3-elf-" if IDF_TARGET_ESP32S3 + default "riscv32-esp-elf-" if IDF_TARGET_ESP32C3 + help The prefix/path that is used to call the toolchain. The default setting assumes a crosstool-ng gcc setup that is in your PATH. From a7683fc2563155bedb0df6e872bc5ed537d0748b Mon Sep 17 00:00:00 2001 From: Jakob Hasse Date: Thu, 26 Nov 2020 13:38:09 +0800 Subject: [PATCH 2/9] [system/tools]: gdbstub support C3 Closes IDF-1757 Closes IDF-2489 --- components/esp_gdbstub/CMakeLists.txt | 19 +++-- .../esp_gdbstub/esp32c3/gdbstub_esp32c3.c | 83 +++++++++++++++++++ .../esp_gdbstub/riscv/esp_gdbstub_arch.h | 34 ++++++++ components/esp_gdbstub/riscv/gdbstub_riscv.c | 60 ++++++++++++++ 4 files changed, 188 insertions(+), 8 deletions(-) create mode 100644 components/esp_gdbstub/esp32c3/gdbstub_esp32c3.c create mode 100644 components/esp_gdbstub/riscv/esp_gdbstub_arch.h create mode 100644 components/esp_gdbstub/riscv/gdbstub_riscv.c diff --git a/components/esp_gdbstub/CMakeLists.txt b/components/esp_gdbstub/CMakeLists.txt index 74213d20a0..0d64fc4465 100644 --- a/components/esp_gdbstub/CMakeLists.txt +++ b/components/esp_gdbstub/CMakeLists.txt @@ -1,13 +1,16 @@ idf_build_get_property(target IDF_TARGET) -set(esp_gdbstub_srcs "src/gdbstub.c" - "src/packet.c" - "${target}/gdbstub_${target}.c" - "xtensa/gdbstub_xtensa.c") - -idf_component_register(SRCS "${esp_gdbstub_srcs}" - INCLUDE_DIRS "include" "xtensa" "${target}" +idf_component_register(SRCS "src/gdbstub.c" "src/packet.c" + INCLUDE_DIRS "include" PRIV_INCLUDE_DIRS "private_include" LDFRAGMENTS "linker.lf" REQUIRES "freertos" - PRIV_REQUIRES "soc" "xtensa" "esp_rom") + PRIV_REQUIRES "soc" "esp_rom") + +if(CONFIG_IDF_TARGET_ARCH_XTENSA) + target_include_directories(${COMPONENT_LIB} PUBLIC "xtensa" "${target}") + target_sources(${COMPONENT_LIB} PRIVATE "xtensa/gdbstub_xtensa.c" "${target}/gdbstub_${target}.c") +elseif(CONFIG_IDF_TARGET_ARCH_RISCV) + target_include_directories(${COMPONENT_LIB} PUBLIC "riscv" "${target}") + target_sources(${COMPONENT_LIB} PRIVATE "riscv/gdbstub_riscv.c" "${target}/gdbstub_${target}.c") +endif() diff --git a/components/esp_gdbstub/esp32c3/gdbstub_esp32c3.c b/components/esp_gdbstub/esp32c3/gdbstub_esp32c3.c new file mode 100644 index 0000000000..93d3a6016d --- /dev/null +++ b/components/esp_gdbstub/esp32c3/gdbstub_esp32c3.c @@ -0,0 +1,83 @@ +// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include "soc/uart_periph.h" +#include "soc/gpio_periph.h" +#include "soc/soc.h" +#include "esp_gdbstub_common.h" +#include "sdkconfig.h" + +#define UART_NUM CONFIG_ESP_CONSOLE_UART_NUM + +#define GDBSTUB_MEM_REGION_COUNT 9 + +typedef struct { + intptr_t lower; + intptr_t upper; +} mem_bound_t; + +static const mem_bound_t mem_region_table [GDBSTUB_MEM_REGION_COUNT] = +{ + {SOC_DROM_LOW, SOC_DROM_HIGH}, + {SOC_IROM_LOW, SOC_IROM_HIGH}, + {SOC_IRAM_LOW, SOC_IRAM_HIGH}, + {SOC_DRAM_LOW, SOC_DRAM_HIGH}, + {SOC_IROM_MASK_LOW, SOC_IROM_MASK_HIGH}, + {SOC_DROM_MASK_LOW, SOC_DROM_MASK_HIGH}, + {SOC_RTC_IRAM_LOW, SOC_RTC_IRAM_HIGH}, + // RTC DRAM and RTC DATA are identical with RTC IRAM + {SOC_PERIPHERAL_LOW, SOC_PERIPHERAL_HIGH}, + {SOC_DEBUG_LOW, SOC_DEBUG_HIGH}, +}; + +static inline bool check_inside_valid_region(intptr_t addr) +{ + for (size_t i = 0; i < GDBSTUB_MEM_REGION_COUNT; i++) { + if (addr >= mem_region_table[i].lower && addr < mem_region_table[i].upper) { + return true; + } + } + return false; +} + +void esp_gdbstub_target_init() +{ +} + +int esp_gdbstub_getchar() +{ + while (REG_GET_FIELD(UART_STATUS_REG(UART_NUM), UART_RXFIFO_CNT) == 0) { + ; + } + return REG_READ(UART_FIFO_AHB_REG(UART_NUM)); +} + +void esp_gdbstub_putchar(int c) +{ + while (REG_GET_FIELD(UART_STATUS_REG(UART_NUM), UART_TXFIFO_CNT) >= 126) { + ; + } + REG_WRITE(UART_FIFO_AHB_REG(UART_NUM), c); +} + +int esp_gdbstub_readmem(intptr_t addr) +{ + if (!check_inside_valid_region(addr)) { + /* see esp_cpu_configure_region_protection */ + return -1; + } + uint32_t val_aligned = *(uint32_t *)(addr & (~3)); + uint32_t shift = (addr & 3) * 8; + return (val_aligned >> shift) & 0xff; +} diff --git a/components/esp_gdbstub/riscv/esp_gdbstub_arch.h b/components/esp_gdbstub/riscv/esp_gdbstub_arch.h new file mode 100644 index 0000000000..d7c3aca0e7 --- /dev/null +++ b/components/esp_gdbstub/riscv/esp_gdbstub_arch.h @@ -0,0 +1,34 @@ +// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once +#include +#include "riscv/rvruntime-frames.h" +#include "gdbstub_target_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + +typedef RvExcFrame esp_gdbstub_frame_t; + +/* GDB regfile structure, configuration dependent */ +typedef struct { + uint32_t x[32]; + uint32_t pc; +} esp_gdbstub_gdb_regfile_t; + +#ifdef __cplusplus +} +#endif diff --git a/components/esp_gdbstub/riscv/gdbstub_riscv.c b/components/esp_gdbstub/riscv/gdbstub_riscv.c new file mode 100644 index 0000000000..7cded48a34 --- /dev/null +++ b/components/esp_gdbstub/riscv/gdbstub_riscv.c @@ -0,0 +1,60 @@ +// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include +#include "esp_gdbstub.h" +#include "esp_gdbstub_common.h" +#include "soc/cpu.h" +#include "sdkconfig.h" +#include "freertos/FreeRTOS.h" +#include "freertos/task.h" + +static void init_regfile(esp_gdbstub_gdb_regfile_t *dst) +{ + memset(dst, 0, sizeof(*dst)); +} + +void esp_gdbstub_frame_to_regfile(const esp_gdbstub_frame_t *frame, esp_gdbstub_gdb_regfile_t *dst) +{ + init_regfile(dst); + dst->pc = frame->mepc; + + // We omit register x0 here since it's the zero register and always hard-wired to 0. + // See The RISC-V Instruction Set Manual Volume I: Unprivileged ISA Document Version 20191213 for more details. + memcpy(&(dst->x[1]), &frame->ra, sizeof(uint32_t) * 31); +} + +#ifdef CONFIG_ESP_GDBSTUB_SUPPORT_TASKS + +/* Represents FreeRTOS TCB structure */ +typedef struct { + uint8_t *top_of_stack; + /* Other members aren't needed */ +} dummy_tcb_t; + + +void esp_gdbstub_tcb_to_regfile(TaskHandle_t tcb, esp_gdbstub_gdb_regfile_t *dst) +{ + const dummy_tcb_t *dummy_tcb = (const dummy_tcb_t *) tcb; + + const RvExcFrame *frame = (RvExcFrame *) dummy_tcb->top_of_stack; + esp_gdbstub_frame_to_regfile(frame, dst); +} + +#endif // CONFIG_ESP_GDBSTUB_SUPPORT_TASKS + +int esp_gdbstub_get_signal(const esp_gdbstub_frame_t *frame) +{ + return 5; // SIGTRAP, see IDF-2490 +} From 34584692043227e234641da2cb1d81f9d44de7f1 Mon Sep 17 00:00:00 2001 From: Marius Vikhammer Date: Wed, 30 Dec 2020 09:31:16 +0800 Subject: [PATCH 3/9] newlib: Update esp32c3 ROM support, use single init function --- components/esp_system/startup.c | 3 +- components/newlib/CMakeLists.txt | 4 +- .../newlib/{syscall_table.c => newlib_init.c} | 46 +++++++++++++++++-- .../newlib/platform_include/esp_newlib.h | 8 +++- components/newlib/test/test_newlib.c | 2 +- tools/ci/test_build_system.sh | 4 +- tools/ci/test_build_system_cmake.sh | 4 +- 7 files changed, 57 insertions(+), 14 deletions(-) rename components/newlib/{syscall_table.c => newlib_init.c} (64%) diff --git a/components/esp_system/startup.c b/components/esp_system/startup.c index 0c4ad2d685..d8f4d039d5 100644 --- a/components/esp_system/startup.c +++ b/components/esp_system/startup.c @@ -198,8 +198,7 @@ static void do_core_init(void) app CPU, and when that is not up yet, the memory will be inaccessible and heap_caps_init may fail initializing it properly. */ heap_caps_init(); - esp_setup_syscall_table(); - esp_newlib_locks_init(); + esp_newlib_init(); esp_newlib_time_init(); if (g_spiram_ok) { diff --git a/components/newlib/CMakeLists.txt b/components/newlib/CMakeLists.txt index 670be02dbc..0f869ed475 100644 --- a/components/newlib/CMakeLists.txt +++ b/components/newlib/CMakeLists.txt @@ -6,7 +6,7 @@ set(srcs "pthread.c" "random.c" "reent_init.c" - "syscall_table.c" + "newlib_init.c" "syscalls.c" "termios.c" "time.c") @@ -30,7 +30,7 @@ target_link_libraries(${COMPONENT_LIB} INTERFACE c m gcc "$ #include #include "esp_newlib.h" +#include "esp_attr.h" #include "sdkconfig.h" #include "soc/soc_caps.h" @@ -32,6 +33,8 @@ #include "esp32s2/rom/libc_stubs.h" #elif CONFIG_IDF_TARGET_ESP32S3 #include "esp32s3/rom/libc_stubs.h" +#elif CONFIG_IDF_TARGET_ESP32C3 +#include "esp32c3/rom/libc_stubs.h" #endif static struct _reent s_reent; @@ -78,6 +81,18 @@ static struct syscall_stub_table s_stub_table = { ._write_r = (int (*)(struct _reent *r, int, const void *, int)) &_write_r, ._lseek_r = (int (*)(struct _reent *r, int, int, int)) &_lseek_r, ._read_r = (int (*)(struct _reent *r, int, void *, int)) &_read_r, +#if _RETARGETABLE_LOCKING /* TODO: only if RETARGETABLE LOCKING IS IN ROM */ + ._retarget_lock_init = &__retarget_lock_init, + ._retarget_lock_init_recursive = &__retarget_lock_init_recursive, + ._retarget_lock_close = &__retarget_lock_close, + ._retarget_lock_close_recursive = &__retarget_lock_close_recursive, + ._retarget_lock_acquire = &__retarget_lock_acquire, + ._retarget_lock_acquire_recursive = &__retarget_lock_acquire_recursive, + ._retarget_lock_try_acquire = &__retarget_lock_try_acquire, + ._retarget_lock_try_acquire_recursive = &__retarget_lock_try_acquire_recursive, + ._retarget_lock_release = &__retarget_lock_release, + ._retarget_lock_release_recursive = &__retarget_lock_release_recursive, +#else ._lock_init = &_lock_init, ._lock_init_recursive = &_lock_init_recursive, ._lock_close = &_lock_close, @@ -88,6 +103,7 @@ static struct syscall_stub_table s_stub_table = { ._lock_try_acquire_recursive = &_lock_try_acquire_recursive, ._lock_release = &_lock_release, ._lock_release_recursive = &_lock_release_recursive, +#endif #ifdef CONFIG_NEWLIB_NANO_FORMAT ._printf_float = &_printf_float, ._scanf_float = &_scanf_float, @@ -95,15 +111,39 @@ static struct syscall_stub_table s_stub_table = { ._printf_float = NULL, ._scanf_float = NULL, #endif +#ifdef CONFIG_IDF_TARGET_ESP32C3 + /* TODO: mark that this assert failed in ROM, to avoid confusion between IDF & ROM + assertion failures (as function names & source file names will be similar) + */ + .__assert_func = __assert_func, + + /* We don't expect either ROM code or IDF to ever call __sinit, so it's implemented as abort() for now. + + esp_reent_init() does this job inside IDF. + + Kept in the syscall table in case we find a need for it later. + */ + .__sinit = (void *)abort, + ._cleanup_r = &_cleanup_r, +#endif }; -void esp_setup_syscall_table(void) +void esp_newlib_init(void) { +#if CONFIG_IDF_TARGET_ESP32 + syscall_table_ptr_pro = syscall_table_ptr_app = &s_stub_table; +#elif CONFIG_IDF_TARGET_ESP32S2 syscall_table_ptr_pro = &s_stub_table; -#if SOC_CPU_CORES_NUM == 2 - syscall_table_ptr_app = &s_stub_table; +#elif CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3 + syscall_table_ptr = &s_stub_table; #endif + _GLOBAL_REENT = &s_reent; + environ = malloc(sizeof(char*)); environ[0] = NULL; + + esp_newlib_locks_init(); } + +void esp_setup_newlib_syscalls(void) __attribute__((alias("esp_newlib_init"))); diff --git a/components/newlib/platform_include/esp_newlib.h b/components/newlib/platform_include/esp_newlib.h index b4aa54e41a..fe06a33486 100644 --- a/components/newlib/platform_include/esp_newlib.h +++ b/components/newlib/platform_include/esp_newlib.h @@ -36,12 +36,16 @@ void esp_reent_init(struct _reent* r); void esp_reent_cleanup(void); /** - * Function which sets up syscall table used by newlib functions in ROM. + * Function which sets up newlib in ROM for use with ESP-IDF + * + * Includes defining the syscall table, setting up any common locks, etc. * * Called from the startup code, not intended to be called from application * code. */ -void esp_setup_syscall_table(void); +void esp_newlib_init(void); + +void esp_setup_syscall_table(void) __attribute__((deprecated("Please call esp_newlib_init() in newer code"))); /** * Update current microsecond time from RTC diff --git a/components/newlib/test/test_newlib.c b/components/newlib/test/test_newlib.c index 69d31bfe60..adca8f9ed3 100644 --- a/components/newlib/test/test_newlib.c +++ b/components/newlib/test/test_newlib.c @@ -141,7 +141,7 @@ TEST_CASE("check if ROM or Flash is used for functions", "[newlib]") #if defined(CONFIG_IDF_TARGET_ESP32) && !defined(CONFIG_SPIRAM) TEST_ASSERT(fn_in_rom(atoi)); TEST_ASSERT(fn_in_rom(strtol)); -#elif defined(CONFIG_IDF_TARGET_ESP32S3) || defined(CONFIG_IDF_TARGET_ESP32C3) +#elif defined(CONFIG_IDF_TARGET_ESP32C3) || defined(CONFIG_IDF_TARGET_ESP32C3) /* S3 and C3 always use these from ROM */ TEST_ASSERT(fn_in_rom(atoi)); TEST_ASSERT(fn_in_rom(strtol)); diff --git a/tools/ci/test_build_system.sh b/tools/ci/test_build_system.sh index 780bda49f6..8ffffbd994 100755 --- a/tools/ci/test_build_system.sh +++ b/tools/ci/test_build_system.sh @@ -181,7 +181,7 @@ function run_tests() assert_rebuilt esp32/component_project_vars.mk # pick one each of .c, .cpp, .S that #includes sdkconfig.h # and therefore should rebuild - assert_rebuilt newlib/syscall_table.o + assert_rebuilt newlib/newlib_init.o assert_rebuilt nvs_flash/src/nvs_api.o assert_rebuilt freertos/port/xtensa/xtensa_vectors.o @@ -191,7 +191,7 @@ function run_tests() touch Makefile make # similar to previous test - assert_rebuilt newlib/syscall_table.o + assert_rebuilt newlib/newlib_init.o assert_rebuilt nvs_flash/src/nvs_api.o assert_rebuilt freertos/port/xtensa/xtensa_vectors.o diff --git a/tools/ci/test_build_system_cmake.sh b/tools/ci/test_build_system_cmake.sh index 10794abcb6..2d35ee50b3 100755 --- a/tools/ci/test_build_system_cmake.sh +++ b/tools/ci/test_build_system_cmake.sh @@ -225,7 +225,7 @@ function run_tests() assert_rebuilt config/sdkconfig.h # pick one each of .c, .cpp, .S that #includes sdkconfig.h # and therefore should rebuild - assert_rebuilt esp-idf/newlib/CMakeFiles/${IDF_COMPONENT_PREFIX}_newlib.dir/syscall_table.c.obj + assert_rebuilt esp-idf/newlib/CMakeFiles/${IDF_COMPONENT_PREFIX}_newlib.dir/newlib_init.c.obj assert_rebuilt esp-idf/nvs_flash/CMakeFiles/${IDF_COMPONENT_PREFIX}_nvs_flash.dir/src/nvs_api.cpp.obj assert_rebuilt esp-idf/freertos/CMakeFiles/${IDF_COMPONENT_PREFIX}_freertos.dir/port/xtensa/xtensa_vectors.S.obj mv sdkconfig.bak sdkconfig @@ -240,7 +240,7 @@ function run_tests() idf.py build || failure "Build failed" mv CMakeLists.bak CMakeLists.txt # similar to previous test - assert_rebuilt esp-idf/newlib/CMakeFiles/${IDF_COMPONENT_PREFIX}_newlib.dir/syscall_table.c.obj + assert_rebuilt esp-idf/newlib/CMakeFiles/${IDF_COMPONENT_PREFIX}_newlib.dir/newlib_init.c.obj assert_rebuilt esp-idf/nvs_flash/CMakeFiles/${IDF_COMPONENT_PREFIX}_nvs_flash.dir/src/nvs_api.cpp.obj assert_rebuilt esp-idf/freertos/CMakeFiles/${IDF_COMPONENT_PREFIX}_freertos.dir/port/xtensa/xtensa_vectors.S.obj mv sdkconfig.bak sdkconfig From 0301c66bf0dbfe9c46f0048d084e770473393f36 Mon Sep 17 00:00:00 2001 From: Marius Vikhammer Date: Tue, 29 Dec 2020 12:17:54 +0800 Subject: [PATCH 4/9] esp32c3: Disable components that are not yet supported --- components/esp_wifi/CMakeLists.txt | 8 ++++++++ components/freemodbus/CMakeLists.txt | 5 +++++ components/perfmon/CMakeLists.txt | 5 +++++ 3 files changed, 18 insertions(+) diff --git a/components/esp_wifi/CMakeLists.txt b/components/esp_wifi/CMakeLists.txt index 0fe1899f3b..62a6dd7f00 100644 --- a/components/esp_wifi/CMakeLists.txt +++ b/components/esp_wifi/CMakeLists.txt @@ -8,6 +8,14 @@ if(${idf_target} STREQUAL "esp32s3") return() endif() +# remove these when wifi support is ready on esp32-c3 +if(${idf_target} STREQUAL "esp32c3") + idf_component_register(INCLUDE_DIRS "include" + REQUIRES esp_event + PRIV_REQUIRES wpa_supplicant nvs_flash esp_netif) + return() +endif() + if(CONFIG_ESP32_NO_BLOBS OR CONFIG_ESP32S2_NO_BLOBS) set(link_binary_libs 0) set(ldfragments) diff --git a/components/freemodbus/CMakeLists.txt b/components/freemodbus/CMakeLists.txt index 43765eab94..3af4831360 100644 --- a/components/freemodbus/CMakeLists.txt +++ b/components/freemodbus/CMakeLists.txt @@ -1,3 +1,8 @@ +idf_build_get_property(target IDF_TARGET) +if(${target} STREQUAL "esp32c3") + return() # TODO ESP32-C3 IDF-2173 +endif() + # The following five lines of boilerplate have to be in your project's # CMakeLists in this exact order for cmake to work correctly set(srcs diff --git a/components/perfmon/CMakeLists.txt b/components/perfmon/CMakeLists.txt index 3f2efc3e92..bf463e4f73 100644 --- a/components/perfmon/CMakeLists.txt +++ b/components/perfmon/CMakeLists.txt @@ -1,3 +1,8 @@ +idf_build_get_property(target IDF_TARGET) +if(${target} STREQUAL "esp32c3") + return() +endif() + set(xtensa_perfmon_srcs "xtensa_perfmon_access.c" "xtensa_perfmon_apis.c" "xtensa_perfmon_masks.c") From 68608f804c51e41ace6f73c94224d57cdb2df7d2 Mon Sep 17 00:00:00 2001 From: Marius Vikhammer Date: Tue, 29 Dec 2020 13:20:24 +0800 Subject: [PATCH 5/9] esp32c3: Misc fixes needed to build & run --- .../src/esp32c3/bootloader_esp32c3.c | 3 +- components/driver/CMakeLists.txt | 3 +- components/esp_common/src/task_wdt.c | 7 +- .../esp32c3/gdbstub_target_config.h | 15 + components/esp_pm/CMakeLists.txt | 8 + components/esp_system/CMakeLists.txt | 1 - components/esp_system/intr_alloc.c | 7 + components/esp_system/sleep_modes.c | 4 +- components/hal/CMakeLists.txt | 8 +- components/hal/esp32c3/adc_hal.c | 2 + components/hal/esp32c3/include/hal/i2s_ll.h | 912 ++++++++++++++++++ components/soc/esp32c3/CMakeLists.txt | 1 - components/ulp/CMakeLists.txt | 18 +- components/wifi_provisioning/CMakeLists.txt | 5 + 14 files changed, 976 insertions(+), 18 deletions(-) create mode 100644 components/esp_gdbstub/esp32c3/gdbstub_target_config.h create mode 100644 components/hal/esp32c3/include/hal/i2s_ll.h diff --git a/components/bootloader_support/src/esp32c3/bootloader_esp32c3.c b/components/bootloader_support/src/esp32c3/bootloader_esp32c3.c index e3129c84e8..c3eec1e440 100644 --- a/components/bootloader_support/src/esp32c3/bootloader_esp32c3.c +++ b/components/bootloader_support/src/esp32c3/bootloader_esp32c3.c @@ -44,6 +44,7 @@ #include "bootloader_mem.h" #include "regi2c_ctrl.h" #include "bootloader_console.h" +#include "bootloader_flash_priv.h" static const char *TAG = "boot.esp32c3"; @@ -226,7 +227,7 @@ static void wdt_reset_cpu0_info_enable(void) static void wdt_reset_info_dump(int cpu) { // TODO ESP32-C3 IDF-2118 - ESP_LOGE(TAG, "WDT reset info dump is not supported yet", cpu_name); + ESP_LOGE(TAG, "WDT reset info dump is not supported yet"); } static void bootloader_check_wdt_reset(void) diff --git a/components/driver/CMakeLists.txt b/components/driver/CMakeLists.txt index 83d232bf6e..2c37813d1a 100644 --- a/components/driver/CMakeLists.txt +++ b/components/driver/CMakeLists.txt @@ -66,8 +66,7 @@ endif() if(IDF_TARGET STREQUAL "esp32c3") list(APPEND srcs "spi_slave_hd.c" - "esp32c3/adc.c" - "esp32c3/rtc_tempsensor.c") + "esp32c3/adc.c") endif() idf_component_register(SRCS "${srcs}" diff --git a/components/esp_common/src/task_wdt.c b/components/esp_common/src/task_wdt.c index f2b3957292..5c73e20774 100644 --- a/components/esp_common/src/task_wdt.c +++ b/components/esp_common/src/task_wdt.c @@ -181,15 +181,18 @@ static void task_wdt_isr(void *arg) esp_reset_reason_set_hint(ESP_RST_TASK_WDT); abort(); } else { + +#if !CONFIG_IDF_TARGET_ESP32C3 // TODO ESP32-C3 add backtrace printing support IDF-2285 int current_core = xPortGetCoreID(); //Print backtrace of current core ESP_EARLY_LOGE(TAG, "Print CPU %d (current core) backtrace", current_core); esp_backtrace_print(100); - #if !CONFIG_FREERTOS_UNICORE +#if !CONFIG_FREERTOS_UNICORE //Print backtrace of other core ESP_EARLY_LOGE(TAG, "Print CPU %d backtrace", !current_core); esp_crosscore_int_send_print_backtrace(!current_core); - #endif +#endif +#endif } portEXIT_CRITICAL_ISR(&twdt_spinlock); diff --git a/components/esp_gdbstub/esp32c3/gdbstub_target_config.h b/components/esp_gdbstub/esp32c3/gdbstub_target_config.h new file mode 100644 index 0000000000..527dc5e2da --- /dev/null +++ b/components/esp_gdbstub/esp32c3/gdbstub_target_config.h @@ -0,0 +1,15 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once diff --git a/components/esp_pm/CMakeLists.txt b/components/esp_pm/CMakeLists.txt index b802986ec1..f57c21df69 100644 --- a/components/esp_pm/CMakeLists.txt +++ b/components/esp_pm/CMakeLists.txt @@ -1,3 +1,11 @@ +idf_build_get_property(target IDF_TARGET) +if(${target} STREQUAL "esp32c3") + # TODO ESP32-C3 IDF-2107 - include the headers to avoid compile errors, no functions available to link... + idf_component_register(SRCS "pm_impl_riscv_temp.c" INCLUDE_DIRS include) + return() +endif() + + idf_component_register(SRCS "pm_locks.c" "pm_trace.c" "pm_impl.c" INCLUDE_DIRS include LDFRAGMENTS linker.lf) diff --git a/components/esp_system/CMakeLists.txt b/components/esp_system/CMakeLists.txt index cee7ad3301..3342896fa6 100644 --- a/components/esp_system/CMakeLists.txt +++ b/components/esp_system/CMakeLists.txt @@ -3,7 +3,6 @@ idf_component_register(SRCS "intr_alloc.c" "panic.c" "system_api.c" "startup.c" - "sleep_modes.c" "system_time.c" INCLUDE_DIRS include PRIV_REQUIRES spi_flash diff --git a/components/esp_system/intr_alloc.c b/components/esp_system/intr_alloc.c index 603138b23b..d440ca9f24 100644 --- a/components/esp_system/intr_alloc.c +++ b/components/esp_system/intr_alloc.c @@ -551,7 +551,14 @@ esp_err_t esp_intr_alloc_intrstatus(int source, int flags, uint32_t intrstatusre interrupt_controller_hal_set_int_handler(intr, handler, arg); #endif } +#ifdef __XTENSA__ // TODO ESP32-C3 IDF-2126 if (flags&ESP_INTR_FLAG_EDGE) xthal_set_intclear(1 << intr); +#else + if (flags & ESP_INTR_FLAG_EDGE) { + ESP_INTR_DISABLE(intr); + esprv_intc_int_set_priority(intr, 0); + } +#endif vd->source=source; } if (flags&ESP_INTR_FLAG_IRAM) { diff --git a/components/esp_system/sleep_modes.c b/components/esp_system/sleep_modes.c index c01bec714f..3aa8b66460 100644 --- a/components/esp_system/sleep_modes.c +++ b/components/esp_system/sleep_modes.c @@ -26,8 +26,6 @@ #include "esp_timer.h" #include "freertos/FreeRTOS.h" #include "freertos/task.h" -#include "driver/touch_sensor.h" -#include "driver/touch_sensor_common.h" #include "soc/soc_caps.h" #include "driver/rtc_io.h" #include "hal/rtc_io_hal.h" @@ -43,6 +41,8 @@ #include "hal/uart_hal.h" #if SOC_TOUCH_SENSOR_NUM > 0 #include "hal/touch_sensor_hal.h" +#include "driver/touch_sensor.h" +#include "driver/touch_sensor_common.h" #endif #include "hal/clk_gate_ll.h" diff --git a/components/hal/CMakeLists.txt b/components/hal/CMakeLists.txt index 2c7fff2c4c..e43a4c44f8 100644 --- a/components/hal/CMakeLists.txt +++ b/components/hal/CMakeLists.txt @@ -29,8 +29,6 @@ if(NOT BOOTLOADER_BUILD) "interrupt_controller_hal.c" "sha_hal.c" "aes_hal.c" - "twai_hal.c" - "twai_hal_iram.c" "${target}/interrupt_descriptor_table.c") if(${target} STREQUAL "esp32") @@ -41,6 +39,8 @@ if(NOT BOOTLOADER_BUILD) "pcnt_hal.c" "sdio_slave_hal.c" "touch_sensor_hal.c" + "twai_hal.c" + "twai_hal_iram.c" "esp32/adc_hal.c" "esp32/brownout_hal.c" "esp32/touch_sensor_hal.c") @@ -57,6 +57,8 @@ if(NOT BOOTLOADER_BUILD) "spi_flash_hal_gpspi.c" "spi_slave_hd_hal.c" "touch_sensor_hal.c" + "twai_hal.c" + "twai_hal_iram.c" "esp32s2/adc_hal.c" "esp32s2/brownout_hal.c" "esp32s2/cp_dma_hal.c" @@ -74,6 +76,8 @@ if(NOT BOOTLOADER_BUILD) "spi_flash_hal_gpspi.c" "spi_slave_hd_hal.c" "touch_sensor_hal.c" + "twai_hal.c" + "twai_hal_iram.c" "esp32s3/brownout_hal.c" "esp32s3/systimer_hal.c" "esp32s3/touch_sensor_hal.c") diff --git a/components/hal/esp32c3/adc_hal.c b/components/hal/esp32c3/adc_hal.c index 1b417f33e8..b000a6c9d8 100644 --- a/components/hal/esp32c3/adc_hal.c +++ b/components/hal/esp32c3/adc_hal.c @@ -33,6 +33,8 @@ void adc_hal_digi_deinit(void) adc_hal_deinit(); } +uint32_t adc_hal_calibration(adc_ll_num_t adc_n, adc_channel_t channel, adc_atten_t atten, bool internal_gnd, bool force_cal); + static inline void adc_set_init_code(adc_ll_num_t adc_n, adc_channel_t channel, adc_atten_t atten) { uint32_t cal_val = adc_hal_calibration(adc_n, channel, atten, true, false); diff --git a/components/hal/esp32c3/include/hal/i2s_ll.h b/components/hal/esp32c3/include/hal/i2s_ll.h new file mode 100644 index 0000000000..87d0886d0c --- /dev/null +++ b/components/hal/esp32c3/include/hal/i2s_ll.h @@ -0,0 +1,912 @@ +// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +/******************************************************************************* + * NOTICE + * The hal is not public api, don't use in application code. + * See readme.md in soc/include/hal/readme.md + ******************************************************************************/ + +// The LL layer for ESP32-S3 I2S register operations + +#pragma once + +#include +#include +#include "soc/i2s_periph.h" +#include "hal/i2s_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +// Get I2S hardware instance with giving i2s num +#define I2S_LL_GET_HW(num) (((num) == 0) ? (&I2S0) : NULL) + +#define I2S_INTR_IN_SUC_EOF BIT(9) +#define I2S_INTR_OUT_EOF BIT(12) +#define I2S_INTR_IN_DSCR_ERR BIT(13) +#define I2S_INTR_OUT_DSCR_ERR BIT(14) +#define I2S_INTR_MAX (0xFFFFFFFF) + +/** + * @brief Reset rx fifo + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_reset_rx_fifo(i2s_dev_t *hw) +{ + abort(); // FIXME + // hw->conf.rx_fifo_reset = 1; + // hw->conf.rx_fifo_reset = 0; +} + +/** + * @brief Reset tx fifo + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_reset_tx_fifo(i2s_dev_t *hw) +{ + abort(); // FIXME + // hw->conf.tx_fifo_reset = 1; + // hw->conf.tx_fifo_reset = 0; +} + +/** + * @brief Enable rx interrupt + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_enable_rx_intr(i2s_dev_t *hw) +{ + abort(); // FIXME + // hw->int_ena.in_suc_eof = 1; + // hw->int_ena.in_dscr_err = 1; +} + +/** + * @brief Disable rx interrupt + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_disable_rx_intr(i2s_dev_t *hw) +{ + abort(); // FIXME + // hw->int_ena.in_suc_eof = 0; + // hw->int_ena.in_dscr_err = 0; +} + +/** + * @brief Disable tx interrupt + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_disable_tx_intr(i2s_dev_t *hw) +{ + abort(); // FIXME + // hw->int_ena.out_eof = 0; + // hw->int_ena.out_dscr_err = 0; +} + +/** + * @brief Enable tx interrupt + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_enable_tx_intr(i2s_dev_t *hw) +{ + abort(); // FIXME + // hw->int_ena.out_eof = 1; + // hw->int_ena.out_dscr_err = 1; +} + +/** + * @brief Reset dma in + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_reset_dma_in(i2s_dev_t *hw) +{ + abort(); // FIXME + // hw->lc_conf.in_rst = 1; + // hw->lc_conf.in_rst = 0; +} + +/** + * @brief Reset dma out + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_reset_dma_out(i2s_dev_t *hw) +{ + abort(); // FIXME + // hw->lc_conf.out_rst = 1; + // hw->lc_conf.out_rst = 0; +} + +/** + * @brief Reset tx + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_reset_tx(i2s_dev_t *hw) +{ + abort(); // FIXME + // hw->conf.tx_reset = 1; + // hw->conf.tx_reset = 0; +} + +/** + * @brief Reset rx + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_reset_rx(i2s_dev_t *hw) +{ + abort(); // FIXME + // hw->conf.rx_reset = 1; + // hw->conf.rx_reset = 0; +} + +/** + * @brief Start out link + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_start_out_link(i2s_dev_t *hw) +{ + abort(); // FIXME + // hw->out_link.start = 1; +} + +/** + * @brief Start tx + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_start_tx(i2s_dev_t *hw) +{ + abort(); // FIXME + // hw->conf.tx_start = 1; +} + +/** + * @brief Start in link + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_start_in_link(i2s_dev_t *hw) +{ + abort(); // FIXME + // hw->in_link.start = 1; +} + +/** + * @brief Start rx + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_start_rx(i2s_dev_t *hw) +{ + abort(); // FIXME + // hw->conf.rx_start = 1; +} + +/** + * @brief Stop out link + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_stop_out_link(i2s_dev_t *hw) +{ + abort(); // FIXME + // hw->out_link.stop = 1; +} + +/** + * @brief Stop tx + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_stop_tx(i2s_dev_t *hw) +{ + abort(); // FIXME + // hw->conf.tx_start = 0; +} + +/** + * @brief Stop in link + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_stop_in_link(i2s_dev_t *hw) +{ + abort(); // FIXME + // hw->in_link.stop = 1; +} + +/** + * @brief Stop rx + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_stop_rx(i2s_dev_t *hw) +{ + abort(); // FIXME + // hw->conf.rx_start = 0; +} + +/** + * @brief Enable dma + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_enable_dma(i2s_dev_t *hw) +{ + abort(); // FIXME + // //Enable and configure DMA + // typeof(hw->lc_conf) lc_conf; + // lc_conf.val = 0; + // lc_conf.out_eof_mode = 1; + // hw->lc_conf.val = lc_conf.val; +} + +/** + * @brief Get I2S interrupt status + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to get interrupt status + */ +static inline void i2s_ll_get_intr_status(i2s_dev_t *hw, uint32_t *val) +{ + abort(); // FIXME + // *val = hw->int_st.val; +} + +/** + * @brief Clear I2S interrupt status + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to clear interrupt status + */ +static inline void i2s_ll_clear_intr_status(i2s_dev_t *hw, uint32_t val) +{ + abort(); // FIXME + // hw->int_clr.val = val; +} + +/** + * @brief Get I2S out eof des address + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to get out eof des address + */ +static inline void i2s_ll_get_out_eof_des_addr(i2s_dev_t *hw, uint32_t *val) +{ + abort(); // FIXME + // *val = hw->out_eof_des_addr; +} + +/** + * @brief Get I2S in eof des address + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to get in eof des address + */ +static inline void i2s_ll_get_in_eof_des_addr(i2s_dev_t *hw, uint32_t *val) +{ + abort(); // FIXME + // *val = hw->in_eof_des_addr; +} + +/** + * @brief Get I2S tx fifo mode + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to get tx fifo mode + */ +static inline void i2s_ll_get_tx_fifo_mod(i2s_dev_t *hw, uint32_t *val) +{ + abort(); // FIXME + // *val = hw->fifo_conf.tx_fifo_mod; +} + +/** + * @brief Set I2S tx fifo mode + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set tx fifo mode + */ +static inline void i2s_ll_set_tx_fifo_mod(i2s_dev_t *hw, uint32_t val) +{ + abort(); // FIXME + // hw->fifo_conf.tx_fifo_mod = val; +} + +/** + * @brief Get I2S rx fifo mode + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to get rx fifo mode + */ +static inline void i2s_ll_get_rx_fifo_mod(i2s_dev_t *hw, uint32_t *val) +{ + abort(); // FIXME + // *val = hw->fifo_conf.rx_fifo_mod; +} + +/** + * @brief Set I2S rx fifo mode + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set rx fifo mode + */ +static inline void i2s_ll_set_rx_fifo_mod(i2s_dev_t *hw, uint32_t val) +{ + abort(); // FIXME + // hw->fifo_conf.rx_fifo_mod = val; +} + +/** + * @brief Set I2S tx chan mode + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set tx chan mode + */ +static inline void i2s_ll_set_tx_chan_mod(i2s_dev_t *hw, uint32_t val) +{ + abort(); // FIXME + // hw->conf_chan.tx_chan_mod = val; +} + +/** + * @brief Set I2S rx chan mode + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set rx chan mode + */ +static inline void i2s_ll_set_rx_chan_mod(i2s_dev_t *hw, uint32_t val) +{ + abort(); // FIXME + // hw->conf_chan.rx_chan_mod = val; +} + +/** + * @brief Set I2S out link address + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set out link address + */ +static inline void i2s_ll_set_out_link_addr(i2s_dev_t *hw, uint32_t val) +{ + abort(); // FIXME + // hw->out_link.addr = val; +} + +/** + * @brief Set I2S in link address + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set in link address + */ +static inline void i2s_ll_set_in_link_addr(i2s_dev_t *hw, uint32_t val) +{ + abort(); // FIXME + // hw->in_link.addr = val; +} + +/** + * @brief Set I2S rx eof num + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set rx eof num + */ +static inline void i2s_ll_set_rx_eof_num(i2s_dev_t *hw, uint32_t val) +{ + abort(); // FIXME + // hw->rx_eof_num = val; +} + +/** + * @brief Get I2S tx pdm fp + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to get tx pdm fp + */ +static inline void i2s_ll_get_tx_pdm_fp(i2s_dev_t *hw, uint32_t *val) +{ + abort(); // FIXME + // *val = hw->pdm_freq_conf.tx_pdm_fp; +} + +/** + * @brief Get I2S tx pdm fs + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to get tx pdm fs + */ +static inline void i2s_ll_get_tx_pdm_fs(i2s_dev_t *hw, uint32_t *val) +{ + abort(); // FIXME + // *val = hw->pdm_freq_conf.tx_pdm_fs; +} + +/** + * @brief Set I2S tx pdm fp + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set tx pdm fp + */ +static inline void i2s_ll_set_tx_pdm_fp(i2s_dev_t *hw, uint32_t val) +{ + abort(); // FIXME + // hw->pdm_freq_conf.tx_pdm_fp = val; +} + +/** + * @brief Set I2S tx pdm fs + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set tx pdm fs + */ +static inline void i2s_ll_set_tx_pdm_fs(i2s_dev_t *hw, uint32_t val) +{ + abort(); // FIXME + // hw->pdm_freq_conf.tx_pdm_fs = val; +} + +/** + * @brief Get I2S rx sinc dsr 16 en + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to get rx sinc dsr 16 en + */ +static inline void i2s_ll_get_rx_sinc_dsr_16_en(i2s_dev_t *hw, bool *val) +{ + abort(); // FIXME + // *val = hw->pdm_conf.rx_sinc_dsr_16_en; +} + +/** + * @brief Set I2S clkm div num + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set clkm div num + */ +static inline void i2s_ll_set_clkm_div_num(i2s_dev_t *hw, uint32_t val) +{ + abort(); // FIXME + // hw->clkm_conf.clkm_div_num = val; +} + +/** + * @brief Set I2S clkm div b + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set clkm div b + */ +static inline void i2s_ll_set_clkm_div_b(i2s_dev_t *hw, uint32_t val) +{ + abort(); // FIXME + // hw->clkm_conf.clkm_div_b = val; +} + +/** + * @brief Set I2S clkm div a + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set clkm div a + */ +static inline void i2s_ll_set_clkm_div_a(i2s_dev_t *hw, uint32_t val) +{ + abort(); // FIXME + // hw->clkm_conf.clkm_div_a = val; +} + +/** + * @brief Set I2S tx bck div num + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set tx bck div num + */ +static inline void i2s_ll_set_tx_bck_div_num(i2s_dev_t *hw, uint32_t val) +{ + abort(); // FIXME + // hw->sample_rate_conf.tx_bck_div_num = val; +} + +/** + * @brief Set I2S rx bck div num + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set rx bck div num + */ +static inline void i2s_ll_set_rx_bck_div_num(i2s_dev_t *hw, uint32_t val) +{ + abort(); // FIXME + // hw->sample_rate_conf.rx_bck_div_num = val; +} + +/** + * @brief Set I2S clk sel + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set clk sel + */ +static inline void i2s_ll_set_clk_sel(i2s_dev_t *hw, uint32_t val) +{ + abort(); // FIXME + // hw->clkm_conf.clk_sel = (val == 1) ? 1 : 2; +} + +/** + * @brief Set I2S tx bits mod + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set tx bits mod + */ +static inline void i2s_ll_set_tx_bits_mod(i2s_dev_t *hw, uint32_t val) +{ + abort(); // FIXME + // hw->sample_rate_conf.tx_bits_mod = val; +} + +/** + * @brief Set I2S rx bits mod + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set rx bits mod + */ +static inline void i2s_ll_set_rx_bits_mod(i2s_dev_t *hw, uint32_t val) +{ + abort(); // FIXME + // hw->sample_rate_conf.rx_bits_mod = val; +} + +/** + * @brief Set I2S rx sinc dsr 16 en + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set rx sinc dsr 16 en + */ +static inline void i2s_ll_set_rx_sinc_dsr_16_en(i2s_dev_t *hw, bool val) +{ + abort(); // FIXME + // hw->pdm_conf.rx_sinc_dsr_16_en = val; +} + +/** + * @brief Set I2S dscr en + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set dscr en + */ +static inline void i2s_ll_set_dscr_en(i2s_dev_t *hw, bool val) +{ + abort(); // FIXME + // hw->fifo_conf.dscr_en = val; +} + +/** + * @brief Set I2S lcd en + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set lcd en + */ +static inline void i2s_ll_set_lcd_en(i2s_dev_t *hw, bool val) +{ + abort(); // FIXME + // hw->conf2.lcd_en = val; +} + +/** + * @brief Set I2S camera en + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set camera en + */ +static inline void i2s_ll_set_camera_en(i2s_dev_t *hw, bool val) +{ + abort(); // FIXME + // hw->conf2.camera_en = val; +} + +/** + * @brief Set I2S pcm2pdm conv en + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set pcm2pdm conv en + */ +static inline void i2s_ll_set_pcm2pdm_conv_en(i2s_dev_t *hw, bool val) +{ + abort(); // FIXME + // hw->pdm_conf.pcm2pdm_conv_en = val; +} + +/** + * @brief Set I2S TX to MSB Alignment Standard + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_set_tx_format_msb_align(i2s_dev_t *hw) +{ +} + + +static inline void i2s_ll_set_rx_format_msb_align(i2s_dev_t *hw) +{ +} + +/** + * @brief Set I2S TX to PCM long standard + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_set_tx_pcm_long(i2s_dev_t *hw) +{ +} + +/** + * @brief Set I2S RX to PCM long standard + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_set_rx_pcm_long(i2s_dev_t *hw) +{ +} + +/** + * @brief Set I2S RX to PCM short standard + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_set_rx_pcm_short(i2s_dev_t *hw) +{ +} + +/** + * @brief Set I2S RX to philip standard + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_set_rx_format_philip(i2s_dev_t *hw) +{ +} + +/** + * @brief Set I2S TX to PCM short standard + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_set_tx_pcm_short(i2s_dev_t *hw) +{ +} + +/** + * @brief Set I2S TX to philip standard + * + * @param hw Peripheral I2S hardware instance address. + */ +static inline void i2s_ll_set_tx_format_philip(i2s_dev_t *hw) +{ +} + +/** + * @brief Set I2S pdm2pcm conv en + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set pdm2pcm conv en + */ +static inline void i2s_ll_set_pdm2pcm_conv_en(i2s_dev_t *hw, bool val) +{ + abort(); // FIXME + // hw->pdm_conf.pdm2pcm_conv_en = val; +} + +/** + * @brief Set I2S rx pdm en + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set rx pdm en + */ +static inline void i2s_ll_set_rx_pdm_en(i2s_dev_t *hw, bool val) +{ + abort(); // FIXME + // hw->pdm_conf.rx_pdm_en = val; +} + +/** + * @brief Set I2S tx pdm en + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set tx pdm en + */ +static inline void i2s_ll_set_tx_pdm_en(i2s_dev_t *hw, bool val) +{ + abort(); // FIXME + // hw->pdm_conf.tx_pdm_en = val; +} + +/** + * @brief Set I2S tx fifo mod force en + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set tx fifo mod force en + */ +static inline void i2s_ll_set_tx_fifo_mod_force_en(i2s_dev_t *hw, bool val) +{ + abort(); // FIXME + // hw->fifo_conf.tx_fifo_mod_force_en = val; +} + +/** + * @brief Set I2S rx fifo mod force en + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set rx fifo mod force en + */ +static inline void i2s_ll_set_rx_fifo_mod_force_en(i2s_dev_t *hw, bool val) +{ + abort(); // FIXME + // hw->fifo_conf.rx_fifo_mod_force_en = val; +} + +/** + * @brief Set I2S tx right first + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set tx right first + */ +static inline void i2s_ll_set_tx_right_first(i2s_dev_t *hw, uint32_t val) +{ + abort(); // FIXME + // hw->conf.tx_right_first = val; +} + +/** + * @brief Set I2S rx right first + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set rx right first + */ +static inline void i2s_ll_set_rx_right_first(i2s_dev_t *hw, uint32_t val) +{ + abort(); // FIXME + // hw->conf.rx_right_first = val; +} + +/** + * @brief Set I2S tx slave mod + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set tx slave mod + */ +static inline void i2s_ll_set_tx_slave_mod(i2s_dev_t *hw, uint32_t val) +{ + abort(); // FIXME + // hw->conf.tx_slave_mod = val; +} + +/** + * @brief Set I2S rx slave mod + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set rx slave mod + */ +static inline void i2s_ll_set_rx_slave_mod(i2s_dev_t *hw, uint32_t val) +{ + abort(); // FIXME + // hw->conf.rx_slave_mod = val; +} + +/** + * @brief Get I2S tx msb right + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to get tx msb right + */ +static inline void i2s_ll_get_tx_msb_right(i2s_dev_t *hw, uint32_t *val) +{ + abort(); // FIXME + // *val = hw->conf.tx_msb_right; +} + +/** + * @brief Get I2S rx msb right + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to get rx msb right + */ +static inline void i2s_ll_get_rx_msb_right(i2s_dev_t *hw, uint32_t *val) +{ + abort(); // FIXME + // *val = hw->conf.rx_msb_right; +} + +/** + * @brief Set I2S tx msb right + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set tx msb right + */ +static inline void i2s_ll_set_tx_msb_right(i2s_dev_t *hw, uint32_t val) +{ + abort(); // FIXME + // hw->conf.tx_msb_right = val; +} + +/** + * @brief Set I2S rx msb right + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set rx msb right + */ +static inline void i2s_ll_set_rx_msb_right(i2s_dev_t *hw, uint32_t val) +{ + abort(); // FIXME + // hw->conf.rx_msb_right = val; +} + +/** + * @brief Set I2S tx mono + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set tx mono + */ +static inline void i2s_ll_set_tx_mono(i2s_dev_t *hw, uint32_t val) +{ + abort(); // FIXME + // hw->conf.tx_mono = val; +} + +/** + * @brief Set I2S rx mono + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set rx mono + */ +static inline void i2s_ll_set_rx_mono(i2s_dev_t *hw, uint32_t val) +{ + abort(); // FIXME + // hw->conf.rx_mono = val; +} + +/** + * @brief Set I2S tx sinc osr2 + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set tx sinc osr2 + */ +static inline void i2s_ll_set_tx_sinc_osr2(i2s_dev_t *hw, uint32_t val) +{ + abort(); // FIXME + // hw->pdm_conf.tx_sinc_osr2 = val; +} + +/** + * @brief Set I2S sig loopback + * + * @param hw Peripheral I2S hardware instance address. + * @param val value to set sig loopback + */ +static inline void i2s_ll_set_sig_loopback(i2s_dev_t *hw, uint32_t val) +{ + abort(); // FIXME + // hw->conf.sig_loopback = val; +} + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/esp32c3/CMakeLists.txt b/components/soc/esp32c3/CMakeLists.txt index f7d0bf36aa..9e53c3042f 100644 --- a/components/soc/esp32c3/CMakeLists.txt +++ b/components/soc/esp32c3/CMakeLists.txt @@ -1,7 +1,6 @@ set(srcs "adc_periph.c" "gpio_periph.c" - "rtc_periph.c" "interrupts.c" "spi_periph.c" "ledc_periph.c" diff --git a/components/ulp/CMakeLists.txt b/components/ulp/CMakeLists.txt index 3b162300b5..a2dcb8abf0 100644 --- a/components/ulp/CMakeLists.txt +++ b/components/ulp/CMakeLists.txt @@ -1,9 +1,13 @@ -set(srcs "ulp.c" - "ulp_macro.c") +idf_build_get_property(target IDF_TARGET) -if(CONFIG_ESP32S2_ULP_COPROC_RISCV) - list(APPEND srcs "ulp_riscv.c") +if(NOT (IDF_TARGET STREQUAL "esp32c3")) + set(srcs "ulp.c" + "ulp_macro.c") + + if(CONFIG_ESP32S2_ULP_COPROC_RISCV) + list(APPEND srcs "ulp_riscv.c") + endif() + + idf_component_register(SRCS ${srcs} + INCLUDE_DIRS include) endif() - -idf_component_register(SRCS ${srcs} - INCLUDE_DIRS include) diff --git a/components/wifi_provisioning/CMakeLists.txt b/components/wifi_provisioning/CMakeLists.txt index bb47508c69..58000d1d02 100644 --- a/components/wifi_provisioning/CMakeLists.txt +++ b/components/wifi_provisioning/CMakeLists.txt @@ -1,3 +1,8 @@ +idf_build_get_property(target IDF_TARGET) +if(${target} STREQUAL "esp32c3") + return() +endif() + set(srcs "src/wifi_config.c" "src/wifi_scan.c" "src/manager.c" From 5f130ff90951ad7d6ffa28270c0bfcc3cfbd7983 Mon Sep 17 00:00:00 2001 From: Marius Vikhammer Date: Wed, 30 Dec 2020 10:53:06 +0800 Subject: [PATCH 6/9] CI: enable C3 template app --- tools/ci/build_template_app.sh | 3 +++ 1 file changed, 3 insertions(+) diff --git a/tools/ci/build_template_app.sh b/tools/ci/build_template_app.sh index 72332c5a21..abda314691 100755 --- a/tools/ci/build_template_app.sh +++ b/tools/ci/build_template_app.sh @@ -73,6 +73,7 @@ build_stage2() { search_cmake esp32 ${CONFIG_STR} search_cmake esp32s2 ${CONFIG_STR} search_cmake esp32s3 ${CONFIG_STR} + search_cmake esp32c3 ${CONFIG_STR} CONFIG_STR=$(get_config_str sdkconfig.ci.*= sdkconfig.ci2.*=) search_make esp32 ${CONFIG_STR} @@ -84,6 +85,7 @@ build_stage2() { search_cmake esp32 ${CONFIG_STR} search_cmake esp32s2 ${CONFIG_STR} search_cmake esp32s3 ${CONFIG_STR} + search_cmake esp32c3 ${CONFIG_STR} # Override EXTRA_CFLAGS and EXTRA_CXXFLAGS in the environment export EXTRA_CFLAGS=${PEDANTIC_CFLAGS/-Werror=unused-variable -Werror=unused-but-set-variable -Werror=unused-function/} @@ -96,6 +98,7 @@ build_stage1() { search_cmake esp32 ${CONFIG_STR} search_cmake esp32s2 ${CONFIG_STR} search_cmake esp32s3 ${CONFIG_STR} + search_cmake esp32c3 ${CONFIG_STR} build } From f54e9269f33fe699d84cacef4eb09899282f0fbd Mon Sep 17 00:00:00 2001 From: Marius Vikhammer Date: Wed, 30 Dec 2020 12:57:58 +0800 Subject: [PATCH 7/9] esp_system: Don't compile sleep_mode.c on c3 --- components/esp_system/CMakeLists.txt | 8 + components/hal/esp32c3/include/hal/i2s_ll.h | 268 ++++++++++---------- components/newlib/newlib_init.c | 2 +- 3 files changed, 143 insertions(+), 135 deletions(-) diff --git a/components/esp_system/CMakeLists.txt b/components/esp_system/CMakeLists.txt index 3342896fa6..fd0b518f07 100644 --- a/components/esp_system/CMakeLists.txt +++ b/components/esp_system/CMakeLists.txt @@ -1,9 +1,17 @@ + +idf_build_get_property(target IDF_TARGET) +# Remove when sleep is brought up on master for C3 TODO ESP32-C3 IDF-2571 +if(NOT (${target} STREQUAL "esp32c3") ) + list(APPEND sleep_src "sleep_modes.c") +endif() + idf_component_register(SRCS "intr_alloc.c" "esp_async_memcpy.c" "panic.c" "system_api.c" "startup.c" "system_time.c" + "${sleep_src}" INCLUDE_DIRS include PRIV_REQUIRES spi_flash # [refactor-todo] requirements due to init code, diff --git a/components/hal/esp32c3/include/hal/i2s_ll.h b/components/hal/esp32c3/include/hal/i2s_ll.h index 87d0886d0c..4a6042cf12 100644 --- a/components/hal/esp32c3/include/hal/i2s_ll.h +++ b/components/hal/esp32c3/include/hal/i2s_ll.h @@ -47,9 +47,9 @@ extern "C" { */ static inline void i2s_ll_reset_rx_fifo(i2s_dev_t *hw) { - abort(); // FIXME - // hw->conf.rx_fifo_reset = 1; - // hw->conf.rx_fifo_reset = 0; + abort(); // TODO ESP32-C3 IDF-2098 + + } /** @@ -59,9 +59,9 @@ static inline void i2s_ll_reset_rx_fifo(i2s_dev_t *hw) */ static inline void i2s_ll_reset_tx_fifo(i2s_dev_t *hw) { - abort(); // FIXME - // hw->conf.tx_fifo_reset = 1; - // hw->conf.tx_fifo_reset = 0; + abort(); // TODO ESP32-C3 IDF-2098 + + } /** @@ -71,9 +71,9 @@ static inline void i2s_ll_reset_tx_fifo(i2s_dev_t *hw) */ static inline void i2s_ll_enable_rx_intr(i2s_dev_t *hw) { - abort(); // FIXME - // hw->int_ena.in_suc_eof = 1; - // hw->int_ena.in_dscr_err = 1; + abort(); // TODO ESP32-C3 IDF-2098 + + } /** @@ -83,9 +83,9 @@ static inline void i2s_ll_enable_rx_intr(i2s_dev_t *hw) */ static inline void i2s_ll_disable_rx_intr(i2s_dev_t *hw) { - abort(); // FIXME - // hw->int_ena.in_suc_eof = 0; - // hw->int_ena.in_dscr_err = 0; + abort(); // TODO ESP32-C3 IDF-2098 + + } /** @@ -95,9 +95,9 @@ static inline void i2s_ll_disable_rx_intr(i2s_dev_t *hw) */ static inline void i2s_ll_disable_tx_intr(i2s_dev_t *hw) { - abort(); // FIXME - // hw->int_ena.out_eof = 0; - // hw->int_ena.out_dscr_err = 0; + abort(); // TODO ESP32-C3 IDF-2098 + + } /** @@ -107,9 +107,9 @@ static inline void i2s_ll_disable_tx_intr(i2s_dev_t *hw) */ static inline void i2s_ll_enable_tx_intr(i2s_dev_t *hw) { - abort(); // FIXME - // hw->int_ena.out_eof = 1; - // hw->int_ena.out_dscr_err = 1; + abort(); // TODO ESP32-C3 IDF-2098 + + } /** @@ -119,9 +119,9 @@ static inline void i2s_ll_enable_tx_intr(i2s_dev_t *hw) */ static inline void i2s_ll_reset_dma_in(i2s_dev_t *hw) { - abort(); // FIXME - // hw->lc_conf.in_rst = 1; - // hw->lc_conf.in_rst = 0; + abort(); // TODO ESP32-C3 IDF-2098 + + } /** @@ -131,9 +131,9 @@ static inline void i2s_ll_reset_dma_in(i2s_dev_t *hw) */ static inline void i2s_ll_reset_dma_out(i2s_dev_t *hw) { - abort(); // FIXME - // hw->lc_conf.out_rst = 1; - // hw->lc_conf.out_rst = 0; + abort(); // TODO ESP32-C3 IDF-2098 + + } /** @@ -143,9 +143,9 @@ static inline void i2s_ll_reset_dma_out(i2s_dev_t *hw) */ static inline void i2s_ll_reset_tx(i2s_dev_t *hw) { - abort(); // FIXME - // hw->conf.tx_reset = 1; - // hw->conf.tx_reset = 0; + abort(); // TODO ESP32-C3 IDF-2098 + + } /** @@ -155,9 +155,9 @@ static inline void i2s_ll_reset_tx(i2s_dev_t *hw) */ static inline void i2s_ll_reset_rx(i2s_dev_t *hw) { - abort(); // FIXME - // hw->conf.rx_reset = 1; - // hw->conf.rx_reset = 0; + abort(); // TODO ESP32-C3 IDF-2098 + + } /** @@ -167,8 +167,8 @@ static inline void i2s_ll_reset_rx(i2s_dev_t *hw) */ static inline void i2s_ll_start_out_link(i2s_dev_t *hw) { - abort(); // FIXME - // hw->out_link.start = 1; + abort(); // TODO ESP32-C3 IDF-2098 + } /** @@ -178,8 +178,8 @@ static inline void i2s_ll_start_out_link(i2s_dev_t *hw) */ static inline void i2s_ll_start_tx(i2s_dev_t *hw) { - abort(); // FIXME - // hw->conf.tx_start = 1; + abort(); // TODO ESP32-C3 IDF-2098 + } /** @@ -189,8 +189,8 @@ static inline void i2s_ll_start_tx(i2s_dev_t *hw) */ static inline void i2s_ll_start_in_link(i2s_dev_t *hw) { - abort(); // FIXME - // hw->in_link.start = 1; + abort(); // TODO ESP32-C3 IDF-2098 + } /** @@ -200,8 +200,8 @@ static inline void i2s_ll_start_in_link(i2s_dev_t *hw) */ static inline void i2s_ll_start_rx(i2s_dev_t *hw) { - abort(); // FIXME - // hw->conf.rx_start = 1; + abort(); // TODO ESP32-C3 IDF-2098 + } /** @@ -211,8 +211,8 @@ static inline void i2s_ll_start_rx(i2s_dev_t *hw) */ static inline void i2s_ll_stop_out_link(i2s_dev_t *hw) { - abort(); // FIXME - // hw->out_link.stop = 1; + abort(); // TODO ESP32-C3 IDF-2098 + } /** @@ -222,8 +222,8 @@ static inline void i2s_ll_stop_out_link(i2s_dev_t *hw) */ static inline void i2s_ll_stop_tx(i2s_dev_t *hw) { - abort(); // FIXME - // hw->conf.tx_start = 0; + abort(); // TODO ESP32-C3 IDF-2098 + } /** @@ -233,8 +233,8 @@ static inline void i2s_ll_stop_tx(i2s_dev_t *hw) */ static inline void i2s_ll_stop_in_link(i2s_dev_t *hw) { - abort(); // FIXME - // hw->in_link.stop = 1; + abort(); // TODO ESP32-C3 IDF-2098 + } /** @@ -244,8 +244,8 @@ static inline void i2s_ll_stop_in_link(i2s_dev_t *hw) */ static inline void i2s_ll_stop_rx(i2s_dev_t *hw) { - abort(); // FIXME - // hw->conf.rx_start = 0; + abort(); // TODO ESP32-C3 IDF-2098 + } /** @@ -255,12 +255,12 @@ static inline void i2s_ll_stop_rx(i2s_dev_t *hw) */ static inline void i2s_ll_enable_dma(i2s_dev_t *hw) { - abort(); // FIXME + abort(); // TODO ESP32-C3 IDF-2098 // //Enable and configure DMA // typeof(hw->lc_conf) lc_conf; // lc_conf.val = 0; // lc_conf.out_eof_mode = 1; - // hw->lc_conf.val = lc_conf.val; + } /** @@ -271,7 +271,7 @@ static inline void i2s_ll_enable_dma(i2s_dev_t *hw) */ static inline void i2s_ll_get_intr_status(i2s_dev_t *hw, uint32_t *val) { - abort(); // FIXME + abort(); // TODO ESP32-C3 IDF-2098 // *val = hw->int_st.val; } @@ -283,8 +283,8 @@ static inline void i2s_ll_get_intr_status(i2s_dev_t *hw, uint32_t *val) */ static inline void i2s_ll_clear_intr_status(i2s_dev_t *hw, uint32_t val) { - abort(); // FIXME - // hw->int_clr.val = val; + abort(); // TODO ESP32-C3 IDF-2098 + } /** @@ -295,7 +295,7 @@ static inline void i2s_ll_clear_intr_status(i2s_dev_t *hw, uint32_t val) */ static inline void i2s_ll_get_out_eof_des_addr(i2s_dev_t *hw, uint32_t *val) { - abort(); // FIXME + abort(); // TODO ESP32-C3 IDF-2098 // *val = hw->out_eof_des_addr; } @@ -307,7 +307,7 @@ static inline void i2s_ll_get_out_eof_des_addr(i2s_dev_t *hw, uint32_t *val) */ static inline void i2s_ll_get_in_eof_des_addr(i2s_dev_t *hw, uint32_t *val) { - abort(); // FIXME + abort(); // TODO ESP32-C3 IDF-2098 // *val = hw->in_eof_des_addr; } @@ -319,7 +319,7 @@ static inline void i2s_ll_get_in_eof_des_addr(i2s_dev_t *hw, uint32_t *val) */ static inline void i2s_ll_get_tx_fifo_mod(i2s_dev_t *hw, uint32_t *val) { - abort(); // FIXME + abort(); // TODO ESP32-C3 IDF-2098 // *val = hw->fifo_conf.tx_fifo_mod; } @@ -331,8 +331,8 @@ static inline void i2s_ll_get_tx_fifo_mod(i2s_dev_t *hw, uint32_t *val) */ static inline void i2s_ll_set_tx_fifo_mod(i2s_dev_t *hw, uint32_t val) { - abort(); // FIXME - // hw->fifo_conf.tx_fifo_mod = val; + abort(); // TODO ESP32-C3 IDF-2098 + } /** @@ -343,7 +343,7 @@ static inline void i2s_ll_set_tx_fifo_mod(i2s_dev_t *hw, uint32_t val) */ static inline void i2s_ll_get_rx_fifo_mod(i2s_dev_t *hw, uint32_t *val) { - abort(); // FIXME + abort(); // TODO ESP32-C3 IDF-2098 // *val = hw->fifo_conf.rx_fifo_mod; } @@ -355,8 +355,8 @@ static inline void i2s_ll_get_rx_fifo_mod(i2s_dev_t *hw, uint32_t *val) */ static inline void i2s_ll_set_rx_fifo_mod(i2s_dev_t *hw, uint32_t val) { - abort(); // FIXME - // hw->fifo_conf.rx_fifo_mod = val; + abort(); // TODO ESP32-C3 IDF-2098 + } /** @@ -367,8 +367,8 @@ static inline void i2s_ll_set_rx_fifo_mod(i2s_dev_t *hw, uint32_t val) */ static inline void i2s_ll_set_tx_chan_mod(i2s_dev_t *hw, uint32_t val) { - abort(); // FIXME - // hw->conf_chan.tx_chan_mod = val; + abort(); // TODO ESP32-C3 IDF-2098 + } /** @@ -379,8 +379,8 @@ static inline void i2s_ll_set_tx_chan_mod(i2s_dev_t *hw, uint32_t val) */ static inline void i2s_ll_set_rx_chan_mod(i2s_dev_t *hw, uint32_t val) { - abort(); // FIXME - // hw->conf_chan.rx_chan_mod = val; + abort(); // TODO ESP32-C3 IDF-2098 + } /** @@ -391,8 +391,8 @@ static inline void i2s_ll_set_rx_chan_mod(i2s_dev_t *hw, uint32_t val) */ static inline void i2s_ll_set_out_link_addr(i2s_dev_t *hw, uint32_t val) { - abort(); // FIXME - // hw->out_link.addr = val; + abort(); // TODO ESP32-C3 IDF-2098 + } /** @@ -403,8 +403,8 @@ static inline void i2s_ll_set_out_link_addr(i2s_dev_t *hw, uint32_t val) */ static inline void i2s_ll_set_in_link_addr(i2s_dev_t *hw, uint32_t val) { - abort(); // FIXME - // hw->in_link.addr = val; + abort(); // TODO ESP32-C3 IDF-2098 + } /** @@ -415,8 +415,8 @@ static inline void i2s_ll_set_in_link_addr(i2s_dev_t *hw, uint32_t val) */ static inline void i2s_ll_set_rx_eof_num(i2s_dev_t *hw, uint32_t val) { - abort(); // FIXME - // hw->rx_eof_num = val; + abort(); // TODO ESP32-C3 IDF-2098 + } /** @@ -427,7 +427,7 @@ static inline void i2s_ll_set_rx_eof_num(i2s_dev_t *hw, uint32_t val) */ static inline void i2s_ll_get_tx_pdm_fp(i2s_dev_t *hw, uint32_t *val) { - abort(); // FIXME + abort(); // TODO ESP32-C3 IDF-2098 // *val = hw->pdm_freq_conf.tx_pdm_fp; } @@ -439,7 +439,7 @@ static inline void i2s_ll_get_tx_pdm_fp(i2s_dev_t *hw, uint32_t *val) */ static inline void i2s_ll_get_tx_pdm_fs(i2s_dev_t *hw, uint32_t *val) { - abort(); // FIXME + abort(); // TODO ESP32-C3 IDF-2098 // *val = hw->pdm_freq_conf.tx_pdm_fs; } @@ -451,8 +451,8 @@ static inline void i2s_ll_get_tx_pdm_fs(i2s_dev_t *hw, uint32_t *val) */ static inline void i2s_ll_set_tx_pdm_fp(i2s_dev_t *hw, uint32_t val) { - abort(); // FIXME - // hw->pdm_freq_conf.tx_pdm_fp = val; + abort(); // TODO ESP32-C3 IDF-2098 + } /** @@ -463,8 +463,8 @@ static inline void i2s_ll_set_tx_pdm_fp(i2s_dev_t *hw, uint32_t val) */ static inline void i2s_ll_set_tx_pdm_fs(i2s_dev_t *hw, uint32_t val) { - abort(); // FIXME - // hw->pdm_freq_conf.tx_pdm_fs = val; + abort(); // TODO ESP32-C3 IDF-2098 + } /** @@ -475,7 +475,7 @@ static inline void i2s_ll_set_tx_pdm_fs(i2s_dev_t *hw, uint32_t val) */ static inline void i2s_ll_get_rx_sinc_dsr_16_en(i2s_dev_t *hw, bool *val) { - abort(); // FIXME + abort(); // TODO ESP32-C3 IDF-2098 // *val = hw->pdm_conf.rx_sinc_dsr_16_en; } @@ -487,8 +487,8 @@ static inline void i2s_ll_get_rx_sinc_dsr_16_en(i2s_dev_t *hw, bool *val) */ static inline void i2s_ll_set_clkm_div_num(i2s_dev_t *hw, uint32_t val) { - abort(); // FIXME - // hw->clkm_conf.clkm_div_num = val; + abort(); // TODO ESP32-C3 IDF-2098 + } /** @@ -499,8 +499,8 @@ static inline void i2s_ll_set_clkm_div_num(i2s_dev_t *hw, uint32_t val) */ static inline void i2s_ll_set_clkm_div_b(i2s_dev_t *hw, uint32_t val) { - abort(); // FIXME - // hw->clkm_conf.clkm_div_b = val; + abort(); // TODO ESP32-C3 IDF-2098 + } /** @@ -511,8 +511,8 @@ static inline void i2s_ll_set_clkm_div_b(i2s_dev_t *hw, uint32_t val) */ static inline void i2s_ll_set_clkm_div_a(i2s_dev_t *hw, uint32_t val) { - abort(); // FIXME - // hw->clkm_conf.clkm_div_a = val; + abort(); // TODO ESP32-C3 IDF-2098 + } /** @@ -523,8 +523,8 @@ static inline void i2s_ll_set_clkm_div_a(i2s_dev_t *hw, uint32_t val) */ static inline void i2s_ll_set_tx_bck_div_num(i2s_dev_t *hw, uint32_t val) { - abort(); // FIXME - // hw->sample_rate_conf.tx_bck_div_num = val; + abort(); // TODO ESP32-C3 IDF-2098 + } /** @@ -535,8 +535,8 @@ static inline void i2s_ll_set_tx_bck_div_num(i2s_dev_t *hw, uint32_t val) */ static inline void i2s_ll_set_rx_bck_div_num(i2s_dev_t *hw, uint32_t val) { - abort(); // FIXME - // hw->sample_rate_conf.rx_bck_div_num = val; + abort(); // TODO ESP32-C3 IDF-2098 + } /** @@ -547,8 +547,8 @@ static inline void i2s_ll_set_rx_bck_div_num(i2s_dev_t *hw, uint32_t val) */ static inline void i2s_ll_set_clk_sel(i2s_dev_t *hw, uint32_t val) { - abort(); // FIXME - // hw->clkm_conf.clk_sel = (val == 1) ? 1 : 2; + abort(); // TODO ESP32-C3 IDF-2098 + } /** @@ -559,8 +559,8 @@ static inline void i2s_ll_set_clk_sel(i2s_dev_t *hw, uint32_t val) */ static inline void i2s_ll_set_tx_bits_mod(i2s_dev_t *hw, uint32_t val) { - abort(); // FIXME - // hw->sample_rate_conf.tx_bits_mod = val; + abort(); // TODO ESP32-C3 IDF-2098 + } /** @@ -571,8 +571,8 @@ static inline void i2s_ll_set_tx_bits_mod(i2s_dev_t *hw, uint32_t val) */ static inline void i2s_ll_set_rx_bits_mod(i2s_dev_t *hw, uint32_t val) { - abort(); // FIXME - // hw->sample_rate_conf.rx_bits_mod = val; + abort(); // TODO ESP32-C3 IDF-2098 + } /** @@ -583,8 +583,8 @@ static inline void i2s_ll_set_rx_bits_mod(i2s_dev_t *hw, uint32_t val) */ static inline void i2s_ll_set_rx_sinc_dsr_16_en(i2s_dev_t *hw, bool val) { - abort(); // FIXME - // hw->pdm_conf.rx_sinc_dsr_16_en = val; + abort(); // TODO ESP32-C3 IDF-2098 + } /** @@ -595,8 +595,8 @@ static inline void i2s_ll_set_rx_sinc_dsr_16_en(i2s_dev_t *hw, bool val) */ static inline void i2s_ll_set_dscr_en(i2s_dev_t *hw, bool val) { - abort(); // FIXME - // hw->fifo_conf.dscr_en = val; + abort(); // TODO ESP32-C3 IDF-2098 + } /** @@ -607,8 +607,8 @@ static inline void i2s_ll_set_dscr_en(i2s_dev_t *hw, bool val) */ static inline void i2s_ll_set_lcd_en(i2s_dev_t *hw, bool val) { - abort(); // FIXME - // hw->conf2.lcd_en = val; + abort(); // TODO ESP32-C3 IDF-2098 + } /** @@ -619,8 +619,8 @@ static inline void i2s_ll_set_lcd_en(i2s_dev_t *hw, bool val) */ static inline void i2s_ll_set_camera_en(i2s_dev_t *hw, bool val) { - abort(); // FIXME - // hw->conf2.camera_en = val; + abort(); // TODO ESP32-C3 IDF-2098 + } /** @@ -631,8 +631,8 @@ static inline void i2s_ll_set_camera_en(i2s_dev_t *hw, bool val) */ static inline void i2s_ll_set_pcm2pdm_conv_en(i2s_dev_t *hw, bool val) { - abort(); // FIXME - // hw->pdm_conf.pcm2pdm_conv_en = val; + abort(); // TODO ESP32-C3 IDF-2098 + } /** @@ -711,8 +711,8 @@ static inline void i2s_ll_set_tx_format_philip(i2s_dev_t *hw) */ static inline void i2s_ll_set_pdm2pcm_conv_en(i2s_dev_t *hw, bool val) { - abort(); // FIXME - // hw->pdm_conf.pdm2pcm_conv_en = val; + abort(); // TODO ESP32-C3 IDF-2098 + } /** @@ -723,8 +723,8 @@ static inline void i2s_ll_set_pdm2pcm_conv_en(i2s_dev_t *hw, bool val) */ static inline void i2s_ll_set_rx_pdm_en(i2s_dev_t *hw, bool val) { - abort(); // FIXME - // hw->pdm_conf.rx_pdm_en = val; + abort(); // TODO ESP32-C3 IDF-2098 + } /** @@ -735,8 +735,8 @@ static inline void i2s_ll_set_rx_pdm_en(i2s_dev_t *hw, bool val) */ static inline void i2s_ll_set_tx_pdm_en(i2s_dev_t *hw, bool val) { - abort(); // FIXME - // hw->pdm_conf.tx_pdm_en = val; + abort(); // TODO ESP32-C3 IDF-2098 + } /** @@ -747,8 +747,8 @@ static inline void i2s_ll_set_tx_pdm_en(i2s_dev_t *hw, bool val) */ static inline void i2s_ll_set_tx_fifo_mod_force_en(i2s_dev_t *hw, bool val) { - abort(); // FIXME - // hw->fifo_conf.tx_fifo_mod_force_en = val; + abort(); // TODO ESP32-C3 IDF-2098 + } /** @@ -759,8 +759,8 @@ static inline void i2s_ll_set_tx_fifo_mod_force_en(i2s_dev_t *hw, bool val) */ static inline void i2s_ll_set_rx_fifo_mod_force_en(i2s_dev_t *hw, bool val) { - abort(); // FIXME - // hw->fifo_conf.rx_fifo_mod_force_en = val; + abort(); // TODO ESP32-C3 IDF-2098 + } /** @@ -771,8 +771,8 @@ static inline void i2s_ll_set_rx_fifo_mod_force_en(i2s_dev_t *hw, bool val) */ static inline void i2s_ll_set_tx_right_first(i2s_dev_t *hw, uint32_t val) { - abort(); // FIXME - // hw->conf.tx_right_first = val; + abort(); // TODO ESP32-C3 IDF-2098 + } /** @@ -783,8 +783,8 @@ static inline void i2s_ll_set_tx_right_first(i2s_dev_t *hw, uint32_t val) */ static inline void i2s_ll_set_rx_right_first(i2s_dev_t *hw, uint32_t val) { - abort(); // FIXME - // hw->conf.rx_right_first = val; + abort(); // TODO ESP32-C3 IDF-2098 + } /** @@ -795,8 +795,8 @@ static inline void i2s_ll_set_rx_right_first(i2s_dev_t *hw, uint32_t val) */ static inline void i2s_ll_set_tx_slave_mod(i2s_dev_t *hw, uint32_t val) { - abort(); // FIXME - // hw->conf.tx_slave_mod = val; + abort(); // TODO ESP32-C3 IDF-2098 + } /** @@ -807,8 +807,8 @@ static inline void i2s_ll_set_tx_slave_mod(i2s_dev_t *hw, uint32_t val) */ static inline void i2s_ll_set_rx_slave_mod(i2s_dev_t *hw, uint32_t val) { - abort(); // FIXME - // hw->conf.rx_slave_mod = val; + abort(); // TODO ESP32-C3 IDF-2098 + } /** @@ -819,7 +819,7 @@ static inline void i2s_ll_set_rx_slave_mod(i2s_dev_t *hw, uint32_t val) */ static inline void i2s_ll_get_tx_msb_right(i2s_dev_t *hw, uint32_t *val) { - abort(); // FIXME + abort(); // TODO ESP32-C3 IDF-2098 // *val = hw->conf.tx_msb_right; } @@ -831,7 +831,7 @@ static inline void i2s_ll_get_tx_msb_right(i2s_dev_t *hw, uint32_t *val) */ static inline void i2s_ll_get_rx_msb_right(i2s_dev_t *hw, uint32_t *val) { - abort(); // FIXME + abort(); // TODO ESP32-C3 IDF-2098 // *val = hw->conf.rx_msb_right; } @@ -843,8 +843,8 @@ static inline void i2s_ll_get_rx_msb_right(i2s_dev_t *hw, uint32_t *val) */ static inline void i2s_ll_set_tx_msb_right(i2s_dev_t *hw, uint32_t val) { - abort(); // FIXME - // hw->conf.tx_msb_right = val; + abort(); // TODO ESP32-C3 IDF-2098 + } /** @@ -855,8 +855,8 @@ static inline void i2s_ll_set_tx_msb_right(i2s_dev_t *hw, uint32_t val) */ static inline void i2s_ll_set_rx_msb_right(i2s_dev_t *hw, uint32_t val) { - abort(); // FIXME - // hw->conf.rx_msb_right = val; + abort(); // TODO ESP32-C3 IDF-2098 + } /** @@ -867,8 +867,8 @@ static inline void i2s_ll_set_rx_msb_right(i2s_dev_t *hw, uint32_t val) */ static inline void i2s_ll_set_tx_mono(i2s_dev_t *hw, uint32_t val) { - abort(); // FIXME - // hw->conf.tx_mono = val; + abort(); // TODO ESP32-C3 IDF-2098 + } /** @@ -879,8 +879,8 @@ static inline void i2s_ll_set_tx_mono(i2s_dev_t *hw, uint32_t val) */ static inline void i2s_ll_set_rx_mono(i2s_dev_t *hw, uint32_t val) { - abort(); // FIXME - // hw->conf.rx_mono = val; + abort(); // TODO ESP32-C3 IDF-2098 + } /** @@ -891,8 +891,8 @@ static inline void i2s_ll_set_rx_mono(i2s_dev_t *hw, uint32_t val) */ static inline void i2s_ll_set_tx_sinc_osr2(i2s_dev_t *hw, uint32_t val) { - abort(); // FIXME - // hw->pdm_conf.tx_sinc_osr2 = val; + abort(); // TODO ESP32-C3 IDF-2098 + } /** @@ -903,8 +903,8 @@ static inline void i2s_ll_set_tx_sinc_osr2(i2s_dev_t *hw, uint32_t val) */ static inline void i2s_ll_set_sig_loopback(i2s_dev_t *hw, uint32_t val) { - abort(); // FIXME - // hw->conf.sig_loopback = val; + abort(); // TODO ESP32-C3 IDF-2098 + } #ifdef __cplusplus diff --git a/components/newlib/newlib_init.c b/components/newlib/newlib_init.c index b33d3b9dda..24ef68e737 100644 --- a/components/newlib/newlib_init.c +++ b/components/newlib/newlib_init.c @@ -112,7 +112,7 @@ static struct syscall_stub_table s_stub_table = { ._scanf_float = NULL, #endif #ifdef CONFIG_IDF_TARGET_ESP32C3 - /* TODO: mark that this assert failed in ROM, to avoid confusion between IDF & ROM + /* TODO IDF-2570 : mark that this assert failed in ROM, to avoid confusion between IDF & ROM assertion failures (as function names & source file names will be similar) */ .__assert_func = __assert_func, From eed154a583d4c35faf036b1b6fde0d92c07ed3a1 Mon Sep 17 00:00:00 2001 From: Marius Vikhammer Date: Wed, 30 Dec 2020 15:33:03 +0800 Subject: [PATCH 8/9] esp_system: sync with C3 changes Fixes interrupt allocation issue --- components/esp_system/include/esp_sleep.h | 1 + components/esp_system/include/esp_system.h | 2 ++ components/esp_system/intr_alloc.c | 7 +++++++ components/esp_system/test/test_intr_alloc.c | 4 +--- components/esp_system/test/test_sleep.c | 13 ++++++------- 5 files changed, 17 insertions(+), 10 deletions(-) diff --git a/components/esp_system/include/esp_sleep.h b/components/esp_system/include/esp_sleep.h index bcfe6227e6..5b90614cc3 100644 --- a/components/esp_system/include/esp_sleep.h +++ b/components/esp_system/include/esp_sleep.h @@ -68,6 +68,7 @@ typedef enum { ESP_SLEEP_WAKEUP_WIFI, //!< Wakeup caused by WIFI (light sleep only) ESP_SLEEP_WAKEUP_COCPU, //!< Wakeup caused by COCPU int ESP_SLEEP_WAKEUP_COCPU_TRAP_TRIG, //!< Wakeup caused by COCPU crash + ESP_SLEEP_WAKEUP_BT, //!< Wakeup caused by BT (light sleep only) } esp_sleep_source_t; /* Leave this type define for compatibility */ diff --git a/components/esp_system/include/esp_system.h b/components/esp_system/include/esp_system.h index ea3e914159..c251b41635 100644 --- a/components/esp_system/include/esp_system.h +++ b/components/esp_system/include/esp_system.h @@ -42,6 +42,8 @@ typedef enum { #define UNIVERSAL_MAC_ADDR_NUM CONFIG_ESP32_UNIVERSAL_MAC_ADDRESSES #elif CONFIG_IDF_TARGET_ESP32S2 #define UNIVERSAL_MAC_ADDR_NUM CONFIG_ESP32S2_UNIVERSAL_MAC_ADDRESSES +#elif CONFIG_IDF_TARGET_ESP32C3 +#define UNIVERSAL_MAC_ADDR_NUM CONFIG_ESP32C3_UNIVERSAL_MAC_ADDRESSES #endif /** @endcond */ diff --git a/components/esp_system/intr_alloc.c b/components/esp_system/intr_alloc.c index d440ca9f24..22650cfc25 100644 --- a/components/esp_system/intr_alloc.c +++ b/components/esp_system/intr_alloc.c @@ -585,6 +585,13 @@ esp_err_t esp_intr_alloc_intrstatus(int source, int flags, uint32_t intrstatusre esp_intr_disable(ret); } +#if CONFIG_IDF_TARGET_ESP32C3 + // TODO ESP32-C3 IDF-2126, these need to be set or the new interrupt won't fire, but are currently hard-coded + // for priority and level... + esprv_intc_int_set_priority(intr, 1); + esprv_intc_int_set_type(BIT(intr), INTR_TYPE_LEVEL); +#endif + portEXIT_CRITICAL(&spinlock); //Fill return handle if needed, otherwise free handle. diff --git a/components/esp_system/test/test_intr_alloc.c b/components/esp_system/test/test_intr_alloc.c index 67bb6b039f..a917a79c4d 100644 --- a/components/esp_system/test/test_intr_alloc.c +++ b/components/esp_system/test/test_intr_alloc.c @@ -9,17 +9,15 @@ #include "freertos/task.h" #include "freertos/semphr.h" #include "freertos/queue.h" -#include "freertos/xtensa_api.h" #include "unity.h" #include "soc/uart_periph.h" -#include "soc/dport_reg.h" #include "soc/gpio_periph.h" #include "esp_intr_alloc.h" #include "driver/periph_ctrl.h" #include "driver/timer.h" #include "sdkconfig.h" -#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3) +#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3,ESP32C3) #define TIMER_DIVIDER 16 /*!< Hardware timer clock divider */ #define TIMER_SCALE (TIMER_BASE_CLK / TIMER_DIVIDER) /*!< used to calculate counter value */ diff --git a/components/esp_system/test/test_sleep.c b/components/esp_system/test/test_sleep.c index fdc438fd53..18ae86d897 100644 --- a/components/esp_system/test/test_sleep.c +++ b/components/esp_system/test/test_sleep.c @@ -19,6 +19,7 @@ #include "sdkconfig.h" #include "esp_rom_sys.h" +#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32C3, ESP32S3) #if CONFIG_IDF_TARGET_ESP32 #include "esp32/clk.h" @@ -31,8 +32,6 @@ #include "esp32s3/rom/rtc.h" #endif -#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3) - #define ESP_EXT0_WAKEUP_LEVEL_LOW 0 #define ESP_EXT0_WAKEUP_LEVEL_HIGH 1 @@ -63,7 +62,7 @@ TEST_CASE("wake up from deep sleep using timer", "[deepsleep][reset=DEEPSLEEP_RE esp_deep_sleep_start(); } -#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2) +#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2, ESP32C3) TEST_CASE("light sleep followed by deep sleep", "[deepsleep][reset=DEEPSLEEP_RESET]") { esp_sleep_enable_timer_wakeup(1000000); @@ -82,7 +81,7 @@ TEST_CASE("wake up from light sleep using timer", "[deepsleep]") (tv_stop.tv_usec - tv_start.tv_usec) * 1e-3f; TEST_ASSERT_INT32_WITHIN(500, 2000, (int) dt); } -#endif // !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2) +#endif // !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2, ESP32C3) static void test_light_sleep(void* arg) { @@ -417,7 +416,7 @@ __attribute__((unused)) static uint32_t get_cause(void) return wakeup_cause; } -#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2) +#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2, ESP32C3) // This test case verifies deactivation of trigger for wake up sources TEST_CASE("disable source trigger behavior", "[deepsleep]") { @@ -490,7 +489,7 @@ TEST_CASE("disable source trigger behavior", "[deepsleep]") // Disable ext0 wakeup source, as this might interfere with other tests ESP_ERROR_CHECK(esp_sleep_disable_wakeup_source(ESP_SLEEP_WAKEUP_EXT0)); } -#endif // !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2) +#endif // !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2, ESP32C3) static RTC_DATA_ATTR struct timeval start; static void trigger_deepsleep(void) @@ -527,4 +526,4 @@ static void check_time_deepsleep(void) TEST_CASE_MULTIPLE_STAGES("check a time after wakeup from deep sleep", "[deepsleep][reset=DEEPSLEEP_RESET]", trigger_deepsleep, check_time_deepsleep); -#endif // #if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S3) +#endif // #if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32C3, ESP32S3) From db4fb49432d8c361155d26bc22e9d5b8a1bdbf90 Mon Sep 17 00:00:00 2001 From: Angus Gratton Date: Wed, 30 Dec 2020 19:12:07 +1100 Subject: [PATCH 9/9] esp_common: Fix issue with SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY not visible on c3 Create a common symbol name to use from linker.lf fragments --- components/bt/linker.lf | 2 +- components/esp32/ld/esp32_fragments.lf | 2 +- components/esp_common/Kconfig | 5 +++++ components/esp_common/Kconfig.spiram.common | 1 + components/esp_wifi/linker.lf | 4 ++-- components/lwip/linker.lf | 2 +- 6 files changed, 11 insertions(+), 5 deletions(-) diff --git a/components/bt/linker.lf b/components/bt/linker.lf index f239404450..e8cbc14628 100644 --- a/components/bt/linker.lf +++ b/components/bt/linker.lf @@ -1,5 +1,5 @@ [mapping:bt] archive: libbt.a entries: - if SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY = y: + if ESP_ALLOW_BSS_SEG_EXTERNAL_MEMORY = y: * (extram_bss) diff --git a/components/esp32/ld/esp32_fragments.lf b/components/esp32/ld/esp32_fragments.lf index 4c6b0a9ddb..f334beee8a 100644 --- a/components/esp32/ld/esp32_fragments.lf +++ b/components/esp32/ld/esp32_fragments.lf @@ -107,7 +107,7 @@ entries: data -> dram0_data bss -> dram0_bss common -> dram0_bss - if SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY = y: + if ESP_ALLOW_BSS_SEG_EXTERNAL_MEMORY = y: extram_bss -> extern_ram else: extram_bss -> dram0_bss diff --git a/components/esp_common/Kconfig b/components/esp_common/Kconfig index de0d76afbc..ab0c2277bd 100644 --- a/components/esp_common/Kconfig +++ b/components/esp_common/Kconfig @@ -304,4 +304,9 @@ menu "Common ESP-related" config ESP_MAC_ADDR_UNIVERSE_ETH bool + config ESP_ALLOW_BSS_SEG_EXTERNAL_MEMORY + # Invisible option that is set by SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY, but + # exists even if SPIRAM is not supported + bool + endmenu # Common ESP-related diff --git a/components/esp_common/Kconfig.spiram.common b/components/esp_common/Kconfig.spiram.common index bf45f1e0e3..b7229bd49d 100644 --- a/components/esp_common/Kconfig.spiram.common +++ b/components/esp_common/Kconfig.spiram.common @@ -93,6 +93,7 @@ config SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY bool "Allow .bss segment placed in external memory" default n depends on SPIRAM + select ESP_ALLOW_BSS_SEG_EXTERNAL_MEMORY help If enabled, variables with EXT_RAM_ATTR attribute will be placed in SPIRAM instead of internal DRAM. BSS section of `lwip`, `net80211`, `pp`, `bt` libraries will be automatically placed diff --git a/components/esp_wifi/linker.lf b/components/esp_wifi/linker.lf index 9acda0dfc8..8ea33b9818 100644 --- a/components/esp_wifi/linker.lf +++ b/components/esp_wifi/linker.lf @@ -17,7 +17,7 @@ entries: if ESP32_WIFI_RX_IRAM_OPT = y: * (wifi_rx_iram) - if SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY = y: + if ESP_ALLOW_BSS_SEG_EXTERNAL_MEMORY = y: * (extram_bss) [mapping:net80211] @@ -29,5 +29,5 @@ entries: if ESP32_WIFI_RX_IRAM_OPT = y: * (wifi_rx_iram) - if SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY = y: + if ESP_ALLOW_BSS_SEG_EXTERNAL_MEMORY = y: * (extram_bss) diff --git a/components/lwip/linker.lf b/components/lwip/linker.lf index 6d95da947e..6ee75ab24c 100644 --- a/components/lwip/linker.lf +++ b/components/lwip/linker.lf @@ -86,5 +86,5 @@ entries: * (default) - if SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY = y: + if ESP_ALLOW_BSS_SEG_EXTERNAL_MEMORY = y: * (extram_bss)