gptimer: clean up hal and ll for driver-ng

components/hal/esp32/include/hal/mwdt_ll.h

@@ -1,16 +1,8 @@
-// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 
 // The LL layer for Timer Group register operations.
 // Note that most of the register operations in this layer are non-atomic operations.
@@ -24,6 +16,7 @@ extern "C" {
 #include <stdint.h>
 #include <stdbool.h>
 #include "hal/misc.h"
+#include "hal/assert.h"
 #include "soc/timer_periph.h"
 #include "soc/timer_group_struct.h"
 #include "hal/wdt_types.h"
@@ -51,7 +44,7 @@ _Static_assert(WDT_RESET_SIG_LENGTH_3_2us == TIMG_WDT_RESET_LENGTH_3200_NS, "Add
  */
 FORCE_INLINE_ATTR void mwdt_ll_enable(timg_dev_t *hw)
 {
-    hw->wdt_config0.en = 1;
+    hw->wdtconfig0.wdt_en = 1;
 }
 
 /**
@@ -64,7 +57,7 @@ FORCE_INLINE_ATTR void mwdt_ll_enable(timg_dev_t *hw)
  */
 FORCE_INLINE_ATTR void mwdt_ll_disable(timg_dev_t *hw)
 {
-    hw->wdt_config0.en = 0;
+    hw->wdtconfig0.wdt_en = 0;
 }
 
 /**
@@ -75,7 +68,7 @@ FORCE_INLINE_ATTR void mwdt_ll_disable(timg_dev_t *hw)
  */
 FORCE_INLINE_ATTR bool mwdt_ll_check_if_enabled(timg_dev_t *hw)
 {
-    return (hw->wdt_config0.en) ? true : false;
+    return (hw->wdtconfig0.wdt_en) ? true : false;
 }
 
 /**
@@ -89,24 +82,25 @@ FORCE_INLINE_ATTR bool mwdt_ll_check_if_enabled(timg_dev_t *hw)
 FORCE_INLINE_ATTR void mwdt_ll_config_stage(timg_dev_t *hw, wdt_stage_t stage, uint32_t timeout, wdt_stage_action_t behavior)
 {
     switch (stage) {
-        case WDT_STAGE0:
-            hw->wdt_config0.stg0 = behavior;
-            hw->wdt_config2 = timeout;
-            break;
-        case WDT_STAGE1:
-            hw->wdt_config0.stg1 = behavior;
-            hw->wdt_config3 = timeout;
-            break;
-        case WDT_STAGE2:
-            hw->wdt_config0.stg2 = behavior;
-            hw->wdt_config4 = timeout;
-            break;
-        case WDT_STAGE3:
-            hw->wdt_config0.stg3 = behavior;
-            hw->wdt_config5 = timeout;
-            break;
-        default:
-            break;
+    case WDT_STAGE0:
+        hw->wdtconfig0.wdt_stg0 = behavior;
+        hw->wdtconfig2.wdt_stg0_hold = timeout;
+        break;
+    case WDT_STAGE1:
+        hw->wdtconfig0.wdt_stg1 = behavior;
+        hw->wdtconfig3.wdt_stg1_hold = timeout;
+        break;
+    case WDT_STAGE2:
+        hw->wdtconfig0.wdt_stg2 = behavior;
+        hw->wdtconfig4.wdt_stg2_hold = timeout;
+        break;
+    case WDT_STAGE3:
+        hw->wdtconfig0.wdt_stg3 = behavior;
+        hw->wdtconfig5.wdt_stg3_hold = timeout;
+        break;
+    default:
+        HAL_ASSERT(false && "unsupported WDT stage");
+        break;
     }
 }
 
@@ -119,20 +113,21 @@ FORCE_INLINE_ATTR void mwdt_ll_config_stage(timg_dev_t *hw, wdt_stage_t stage, u
 FORCE_INLINE_ATTR void mwdt_ll_disable_stage(timg_dev_t *hw, uint32_t stage)
 {
     switch (stage) {
-        case WDT_STAGE0:
-            hw->wdt_config0.stg0 = WDT_STAGE_ACTION_OFF;
-            break;
-        case WDT_STAGE1:
-            hw->wdt_config0.stg1 = WDT_STAGE_ACTION_OFF;
-            break;
-        case WDT_STAGE2:
-            hw->wdt_config0.stg2 = WDT_STAGE_ACTION_OFF;
-            break;
-        case WDT_STAGE3:
-            hw->wdt_config0.stg3 = WDT_STAGE_ACTION_OFF;
-            break;
-        default:
-            break;
+    case WDT_STAGE0:
+        hw->wdtconfig0.wdt_stg0 = WDT_STAGE_ACTION_OFF;
+        break;
+    case WDT_STAGE1:
+        hw->wdtconfig0.wdt_stg1 = WDT_STAGE_ACTION_OFF;
+        break;
+    case WDT_STAGE2:
+        hw->wdtconfig0.wdt_stg2 = WDT_STAGE_ACTION_OFF;
+        break;
+    case WDT_STAGE3:
+        hw->wdtconfig0.wdt_stg3 = WDT_STAGE_ACTION_OFF;
+        break;
+    default:
+        HAL_ASSERT(false && "unsupported WDT stage");
+        break;
     }
 }
 
@@ -144,7 +139,7 @@ FORCE_INLINE_ATTR void mwdt_ll_disable_stage(timg_dev_t *hw, uint32_t stage)
  */
 FORCE_INLINE_ATTR void mwdt_ll_set_edge_intr(timg_dev_t *hw, bool enable)
 {
-    hw->wdt_config0.edge_int_en = (enable) ? 1 : 0;
+    hw->wdtconfig0.wdt_edge_int_en = enable;
 }
 
 /**
@@ -155,7 +150,7 @@ FORCE_INLINE_ATTR void mwdt_ll_set_edge_intr(timg_dev_t *hw, bool enable)
  */
 FORCE_INLINE_ATTR void mwdt_ll_set_level_intr(timg_dev_t *hw, bool enable)
 {
-    hw->wdt_config0.level_int_en = (enable) ? 1 : 0;
+    hw->wdtconfig0.wdt_level_int_en = enable;
 }
 
 /**
@@ -166,7 +161,7 @@ FORCE_INLINE_ATTR void mwdt_ll_set_level_intr(timg_dev_t *hw, bool enable)
  */
 FORCE_INLINE_ATTR void mwdt_ll_set_cpu_reset_length(timg_dev_t *hw, wdt_reset_sig_length_t length)
 {
-    hw->wdt_config0.cpu_reset_length = length;
+    hw->wdtconfig0.wdt_cpu_reset_length = length;
 }
 
 /**
@@ -177,7 +172,7 @@ FORCE_INLINE_ATTR void mwdt_ll_set_cpu_reset_length(timg_dev_t *hw, wdt_reset_si
  */
 FORCE_INLINE_ATTR void mwdt_ll_set_sys_reset_length(timg_dev_t *hw, wdt_reset_sig_length_t length)
 {
-    hw->wdt_config0.sys_reset_length = length;
+    hw->wdtconfig0.wdt_sys_reset_length = length;
 }
 
 /**
@@ -190,9 +185,9 @@ FORCE_INLINE_ATTR void mwdt_ll_set_sys_reset_length(timg_dev_t *hw, wdt_reset_si
  *       WDT's enable bit is set to 0. Flashboot mode for TG0 is automatically enabled
  *       on flashboot, and should be disabled by software when flashbooting completes.
  */
-FORCE_INLINE_ATTR void mwdt_ll_set_flashboot_en(timg_dev_t* hw, bool enable)
+FORCE_INLINE_ATTR void mwdt_ll_set_flashboot_en(timg_dev_t *hw, bool enable)
 {
-    hw->wdt_config0.flashboot_mod_en = (enable) ? 1 : 0;
+    hw->wdtconfig0.wdt_flashboot_mod_en = (enable) ? 1 : 0;
 }
 
 /**
@@ -203,7 +198,7 @@ FORCE_INLINE_ATTR void mwdt_ll_set_flashboot_en(timg_dev_t* hw, bool enable)
  */
 FORCE_INLINE_ATTR void mwdt_ll_set_prescaler(timg_dev_t *hw, uint32_t prescaler)
 {
-    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->wdt_config1, clk_prescale, prescaler);
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->wdtconfig1, wdt_clk_prescaler, prescaler);
 }
 
 /**
@@ -215,7 +210,7 @@ FORCE_INLINE_ATTR void mwdt_ll_set_prescaler(timg_dev_t *hw, uint32_t prescaler)
  */
 FORCE_INLINE_ATTR void mwdt_ll_feed(timg_dev_t *hw)
 {
-    hw->wdt_feed = 1;
+    hw->wdtfeed.wdt_feed = 1;
 }
 
 /**
@@ -225,7 +220,7 @@ FORCE_INLINE_ATTR void mwdt_ll_feed(timg_dev_t *hw)
  */
 FORCE_INLINE_ATTR void mwdt_ll_write_protect_enable(timg_dev_t *hw)
 {
-    hw->wdt_wprotect = 0;
+    hw->wdtwprotect.wdt_wkey = 0;
 }
 
 /**
@@ -235,7 +230,7 @@ FORCE_INLINE_ATTR void mwdt_ll_write_protect_enable(timg_dev_t *hw)
  */
 FORCE_INLINE_ATTR void mwdt_ll_write_protect_disable(timg_dev_t *hw)
 {
-    hw->wdt_wprotect = TIMG_WDT_WKEY_VALUE;
+    hw->wdtwprotect.wdt_wkey = TIMG_WDT_WKEY_VALUE;
 }
 
 /**
@@ -243,9 +238,9 @@ FORCE_INLINE_ATTR void mwdt_ll_write_protect_disable(timg_dev_t *hw)
  *
  * @param hw Start address of the peripheral registers.
  */
-FORCE_INLINE_ATTR void mwdt_ll_clear_intr_status(timg_dev_t* hw)
+FORCE_INLINE_ATTR void mwdt_ll_clear_intr_status(timg_dev_t *hw)
 {
-    hw->int_clr_timers.wdt = 1;
+    hw->int_clr_timers.wdt_int_clr = 1;
 }
 
 /**
@@ -254,9 +249,9 @@ FORCE_INLINE_ATTR void mwdt_ll_clear_intr_status(timg_dev_t* hw)
  * @param hw Beginning address of the peripheral registers.
  * @param enable Whether to enable the MWDT interrupt
  */
-FORCE_INLINE_ATTR void mwdt_ll_set_intr_enable(timg_dev_t* hw, bool enable)
+FORCE_INLINE_ATTR void mwdt_ll_set_intr_enable(timg_dev_t *hw, bool enable)
 {
-    hw->int_ena.wdt = (enable) ? 1 : 0;
+    hw->int_ena_timers.wdt_int_ena = enable;
 }
 
 #ifdef __cplusplus

components/hal/esp32/include/hal/timer_ll.h

@@ -1,382 +1,250 @@
-// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 
-// The LL layer for Timer Group register operations.
 // Note that most of the register operations in this layer are non-atomic operations.
 
 #pragma once
 
+#include <stdbool.h>
+#include "hal/assert.h"
+#include "hal/misc.h"
+#include "hal/timer_types.h"
+#include "soc/timer_group_struct.h"
+
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-#include <stdlib.h>
-#include "hal/misc.h"
-#include "hal/assert.h"
-#include "hal/timer_types.h"
-#include "soc/timer_periph.h"
-#include "soc/timer_group_struct.h"
-
-_Static_assert(TIMER_INTR_T0 == TIMG_T0_INT_CLR, "Add mapping to LL interrupt handling, since it's no longer naturally compatible with the timer_intr_t");
-_Static_assert(TIMER_INTR_T1 == TIMG_T1_INT_CLR, "Add mapping to LL interrupt handling, since it's no longer naturally compatible with the timer_intr_t");
-_Static_assert(TIMER_INTR_WDT == TIMG_WDT_INT_CLR, "Add mapping to LL interrupt handling, since it's no longer naturally compatible with the timer_intr_t");
-
-// Get timer group instance with giving group number
-#define TIMER_LL_GET_HW(num) ((num == 0) ? (&TIMERG0) : (&TIMERG1))
+// Get timer group register base address with giving group number
+#define TIMER_LL_GET_HW(group_id) ((group_id == 0) ? (&TIMERG0) : (&TIMERG1))
+#define TIMER_LL_EVENT_ALARM(timer_id) (1 << (timer_id))
 
 /**
- * @brief Set timer clock prescale value
+ * @brief Set clock source for timer
  *
- * @param hw Beginning address of the peripheral registers.
- * @param timer_num The timer number
- * @param divider Prescale value (0 and 1 are not valid)
- *
- * @return None
+ * @param hw Timer Group register base address
+ * @param timer_num Timer number in the group
+ * @param clk_src Clock source
  */
-static inline void timer_ll_set_divider(timg_dev_t *hw, timer_idx_t timer_num, uint32_t divider)
+static inline void timer_ll_set_clock_source(timg_dev_t *hw, uint32_t timer_num, gptimer_clock_source_t clk_src)
+{
+    switch (clk_src) {
+    case GPTIMER_CLK_SRC_APB:
+        break;
+    default:
+        HAL_ASSERT(false && "unsupported clock source");
+        break;
+    }
+}
+
+/**
+ * @brief Enable alarm event
+ *
+ * @param hw Timer Group register base address
+ * @param timer_num Timer number in the group
+ * @param en True: enable alarm
+ *           False: disable alarm
+ */
+__attribute__((always_inline))
+static inline void timer_ll_enable_alarm(timg_dev_t *hw, uint32_t timer_num, bool en)
+{
+    hw->hw_timer[timer_num].config.tx_alarm_en = en;
+    // use level type interrupt
+    hw->hw_timer[timer_num].config.tx_level_int_en = en;
+}
+
+/**
+ * @brief Set clock prescale for timer
+ *
+ * @param hw Timer Group register base address
+ * @param timer_num Timer number in the group
+ * @param divider Prescale value (0 and 1 are not valid)
+ */
+static inline void timer_ll_set_clock_prescale(timg_dev_t *hw, uint32_t timer_num, uint32_t divider)
 {
     HAL_ASSERT(divider >= 2 && divider <= 65536);
     if (divider >= 65536) {
         divider = 0;
     }
-    int timer_en = hw->hw_timer[timer_num].config.enable;
-    hw->hw_timer[timer_num].config.enable = 0;
-    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hw_timer[timer_num].config, divider, divider);
-    hw->hw_timer[timer_num].config.enable = timer_en;
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hw_timer[timer_num].config, tx_divider, divider);
 }
 
 /**
- * @brief Get timer clock prescale value
+ * @brief Enable auto-reload mode
  *
- * @param hw Beginning address of the peripheral registers.
- * @param timer_num The timer number
- * @param divider Pointer to accept the prescale value
- *
- * @return None
+ * @param hw Timer Group register base address
+ * @param timer_num Timer number in the group
+ * @param en True: enable auto reload mode
+ *           False: disable auto reload mode
  */
-static inline void timer_ll_get_divider(timg_dev_t *hw, timer_idx_t timer_num, uint32_t *divider)
+static inline void timer_ll_enable_auto_reload(timg_dev_t *hw, uint32_t timer_num, bool en)
 {
-    uint32_t d = HAL_FORCE_READ_U32_REG_FIELD(hw->hw_timer[timer_num].config, divider);
-    if (d == 0) {
-        d = 65536;
-    } else if (d == 1) {
-        d = 2;
+    hw->hw_timer[timer_num].config.tx_autoreload = en;
+}
+
+/**
+ * @brief Set count direction
+ *
+ * @param hw Timer peripheral register base address
+ * @param timer_num Timer number in the group
+ * @param direction Count direction
+ */
+static inline void timer_ll_set_count_direction(timg_dev_t *hw, uint32_t timer_num, gptimer_count_direction_t direction)
+{
+    hw->hw_timer[timer_num].config.tx_increase = direction == GPTIMER_COUNT_UP;
+}
+
+/**
+ * @brief Enable timer, start couting
+ *
+ * @param hw Timer Group register base address
+ * @param timer_num Timer number in the group
+ * @param en True: enable the counter
+ *           False: disable the counter
+ */
+__attribute__((always_inline))
+static inline void timer_ll_enable_counter(timg_dev_t *hw, uint32_t timer_num, bool en)
+{
+    hw->hw_timer[timer_num].config.tx_en = en;
+}
+
+/**
+ * @brief Get counter value
+ *
+ * @param hw Timer Group register base address
+ * @param timer_num Timer number in the group
+ *
+ * @return counter value
+ */
+__attribute__((always_inline))
+static inline uint64_t timer_ll_get_counter_value(timg_dev_t *hw, uint32_t timer_num)
+{
+    hw->hw_timer[timer_num].update.tx_update = 1;
+    // Timer register is in a different clock domain from Timer hardware logic
+    // We need to wait for the update to take effect before fetching the count value
+    while (hw->hw_timer[timer_num].update.tx_update) {
     }
-    *divider = d;
+    return ((uint64_t) hw->hw_timer[timer_num].hi.tx_hi << 32) | (hw->hw_timer[timer_num].lo.tx_lo);
 }
 
 /**
- * @brief Load counter value into time-base counter
+ * @brief Set alarm value
  *
- * @param hw Beginning address of the peripheral registers.
- * @param timer_num The timer number
- * @param load_val Counter value
- *
- * @return None
+ * @param hw Timer Group register base address
+ * @param timer_num Timer number in the group
+ * @param alarm_value When counter reaches alarm value, alarm event will be triggered
  */
-static inline void timer_ll_set_counter_value(timg_dev_t *hw, timer_idx_t timer_num, uint64_t load_val)
+__attribute__((always_inline))
+static inline void timer_ll_set_alarm_value(timg_dev_t *hw, uint32_t timer_num, uint64_t alarm_value)
 {
-    hw->hw_timer[timer_num].load_high = (uint32_t) (load_val >> 32);
-    hw->hw_timer[timer_num].load_low = (uint32_t) load_val;
-    hw->hw_timer[timer_num].reload = 1;
+    hw->hw_timer[timer_num].alarmhi.tx_alarm_hi = (uint32_t) (alarm_value >> 32);
+    hw->hw_timer[timer_num].alarmlo.tx_alarm_lo = (uint32_t) alarm_value;
 }
 
 /**
- * @brief Get counter value from time-base counter
+ * @brief Get alarm value
  *
- * @param hw Beginning address of the peripheral registers.
- * @param timer_num The timer number
- * @param timer_val Pointer to accept the counter value
- *
- * @return None
+ * @param hw Timer Group register base address
+ * @param timer_num Timer number in the group
+ * @return Counter value to trigger the alarm event
  */
-FORCE_INLINE_ATTR void timer_ll_get_counter_value(timg_dev_t *hw, timer_idx_t timer_num, uint64_t *timer_val)
+static inline uint64_t timer_ll_get_alarm_value(timg_dev_t *hw, uint32_t timer_num)
 {
-    hw->hw_timer[timer_num].update = 1;
-    while (hw->hw_timer[timer_num].update) {}
-    *timer_val = ((uint64_t) hw->hw_timer[timer_num].cnt_high << 32) | (hw->hw_timer[timer_num].cnt_low);
+    return ((uint64_t) hw->hw_timer[timer_num].alarmhi.tx_alarm_hi << 32) | (hw->hw_timer[timer_num].alarmlo.tx_alarm_lo);
 }
 
 /**
- * @brief Set counter mode, include increment mode and decrement mode.
+ * @brief Set reload value
  *
- * @param hw Beginning address of the peripheral registers.
- * @param timer_num The timer number
- * @param increase_en True to increment mode, fasle to decrement mode
- *
- * @return None
+ * @param hw Timer Group register base address
+ * @param timer_num Timer number in the group
+ * @param reload_val Reload counter value
  */
-static inline void timer_ll_set_counter_increase(timg_dev_t *hw, timer_idx_t timer_num, bool increase_en)
+static inline void timer_ll_set_reload_value(timg_dev_t *hw, uint32_t timer_num, uint64_t load_val)
 {
-    hw->hw_timer[timer_num].config.increase = increase_en;
+    hw->hw_timer[timer_num].loadhi.tx_load_hi = (uint32_t) (load_val >> 32);
+    hw->hw_timer[timer_num].loadlo.tx_load_lo = (uint32_t) load_val;
 }
 
 /**
- * @brief Get counter mode, include increment mode and decrement mode.
+ * @brief Get reload value
  *
- * @param hw Beginning address of the peripheral registers.
- * @param timer_num The timer number
- *
- * @return
- *     - true Increment mode
- *     - false Decrement mode
+ * @param hw Timer Group register base address
+ * @param timer_num Timer number in the group
+ * @return reload count value
  */
-static inline bool timer_ll_get_counter_increase(timg_dev_t *hw, timer_idx_t timer_num)
+static inline uint64_t timer_ll_get_reload_value(timg_dev_t *hw, uint32_t timer_num)
 {
-    return hw->hw_timer[timer_num].config.increase;
+    return ((uint64_t)hw->hw_timer[timer_num].loadhi.tx_load_hi << 32) | (hw->hw_timer[timer_num].loadlo.tx_load_lo);
 }
 
 /**
- * @brief Set counter status, enable or disable counter.
+ * @brief Trigger software reload, value set by `timer_ll_set_reload_value()` will be reflected into counter immediately
  *
- * @param hw Beginning address of the peripheral registers.
- * @param timer_num The timer number
- * @param counter_en True to enable counter, false to disable counter
- *
- * @return None
+ * @param hw Timer Group register base address
+ * @param timer_num Timer number in the group
  */
-FORCE_INLINE_ATTR void timer_ll_set_counter_enable(timg_dev_t *hw, timer_idx_t timer_num, bool counter_en)
+static inline void timer_ll_trigger_soft_reload(timg_dev_t *hw, uint32_t timer_num)
 {
-    hw->hw_timer[timer_num].config.enable = counter_en;
+    hw->hw_timer[timer_num].load.tx_load = 1;
 }
 
 /**
- * @brief Get counter status.
+ * @brief Enable timer interrupt by mask
  *
- * @param hw Beginning address of the peripheral registers.
- * @param timer_num The timer number
- *
- * @return
- *     - true Enable counter
- *     - false Disable conuter
+ * @param hw Timer Group register base address
+ * @param mask Mask of interrupt events
+ * @param en True: enable interrupt
+ *           False: disable interrupt
  */
-static inline bool timer_ll_get_counter_enable(timg_dev_t *hw, timer_idx_t timer_num)
+__attribute__((always_inline))
+static inline void timer_ll_enable_intr(timg_dev_t *hw, uint32_t mask, bool en)
 {
-    return hw->hw_timer[timer_num].config.enable;
+    if (en) {
+        hw->int_ena_timers.val |= mask;
+    } else {
+        hw->int_ena_timers.val &= ~mask;
+    }
 }
 
 /**
- * @brief Set auto reload mode.
+ * @brief Get interrupt status
  *
- * @param hw Beginning address of the peripheral registers.
- * @param timer_num The timer number
- * @param auto_reload_en True to enable auto reload mode, flase to disable auto reload mode
+ * @param hw Timer Group register base address
  *
- * @return None
+ * @return Interrupt status
  */
-static inline void timer_ll_set_auto_reload(timg_dev_t *hw, timer_idx_t timer_num, bool auto_reload_en)
+__attribute__((always_inline))
+static inline uint32_t timer_ll_get_intr_status(timg_dev_t *hw)
 {
-    hw->hw_timer[timer_num].config.autoreload = auto_reload_en;
+    return hw->int_st_timers.val & 0x03;
 }
 
 /**
- * @brief Get auto reload mode.
+ * @brief Clear interrupt status by mask
  *
- * @param hw Beginning address of the peripheral registers.
- * @param timer_num The timer number
- *
- * @return
- *     - true Enable auto reload mode
- *     - false Disable auto reload mode
+ * @param hw Timer Group register base address
+ * @param mask Interrupt events mask
  */
-FORCE_INLINE_ATTR bool timer_ll_get_auto_reload(timg_dev_t *hw, timer_idx_t timer_num)
+__attribute__((always_inline))
+static inline void timer_ll_clear_intr_status(timg_dev_t *hw, uint32_t mask)
 {
-    return hw->hw_timer[timer_num].config.autoreload;
+    hw->int_clr_timers.val = mask;
 }
 
 /**
- * @brief Set the counter value to trigger the alarm.
+ * @brief Enable the register clock forever
  *
- * @param hw Beginning address of the peripheral registers.
- * @param timer_num The timer number
- * @param alarm_value Counter value to trigger the alarm
- *
- * @return None
+ * @param hw Timer Group register base address
+ * @param en True: Enable the register clock forever
+ *           False: Register clock is enabled only when register operation happens
  */
-FORCE_INLINE_ATTR void timer_ll_set_alarm_value(timg_dev_t *hw, timer_idx_t timer_num, uint64_t alarm_value)
+static inline void timer_ll_enable_register_clock_always_on(timg_dev_t *hw, bool en)
 {
-    hw->hw_timer[timer_num].alarm_high = (uint32_t) (alarm_value >> 32);
-    hw->hw_timer[timer_num].alarm_low = (uint32_t) alarm_value;
-}
-
-/**
- * @brief Get the counter value to trigger the alarm.
- *
- * @param hw Beginning address of the peripheral registers.
- * @param timer_num The timer number
- * @param alarm_value Pointer to accept the counter value to trigger the alarm
- *
- * @return None
- */
-static inline void timer_ll_get_alarm_value(timg_dev_t *hw, timer_idx_t timer_num, uint64_t *alarm_value)
-{
-    *alarm_value = ((uint64_t) hw->hw_timer[timer_num].alarm_high << 32) | (hw->hw_timer[timer_num].alarm_low);
-}
-
-/**
- * @brief Set the alarm status, enable or disable the alarm.
- *
- * @param hw Beginning address of the peripheral registers.
- * @param timer_num The timer number
- * @param alarm_en True to enable alarm, false to disable alarm
- *
- * @return None
- */
-FORCE_INLINE_ATTR void timer_ll_set_alarm_enable(timg_dev_t *hw, timer_idx_t timer_num, bool alarm_en)
-{
-    hw->hw_timer[timer_num].config.alarm_en = alarm_en;
-}
-
-/**
- * @brief Get the alarm status.
- *
- * @param hw Beginning address of the peripheral registers.
- * @param timer_num The timer number
- *
- * @return
- *     - true Enable alarm
- *     - false Disable alarm
- */
-static inline bool timer_ll_get_alarm_enable(timg_dev_t *hw, timer_idx_t timer_num)
-{
-    return hw->hw_timer[timer_num].config.alarm_en;
-}
-
-/**
- * @brief Enable timer interrupt.
- *
- * @param hw Beginning address of the peripheral registers.
- * @param timer_num The timer number
- *
- * @return None
- */
-FORCE_INLINE_ATTR void timer_ll_intr_enable(timg_dev_t *hw, timer_idx_t timer_num)
-{
-    hw->int_ena.val |= BIT(timer_num);
-    hw->hw_timer[timer_num].config.level_int_en = 1;
-}
-
-/**
- * @brief Disable timer interrupt.
- *
- * @param hw Beginning address of the peripheral registers.
- * @param timer_num The timer number
- *
- * @return None
- */
-FORCE_INLINE_ATTR void timer_ll_intr_disable(timg_dev_t *hw, timer_idx_t timer_num)
-{
-    hw->int_ena.val &= (~BIT(timer_num));
-    hw->hw_timer[timer_num].config.level_int_en = 0;
-}
-
-/**
- * @brief Disable timer interrupt.
- *
- * @param hw Beginning address of the peripheral registers.
- * @param timer_num The timer number
- *
- * @return None
- */
-FORCE_INLINE_ATTR void timer_ll_clear_intr_status(timg_dev_t *hw, timer_idx_t timer_num)
-{
-    hw->int_clr_timers.val |= BIT(timer_num);
-}
-
-/**
- * @brief Get interrupt status.
- *
- * @param hw Beginning address of the peripheral registers.
- * @param intr_status Interrupt status
- *
- * @return None
- */
-FORCE_INLINE_ATTR void timer_ll_get_intr_status(timg_dev_t *hw, uint32_t *intr_status)
-{
-    *intr_status = hw->int_st_timers.val & 0x03;
-}
-
-/**
- * @brief Get interrupt raw status.
- *
- * @param group_num Timer group number, 0 for TIMERG0 or 1 for TIMERG1
- * @param intr_raw_status Interrupt raw status
- *
- * @return None
- */
-FORCE_INLINE_ATTR void timer_ll_get_intr_raw_status(timer_group_t group_num, uint32_t *intr_raw_status)
-{
-    timg_dev_t *hw = TIMER_LL_GET_HW(group_num);
-    *intr_raw_status = hw->int_raw.val & 0x03;
-}
-
-/**
- * @brief Set the level interrupt status, enable or disable the level interrupt.
- *
- * @param hw Beginning address of the peripheral registers.
- * @param timer_num The timer number
- * @param level_int_en True to enable level interrupt, false to disable level interrupt
- *
- * @return None
- */
-static inline void timer_ll_set_level_int_enable(timg_dev_t *hw, timer_idx_t timer_num, bool level_int_en)
-{
-    hw->hw_timer[timer_num].config.level_int_en = level_int_en;
-}
-
-/**
- * @brief Get the level interrupt status.
- *
- * @param hw Beginning address of the peripheral registers.
- * @param timer_num The timer number
- *
- * @return
- *     - true Enable level interrupt
- *     - false Disable level interrupt
- */
-static inline bool timer_ll_get_level_int_enable(timg_dev_t *hw, timer_idx_t timer_num)
-{
-    return hw->hw_timer[timer_num].config.level_int_en;
-}
-
-/**
- * @brief Set the edge interrupt status, enable or disable the edge interrupt.
- *
- * @param hw Beginning address of the peripheral registers.
- * @param timer_num The timer number
- * @param edge_int_en True to enable edge interrupt, false to disable edge interrupt
- *
- * @return None
- */
-static inline void timer_ll_set_edge_int_enable(timg_dev_t *hw, timer_idx_t timer_num, bool edge_int_en)
-{
-    hw->hw_timer[timer_num].config.edge_int_en = edge_int_en;
-}
-
-/**
- * @brief Get the edge interrupt status.
- *
- * @param hw Beginning address of the peripheral registers.
- * @param timer_num The timer number
- *
- * @return
- *     - true Enable edge interrupt
- *     - false Disable edge interrupt
- */
-static inline bool timer_ll_get_edge_int_enable(timg_dev_t *hw, timer_idx_t timer_num)
-{
-    return hw->hw_timer[timer_num].config.edge_int_en;
+    hw->regclk.clk_en = en;
 }
 
 /**
@@ -386,14 +254,9 @@ static inline bool timer_ll_get_edge_int_enable(timg_dev_t *hw, timer_idx_t time
  *
  * @return Interrupt status register address
  */
-static inline uint32_t timer_ll_get_intr_status_reg(timg_dev_t *hw)
+static inline volatile void *timer_ll_get_intr_status_reg(timg_dev_t *hw)
 {
-    return (uint32_t) & (hw->int_st_timers.val);
-}
-
-static inline uint32_t timer_ll_get_intr_mask_bit(timg_dev_t *hw, timer_idx_t timer_num)
-{
-    return (1U << timer_num);
+    return &hw->int_st_timers.val;
 }
 
 #ifdef __cplusplus