diff --git a/components/driver/Kconfig b/components/driver/Kconfig
index b8b3bf3b9f..e54029b894 100644
--- a/components/driver/Kconfig
+++ b/components/driver/Kconfig
@@ -1,4 +1,4 @@
-menu "Driver Configurations"
+menu "Legacy Driver Configurations"
 
     orsource "./twai/Kconfig.twai"
 
diff --git a/components/driver/deprecated/driver/periph_ctrl.h b/components/driver/deprecated/driver/periph_ctrl.h
deleted file mode 100644
index 4077aacab8..0000000000
--- a/components/driver/deprecated/driver/periph_ctrl.h
+++ /dev/null
@@ -1,8 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-#warning driver/periph_ctrl.h header is no longer used, and will be removed in future versions.
-#include "esp_private/periph_ctrl.h"
diff --git a/components/driver/deprecated/driver/rtc_cntl.h b/components/driver/deprecated/driver/rtc_cntl.h
deleted file mode 100644
index 3bf2a5d8cf..0000000000
--- a/components/driver/deprecated/driver/rtc_cntl.h
+++ /dev/null
@@ -1,8 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-#warning driver/rtc_cntl.h header is no longer used, and will be removed in future versions.
-#include "esp_private/rtc_ctrl.h"
diff --git a/components/esp_driver_bitscrambler/Kconfig b/components/esp_driver_bitscrambler/Kconfig
index 7efdc2e17c..ff496db2ba 100644
--- a/components/esp_driver_bitscrambler/Kconfig
+++ b/components/esp_driver_bitscrambler/Kconfig
@@ -1,4 +1,4 @@
-menu "BitScrambler Configurations"
+menu "ESP-Driver:BitScrambler Configurations"
     depends on SOC_BITSCRAMBLER_SUPPORTED
     config BITSCRAMBLER_CTRL_FUNC_IN_IRAM
         bool "Place BitScrambler control functions in IRAM"
diff --git a/components/soc/esp32p4/include/soc/clk_tree_defs.h b/components/soc/esp32p4/include/soc/clk_tree_defs.h
index 4a1913ed47..80864fd0a8 100644
--- a/components/soc/esp32p4/include/soc/clk_tree_defs.h
+++ b/components/soc/esp32p4/include/soc/clk_tree_defs.h
@@ -396,7 +396,7 @@ typedef enum {
     LCD_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default choice */
 } soc_periph_lcd_clk_src_t;
 
-//////////////////////////////////////////////////LCD///////////////////////////////////////////////////////////////////
+//////////////////////////////////////////////////CAM///////////////////////////////////////////////////////////////////
 
 /**
  * @brief Array initializer for all supported clock sources of CAM
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/bitscrambler_eco5_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/bitscrambler_eco5_struct.h
deleted file mode 100644
index 904de77a89..0000000000
--- a/components/soc/esp32p4/register/hw_ver3/soc/bitscrambler_eco5_struct.h
+++ /dev/null
@@ -1,437 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: Control and configuration registers */
-/** Type of tx_inst_cfg0 register
- *  Control and configuration registers
- */
-typedef union {
-    struct {
-        /** tx_inst_idx : R/W; bitpos: [2:0]; default: 0;
-         *  write this bits to specify the one of 8 instruction
-         */
-        uint32_t tx_inst_idx:3;
-        /** tx_inst_pos : R/W; bitpos: [6:3]; default: 0;
-         *  write this bits to specify the bit position of 257 bit instruction which in units
-         *  of 32 bits
-         */
-        uint32_t tx_inst_pos:4;
-        uint32_t reserved_7:25;
-    };
-    uint32_t val;
-} bitscrambler_tx_inst_cfg0_reg_t;
-
-/** Type of tx_inst_cfg1 register
- *  Control and configuration registers
- */
-typedef union {
-    struct {
-        /** tx_inst : R/W; bitpos: [31:0]; default: 4;
-         *  write this bits to update instruction which specified by
-         *  BITSCRAMBLER_TX_INST_CFG0_REG, Read this bits to get instruction which specified by
-         *  BITSCRAMBLER_TX_INST_CFG0_REG
-         */
-        uint32_t tx_inst:32;
-    };
-    uint32_t val;
-} bitscrambler_tx_inst_cfg1_reg_t;
-
-/** Type of rx_inst_cfg0 register
- *  Control and configuration registers
- */
-typedef union {
-    struct {
-        /** rx_inst_idx : R/W; bitpos: [2:0]; default: 0;
-         *  write this bits to specify the one of 8 instruction
-         */
-        uint32_t rx_inst_idx:3;
-        /** rx_inst_pos : R/W; bitpos: [6:3]; default: 0;
-         *  write this bits to specify the bit position of 257 bit instruction which in units
-         *  of 32 bits
-         */
-        uint32_t rx_inst_pos:4;
-        uint32_t reserved_7:25;
-    };
-    uint32_t val;
-} bitscrambler_rx_inst_cfg0_reg_t;
-
-/** Type of rx_inst_cfg1 register
- *  Control and configuration registers
- */
-typedef union {
-    struct {
-        /** rx_inst : R/W; bitpos: [31:0]; default: 12;
-         *  write this bits to update instruction which specified by
-         *  BITSCRAMBLER_RX_INST_CFG0_REG, Read this bits to get instruction which specified by
-         *  BITSCRAMBLER_RX_INST_CFG0_REG
-         */
-        uint32_t rx_inst:32;
-    };
-    uint32_t val;
-} bitscrambler_rx_inst_cfg1_reg_t;
-
-/** Type of tx_lut_cfg0 register
- *  Control and configuration registers
- */
-typedef union {
-    struct {
-        /** tx_lut_idx : R/W; bitpos: [10:0]; default: 0;
-         *  write this bits to specify the bytes position of LUT RAM based on
-         *  reg_bitscrambler_tx_lut_mode
-         */
-        uint32_t tx_lut_idx:11;
-        /** tx_lut_mode : R/W; bitpos: [12:11]; default: 0;
-         *  write this bits to specify the bytes mode of LUT RAM, 0: 1 byte,1: 2bytes, 2: 4
-         *  bytes
-         */
-        uint32_t tx_lut_mode:2;
-        uint32_t reserved_13:19;
-    };
-    uint32_t val;
-} bitscrambler_tx_lut_cfg0_reg_t;
-
-/** Type of tx_lut_cfg1 register
- *  Control and configuration registers
- */
-typedef union {
-    struct {
-        /** tx_lut : R/W; bitpos: [31:0]; default: 20;
-         *  write this bits to update LUT which specified by BITSCRAMBLER_TX_LUT_CFG0_REG, Read
-         *  this bits to get LUT which specified by BITSCRAMBLER_TX_LUT_CFG0_REG
-         */
-        uint32_t tx_lut:32;
-    };
-    uint32_t val;
-} bitscrambler_tx_lut_cfg1_reg_t;
-
-/** Type of rx_lut_cfg0 register
- *  Control and configuration registers
- */
-typedef union {
-    struct {
-        /** rx_lut_idx : R/W; bitpos: [10:0]; default: 0;
-         *  write this bits to specify the bytes position of LUT RAM based on
-         *  reg_bitscrambler_rx_lut_mode
-         */
-        uint32_t rx_lut_idx:11;
-        /** rx_lut_mode : R/W; bitpos: [12:11]; default: 0;
-         *  write this bits to specify the bytes mode of LUT RAM, 0: 1 byte,1: 2bytes, 2: 4
-         *  bytes
-         */
-        uint32_t rx_lut_mode:2;
-        uint32_t reserved_13:19;
-    };
-    uint32_t val;
-} bitscrambler_rx_lut_cfg0_reg_t;
-
-/** Type of rx_lut_cfg1 register
- *  Control and configuration registers
- */
-typedef union {
-    struct {
-        /** rx_lut : R/W; bitpos: [31:0]; default: 28;
-         *  write this bits to update LUT which specified by BITSCRAMBLER_RX_LUT_CFG0_REG, Read
-         *  this bits to get LUT which specified by BITSCRAMBLER_RX_LUT_CFG0_REG
-         */
-        uint32_t rx_lut:32;
-    };
-    uint32_t val;
-} bitscrambler_rx_lut_cfg1_reg_t;
-
-
-/** Group: Configuration registers */
-/** Type of tx_tailing_bits register
- *  Control and configuration registers
- */
-typedef union {
-    struct {
-        /** tx_tailing_bits : R/W; bitpos: [15:0]; default: 0;
-         *  write this bits to specify the extra data bit length after getting EOF
-         */
-        uint32_t tx_tailing_bits:16;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} bitscrambler_tx_tailing_bits_reg_t;
-
-/** Type of rx_tailing_bits register
- *  Control and configuration registers
- */
-typedef union {
-    struct {
-        /** rx_tailing_bits : R/W; bitpos: [15:0]; default: 0;
-         *  write this bits to specify the extra data bit length after getting EOF
-         */
-        uint32_t rx_tailing_bits:16;
-        uint32_t reserved_16:16;
-    };
-    uint32_t val;
-} bitscrambler_rx_tailing_bits_reg_t;
-
-/** Type of tx_ctrl register
- *  Control and configuration registers
- */
-typedef union {
-    struct {
-        /** tx_ena : R/W; bitpos: [0]; default: 0;
-         *  write this bit to enable the bitscrambler tx
-         */
-        uint32_t tx_ena:1;
-        /** tx_pause : R/W; bitpos: [1]; default: 0;
-         *  write this bit to pause the bitscrambler tx core
-         */
-        uint32_t tx_pause:1;
-        /** tx_halt : R/W; bitpos: [2]; default: 1;
-         *  write this bit to halt the bitscrambler tx core
-         */
-        uint32_t tx_halt:1;
-        /** tx_eof_mode : R/W; bitpos: [3]; default: 0;
-         *  write this bit to ser the bitscrambler tx core EOF signal generating mode which is
-         *  combined with reg_bitscrambler_tx_tailing_bits, 0: counter by read dma fifo, 0
-         *  counter by write peripheral buffer
-         */
-        uint32_t tx_eof_mode:1;
-        /** tx_cond_mode : R/W; bitpos: [4]; default: 0;
-         *  write this bit to specify the LOOP instruction condition mode of bitscrambler tx
-         *  core, 0: use the little than operator to get the condition, 1: use not equal
-         *  operator to get the condition
-         */
-        uint32_t tx_cond_mode:1;
-        /** tx_fetch_mode : R/W; bitpos: [5]; default: 0;
-         *  write this bit to set the bitscrambler tx core fetch instruction mode, 0: prefetch
-         *  by reset, 1: fetch by instructions
-         */
-        uint32_t tx_fetch_mode:1;
-        /** tx_halt_mode : R/W; bitpos: [6]; default: 0;
-         *  write this bit to set the bitscrambler tx core halt mode when tx_halt is set, 0:
-         *  wait write data back done, , 1: ignore write data back
-         */
-        uint32_t tx_halt_mode:1;
-        /** tx_rd_dummy : R/W; bitpos: [7]; default: 0;
-         *  write this bit to set the bitscrambler tx core read data mode when EOF received.0:
-         *  wait read data, 1: ignore read data
-         */
-        uint32_t tx_rd_dummy:1;
-        /** tx_fifo_rst : WT; bitpos: [8]; default: 0;
-         *  write this bit to reset the bitscrambler tx fifo
-         */
-        uint32_t tx_fifo_rst:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} bitscrambler_tx_ctrl_reg_t;
-
-/** Type of rx_ctrl register
- *  Control and configuration registers
- */
-typedef union {
-    struct {
-        /** rx_ena : R/W; bitpos: [0]; default: 0;
-         *  write this bit to enable the bitscrambler rx
-         */
-        uint32_t rx_ena:1;
-        /** rx_pause : R/W; bitpos: [1]; default: 0;
-         *  write this bit to pause the bitscrambler rx core
-         */
-        uint32_t rx_pause:1;
-        /** rx_halt : R/W; bitpos: [2]; default: 1;
-         *  write this bit to halt the bitscrambler rx core
-         */
-        uint32_t rx_halt:1;
-        /** rx_eof_mode : R/W; bitpos: [3]; default: 0;
-         *  write this bit to ser the bitscrambler rx core EOF signal generating mode which is
-         *  combined with reg_bitscrambler_rx_tailing_bits, 0: counter by read peripheral
-         *  buffer, 0 counter by write dma fifo
-         */
-        uint32_t rx_eof_mode:1;
-        /** rx_cond_mode : R/W; bitpos: [4]; default: 0;
-         *  write this bit to specify the LOOP instruction condition mode of bitscrambler rx
-         *  core, 0: use the little than operator to get the condition, 1: use not equal
-         *  operator to get the condition
-         */
-        uint32_t rx_cond_mode:1;
-        /** rx_fetch_mode : R/W; bitpos: [5]; default: 0;
-         *  write this bit to set the bitscrambler rx core fetch instruction mode, 0: prefetch
-         *  by reset, 1: fetch by instructions
-         */
-        uint32_t rx_fetch_mode:1;
-        /** rx_halt_mode : R/W; bitpos: [6]; default: 0;
-         *  write this bit to set the bitscrambler rx core halt mode when rx_halt is set, 0:
-         *  wait write data back done, , 1: ignore write data back
-         */
-        uint32_t rx_halt_mode:1;
-        /** rx_rd_dummy : R/W; bitpos: [7]; default: 0;
-         *  write this bit to set the bitscrambler rx core read data mode when EOF received.0:
-         *  wait read data, 1: ignore read data
-         */
-        uint32_t rx_rd_dummy:1;
-        /** rx_fifo_rst : WT; bitpos: [8]; default: 0;
-         *  write this bit to reset the bitscrambler rx fifo
-         */
-        uint32_t rx_fifo_rst:1;
-        uint32_t reserved_9:23;
-    };
-    uint32_t val;
-} bitscrambler_rx_ctrl_reg_t;
-
-/** Type of sys register
- *  Control and configuration registers
- */
-typedef union {
-    struct {
-        /** loop_mode : R/W; bitpos: [0]; default: 0;
-         *  write this bit to set the bitscrambler tx loop back to DMA rx
-         */
-        uint32_t loop_mode:1;
-        uint32_t reserved_1:30;
-        /** clk_en : R/W; bitpos: [31]; default: 0;
-         *  Reserved
-         */
-        uint32_t clk_en:1;
-    };
-    uint32_t val;
-} bitscrambler_sys_reg_t;
-
-
-/** Group: Status registers */
-/** Type of tx_state register
- *  Status registers
- */
-typedef union {
-    struct {
-        /** tx_in_idle : RO; bitpos: [0]; default: 1;
-         *  represents the bitscrambler tx core in halt mode
-         */
-        uint32_t tx_in_idle:1;
-        /** tx_in_run : RO; bitpos: [1]; default: 0;
-         *  represents the bitscrambler tx core in run mode
-         */
-        uint32_t tx_in_run:1;
-        /** tx_in_wait : RO; bitpos: [2]; default: 0;
-         *  represents the bitscrambler tx core in wait mode to wait write back done
-         */
-        uint32_t tx_in_wait:1;
-        /** tx_in_pause : RO; bitpos: [3]; default: 0;
-         *  represents the bitscrambler tx core in pause mode
-         */
-        uint32_t tx_in_pause:1;
-        /** tx_fifo_empty : RO; bitpos: [4]; default: 0;
-         *  represents the bitscrambler tx fifo in empty state
-         */
-        uint32_t tx_fifo_empty:1;
-        uint32_t reserved_5:11;
-        /** tx_eof_get_cnt : RO; bitpos: [29:16]; default: 0;
-         *  represents the bytes numbers of bitscrambler tx core when get EOF
-         */
-        uint32_t tx_eof_get_cnt:14;
-        /** tx_eof_overload : RO; bitpos: [30]; default: 0;
-         *  represents the some EOFs will be lost for bitscrambler tx core
-         */
-        uint32_t tx_eof_overload:1;
-        /** tx_eof_trace_clr : WT; bitpos: [31]; default: 0;
-         *  write this bit to clear reg_bitscrambler_tx_eof_overload and
-         *  reg_bitscrambler_tx_eof_get_cnt registers
-         */
-        uint32_t tx_eof_trace_clr:1;
-    };
-    uint32_t val;
-} bitscrambler_tx_state_reg_t;
-
-/** Type of rx_state register
- *  Status registers
- */
-typedef union {
-    struct {
-        /** rx_in_idle : RO; bitpos: [0]; default: 1;
-         *  represents the bitscrambler rx core in halt mode
-         */
-        uint32_t rx_in_idle:1;
-        /** rx_in_run : RO; bitpos: [1]; default: 0;
-         *  represents the bitscrambler rx core in run mode
-         */
-        uint32_t rx_in_run:1;
-        /** rx_in_wait : RO; bitpos: [2]; default: 0;
-         *  represents the bitscrambler rx core in wait mode to wait write back done
-         */
-        uint32_t rx_in_wait:1;
-        /** rx_in_pause : RO; bitpos: [3]; default: 0;
-         *  represents the bitscrambler rx core in pause mode
-         */
-        uint32_t rx_in_pause:1;
-        /** rx_fifo_full : RO; bitpos: [4]; default: 0;
-         *  represents the bitscrambler rx fifo in full state
-         */
-        uint32_t rx_fifo_full:1;
-        uint32_t reserved_5:11;
-        /** rx_eof_get_cnt : RO; bitpos: [29:16]; default: 0;
-         *  represents the bytes numbers of bitscrambler rx core when get EOF
-         */
-        uint32_t rx_eof_get_cnt:14;
-        /** rx_eof_overload : RO; bitpos: [30]; default: 0;
-         *  represents the some EOFs will be lost for bitscrambler rx core
-         */
-        uint32_t rx_eof_overload:1;
-        /** rx_eof_trace_clr : WT; bitpos: [31]; default: 0;
-         *  write this bit to clear reg_bitscrambler_rx_eof_overload and
-         *  reg_bitscrambler_rx_eof_get_cnt registers
-         */
-        uint32_t rx_eof_trace_clr:1;
-    };
-    uint32_t val;
-} bitscrambler_rx_state_reg_t;
-
-
-/** Group: Version register */
-/** Type of version register
- *  Control and configuration registers
- */
-typedef union {
-    struct {
-        /** bitscrambler_ver : R/W; bitpos: [27:0]; default: 36713024;
-         *  Reserved
-         */
-        uint32_t bitscrambler_ver:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} bitscrambler_version_reg_t;
-
-
-typedef struct {
-    volatile bitscrambler_tx_inst_cfg0_reg_t tx_inst_cfg0;
-    volatile bitscrambler_tx_inst_cfg1_reg_t tx_inst_cfg1;
-    volatile bitscrambler_rx_inst_cfg0_reg_t rx_inst_cfg0;
-    volatile bitscrambler_rx_inst_cfg1_reg_t rx_inst_cfg1;
-    volatile bitscrambler_tx_lut_cfg0_reg_t tx_lut_cfg0;
-    volatile bitscrambler_tx_lut_cfg1_reg_t tx_lut_cfg1;
-    volatile bitscrambler_rx_lut_cfg0_reg_t rx_lut_cfg0;
-    volatile bitscrambler_rx_lut_cfg1_reg_t rx_lut_cfg1;
-    volatile bitscrambler_tx_tailing_bits_reg_t tx_tailing_bits;
-    volatile bitscrambler_rx_tailing_bits_reg_t rx_tailing_bits;
-    volatile bitscrambler_tx_ctrl_reg_t tx_ctrl;
-    volatile bitscrambler_rx_ctrl_reg_t rx_ctrl;
-    volatile bitscrambler_tx_state_reg_t tx_state;
-    volatile bitscrambler_rx_state_reg_t rx_state;
-    uint32_t reserved_038[48];
-    volatile bitscrambler_sys_reg_t sys;
-    volatile bitscrambler_version_reg_t version;
-} bitscrambler_dev_t;
-
-extern bitscrambler_dev_t BITSCRAMBLER;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(bitscrambler_dev_t) == 0x100, "Invalid size of bitscrambler_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/lcd_cam_eco5_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/lcd_cam_eco5_struct.h
deleted file mode 100644
index 6864fab433..0000000000
--- a/components/soc/esp32p4/register/hw_ver3/soc/lcd_cam_eco5_struct.h
+++ /dev/null
@@ -1,875 +0,0 @@
-/**
- * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
- *
- *  SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Group: lcd configuration registers */
-/** Type of lcd_clock register
- *  LCD clock config register.
- */
-typedef union {
-    struct {
-        /** lcd_clkcnt_n : R/W; bitpos: [5:0]; default: 3;
-         *  f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1) when reg_clk_equ_sysclk is 0.
-         */
-        uint32_t lcd_clkcnt_n:6;
-        /** lcd_clk_equ_sysclk : R/W; bitpos: [6]; default: 1;
-         *  1: f_LCD_PCLK = f_LCD_CLK. 0: f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1).
-         */
-        uint32_t lcd_clk_equ_sysclk:1;
-        /** lcd_ck_idle_edge : R/W; bitpos: [7]; default: 0;
-         *  1: LCD_PCLK line is high when idle     0: LCD_PCLK line is low when idle.
-         */
-        uint32_t lcd_ck_idle_edge:1;
-        /** lcd_ck_out_edge : R/W; bitpos: [8]; default: 0;
-         *  1: LCD_PCLK line is high in the first half data cycle.     0: LCD_PCLK line is low
-         *  in the second half data cycle.
-         */
-        uint32_t lcd_ck_out_edge:1;
-        /** lcd_clkm_div_num : R/W; bitpos: [16:9]; default: 4;
-         *  Integral LCD clock divider value
-         */
-        uint32_t lcd_clkm_div_num:8;
-        /** lcd_clkm_div_b : R/W; bitpos: [22:17]; default: 0;
-         *  Fractional clock divider numerator value
-         */
-        uint32_t lcd_clkm_div_b:6;
-        /** lcd_clkm_div_a : R/W; bitpos: [28:23]; default: 0;
-         *  Fractional clock divider denominator value
-         */
-        uint32_t lcd_clkm_div_a:6;
-        /** lcd_clk_sel : R/W; bitpos: [30:29]; default: 0;
-         *  Select LCD module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock.
-         */
-        uint32_t lcd_clk_sel:2;
-        /** clk_en : R/W; bitpos: [31]; default: 0;
-         *  Set this bit to enable clk gate
-         */
-        uint32_t clk_en:1;
-    };
-    uint32_t val;
-} lcdcam_lcd_clock_reg_t;
-
-/** Type of lcd_rgb_yuv register
- *  LCD YUV/RGB converter configuration register.
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:18;
-        /** lcd_conv_rgb2rgb_mode : R/W; bitpos: [19:18]; default: 3;
-         *  0:rgb888 trans to rgb565. 1:rgb565 trans to rgb888.2,3:disabled
-         */
-        uint32_t lcd_conv_rgb2rgb_mode:2;
-        /** lcd_conv_8bits_data_inv : R/W; bitpos: [20]; default: 0;
-         *  1:invert every two 8bits input data. 2. disabled.
-         */
-        uint32_t lcd_conv_8bits_data_inv:1;
-        /** lcd_conv_txtorx : R/W; bitpos: [21]; default: 0;
-         *  0: txtorx mode off. 1: txtorx mode on.
-         */
-        uint32_t lcd_conv_txtorx:1;
-        /** lcd_conv_yuv2yuv_mode : R/W; bitpos: [23:22]; default: 3;
-         *  0: to yuv422.  2: to yuv411. 1,3: disabled.  To enable yuv2yuv mode, trans_mode
-         *  must be set to 1.
-         */
-        uint32_t lcd_conv_yuv2yuv_mode:2;
-        /** lcd_conv_yuv_mode : R/W; bitpos: [25:24]; default: 0;
-         *  0: yuv422. 2: yuv411. When in yuv2yuv mode, yuv_mode decides the yuv mode of Data_in
-         */
-        uint32_t lcd_conv_yuv_mode:2;
-        /** lcd_conv_protocol_mode : R/W; bitpos: [26]; default: 0;
-         *  0:BT601. 1:BT709.
-         */
-        uint32_t lcd_conv_protocol_mode:1;
-        /** lcd_conv_data_out_mode : R/W; bitpos: [27]; default: 0;
-         *  LIMIT or FULL mode of Data out. 0: limit. 1: full
-         */
-        uint32_t lcd_conv_data_out_mode:1;
-        /** lcd_conv_data_in_mode : R/W; bitpos: [28]; default: 0;
-         *  LIMIT or FULL mode of Data in. 0: limit. 1: full
-         */
-        uint32_t lcd_conv_data_in_mode:1;
-        /** lcd_conv_mode_8bits_on : R/W; bitpos: [29]; default: 0;
-         *  0: 16bits mode. 1: 8bits mode.
-         */
-        uint32_t lcd_conv_mode_8bits_on:1;
-        /** lcd_conv_trans_mode : R/W; bitpos: [30]; default: 0;
-         *  0: YUV to RGB. 1: RGB to YUV.
-         */
-        uint32_t lcd_conv_trans_mode:1;
-        /** lcd_conv_enable : R/W; bitpos: [31]; default: 0;
-         *  0: Bypass converter. 1: Enable converter.
-         */
-        uint32_t lcd_conv_enable:1;
-    };
-    uint32_t val;
-} lcdcam_lcd_rgb_yuv_reg_t;
-
-/** Type of lcd_user register
- *  LCD config register.
- */
-typedef union {
-    struct {
-        /** lcd_dout_cyclelen : R/W; bitpos: [12:0]; default: 1;
-         *  The output data cycles minus 1 of LCD module.
-         */
-        uint32_t lcd_dout_cyclelen:13;
-        /** lcd_always_out_en : R/W; bitpos: [13]; default: 0;
-         *  LCD always output when LCD is in LCD_DOUT state, unless reg_lcd_start is cleared or
-         *  reg_lcd_reset is set.
-         */
-        uint32_t lcd_always_out_en:1;
-        /** lcd_dout_byte_swizzle_mode : R/W; bitpos: [16:14]; default: 0;
-         *  0: ABAB->BABA. 1: ABC->ACB. 2: ABC->BAC. 3: ABC->BCA. 4:ABC->CAB. 5:ABC->CBA
-         */
-        uint32_t lcd_dout_byte_swizzle_mode:3;
-        /** lcd_dout_byte_swizzle_enable : R/W; bitpos: [17]; default: 0;
-         *  1: enable byte swizzle 0: disable
-         */
-        uint32_t lcd_dout_byte_swizzle_enable:1;
-        /** lcd_dout_bit_order : R/W; bitpos: [18]; default: 0;
-         *  1: change bit order in every byte. 0: Not change.
-         */
-        uint32_t lcd_dout_bit_order:1;
-        /** lcd_byte_mode : R/W; bitpos: [20:19]; default: 0;
-         *  2: 24bit mode. 1: 16bit mode. 0: 8bit mode
-         */
-        uint32_t lcd_byte_mode:2;
-        /** lcd_update_reg : R/W/SC; bitpos: [21]; default: 0;
-         *  1: Update LCD registers, will be cleared by hardware. 0 : Not care.
-         */
-        uint32_t lcd_update_reg:1;
-        /** lcd_bit_order : R/W; bitpos: [22]; default: 0;
-         *  1: Change data bit order, change LCD_DATA_out[7:0] to LCD_DATA_out[0:7] in one byte
-         *  mode, and bits[15:0] to bits[0:15] in two byte mode.  0: Not change.
-         */
-        uint32_t lcd_bit_order:1;
-        /** lcd_byte_order : R/W; bitpos: [23]; default: 0;
-         *  1: invert data byte order, only valid in 2 byte mode. 0: Not change.
-         */
-        uint32_t lcd_byte_order:1;
-        /** lcd_dout : R/W; bitpos: [24]; default: 0;
-         *  1: Be able to send data out in LCD sequence when LCD starts. 0: Disable.
-         */
-        uint32_t lcd_dout:1;
-        /** lcd_dummy : R/W; bitpos: [25]; default: 0;
-         *  1: Enable DUMMY phase in LCD sequence when LCD starts. 0: Disable.
-         */
-        uint32_t lcd_dummy:1;
-        /** lcd_cmd : R/W; bitpos: [26]; default: 0;
-         *  1: Be able to send command in LCD sequence when LCD starts. 0: Disable.
-         */
-        uint32_t lcd_cmd:1;
-        /** lcd_start : R/W/SC; bitpos: [27]; default: 0;
-         *  LCD start sending data enable signal, valid in high level.
-         */
-        uint32_t lcd_start:1;
-        /** lcd_reset : WT; bitpos: [28]; default: 0;
-         *  The value of  command.
-         */
-        uint32_t lcd_reset:1;
-        /** lcd_dummy_cyclelen : R/W; bitpos: [30:29]; default: 0;
-         *  The dummy cycle length minus 1.
-         */
-        uint32_t lcd_dummy_cyclelen:2;
-        /** lcd_cmd_2_cycle_en : R/W; bitpos: [31]; default: 0;
-         *  The cycle length of command phase. 1: 2 cycles. 0: 1 cycle.
-         */
-        uint32_t lcd_cmd_2_cycle_en:1;
-    };
-    uint32_t val;
-} lcdcam_lcd_user_reg_t;
-
-/** Type of lcd_misc register
- *  LCD config register.
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:4;
-        /** lcd_wire_mode : R/W; bitpos: [5:4]; default: 0;
-         *  The wire width of LCD output. 0: 8bit. 1: 16bit 2: 24bit
-         */
-        uint32_t lcd_wire_mode:2;
-        /** lcd_vfk_cyclelen : R/W; bitpos: [11:6]; default: 3;
-         *  The setup cycle length minus 1 in LCD non-RGB mode.
-         */
-        uint32_t lcd_vfk_cyclelen:6;
-        /** lcd_vbk_cyclelen : R/W; bitpos: [24:12]; default: 0;
-         *  The vertical back blank region cycle length minus 1 in LCD RGB mode, or the hold
-         *  time cycle length in LCD non-RGB mode.
-         */
-        uint32_t lcd_vbk_cyclelen:13;
-        /** lcd_next_frame_en : R/W; bitpos: [25]; default: 0;
-         *  1: Send the next frame data when the current frame is sent out. 0: LCD stops when
-         *  the current frame is sent out.
-         */
-        uint32_t lcd_next_frame_en:1;
-        /** lcd_bk_en : R/W; bitpos: [26]; default: 0;
-         *  1: Enable blank region when LCD sends data out. 0: No blank region.
-         */
-        uint32_t lcd_bk_en:1;
-        /** lcd_afifo_reset : WT; bitpos: [27]; default: 0;
-         *  LCD AFIFO reset signal.
-         */
-        uint32_t lcd_afifo_reset:1;
-        /** lcd_cd_data_set : R/W; bitpos: [28]; default: 0;
-         *  1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_DOUT state.  0: LCD_CD =
-         *  reg_cd_idle_edge.
-         */
-        uint32_t lcd_cd_data_set:1;
-        /** lcd_cd_dummy_set : R/W; bitpos: [29]; default: 0;
-         *  1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_DUMMY state.  0: LCD_CD =
-         *  reg_cd_idle_edge.
-         */
-        uint32_t lcd_cd_dummy_set:1;
-        /** lcd_cd_cmd_set : R/W; bitpos: [30]; default: 0;
-         *  1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_CMD state.  0: LCD_CD =
-         *  reg_cd_idle_edge.
-         */
-        uint32_t lcd_cd_cmd_set:1;
-        /** lcd_cd_idle_edge : R/W; bitpos: [31]; default: 0;
-         *  The default value of LCD_CD.
-         */
-        uint32_t lcd_cd_idle_edge:1;
-    };
-    uint32_t val;
-} lcdcam_lcd_misc_reg_t;
-
-/** Type of lcd_ctrl register
- *  LCD config register.
- */
-typedef union {
-    struct {
-        /** lcd_hb_front : R/W; bitpos: [10:0]; default: 0;
-         *  It is the horizontal blank front porch of a frame.
-         */
-        uint32_t lcd_hb_front:11;
-        /** lcd_va_height : R/W; bitpos: [20:11]; default: 0;
-         *  It is the vertical active height of a frame.
-         */
-        uint32_t lcd_va_height:10;
-        /** lcd_vt_height : R/W; bitpos: [30:21]; default: 0;
-         *  It is the vertical total height of a frame.
-         */
-        uint32_t lcd_vt_height:10;
-        /** lcd_rgb_mode_en : R/W; bitpos: [31]; default: 0;
-         *  1: Enable LCD RGB mode. 0: Disable LCD RGB mode.
-         */
-        uint32_t lcd_rgb_mode_en:1;
-    };
-    uint32_t val;
-} lcdcam_lcd_ctrl_reg_t;
-
-/** Type of lcd_ctrl1 register
- *  LCD config register.
- */
-typedef union {
-    struct {
-        /** lcd_vb_front : R/W; bitpos: [7:0]; default: 0;
-         *  It is the vertical blank front porch of a frame.
-         */
-        uint32_t lcd_vb_front:8;
-        /** lcd_ha_width : R/W; bitpos: [19:8]; default: 0;
-         *  It is the horizontal active width of a frame.
-         */
-        uint32_t lcd_ha_width:12;
-        /** lcd_ht_width : R/W; bitpos: [31:20]; default: 0;
-         *  It is the horizontal total width of a frame.
-         */
-        uint32_t lcd_ht_width:12;
-    };
-    uint32_t val;
-} lcdcam_lcd_ctrl1_reg_t;
-
-/** Type of lcd_ctrl2 register
- *  LCD config register.
- */
-typedef union {
-    struct {
-        /** lcd_vsync_width : R/W; bitpos: [6:0]; default: 1;
-         *  It is the position of LCD_VSYNC active pulse in a line.
-         */
-        uint32_t lcd_vsync_width:7;
-        /** lcd_vsync_idle_pol : R/W; bitpos: [7]; default: 0;
-         *  It is the idle value of LCD_VSYNC.
-         */
-        uint32_t lcd_vsync_idle_pol:1;
-        /** lcd_de_idle_pol : R/W; bitpos: [8]; default: 0;
-         *  It is the idle value of LCD_DE.
-         */
-        uint32_t lcd_de_idle_pol:1;
-        /** lcd_hs_blank_en : R/W; bitpos: [9]; default: 0;
-         *  1: The pulse of LCD_HSYNC is out in vertical blanking lines RGB mode. 0: LCD_HSYNC
-         *  pulse is valid only in active region lines in RGB mode.
-         */
-        uint32_t lcd_hs_blank_en:1;
-        uint32_t reserved_10:6;
-        /** lcd_hsync_width : R/W; bitpos: [22:16]; default: 1;
-         *  It is the position of LCD_HSYNC active pulse in a line.
-         */
-        uint32_t lcd_hsync_width:7;
-        /** lcd_hsync_idle_pol : R/W; bitpos: [23]; default: 0;
-         *  It is the idle value of LCD_HSYNC.
-         */
-        uint32_t lcd_hsync_idle_pol:1;
-        /** lcd_hsync_position : R/W; bitpos: [31:24]; default: 0;
-         *  It is the position of LCD_HSYNC active pulse in a line.
-         */
-        uint32_t lcd_hsync_position:8;
-    };
-    uint32_t val;
-} lcdcam_lcd_ctrl2_reg_t;
-
-/** Type of lcd_first_cmd_val register
- *  LCD config register.
- */
-typedef union {
-    struct {
-        /** lcd_first_cmd_value : R/W; bitpos: [31:0]; default: 0;
-         *  The LCD write command value of first cmd cycle.
-         */
-        uint32_t lcd_first_cmd_value:32;
-    };
-    uint32_t val;
-} lcdcam_lcd_first_cmd_val_reg_t;
-
-/** Type of lcd_latter_cmd_val register
- *  LCD config register.
- */
-typedef union {
-    struct {
-        /** lcd_latter_cmd_value : R/W; bitpos: [31:0]; default: 0;
-         *  The LCD write command value of latter cmd cycle.
-         */
-        uint32_t lcd_latter_cmd_value:32;
-    };
-    uint32_t val;
-} lcdcam_lcd_latter_cmd_val_reg_t;
-
-/** Type of lcd_dly_mode_cfg1 register
- *  LCD config register.
- */
-typedef union {
-    struct {
-        /** dout16_mode : R/W; bitpos: [1:0]; default: 0;
-         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
-         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
-         *  LCD_CLK.
-         */
-        uint32_t dout16_mode:2;
-        /** dout17_mode : R/W; bitpos: [3:2]; default: 0;
-         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
-         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
-         *  LCD_CLK.
-         */
-        uint32_t dout17_mode:2;
-        /** dout18_mode : R/W; bitpos: [5:4]; default: 0;
-         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
-         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
-         *  LCD_CLK.
-         */
-        uint32_t dout18_mode:2;
-        /** dout19_mode : R/W; bitpos: [7:6]; default: 0;
-         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
-         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
-         *  LCD_CLK.
-         */
-        uint32_t dout19_mode:2;
-        /** dout20_mode : R/W; bitpos: [9:8]; default: 0;
-         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
-         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
-         *  LCD_CLK.
-         */
-        uint32_t dout20_mode:2;
-        /** dout21_mode : R/W; bitpos: [11:10]; default: 0;
-         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
-         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
-         *  LCD_CLK.
-         */
-        uint32_t dout21_mode:2;
-        /** dout22_mode : R/W; bitpos: [13:12]; default: 0;
-         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
-         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
-         *  LCD_CLK.
-         */
-        uint32_t dout22_mode:2;
-        /** dout23_mode : R/W; bitpos: [15:14]; default: 0;
-         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
-         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
-         *  LCD_CLK.
-         */
-        uint32_t dout23_mode:2;
-        /** lcd_cd_mode : R/W; bitpos: [17:16]; default: 0;
-         *  The output LCD_CD is delayed by module clock LCD_CLK. 0: output without delayed. 1:
-         *  delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.
-         */
-        uint32_t lcd_cd_mode:2;
-        /** lcd_de_mode : R/W; bitpos: [19:18]; default: 0;
-         *  The output LCD_DE is delayed by module clock LCD_CLK. 0: output without delayed. 1:
-         *  delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.
-         */
-        uint32_t lcd_de_mode:2;
-        /** lcd_hsync_mode : R/W; bitpos: [21:20]; default: 0;
-         *  The output LCD_HSYNC is delayed by module clock LCD_CLK. 0: output without delayed.
-         *  1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.
-         */
-        uint32_t lcd_hsync_mode:2;
-        /** lcd_vsync_mode : R/W; bitpos: [23:22]; default: 0;
-         *  The output LCD_VSYNC is delayed by module clock LCD_CLK. 0: output without delayed.
-         *  1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of LCD_CLK.
-         */
-        uint32_t lcd_vsync_mode:2;
-        uint32_t reserved_24:8;
-    };
-    uint32_t val;
-} lcdcam_lcd_dly_mode_cfg1_reg_t;
-
-/** Type of lcd_dly_mode_cfg2 register
- *  LCD config register.
- */
-typedef union {
-    struct {
-        /** dout0_mode : R/W; bitpos: [1:0]; default: 0;
-         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
-         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
-         *  LCD_CLK.
-         */
-        uint32_t dout0_mode:2;
-        /** dout1_mode : R/W; bitpos: [3:2]; default: 0;
-         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
-         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
-         *  LCD_CLK.
-         */
-        uint32_t dout1_mode:2;
-        /** dout2_mode : R/W; bitpos: [5:4]; default: 0;
-         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
-         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
-         *  LCD_CLK.
-         */
-        uint32_t dout2_mode:2;
-        /** dout3_mode : R/W; bitpos: [7:6]; default: 0;
-         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
-         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
-         *  LCD_CLK.
-         */
-        uint32_t dout3_mode:2;
-        /** dout4_mode : R/W; bitpos: [9:8]; default: 0;
-         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
-         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
-         *  LCD_CLK.
-         */
-        uint32_t dout4_mode:2;
-        /** dout5_mode : R/W; bitpos: [11:10]; default: 0;
-         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
-         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
-         *  LCD_CLK.
-         */
-        uint32_t dout5_mode:2;
-        /** dout6_mode : R/W; bitpos: [13:12]; default: 0;
-         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
-         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
-         *  LCD_CLK.
-         */
-        uint32_t dout6_mode:2;
-        /** dout7_mode : R/W; bitpos: [15:14]; default: 0;
-         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
-         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
-         *  LCD_CLK.
-         */
-        uint32_t dout7_mode:2;
-        /** dout8_mode : R/W; bitpos: [17:16]; default: 0;
-         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
-         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
-         *  LCD_CLK.
-         */
-        uint32_t dout8_mode:2;
-        /** dout9_mode : R/W; bitpos: [19:18]; default: 0;
-         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
-         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
-         *  LCD_CLK.
-         */
-        uint32_t dout9_mode:2;
-        /** dout10_mode : R/W; bitpos: [21:20]; default: 0;
-         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
-         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
-         *  LCD_CLK.
-         */
-        uint32_t dout10_mode:2;
-        /** dout11_mode : R/W; bitpos: [23:22]; default: 0;
-         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
-         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
-         *  LCD_CLK.
-         */
-        uint32_t dout11_mode:2;
-        /** dout12_mode : R/W; bitpos: [25:24]; default: 0;
-         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
-         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
-         *  LCD_CLK.
-         */
-        uint32_t dout12_mode:2;
-        /** dout13_mode : R/W; bitpos: [27:26]; default: 0;
-         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
-         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
-         *  LCD_CLK.
-         */
-        uint32_t dout13_mode:2;
-        /** dout14_mode : R/W; bitpos: [29:28]; default: 0;
-         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
-         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
-         *  LCD_CLK.
-         */
-        uint32_t dout14_mode:2;
-        /** dout15_mode : R/W; bitpos: [31:30]; default: 0;
-         *  The output data bit $n is delayed by module clock LCD_CLK. 0: output without
-         *  delayed. 1: delay by the positive edge of LCD_CLK. 2: delay by the negative edge of
-         *  LCD_CLK.
-         */
-        uint32_t dout15_mode:2;
-    };
-    uint32_t val;
-} lcdcam_lcd_dly_mode_cfg2_reg_t;
-
-
-/** Group: cam configuration registers */
-/** Type of cam_ctrl register
- *  CAM config register.
- */
-typedef union {
-    struct {
-        /** cam_stop_en : R/W; bitpos: [0]; default: 0;
-         *  Camera stop enable signal, 1: camera stops when DMA Rx FIFO is full. 0: Not stop.
-         */
-        uint32_t cam_stop_en:1;
-        /** cam_vsync_filter_thres : R/W; bitpos: [3:1]; default: 0;
-         *  Filter threshold value for CAM_VSYNC signal.
-         */
-        uint32_t cam_vsync_filter_thres:3;
-        /** cam_update_reg : R/W/SC; bitpos: [4]; default: 0;
-         *  1: Update Camera registers, will be cleared by hardware. 0 : Not care.
-         */
-        uint32_t cam_update_reg:1;
-        /** cam_byte_order : R/W; bitpos: [5]; default: 0;
-         *  1: invert data byte order. 0: Not change.
-         */
-        uint32_t cam_byte_order:1;
-        /** cam_bit_order : R/W; bitpos: [6]; default: 0;
-         *  1: Change data bit order, change CAM_DATA_in[7:0] to CAM_DATA_in[0:7] in one byte
-         *  mode, and bits[15:0] to bits[0:15] in two byte mode.  0: Not change.
-         */
-        uint32_t cam_bit_order:1;
-        /** cam_line_int_en : R/W; bitpos: [7]; default: 0;
-         *  1: Enable to generate CAM_HS_INT. 0: Disable.
-         */
-        uint32_t cam_line_int_en:1;
-        /** cam_vs_eof_en : R/W; bitpos: [8]; default: 0;
-         *  1: CAM_VSYNC to generate in_suc_eof. 0: in_suc_eof is controlled by
-         *  reg_cam_rec_data_cyclelen.
-         */
-        uint32_t cam_vs_eof_en:1;
-        /** cam_clkm_div_num : R/W; bitpos: [16:9]; default: 4;
-         *  Integral Camera clock divider value
-         */
-        uint32_t cam_clkm_div_num:8;
-        /** cam_clkm_div_b : R/W; bitpos: [22:17]; default: 0;
-         *  Fractional clock divider numerator value
-         */
-        uint32_t cam_clkm_div_b:6;
-        /** cam_clkm_div_a : R/W; bitpos: [28:23]; default: 0;
-         *  Fractional clock divider denominator value
-         */
-        uint32_t cam_clkm_div_a:6;
-        /** cam_clk_sel : R/W; bitpos: [30:29]; default: 0;
-         *  Select Camera module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock.
-         */
-        uint32_t cam_clk_sel:2;
-        uint32_t reserved_31:1;
-    };
-    uint32_t val;
-} lcdcam_cam_ctrl_reg_t;
-
-/** Type of cam_ctrl1 register
- *  CAM config register.
- */
-typedef union {
-    struct {
-        /** cam_rec_data_bytelen : R/W; bitpos: [15:0]; default: 0;
-         *  Camera receive data byte length minus 1 to set DMA in_suc_eof_int.
-         */
-        uint32_t cam_rec_data_bytelen:16;
-        /** cam_line_int_num : R/W; bitpos: [21:16]; default: 0;
-         *  The line number minus 1 to generate cam_hs_int.
-         */
-        uint32_t cam_line_int_num:6;
-        /** cam_clk_inv : R/W; bitpos: [22]; default: 0;
-         *  1: Invert  the input signal CAM_PCLK. 0: Not invert.
-         */
-        uint32_t cam_clk_inv:1;
-        /** cam_vsync_filter_en : R/W; bitpos: [23]; default: 0;
-         *  1: Enable CAM_VSYNC filter function. 0: bypass.
-         */
-        uint32_t cam_vsync_filter_en:1;
-        /** cam_2byte_en : R/W; bitpos: [24]; default: 0;
-         *  1: The bit number of input data is 9~16.  0: The bit number of input data is 0~8.
-         */
-        uint32_t cam_2byte_en:1;
-        /** cam_de_inv : R/W; bitpos: [25]; default: 0;
-         *  CAM_DE invert enable signal, valid in high level.
-         */
-        uint32_t cam_de_inv:1;
-        /** cam_hsync_inv : R/W; bitpos: [26]; default: 0;
-         *  CAM_HSYNC invert enable signal, valid in high level.
-         */
-        uint32_t cam_hsync_inv:1;
-        /** cam_vsync_inv : R/W; bitpos: [27]; default: 0;
-         *  CAM_VSYNC invert enable signal, valid in high level.
-         */
-        uint32_t cam_vsync_inv:1;
-        /** cam_vh_de_mode_en : R/W; bitpos: [28]; default: 0;
-         *  1: Input control signals are CAM_DE CAM_HSYNC and CAM_VSYNC. 0: Input control
-         *  signals are CAM_DE and CAM_VSYNC.
-         */
-        uint32_t cam_vh_de_mode_en:1;
-        /** cam_start : R/W/SC; bitpos: [29]; default: 0;
-         *  Camera module start signal.
-         */
-        uint32_t cam_start:1;
-        /** cam_reset : WT; bitpos: [30]; default: 0;
-         *  Camera module reset signal.
-         */
-        uint32_t cam_reset:1;
-        /** cam_afifo_reset : WT; bitpos: [31]; default: 0;
-         *  Camera AFIFO reset signal.
-         */
-        uint32_t cam_afifo_reset:1;
-    };
-    uint32_t val;
-} lcdcam_cam_ctrl1_reg_t;
-
-/** Type of cam_rgb_yuv register
- *  CAM YUV/RGB converter configuration register.
- */
-typedef union {
-    struct {
-        uint32_t reserved_0:21;
-        /** cam_conv_8bits_data_inv : R/W; bitpos: [21]; default: 0;
-         *  1:invert every two 8bits input data. 2. disabled.
-         */
-        uint32_t cam_conv_8bits_data_inv:1;
-        /** cam_conv_yuv2yuv_mode : R/W; bitpos: [23:22]; default: 3;
-         *  0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled.  To enable yuv2yuv mode,
-         *  trans_mode must be set to 1.
-         */
-        uint32_t cam_conv_yuv2yuv_mode:2;
-        /** cam_conv_yuv_mode : R/W; bitpos: [25:24]; default: 0;
-         *  0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode, yuv_mode decides the yuv
-         *  mode of Data_in
-         */
-        uint32_t cam_conv_yuv_mode:2;
-        /** cam_conv_protocol_mode : R/W; bitpos: [26]; default: 0;
-         *  0:BT601. 1:BT709.
-         */
-        uint32_t cam_conv_protocol_mode:1;
-        /** cam_conv_data_out_mode : R/W; bitpos: [27]; default: 0;
-         *  LIMIT or FULL mode of Data out. 0: limit. 1: full
-         */
-        uint32_t cam_conv_data_out_mode:1;
-        /** cam_conv_data_in_mode : R/W; bitpos: [28]; default: 0;
-         *  LIMIT or FULL mode of Data in. 0: limit. 1: full
-         */
-        uint32_t cam_conv_data_in_mode:1;
-        /** cam_conv_mode_8bits_on : R/W; bitpos: [29]; default: 0;
-         *  0: 16bits mode. 1: 8bits mode.
-         */
-        uint32_t cam_conv_mode_8bits_on:1;
-        /** cam_conv_trans_mode : R/W; bitpos: [30]; default: 0;
-         *  0: YUV to RGB. 1: RGB to YUV.
-         */
-        uint32_t cam_conv_trans_mode:1;
-        /** cam_conv_enable : R/W; bitpos: [31]; default: 0;
-         *  0: Bypass converter. 1: Enable converter.
-         */
-        uint32_t cam_conv_enable:1;
-    };
-    uint32_t val;
-} lcdcam_cam_rgb_yuv_reg_t;
-
-
-/** Group: Interrupt registers */
-/** Type of lc_dma_int_ena register
- *  LCDCAM interrupt enable register.
- */
-typedef union {
-    struct {
-        /** lcd_vsync_int_ena : R/W; bitpos: [0]; default: 0;
-         *  The enable bit for LCD frame end interrupt.
-         */
-        uint32_t lcd_vsync_int_ena:1;
-        /** lcd_trans_done_int_ena : R/W; bitpos: [1]; default: 0;
-         *  The enable bit for lcd transfer end interrupt.
-         */
-        uint32_t lcd_trans_done_int_ena:1;
-        /** cam_vsync_int_ena : R/W; bitpos: [2]; default: 0;
-         *  The enable bit for Camera frame end interrupt.
-         */
-        uint32_t cam_vsync_int_ena:1;
-        /** cam_hs_int_ena : R/W; bitpos: [3]; default: 0;
-         *  The enable bit for Camera line interrupt.
-         */
-        uint32_t cam_hs_int_ena:1;
-        /** lcd_underrun_int_ena : R/W; bitpos: [4]; default: 0;
-         *  The enable bit for LCD underrun interrupt
-         */
-        uint32_t lcd_underrun_int_ena:1;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} lcdcam_lc_dma_int_ena_reg_t;
-
-/** Type of lc_dma_int_raw register
- *  LCDCAM interrupt raw register, valid in level.
- */
-typedef union {
-    struct {
-        /** lcd_vsync_int_raw : RO/WTC/SS; bitpos: [0]; default: 0;
-         *  The raw bit for LCD frame end interrupt.
-         */
-        uint32_t lcd_vsync_int_raw:1;
-        /** lcd_trans_done_int_raw : RO/WTC/SS; bitpos: [1]; default: 0;
-         *  The raw bit for lcd transfer end interrupt.
-         */
-        uint32_t lcd_trans_done_int_raw:1;
-        /** cam_vsync_int_raw : RO/WTC/SS; bitpos: [2]; default: 0;
-         *  The raw bit for Camera frame end interrupt.
-         */
-        uint32_t cam_vsync_int_raw:1;
-        /** cam_hs_int_raw : RO/WTC/SS; bitpos: [3]; default: 0;
-         *  The raw bit for Camera line interrupt.
-         */
-        uint32_t cam_hs_int_raw:1;
-        /** lcd_underrun_int_raw : RO/WTC/SS; bitpos: [4]; default: 0;
-         *  The raw bit for LCD underrun interrupt
-         */
-        uint32_t lcd_underrun_int_raw:1;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} lcdcam_lc_dma_int_raw_reg_t;
-
-/** Type of lc_dma_int_st register
- *  LCDCAM interrupt status register.
- */
-typedef union {
-    struct {
-        /** lcd_vsync_int_st : RO; bitpos: [0]; default: 0;
-         *  The status bit for LCD frame end interrupt.
-         */
-        uint32_t lcd_vsync_int_st:1;
-        /** lcd_trans_done_int_st : RO; bitpos: [1]; default: 0;
-         *  The status bit for lcd transfer end interrupt.
-         */
-        uint32_t lcd_trans_done_int_st:1;
-        /** cam_vsync_int_st : RO; bitpos: [2]; default: 0;
-         *  The status bit for Camera frame end interrupt.
-         */
-        uint32_t cam_vsync_int_st:1;
-        /** cam_hs_int_st : RO; bitpos: [3]; default: 0;
-         *  The status bit for Camera transfer end interrupt.
-         */
-        uint32_t cam_hs_int_st:1;
-        /** lcd_underrun_int_st : RO; bitpos: [4]; default: 0;
-         *  The status bit for LCD underrun interrupt
-         */
-        uint32_t lcd_underrun_int_st:1;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} lcdcam_lc_dma_int_st_reg_t;
-
-/** Type of lc_dma_int_clr register
- *  LCDCAM interrupt clear register.
- */
-typedef union {
-    struct {
-        /** lcd_vsync_int_clr : WT; bitpos: [0]; default: 0;
-         *  The clear bit for LCD frame end interrupt.
-         */
-        uint32_t lcd_vsync_int_clr:1;
-        /** lcd_trans_done_int_clr : WT; bitpos: [1]; default: 0;
-         *  The clear bit for lcd transfer end interrupt.
-         */
-        uint32_t lcd_trans_done_int_clr:1;
-        /** cam_vsync_int_clr : WT; bitpos: [2]; default: 0;
-         *  The clear bit for Camera frame end interrupt.
-         */
-        uint32_t cam_vsync_int_clr:1;
-        /** cam_hs_int_clr : WT; bitpos: [3]; default: 0;
-         *  The clear bit for Camera line interrupt.
-         */
-        uint32_t cam_hs_int_clr:1;
-        /** lcd_underrun_int_clr : WT; bitpos: [4]; default: 0;
-         *  The clear bit for LCD underrun interrupt
-         */
-        uint32_t lcd_underrun_int_clr:1;
-        uint32_t reserved_5:27;
-    };
-    uint32_t val;
-} lcdcam_lc_dma_int_clr_reg_t;
-
-
-/** Group: Version register */
-/** Type of lc_reg_date register
- *  Version register
- */
-typedef union {
-    struct {
-        /** lc_date : R/W; bitpos: [27:0]; default: 38806054;
-         *  LCD_CAM version control register
-         */
-        uint32_t lc_date:28;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} lcdcam_lc_reg_date_reg_t;
-
-
-typedef struct {
-    volatile lcdcam_lcd_clock_reg_t lcd_clock;
-    volatile lcdcam_cam_ctrl_reg_t cam_ctrl;
-    volatile lcdcam_cam_ctrl1_reg_t cam_ctrl1;
-    volatile lcdcam_cam_rgb_yuv_reg_t cam_rgb_yuv;
-    volatile lcdcam_lcd_rgb_yuv_reg_t lcd_rgb_yuv;
-    volatile lcdcam_lcd_user_reg_t lcd_user;
-    volatile lcdcam_lcd_misc_reg_t lcd_misc;
-    volatile lcdcam_lcd_ctrl_reg_t lcd_ctrl;
-    volatile lcdcam_lcd_ctrl1_reg_t lcd_ctrl1;
-    volatile lcdcam_lcd_ctrl2_reg_t lcd_ctrl2;
-    volatile lcdcam_lcd_first_cmd_val_reg_t lcd_first_cmd_val;
-    volatile lcdcam_lcd_latter_cmd_val_reg_t lcd_latter_cmd_val;
-    volatile lcdcam_lcd_dly_mode_cfg1_reg_t lcd_dly_mode_cfg1;
-    uint32_t reserved_034;
-    volatile lcdcam_lcd_dly_mode_cfg2_reg_t lcd_dly_mode_cfg2;
-    uint32_t reserved_03c[10];
-    volatile lcdcam_lc_dma_int_ena_reg_t lc_dma_int_ena;
-    volatile lcdcam_lc_dma_int_raw_reg_t lc_dma_int_raw;
-    volatile lcdcam_lc_dma_int_st_reg_t lc_dma_int_st;
-    volatile lcdcam_lc_dma_int_clr_reg_t lc_dma_int_clr;
-    uint32_t reserved_074[34];
-    volatile lcdcam_lc_reg_date_reg_t lc_reg_date;
-} lcdcam_dev_t;
-
-extern lcdcam_dev_t LCD_CAM;
-
-#ifndef __cplusplus
-_Static_assert(sizeof(lcdcam_dev_t) == 0x100, "Invalid size of lcdcam_dev_t structure");
-#endif
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/components/soc/esp32p4/register/hw_ver3/soc/lcd_cam_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/lcd_cam_struct.h
index 470ef9961a..08d5844e0e 100644
--- a/components/soc/esp32p4/register/hw_ver3/soc/lcd_cam_struct.h
+++ b/components/soc/esp32p4/register/hw_ver3/soc/lcd_cam_struct.h
@@ -62,7 +62,11 @@ typedef union {
  */
 typedef union {
     struct {
-        uint32_t reserved_0:20;
+        uint32_t reserved_0:18;
+        /** lcd_conv_rgb2rgb_mode : R/W; bitpos: [19:18]; default: 3;
+         *  0:rgb888 trans to rgb565. 1:rgb565 trans to rgb888.2,3:disabled
+         */
+        uint32_t lcd_conv_rgb2rgb_mode:2;
         /** lcd_conv_8bits_data_inv : R/W; bitpos: [20]; default: 0;
          *  1:invert every two 8bits input data. 2. disabled.
          */
@@ -72,13 +76,12 @@ typedef union {
          */
         uint32_t lcd_conv_txtorx:1;
         /** lcd_conv_yuv2yuv_mode : R/W; bitpos: [23:22]; default: 3;
-         *  0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled.  To enable yuv2yuv mode,
-         *  trans_mode must be set to 1.
+         *  0: to yuv422.  2: to yuv411. 1,3: disabled.  To enable yuv2yuv mode, trans_mode
+         *  must be set to 1.
          */
         uint32_t lcd_conv_yuv2yuv_mode:2;
         /** lcd_conv_yuv_mode : R/W; bitpos: [25:24]; default: 0;
-         *  0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode, yuv_mode decides the yuv
-         *  mode of Data_in
+         *  0: yuv422. 2: yuv411. When in yuv2yuv mode, yuv_mode decides the yuv mode of Data_in
          */
         uint32_t lcd_conv_yuv_mode:2;
         /** lcd_conv_protocol_mode : R/W; bitpos: [26]; default: 0;
@@ -553,12 +556,12 @@ typedef union {
          */
         uint32_t cam_update_reg:1;
         /** cam_byte_order : R/W; bitpos: [5]; default: 0;
-         *  1: Change data bit order, change CAM_DATA_in[7:0] to CAM_DATA_in[0:7] in one byte
-         *  mode, and bits[15:0] to bits[0:15] in two byte mode.  0: Not change.
+         *  1: invert data byte order. 0: Not change.
          */
         uint32_t cam_byte_order:1;
         /** cam_bit_order : R/W; bitpos: [6]; default: 0;
-         *  1: invert data byte order, only valid in 2 byte mode. 0: Not change.
+         *  1: Change data bit order, change CAM_DATA_in[7:0] to CAM_DATA_in[0:7] in one byte
+         *  mode, and bits[15:0] to bits[0:15] in two byte mode.  0: Not change.
          */
         uint32_t cam_bit_order:1;
         /** cam_line_int_en : R/W; bitpos: [7]; default: 0;
@@ -720,7 +723,11 @@ typedef union {
          *  The enable bit for Camera line interrupt.
          */
         uint32_t cam_hs_int_ena:1;
-        uint32_t reserved_4:28;
+        /** lcd_underrun_int_ena : R/W; bitpos: [4]; default: 0;
+         *  The enable bit for LCD underrun interrupt
+         */
+        uint32_t lcd_underrun_int_ena:1;
+        uint32_t reserved_5:27;
     };
     uint32_t val;
 } lcdcam_lc_dma_int_ena_reg_t;
@@ -746,7 +753,11 @@ typedef union {
          *  The raw bit for Camera line interrupt.
          */
         uint32_t cam_hs_int_raw:1;
-        uint32_t reserved_4:28;
+        /** lcd_underrun_int_raw : RO/WTC/SS; bitpos: [4]; default: 0;
+         *  The raw bit for LCD underrun interrupt
+         */
+        uint32_t lcd_underrun_int_raw:1;
+        uint32_t reserved_5:27;
     };
     uint32_t val;
 } lcdcam_lc_dma_int_raw_reg_t;
@@ -772,7 +783,11 @@ typedef union {
          *  The status bit for Camera transfer end interrupt.
          */
         uint32_t cam_hs_int_st:1;
-        uint32_t reserved_4:28;
+        /** lcd_underrun_int_st : RO; bitpos: [4]; default: 0;
+         *  The status bit for LCD underrun interrupt
+         */
+        uint32_t lcd_underrun_int_st:1;
+        uint32_t reserved_5:27;
     };
     uint32_t val;
 } lcdcam_lc_dma_int_st_reg_t;
@@ -798,7 +813,11 @@ typedef union {
          *  The clear bit for Camera line interrupt.
          */
         uint32_t cam_hs_int_clr:1;
-        uint32_t reserved_4:28;
+        /** lcd_underrun_int_clr : WT; bitpos: [4]; default: 0;
+         *  The clear bit for LCD underrun interrupt
+         */
+        uint32_t lcd_underrun_int_clr:1;
+        uint32_t reserved_5:27;
     };
     uint32_t val;
 } lcdcam_lc_dma_int_clr_reg_t;
@@ -810,7 +829,7 @@ typedef union {
  */
 typedef union {
     struct {
-        /** lc_date : R/W; bitpos: [27:0]; default: 36712592;
+        /** lc_date : R/W; bitpos: [27:0]; default: 38806054;
          *  LCD_CAM version control register
          */
         uint32_t lc_date:28;
@@ -845,13 +864,12 @@ typedef struct lcd_cam_dev_t {
     volatile lcdcam_lc_reg_date_reg_t lc_reg_date;
 } lcd_cam_dev_t;
 
+extern lcd_cam_dev_t LCD_CAM;
 
 #ifndef __cplusplus
-_Static_assert(sizeof(lcd_cam_dev_t) == 0x100, "Invalid size of lcdcam_dev_t structure");
+_Static_assert(sizeof(lcd_cam_dev_t) == 0x100, "Invalid size of lcd_cam_dev_t structure");
 #endif
 
-extern lcd_cam_dev_t LCD_CAM;
-
 #ifdef __cplusplus
 }
 #endif
diff --git a/docs/en/migration-guides/release-6.x/6.0/peripherals.rst b/docs/en/migration-guides/release-6.x/6.0/peripherals.rst
index 4aa40f71b3..c2c3930797 100644
--- a/docs/en/migration-guides/release-6.x/6.0/peripherals.rst
+++ b/docs/en/migration-guides/release-6.x/6.0/peripherals.rst
@@ -11,6 +11,16 @@ All drivers' ``io_loop_back`` configuration have been removed
 
 Different driver objects can share the same GPIO number, enabling more complex functionalities. For example, you can bind the TX and RX channels of the RMT peripheral to the same GPIO to simulate 1-Wire bus read and write timing. In previous versions, you needed to configure the ``io_loop_back`` setting in the driver to achieve this "loopback" functionality. Now, this configuration has been removed. Simply configuring the same GPIO number in different drivers will achieve the same functionality.
 
+Peripheral Clock Gating
+~~~~~~~~~~~~~~~~~~~~~~~~
+
+Peripheral clock gating is managed within the driver layer. Users do not need to manually handle peripheral module clock gating. Its corresponding APIs are included via a private header file ``esp_private/periph_ctrl.h``. There used to be another header file ``driver/periph_ctrl.h`` for the same purpose, which is now removed.
+
+RTC Subsystem Control
+~~~~~~~~~~~~~~~~~~~~~~
+
+Low power modules usually share some common resources like interrupt number. To avoid conflicts, some private APIs are created in the ``esp_private/rtc_ctrl.h`` header file to manage these shared resources with ease. There used to be another header file ``driver/rtc_cntl.h`` for the same purpose, which is now removed.
+
 ADC
 ---
 
diff --git a/docs/zh_CN/migration-guides/release-6.x/6.0/peripherals.rst b/docs/zh_CN/migration-guides/release-6.x/6.0/peripherals.rst
index c4ee389032..966a3fd181 100644
--- a/docs/zh_CN/migration-guides/release-6.x/6.0/peripherals.rst
+++ b/docs/zh_CN/migration-guides/release-6.x/6.0/peripherals.rst
@@ -11,6 +11,16 @@
 
 不同的驱动对象可以共享同一个 GPIO 编号，联合起来可以实现更加复杂的功能。比如将 RMT 外设的 TX 通道和 RX 通道绑定在同一个 GPIO 上，进而模拟单总线的读写时序。在以前的版本中，你需要在驱动的配置中额外设置 ``io_loop_back`` 来实现这种“回环”功能，现在，这个配置已经被移除。不同的驱动只需要在配置中设置相同的 GPIO 编号就能实现这个功能。
 
+外设时钟门控
+~~~~~~~~~~~~
+
+外设的时钟门控现在由驱动层统一管理，用户无需手动控制外设模块的时钟开关。相关的 API 位于私有头文件 ``esp_private/periph_ctrl.h`` 中。原先用于同样目的的头文件 ``driver/periph_ctrl.h`` 已被移除。
+
+RTC 子系统控制
+~~~~~~~~~~~~~~
+
+低功耗模块通常会共享一些资源，比如中断号。为避免资源冲突，私有头文件 ``esp_private/rtc_ctrl.h`` 提供了相关 API 方便管理这些共享资源。原先用于同样目的的头文件 ``driver/rtc_cntl.h`` 已被移除。
+
 ADC
 ---
 
diff --git a/examples/peripherals/rmt/onewire/main/idf_component.yml b/examples/peripherals/rmt/onewire/main/idf_component.yml
index 1ca3e8bca8..0d70f06b40 100644
--- a/examples/peripherals/rmt/onewire/main/idf_component.yml
+++ b/examples/peripherals/rmt/onewire/main/idf_component.yml
@@ -1,2 +1,2 @@
 dependencies:
-  ds18b20: "^0.1.0"
+  ds18b20: "^0.2.0"
diff --git a/examples/peripherals/rmt/onewire/main/onewire_example_main.c b/examples/peripherals/rmt/onewire/main/onewire_example_main.c
index d1a2b79e75..9e3d6263b6 100644
--- a/examples/peripherals/rmt/onewire/main/onewire_example_main.c
+++ b/examples/peripherals/rmt/onewire/main/onewire_example_main.c
@@ -45,8 +45,11 @@ void app_main(void)
         search_result = onewire_device_iter_get_next(iter, &next_onewire_device);
         if (search_result == ESP_OK) { // found a new device, let's check if we can upgrade it to a DS18B20
             ds18b20_config_t ds_cfg = {};
-            if (ds18b20_new_device(&next_onewire_device, &ds_cfg, &ds18b20s[ds18b20_device_num]) == ESP_OK) {
-                ESP_LOGI(TAG, "Found a DS18B20[%d], address: %016llX", ds18b20_device_num, next_onewire_device.address);
+            onewire_device_address_t address;
+            // wrap the generic 1-wire device into a DS18B20 sensor device
+            if (ds18b20_new_device_from_enumeration(&next_onewire_device, &ds_cfg, &ds18b20s[ds18b20_device_num]) == ESP_OK) {
+                ds18b20_get_device_address(ds18b20s[ds18b20_device_num], &address);
+                ESP_LOGI(TAG, "Found a DS18B20[%d], address: %016llX", ds18b20_device_num, address);
                 ds18b20_device_num++;
                 if (ds18b20_device_num >= EXAMPLE_ONEWIRE_MAX_DS18B20) {
                     ESP_LOGI(TAG, "Max DS18B20 number reached, stop searching...");
@@ -70,9 +73,10 @@ void app_main(void)
     float temperature;
     while (1) {
         vTaskDelay(pdMS_TO_TICKS(200));
-
+        // trigger temperature conversion for all DS18B20s on the bus
+        ESP_ERROR_CHECK(ds18b20_trigger_temperature_conversion_for_all(bus));
+        // read temperature from each DS18B20
         for (int i = 0; i < ds18b20_device_num; i ++) {
-            ESP_ERROR_CHECK(ds18b20_trigger_temperature_conversion(ds18b20s[i]));
             ESP_ERROR_CHECK(ds18b20_get_temperature(ds18b20s[i], &temperature));
             ESP_LOGI(TAG, "temperature read from DS18B20[%d]: %.2fC", i, temperature);
         }
diff --git a/tools/idf_py_actions/hints.yml b/tools/idf_py_actions/hints.yml
index 0c4889ecb4..2ad2e55196 100644
--- a/tools/idf_py_actions/hints.yml
+++ b/tools/idf_py_actions/hints.yml
@@ -111,6 +111,12 @@
         -   re_variables: ['driver/can.h']
             hint_variables: ['driver/can.h', 'driver/twai.h']
 
+        -   re_variables: ['driver/periph_ctrl.h']
+            hint_variables: ['driver/periph_ctrl.h', 'esp_private/periph_ctrl.h']
+
+        -   re_variables: ['driver/rtc_cntl.h']
+            hint_variables: ['driver/rtc_cntl.h', 'esp_private/rtc_ctrl.h']
+
 -
     re: "error: implicit declaration of function 'esp_int_wdt_\\w+'"
     hint: 'The Interrupt Watchdog API has been made private, it shall not be used anymore. You can still force its inclusion with #include "esp_private/esp_int_wdt.h" (not recommended)'