diff --git a/components/efuse/esp32s3/esp_efuse_table.c b/components/efuse/esp32s3/esp_efuse_table.c index b48f6b2010..fb906cd4e7 100644 --- a/components/efuse/esp32s3/esp_efuse_table.c +++ b/components/efuse/esp32s3/esp_efuse_table.c @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -9,7 +9,7 @@ #include #include "esp_efuse_table.h" -// md5_digest_table e0674ff40a1e124670c6eecf33410e76 +// md5_digest_table f8f32987a955792b4fe4534ea428268f // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY. // If you want to change some fields, you need to change esp_efuse_table.csv file // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file. @@ -769,7 +769,8 @@ static const esp_efuse_desc_t FLASH_VENDOR[] = { }; static const esp_efuse_desc_t PSRAM_CAP[] = { - {EFUSE_BLK1, 131, 2}, // [] PSRAM capacity {0: "None"; 1: "8M"; 2: "2M"}, + {EFUSE_BLK1, 131, 2}, // [] PSRAM capacity {0: "None"; 1: "8M"; 2: "2M"; 3: "16M"; 4: "4M"}, + {EFUSE_BLK1, 179, 1}, // [] PSRAM capacity bit 3, }; static const esp_efuse_desc_t PSRAM_TEMP[] = { @@ -1869,7 +1870,8 @@ const esp_efuse_desc_t* ESP_EFUSE_FLASH_VENDOR[] = { }; const esp_efuse_desc_t* ESP_EFUSE_PSRAM_CAP[] = { - &PSRAM_CAP[0], // [] PSRAM capacity {0: "None"; 1: "8M"; 2: "2M"} + &PSRAM_CAP[0], // [] PSRAM capacity {0: "None"; 1: "8M"; 2: "2M"; 3: "16M"; 4: "4M"} + &PSRAM_CAP[1], // [] PSRAM capacity bit 3 NULL }; diff --git a/components/efuse/esp32s3/esp_efuse_table.csv b/components/efuse/esp32s3/esp_efuse_table.csv index a55cfa2d59..a10c75587b 100644 --- a/components/efuse/esp32s3/esp_efuse_table.csv +++ b/components/efuse/esp32s3/esp_efuse_table.csv @@ -9,7 +9,7 @@ # this will generate new source files, next rebuild all the sources. # !!!!!!!!!!! # -# This file was generated by regtools.py based on the efuses.yaml file with the version: f75f74727101326a187188a23f4a6c70 +# This file was generated by regtools.py based on the efuses.yaml file with the version: 7127dd097e72bb90d0b790d460993126 WR_DIS, EFUSE_BLK0, 0, 32, [] Disable programming of individual eFuses WR_DIS.RD_DIS, EFUSE_BLK0, 0, 1, [] wr_dis of RD_DIS @@ -203,7 +203,8 @@ BLK_VERSION_MINOR, EFUSE_BLK1, 120, 3, [] BLK_VE FLASH_CAP, EFUSE_BLK1, 123, 3, [] Flash capacity {0: "None"; 1: "8M"; 2: "4M"} FLASH_TEMP, EFUSE_BLK1, 126, 2, [] Flash temperature {0: "None"; 1: "105C"; 2: "85C"} FLASH_VENDOR, EFUSE_BLK1, 128, 3, [] Flash vendor {0: "None"; 1: "XMC"; 2: "GD"; 3: "FM"; 4: "TT"; 5: "BY"} -PSRAM_CAP, EFUSE_BLK1, 131, 2, [] PSRAM capacity {0: "None"; 1: "8M"; 2: "2M"} +PSRAM_CAP, EFUSE_BLK1, 131, 2, [] PSRAM capacity {0: "None"; 1: "8M"; 2: "2M"; 3: "16M"; 4: "4M"} +, EFUSE_BLK1, 179, 1, [] PSRAM capacity bit 3 PSRAM_TEMP, EFUSE_BLK1, 133, 2, [] PSRAM temperature {0: "None"; 1: "105C"; 2: "85C"} PSRAM_VENDOR, EFUSE_BLK1, 135, 2, [] PSRAM vendor {0: "None"; 1: "AP_3v3"; 2: "AP_1v8"} K_RTC_LDO, EFUSE_BLK1, 141, 7, [] BLOCK1 K_RTC_LDO diff --git a/components/efuse/esp32s3/include/esp_efuse_table.h b/components/efuse/esp32s3/include/esp_efuse_table.h index 5fb75b6872..d43fba2402 100644 --- a/components/efuse/esp32s3/include/esp_efuse_table.h +++ b/components/efuse/esp32s3/include/esp_efuse_table.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2017-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -10,7 +10,7 @@ extern "C" { #include "esp_efuse.h" -// md5_digest_table e0674ff40a1e124670c6eecf33410e76 +// md5_digest_table f8f32987a955792b4fe4534ea428268f // This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY. // If you want to change some fields, you need to change esp_efuse_table.csv file // then run `efuse_common_table` or `efuse_custom_table` command it will generate this file. diff --git a/components/soc/esp32s3/include/soc/efuse_reg.h b/components/soc/esp32s3/include/soc/efuse_reg.h index c4b8a5ed47..7f36131279 100644 --- a/components/soc/esp32s3/include/soc/efuse_reg.h +++ b/components/soc/esp32s3/include/soc/efuse_reg.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -553,7 +553,7 @@ extern "C" { #define EFUSE_DIS_DIRECT_BOOT_V 0x00000001U #define EFUSE_DIS_DIRECT_BOOT_S 1 /** EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT : RO; bitpos: [2]; default: 0; - * Selectes the default UART print channel. 0: UART0. 1: UART1. + * Selects the default UART print channel. 0: UART0. 1: UART1. */ #define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT (BIT(2)) #define EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_M (EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_V << EFUSE_DIS_USB_SERIAL_JTAG_ROM_PRINT_S) @@ -917,13 +917,27 @@ extern "C" { #define EFUSE_DIG_DBIAS_HVT_M (EFUSE_DIG_DBIAS_HVT_V << EFUSE_DIG_DBIAS_HVT_S) #define EFUSE_DIG_DBIAS_HVT_V 0x0000001FU #define EFUSE_DIG_DBIAS_HVT_S 11 -/** EFUSE_RESERVED_1_176 : R; bitpos: [22:16]; default: 0; +/** EFUSE_RESERVED_1_176 : R; bitpos: [18:16]; default: 0; * reserved */ -#define EFUSE_RESERVED_1_176 0x0000007FU +#define EFUSE_RESERVED_1_176 0x00000007U #define EFUSE_RESERVED_1_176_M (EFUSE_RESERVED_1_176_V << EFUSE_RESERVED_1_176_S) -#define EFUSE_RESERVED_1_176_V 0x0000007FU +#define EFUSE_RESERVED_1_176_V 0x00000007U #define EFUSE_RESERVED_1_176_S 16 +/** EFUSE_PSRAM_CAP_3 : R; bitpos: [19]; default: 0; + * PSRAM capacity bit 3 + */ +#define EFUSE_PSRAM_CAP_3 (BIT(19)) +#define EFUSE_PSRAM_CAP_3_M (EFUSE_PSRAM_CAP_3_V << EFUSE_PSRAM_CAP_3_S) +#define EFUSE_PSRAM_CAP_3_V 0x00000001U +#define EFUSE_PSRAM_CAP_3_S 19 +/** EFUSE_RESERVED_1_180 : R; bitpos: [22:20]; default: 0; + * reserved + */ +#define EFUSE_RESERVED_1_180 0x00000007U +#define EFUSE_RESERVED_1_180_M (EFUSE_RESERVED_1_180_V << EFUSE_RESERVED_1_180_S) +#define EFUSE_RESERVED_1_180_V 0x00000007U +#define EFUSE_RESERVED_1_180_S 20 /** EFUSE_WAFER_VERSION_MINOR_HI : R; bitpos: [23]; default: 0; * WAFER_VERSION_MINOR most significant bit */ @@ -2638,7 +2652,7 @@ extern "C" { #define EFUSE_CLK_EN_S 16 /** EFUSE_CONF_REG register - * eFuse operation mode configuraiton register + * eFuse operation mode configuration register */ #define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x1cc) /** EFUSE_OP_CODE : R/W; bitpos: [15:0]; default: 0; diff --git a/components/soc/esp32s3/include/soc/efuse_struct.h b/components/soc/esp32s3/include/soc/efuse_struct.h index a3c589f543..a83ab2b03a 100644 --- a/components/soc/esp32s3/include/soc/efuse_struct.h +++ b/components/soc/esp32s3/include/soc/efuse_struct.h @@ -1,5 +1,5 @@ /** - * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -423,7 +423,7 @@ typedef union { */ uint32_t dis_direct_boot:1; /** dis_usb_serial_jtag_rom_print : RO; bitpos: [2]; default: 0; - * Selectes the default UART print channel. 0: UART0. 1: UART1. + * Selects the default UART print channel. 0: UART0. 1: UART1. */ uint32_t dis_usb_serial_jtag_rom_print:1; /** flash_ecc_mode : RO; bitpos: [3]; default: 0; @@ -672,10 +672,18 @@ typedef union { * BLOCK1 digital dbias when hvt */ uint32_t dig_dbias_hvt:5; - /** reserved_1_176 : R; bitpos: [22:16]; default: 0; + /** reserved_1_176 : R; bitpos: [18:16]; default: 0; * reserved */ - uint32_t reserved_1_176:7; + uint32_t reserved_1_176:3; + /** psram_cap_3 : R; bitpos: [19]; default: 0; + * PSRAM capacity bit 3 + */ + uint32_t psram_cap_3:1; + /** reserved_1_180 : R; bitpos: [22:20]; default: 0; + * reserved + */ + uint32_t reserved_1_180:3; /** wafer_version_minor_hi : R; bitpos: [23]; default: 0; * WAFER_VERSION_MINOR most significant bit */ @@ -2163,7 +2171,7 @@ typedef union { } efuse_clk_reg_t; /** Type of conf register - * eFuse operation mode configuraiton register + * eFuse operation mode configuration register */ typedef union { struct {