diff --git a/components/soc/include/soc/soc_memory_layout.h b/components/soc/include/soc/soc_memory_layout.h
index 7d3ef9d618..d4bced993b 100644
--- a/components/soc/include/soc/soc_memory_layout.h
+++ b/components/soc/include/soc/soc_memory_layout.h
@@ -209,8 +209,26 @@ inline static bool IRAM_ATTR esp_ptr_in_diram_iram(const void *p) {
 }
 
 
-inline static bool IRAM_ATTR esp_stack_ptr_is_sane(uint32_t sp)
+inline static bool IRAM_ATTR esp_stack_ptr_in_dram(uint32_t sp)
 {
     //Check if stack ptr is in between SOC_DRAM_LOW and SOC_DRAM_HIGH, and 16 byte aligned.
     return !(sp < SOC_DRAM_LOW + 0x10 || sp > SOC_DRAM_HIGH - 0x10 || ((sp & 0xF) != 0));
 }
+
+#if CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY
+inline static bool IRAM_ATTR esp_stack_ptr_in_extram(uint32_t sp)
+{
+    //Check if stack ptr is in between SOC_EXTRAM_DATA_LOW and SOC_EXTRAM_DATA_HIGH, and 16 byte aligned.
+    return !(sp < SOC_EXTRAM_DATA_LOW + 0x10 || sp > SOC_EXTRAM_DATA_HIGH - 0x10 || ((sp & 0xF) != 0));
+}
+#endif
+
+inline static bool IRAM_ATTR esp_stack_ptr_is_sane(uint32_t sp)
+{
+#if CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY
+    return (esp_stack_ptr_in_dram(sp) || esp_stack_ptr_in_extram(sp));
+#else
+    return esp_stack_ptr_in_dram(sp);
+#endif
+}
+
diff --git a/components/spi_flash/cache_utils.c b/components/spi_flash/cache_utils.c
index b27b968ad6..c825b7e0dd 100644
--- a/components/spi_flash/cache_utils.c
+++ b/components/spi_flash/cache_utils.c
@@ -30,6 +30,7 @@
 #include "esp_intr_alloc.h"
 #include "esp_spi_flash.h"
 #include "esp_log.h"
+#include "soc/soc_memory_layout.h"
 
 
 static void IRAM_ATTR spi_flash_disable_cache(uint32_t cpuid, uint32_t* saved_state);
@@ -92,6 +93,8 @@ void IRAM_ATTR spi_flash_op_block_func(void* arg)
 
 void IRAM_ATTR spi_flash_disable_interrupts_caches_and_other_cpu()
 {
+    assert(esp_ptr_in_dram((const void *)get_sp()));
+
     spi_flash_op_lock();
 
     const uint32_t cpuid = xPortGetCoreID();