espressif/esp-idf
1
0
Fork 1
mirror of https://github.com/espressif/esp-idf.git synced 2025-10-02 18:10:57 +02:00
Code Issues Packages Projects Releases Wiki Activity

Merge branch 'bugfix/fix_esp32_bt_sw_intr_v5.3' into 'release/v5.3'

Browse Source 
fix(bt): fixed sw_intr issue with BT register or trigger error core on ESP32 (v5.3)

See merge request espressif/esp-idf!41635
This commit is contained in:
Wang Meng Yang
2025-09-18 17:47:16 +08:00
parent 93d25275f7 c354e591fe
commit e4e7633f45
1 changed files with 14 additions and 5 deletions
Download Patch File Download Diff File Expand all files Collapse all files

19
components/bt/controller/esp32/bt.c
View File

@@ -882,9 +882,22 @@ static int IRAM_ATTR cause_sw_intr_to_core_wrapper(int core_id, int intr_no)
#if CONFIG_FREERTOS_UNICORE
cause_sw_intr((void *)intr_no);
#else /* CONFIG_FREERTOS_UNICORE */
#if CONFIG_FREERTOS_SMP
uint32_t state = portDISABLE_INTERRUPTS();
#else
uint32_t state = portSET_INTERRUPT_MASK_FROM_ISR();
#endif
if (xPortGetCoreID() == core_id) {
cause_sw_intr((void *)intr_no);
#if CONFIG_FREERTOS_SMP
portRESTORE_INTERRUPTS(state);
} else {
portRESTORE_INTERRUPTS(state);
#else
portCLEAR_INTERRUPT_MASK_FROM_ISR(state);
} else {
portCLEAR_INTERRUPT_MASK_FROM_ISR(state);
#endif
err = esp_ipc_call(core_id, cause_sw_intr, (void *)intr_no);
}
#endif /* !CONFIG_FREERTOS_UNICORE */
@@ -1505,11 +1518,7 @@ static void hli_queue_setup_pinned_to_core(int core_id)
#if CONFIG_FREERTOS_UNICORE
hli_queue_setup_cb(NULL);
#else /* CONFIG_FREERTOS_UNICORE */
if (xPortGetCoreID() == core_id) {
hli_queue_setup_cb(NULL);
} else {
esp_ipc_call(core_id, hli_queue_setup_cb, NULL);
}
esp_ipc_call_blocking(core_id, hli_queue_setup_cb, NULL);
#endif /* !CONFIG_FREERTOS_UNICORE */
}
#endif /* CONFIG_BTDM_CTRL_HLI */