From e8d5bdd51c9b663664029b907a19719db22349e6 Mon Sep 17 00:00:00 2001 From: Erhan Kurubas Date: Wed, 11 Jun 2025 22:18:53 +0200 Subject: [PATCH] change(sysview): set default core name as core0 --- .../Config/esp/SEGGER_SYSVIEW_Config_FreeRTOS.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/components/app_trace/sys_view/Sample/FreeRTOSV10.4/Config/esp/SEGGER_SYSVIEW_Config_FreeRTOS.c b/components/app_trace/sys_view/Sample/FreeRTOSV10.4/Config/esp/SEGGER_SYSVIEW_Config_FreeRTOS.c index fcf33d365a..da20d6cb02 100644 --- a/components/app_trace/sys_view/Sample/FreeRTOSV10.4/Config/esp/SEGGER_SYSVIEW_Config_FreeRTOS.c +++ b/components/app_trace/sys_view/Sample/FreeRTOSV10.4/Config/esp/SEGGER_SYSVIEW_Config_FreeRTOS.c @@ -3,7 +3,7 @@ * * SPDX-License-Identifier: BSD-1-Clause * - * SPDX-FileContributor: 2017-2022 Espressif Systems (Shanghai) CO LTD + * SPDX-FileContributor: 2017-2025 Espressif Systems (Shanghai) CO LTD */ /********************************************************************* * SEGGER Microcontroller GmbH * @@ -83,11 +83,7 @@ extern const SEGGER_SYSVIEW_OS_API SYSVIEW_X_OS_TraceAPI; // The target device name #define SYSVIEW_DEVICE_NAME CONFIG_IDF_TARGET // The target core name -#if CONFIG_IDF_TARGET_ARCH_XTENSA -#define SYSVIEW_CORE_NAME "xtensa" -#elif CONFIG_IDF_TARGET_ARCH_RISCV -#define SYSVIEW_CORE_NAME "riscv" -#endif +#define SYSVIEW_CORE_NAME "core0" // In dual core, this will be renamed by OpenOCD as core1 // Determine which timer to use as timestamp source #if CONFIG_APPTRACE_SV_TS_SOURCE_CCOUNT