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Merge branch 'bugfix/periph_clk_init_p4_v5.4' into 'release/v5.4'

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fix(esp_system): hp periph clk should not be gated on core/system reset (v5.4)

See merge request espressif/esp-idf!35403
This commit is contained in:
Jiang Jiang Jian
2024-12-13 13:55:16 +08:00
parent 829419cef9 77e88f98cd
commit e8e8e2bc2a
3 changed files with 53 additions and 34 deletions
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6
components/bootloader_support/src/bootloader_console.c
View File

@@ -74,6 +74,12 @@ void bootloader_console_init(void)
// Enable the peripheral
uart_ll_enable_bus_clock(uart_num, true);
uart_ll_reset_register(uart_num);
// Set clock source
#if SOC_UART_SUPPORT_XTAL_CLK
uart_ll_set_sclk(UART_LL_GET_HW(uart_num), (soc_module_clk_t)UART_SCLK_XTAL);
#else
uart_ll_set_sclk(UART_LL_GET_HW(uart_num), (soc_module_clk_t)UART_SCLK_APB);
#endif
// Reset TX and RX FIFOs
uart_ll_txfifo_rst(UART_LL_GET_HW(uart_num));
uart_ll_rxfifo_rst(UART_LL_GET_HW(uart_num));

2
components/esp_system/port/soc/esp32c6/clk.c
View File

@@ -316,8 +316,8 @@ __attribute__((weak)) void esp_perip_clk_init(void)
if ((rst_reason == RESET_REASON_CHIP_POWER_ON) || (rst_reason == RESET_REASON_CHIP_BROWN_OUT) \
|| (rst_reason == RESET_REASON_SYS_RTC_WDT) || (rst_reason == RESET_REASON_SYS_SUPER_WDT)) {
_lp_i2c_ll_enable_bus_clock(0, false);
_lp_uart_ll_enable_bus_clock(0, false);
lp_uart_ll_sclk_disable(0);
_lp_uart_ll_enable_bus_clock(0, false);
lp_core_ll_enable_bus_clock(false);
_lp_clkrst_ll_enable_rng_clock(false);

39
components/esp_system/port/soc/esp32p4/clk.c
View File

@@ -243,9 +243,13 @@ __attribute__((weak)) void esp_perip_clk_init(void)
}
soc_reset_reason_t rst_reason = esp_rom_get_reset_reason(0);
if ((rst_reason != RESET_REASON_CPU0_SW) && (rst_reason != RESET_REASON_CPU_MWDT) \
&& (rst_reason != RESET_REASON_CPU_RWDT) && (rst_reason != RESET_REASON_CPU_JTAG) \
&& (rst_reason != RESET_REASON_CPU_LOCKUP)) {
// HP modules related clock control
if ((rst_reason == RESET_REASON_CHIP_POWER_ON) || (rst_reason == RESET_REASON_CORE_PMU_PWR_DOWN)
|| (rst_reason == RESET_REASON_SYS_BROWN_OUT) || (rst_reason == RESET_REASON_SYS_RWDT) || (rst_reason == RESET_REASON_SYS_SUPER_WDT)
|| (rst_reason == RESET_REASON_CORE_SW) || (rst_reason == RESET_REASON_CORE_MWDT) || (rst_reason == RESET_REASON_CORE_RWDT) || (rst_reason == RESET_REASON_CORE_PWR_GLITCH) || (rst_reason == RESET_REASON_CORE_EFUSE_CRC) || (rst_reason == RESET_REASON_CORE_USB_JTAG) || (rst_reason == RESET_REASON_CORE_USB_UART)
) {
// hp_sys_clkrst register gets reset only if chip reset or pmu powers down hp
// but at core reset and above, we will also disable HP modules' clock gating to save power consumption
_gdma_ll_enable_bus_clock(0, false);
_gdma_ll_enable_bus_clock(1, false);
_pau_ll_enable_bus_clock(false);
@@ -302,14 +306,6 @@ __attribute__((weak)) void esp_perip_clk_init(void)
_psram_ctrlr_ll_enable_module_clock(PSRAM_CTRLR_LL_MSPI_ID_2, false);
#endif
REG_CLR_BIT(HP_SYS_CLKRST_REF_CLK_CTRL1_REG, HP_SYS_CLKRST_REG_REF_50M_CLK_EN);
REG_CLR_BIT(HP_SYS_CLKRST_REF_CLK_CTRL1_REG, HP_SYS_CLKRST_REG_REF_25M_CLK_EN);
// 240M CLK is for Key Management use, should not be gated
REG_CLR_BIT(HP_SYS_CLKRST_REF_CLK_CTRL2_REG, HP_SYS_CLKRST_REG_REF_160M_CLK_EN);
REG_CLR_BIT(HP_SYS_CLKRST_REF_CLK_CTRL2_REG, HP_SYS_CLKRST_REG_REF_120M_CLK_EN);
REG_CLR_BIT(HP_SYS_CLKRST_REF_CLK_CTRL2_REG, HP_SYS_CLKRST_REG_REF_80M_CLK_EN);
REG_CLR_BIT(HP_SYS_CLKRST_REF_CLK_CTRL2_REG, HP_SYS_CLKRST_REG_REF_20M_CLK_EN);
_spi_ll_enable_bus_clock(SPI2_HOST, false);
_spi_ll_enable_bus_clock(SPI3_HOST, false);
_spi_ll_enable_clock(SPI2_HOST, false);
@@ -356,12 +352,28 @@ __attribute__((weak)) void esp_perip_clk_init(void)
#endif
}
// HP modules' clock source gating control
if ((rst_reason == RESET_REASON_CHIP_POWER_ON) || (rst_reason == RESET_REASON_CORE_PMU_PWR_DOWN)) {
// Only safe to disable these clock source gatings if all HP modules clock configurations has been reset
REG_CLR_BIT(HP_SYS_CLKRST_REF_CLK_CTRL1_REG, HP_SYS_CLKRST_REG_REF_50M_CLK_EN);
REG_CLR_BIT(HP_SYS_CLKRST_REF_CLK_CTRL1_REG, HP_SYS_CLKRST_REG_REF_25M_CLK_EN);
// 240M CLK is for Key Management use, should not be gated
REG_CLR_BIT(HP_SYS_CLKRST_REF_CLK_CTRL2_REG, HP_SYS_CLKRST_REG_REF_160M_CLK_EN);
REG_CLR_BIT(HP_SYS_CLKRST_REF_CLK_CTRL2_REG, HP_SYS_CLKRST_REG_REF_120M_CLK_EN);
REG_CLR_BIT(HP_SYS_CLKRST_REF_CLK_CTRL2_REG, HP_SYS_CLKRST_REG_REF_80M_CLK_EN);
REG_CLR_BIT(HP_SYS_CLKRST_REF_CLK_CTRL2_REG, HP_SYS_CLKRST_REG_REF_20M_CLK_EN);
}
// LP related clock control
if ((rst_reason == RESET_REASON_CHIP_POWER_ON) || (rst_reason == RESET_REASON_SYS_SUPER_WDT) \
|| (rst_reason == RESET_REASON_SYS_RWDT) || (rst_reason == RESET_REASON_SYS_BROWN_OUT)) {
_lp_uart_ll_enable_bus_clock(0, false);
// lpperi,lp peripheral registers get reset for reset level equal or higher than system reset
lp_uart_ll_sclk_disable(0);
_lp_uart_ll_enable_bus_clock(0, false);
_rtcio_ll_enable_io_clock(false);
// LP_Peri & Clock Control
if (rst_reason == RESET_REASON_CHIP_POWER_ON) {
// lp_aon_clkrst, lp_system registers get reset only if chip reset
_uart_ll_enable_pad_sleep_clock(&UART0, false);
_uart_ll_enable_pad_sleep_clock(&UART1, false);
_uart_ll_enable_pad_sleep_clock(&UART2, false);
@@ -386,3 +398,4 @@ __attribute__((weak)) void esp_perip_clk_init(void)
REG_CLR_BIT(LP_SYSTEM_REG_HP_ROOT_CLK_CTRL_REG, LP_SYSTEM_REG_CPU_CLK_EN);
}
}
}