From a1494809b2852cf713029935ab7c0f5a13eba2cf Mon Sep 17 00:00:00 2001 From: morris Date: Mon, 17 May 2021 11:08:17 +0800 Subject: [PATCH 1/6] rmt: clean up LL driver --- components/driver/rmt.c | 4 +- components/hal/esp32/include/hal/rmt_ll.h | 44 +++++++++---------- components/hal/esp32c3/include/hal/rmt_ll.h | 35 +++++++-------- components/hal/esp32s2/include/hal/rmt_ll.h | 39 +++++++--------- components/hal/esp32s3/include/hal/rmt_ll.h | 34 +++++++------- components/hal/rmt_hal.c | 1 + .../soc/esp32s2/include/soc/rmt_struct.h | 11 ----- 7 files changed, 72 insertions(+), 96 deletions(-) diff --git a/components/driver/rmt.c b/components/driver/rmt.c index 03deac5b25..7e8b7d5ef3 100644 --- a/components/driver/rmt.c +++ b/components/driver/rmt.c @@ -441,14 +441,14 @@ esp_err_t rmt_get_status(rmt_channel_t channel, uint32_t *status) void rmt_set_intr_enable_mask(uint32_t mask) { RMT_ENTER_CRITICAL(); - rmt_ll_set_intr_enable_mask(mask); + rmt_ll_enable_interrupt(rmt_contex.hal.regs, mask, true); RMT_EXIT_CRITICAL(); } void rmt_clr_intr_enable_mask(uint32_t mask) { RMT_ENTER_CRITICAL(); - rmt_ll_clr_intr_enable_mask(mask); + rmt_ll_enable_interrupt(rmt_contex.hal.regs, mask, false); RMT_EXIT_CRITICAL(); } diff --git a/components/hal/esp32/include/hal/rmt_ll.h b/components/hal/esp32/include/hal/rmt_ll.h index af7e8b5a2f..edd4f27912 100644 --- a/components/hal/esp32/include/hal/rmt_ll.h +++ b/components/hal/esp32/include/hal/rmt_ll.h @@ -14,8 +14,8 @@ #pragma once #include +#include #include "soc/rmt_struct.h" -#include "soc/soc_caps.h" #ifdef __cplusplus extern "C" { @@ -174,6 +174,11 @@ static inline bool rmt_ll_is_tx_loop_enabled(rmt_dev_t *dev, uint32_t channel) return dev->conf_ch[channel].conf1.tx_conti_mode; } +static inline void rmt_ll_tx_reset_loop(rmt_dev_t *dev, uint32_t channel) +{ + // RMT on esp32 doesn't support loop count, adding this only for HAL API consistency +} + static inline void rmt_ll_rx_enable_filter(rmt_dev_t *dev, uint32_t channel, bool enable) { dev->conf_ch[channel].conf1.rx_filter_en = enable; @@ -219,6 +224,15 @@ static inline void rmt_ll_tx_set_limit(rmt_dev_t *dev, uint32_t channel, uint32_ dev->tx_lim_ch[channel].limit = limit; } +static inline void rmt_ll_enable_interrupt(rmt_dev_t *dev, uint32_t mask, bool enable) +{ + if (enable) { + dev->int_ena.val |= mask; + } else { + dev->int_ena.val &= ~mask; + } +} + static inline void rmt_ll_enable_tx_end_interrupt(rmt_dev_t *dev, uint32_t channel, bool enable) { dev->int_ena.val &= ~(1 << (channel * 3)); @@ -330,33 +344,17 @@ static inline void rmt_ll_tx_set_carrier_level(rmt_dev_t *dev, uint32_t channel, dev->conf_ch[channel].conf0.carrier_out_lv = level; } -//Writes items to the specified TX channel memory with the given offset and writen length. +//Writes items to the specified TX channel memory with the given offset and length. //the caller should ensure that (length + off) <= (memory block * SOC_RMT_MEM_WORDS_PER_CHANNEL) -static inline void rmt_ll_write_memory(rmt_mem_t *mem, uint32_t channel, const rmt_item32_t *data, uint32_t length, uint32_t off) +static inline void rmt_ll_write_memory(rmt_mem_t *mem, uint32_t channel, const void *data, size_t length_in_words, size_t off) { - for (uint32_t i = 0; i < length; i++) { - mem->chan[channel].data32[i + off].val = data[i].val; + volatile uint32_t *to = (volatile uint32_t *)&mem->chan[channel].data32[off]; + uint32_t *from = (uint32_t *)data; + while (length_in_words--) { + *to++ = *from++; } } -static inline void rmt_ll_config_update(rmt_dev_t *dev, uint32_t channel) -{ -} - -/************************************************************************************************ - * Following Low Level APIs only used for backward compatible, will be deprecated in the IDF v5.0 - ***********************************************************************************************/ - -static inline void rmt_ll_set_intr_enable_mask(uint32_t mask) -{ - RMT.int_ena.val |= mask; -} - -static inline void rmt_ll_clr_intr_enable_mask(uint32_t mask) -{ - RMT.int_ena.val &= (~mask); -} - #ifdef __cplusplus } #endif diff --git a/components/hal/esp32c3/include/hal/rmt_ll.h b/components/hal/esp32c3/include/hal/rmt_ll.h index a323adfbc1..f5427d150a 100644 --- a/components/hal/esp32c3/include/hal/rmt_ll.h +++ b/components/hal/esp32c3/include/hal/rmt_ll.h @@ -15,8 +15,8 @@ #include #include +#include #include "soc/rmt_struct.h" -#include "soc/soc_caps.h" #ifdef __cplusplus extern "C" { @@ -279,6 +279,15 @@ static inline uint32_t rmt_ll_rx_get_limit(rmt_dev_t *dev, uint32_t channel) return dev->rx_lim[channel].rx_lim; } +static inline void rmt_ll_enable_interrupt(rmt_dev_t *dev, uint32_t mask, bool enable) +{ + if (enable) { + dev->int_ena.val |= mask; + } else { + dev->int_ena.val &= ~mask; + } +} + static inline void rmt_ll_enable_tx_end_interrupt(rmt_dev_t *dev, uint32_t channel, bool enable) { if (enable) { @@ -469,12 +478,14 @@ static inline void rmt_ll_tx_set_carrier_always_on(rmt_dev_t *dev, uint32_t chan dev->tx_conf[channel].carrier_eff_en = !enable; } -//Writes items to the specified TX channel memory with the given offset and writen length. +//Writes items to the specified TX channel memory with the given offset and length. //the caller should ensure that (length + off) <= (memory block * SOC_RMT_MEM_WORDS_PER_CHANNEL) -static inline void rmt_ll_write_memory(rmt_mem_t *mem, uint32_t channel, const rmt_item32_t *data, uint32_t length, uint32_t off) +static inline void rmt_ll_write_memory(rmt_mem_t *mem, uint32_t channel, const void *data, size_t length_in_words, size_t off) { - for (uint32_t i = 0; i < length; i++) { - mem->chan[channel].data32[i + off].val = data[i].val; + volatile uint32_t *to = (volatile uint32_t *)&mem->chan[channel].data32[off]; + uint32_t *from = (uint32_t *)data; + while (length_in_words--) { + *to++ = *from++; } } @@ -483,20 +494,6 @@ static inline void rmt_ll_rx_enable_pingpong(rmt_dev_t *dev, uint32_t channel, b dev->rx_conf[channel].conf1.mem_rx_wrap_en = enable; } -/************************************************************************************************ - * Following Low Level APIs only used for backward compatible, will be deprecated in the IDF v5.0 - ***********************************************************************************************/ - -static inline void rmt_ll_set_intr_enable_mask(uint32_t mask) -{ - RMT.int_ena.val |= mask; -} - -static inline void rmt_ll_clr_intr_enable_mask(uint32_t mask) -{ - RMT.int_ena.val &= (~mask); -} - #ifdef __cplusplus } #endif diff --git a/components/hal/esp32s2/include/hal/rmt_ll.h b/components/hal/esp32s2/include/hal/rmt_ll.h index 0a71250dfc..0354afc766 100644 --- a/components/hal/esp32s2/include/hal/rmt_ll.h +++ b/components/hal/esp32s2/include/hal/rmt_ll.h @@ -14,7 +14,7 @@ #pragma once #include -#include "soc/soc_caps.h" +#include #include "soc/rmt_struct.h" #ifdef __cplusplus @@ -267,6 +267,15 @@ static inline uint32_t rmt_ll_rx_get_limit(rmt_dev_t *dev, uint32_t channel) return dev->tx_lim_ch[channel].rx_lim; } +static inline void rmt_ll_enable_interrupt(rmt_dev_t *dev, uint32_t mask, bool enable) +{ + if (enable) { + dev->int_ena.val |= mask; + } else { + dev->int_ena.val &= ~mask; + } +} + static inline void rmt_ll_enable_tx_end_interrupt(rmt_dev_t *dev, uint32_t channel, bool enable) { dev->int_ena.val &= ~(1 << (channel * 3)); @@ -443,12 +452,14 @@ static inline void rmt_ll_tx_set_carrier_always_on(rmt_dev_t *dev, uint32_t chan dev->conf_ch[channel].conf0.carrier_eff_en = !enable; } -//Writes items to the specified TX channel memory with the given offset and writen length. +//Writes items to the specified TX channel memory with the given offset and length. //the caller should ensure that (length + off) <= (memory block * SOC_RMT_MEM_WORDS_PER_CHANNEL) -static inline void rmt_ll_write_memory(rmt_mem_t *mem, uint32_t channel, const rmt_item32_t *data, uint32_t length, uint32_t off) +static inline void rmt_ll_write_memory(rmt_mem_t *mem, uint32_t channel, const void *data, size_t length_in_words, size_t off) { - for (uint32_t i = 0; i < length; i++) { - mem->chan[channel].data32[i + off].val = data[i].val; + volatile uint32_t *to = (volatile uint32_t *)&mem->chan[channel].data32[off]; + uint32_t *from = (uint32_t *)data; + while (length_in_words--) { + *to++ = *from++; } } @@ -457,24 +468,6 @@ static inline void rmt_ll_rx_enable_pingpong(rmt_dev_t *dev, uint32_t channel, b dev->conf_ch[channel].conf1.chk_rx_carrier_en = enable; } -static inline void rmt_ll_config_update(rmt_dev_t *dev, uint32_t channel) -{ -} - -/************************************************************************************************ - * Following Low Level APIs only used for backward compatible, will be deprecated in the IDF v5.0 - ***********************************************************************************************/ - -static inline void rmt_ll_set_intr_enable_mask(uint32_t mask) -{ - RMT.int_ena.val |= mask; -} - -static inline void rmt_ll_clr_intr_enable_mask(uint32_t mask) -{ - RMT.int_ena.val &= (~mask); -} - #ifdef __cplusplus } #endif diff --git a/components/hal/esp32s3/include/hal/rmt_ll.h b/components/hal/esp32s3/include/hal/rmt_ll.h index 03795f6fae..b5ef90004d 100644 --- a/components/hal/esp32s3/include/hal/rmt_ll.h +++ b/components/hal/esp32s3/include/hal/rmt_ll.h @@ -14,6 +14,7 @@ #pragma once #include +#include #include #include "soc/rmt_struct.h" #include "soc/soc_caps.h" @@ -279,6 +280,15 @@ static inline uint32_t rmt_ll_rx_get_limit(rmt_dev_t *dev, uint32_t channel) return dev->rx_lim[channel].rx_lim; } +static inline void rmt_ll_enable_interrupt(rmt_dev_t *dev, uint32_t mask, bool enable) +{ + if (enable) { + dev->int_ena.val |= mask; + } else { + dev->int_ena.val &= ~mask; + } +} + static inline void rmt_ll_enable_tx_end_interrupt(rmt_dev_t *dev, uint32_t channel, bool enable) { if (enable) { @@ -469,12 +479,14 @@ static inline void rmt_ll_tx_set_carrier_always_on(rmt_dev_t *dev, uint32_t chan dev->tx_conf[channel].carrier_eff_en = !enable; } -//Writes items to the specified TX channel memory with the given offset and writen length. +//Writes items to the specified TX channel memory with the given offset and length. //the caller should ensure that (length + off) <= (memory block * SOC_RMT_MEM_WORDS_PER_CHANNEL) -static inline void rmt_ll_write_memory(rmt_mem_t *mem, uint32_t channel, const rmt_item32_t *data, uint32_t length, uint32_t off) +static inline void rmt_ll_write_memory(rmt_mem_t *mem, uint32_t channel, const void *data, size_t length_in_words, size_t off) { - for (uint32_t i = 0; i < length; i++) { - mem->chan[channel].data32[i + off].val = data[i].val; + volatile uint32_t *to = (volatile uint32_t *)&mem->chan[channel].data32[off]; + uint32_t *from = (uint32_t *)data; + while (length_in_words--) { + *to++ = *from++; } } @@ -483,20 +495,6 @@ static inline void rmt_ll_rx_enable_pingpong(rmt_dev_t *dev, uint32_t channel, b dev->rx_conf[channel].conf1.mem_rx_wrap_en = enable; } -/************************************************************************************************ - * Following Low Level APIs only used for backward compatible, will be deprecated in the IDF v5.0 - ***********************************************************************************************/ - -static inline void rmt_ll_set_intr_enable_mask(uint32_t mask) -{ - RMT.int_ena.val |= mask; -} - -static inline void rmt_ll_clr_intr_enable_mask(uint32_t mask) -{ - RMT.int_ena.val &= (~mask); -} - #ifdef __cplusplus } #endif diff --git a/components/hal/rmt_hal.c b/components/hal/rmt_hal.c index 7c885784fb..bdb6942690 100644 --- a/components/hal/rmt_hal.c +++ b/components/hal/rmt_hal.c @@ -24,6 +24,7 @@ void rmt_hal_init(rmt_hal_context_t *hal) void rmt_hal_tx_channel_reset(rmt_hal_context_t *hal, uint32_t channel) { rmt_ll_tx_reset_pointer(hal->regs, channel); + rmt_ll_tx_reset_loop(hal->regs, channel); rmt_ll_enable_tx_err_interrupt(hal->regs, channel, false); rmt_ll_enable_tx_end_interrupt(hal->regs, channel, false); rmt_ll_enable_tx_thres_interrupt(hal->regs, channel, false); diff --git a/components/soc/esp32s2/include/soc/rmt_struct.h b/components/soc/esp32s2/include/soc/rmt_struct.h index e33fb3aff0..b92c42a775 100644 --- a/components/soc/esp32s2/include/soc/rmt_struct.h +++ b/components/soc/esp32s2/include/soc/rmt_struct.h @@ -299,22 +299,11 @@ typedef struct { }; } rmt_item32_t; -typedef struct { - union { - struct { - uint16_t duration :15; - uint16_t level :1; - }; - uint16_t val; - }; -} rmt_item16_t; - //Allow access to RMT memory using RMTMEM.chan[0].data32[8] typedef volatile struct { struct { union { rmt_item32_t data32[64]; - rmt_item16_t data16[128]; }; } chan[4]; } rmt_mem_t; From 8e483e34a85fc29fb318e786d163e571e54ed692 Mon Sep 17 00:00:00 2001 From: morris Date: Tue, 20 Apr 2021 14:36:34 +0800 Subject: [PATCH 2/6] rmt: restructure rmt_signal_conn_t --- components/driver/rmt.c | 12 ++--- components/hal/include/hal/rmt_types.h | 4 +- components/soc/esp32/rmt_periph.c | 70 +++++++++++++------------ components/soc/esp32c3/rmt_periph.c | 40 +++++++------- components/soc/esp32s2/rmt_periph.c | 38 ++++++++------ components/soc/esp32s3/rmt_periph.c | 70 +++++++++++++------------ components/soc/include/soc/rmt_periph.h | 14 ++--- 7 files changed, 133 insertions(+), 115 deletions(-) diff --git a/components/driver/rmt.c b/components/driver/rmt.c index 7e8b7d5ef3..66f39929eb 100644 --- a/components/driver/rmt.c +++ b/components/driver/rmt.c @@ -125,8 +125,8 @@ static void rmt_module_enable(void) { RMT_ENTER_CRITICAL(); if (rmt_contex.rmt_module_enabled == false) { - periph_module_reset(rmt_periph_signals.module); - periph_module_enable(rmt_periph_signals.module); + periph_module_reset(rmt_periph_signals.groups[0].module); + periph_module_enable(rmt_periph_signals.groups[0].module); rmt_contex.rmt_module_enabled = true; } RMT_EXIT_CRITICAL(); @@ -137,7 +137,7 @@ static void rmt_module_disable(void) { RMT_ENTER_CRITICAL(); if (rmt_contex.rmt_module_enabled == true) { - periph_module_disable(rmt_periph_signals.module); + periph_module_disable(rmt_periph_signals.groups[0].module); rmt_contex.rmt_module_enabled = false; } RMT_EXIT_CRITICAL(); @@ -533,11 +533,11 @@ esp_err_t rmt_set_gpio(rmt_channel_t channel, rmt_mode_t mode, gpio_num_t gpio_n if (mode == RMT_MODE_TX) { RMT_CHECK(RMT_IS_TX_CHANNEL(channel), RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG); gpio_set_direction(gpio_num, GPIO_MODE_OUTPUT); - esp_rom_gpio_connect_out_signal(gpio_num, rmt_periph_signals.channels[channel].tx_sig, invert_signal, 0); + esp_rom_gpio_connect_out_signal(gpio_num, rmt_periph_signals.groups[0].channels[channel].tx_sig, invert_signal, 0); } else { RMT_CHECK(RMT_IS_RX_CHANNEL(channel), RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG); gpio_set_direction(gpio_num, GPIO_MODE_INPUT); - esp_rom_gpio_connect_in_signal(gpio_num, rmt_periph_signals.channels[channel].rx_sig, invert_signal); + esp_rom_gpio_connect_in_signal(gpio_num, rmt_periph_signals.groups[0].channels[channel].rx_sig, invert_signal); } return ESP_OK; } @@ -722,7 +722,7 @@ esp_err_t rmt_isr_register(void (*fn)(void *), void *arg, int intr_alloc_flags, RMT_CHECK((fn != NULL), RMT_ADDR_ERROR_STR, ESP_ERR_INVALID_ARG); RMT_CHECK(rmt_contex.rmt_driver_channels == 0, "RMT driver installed, can not install generic ISR handler", ESP_FAIL); - return esp_intr_alloc(rmt_periph_signals.irq, intr_alloc_flags, fn, arg, handle); + return esp_intr_alloc(rmt_periph_signals.groups[0].irq, intr_alloc_flags, fn, arg, handle); } esp_err_t rmt_isr_deregister(rmt_isr_handle_t handle) diff --git a/components/hal/include/hal/rmt_types.h b/components/hal/include/hal/rmt_types.h index 28b5bf59a3..9669fd4885 100644 --- a/components/hal/include/hal/rmt_types.h +++ b/components/hal/include/hal/rmt_types.h @@ -14,12 +14,12 @@ #pragma once +#include "soc/soc_caps.h" + #ifdef __cplusplus extern "C" { #endif -#include "soc/soc_caps.h" - /** * @brief RMT channel ID * diff --git a/components/soc/esp32/rmt_periph.c b/components/soc/esp32/rmt_periph.c index 98a9c7b7ae..48d5ea0b02 100644 --- a/components/soc/esp32/rmt_periph.c +++ b/components/soc/esp32/rmt_periph.c @@ -17,40 +17,44 @@ #include "soc/soc.h" const rmt_signal_conn_t rmt_periph_signals = { - .module = PERIPH_RMT_MODULE, - .irq = ETS_RMT_INTR_SOURCE, - .channels = { + .groups = { [0] = { - .tx_sig = RMT_SIG_OUT0_IDX, - .rx_sig = RMT_SIG_IN0_IDX - }, - [1] = { - .tx_sig = RMT_SIG_OUT1_IDX, - .rx_sig = RMT_SIG_IN1_IDX - }, - [2] = { - .tx_sig = RMT_SIG_OUT2_IDX, - .rx_sig = RMT_SIG_IN2_IDX - }, - [3] = { - .tx_sig = RMT_SIG_OUT3_IDX, - .rx_sig = RMT_SIG_IN3_IDX - }, - [4] = { - .tx_sig = RMT_SIG_OUT4_IDX, - .rx_sig = RMT_SIG_IN4_IDX - }, - [5] = { - .tx_sig = RMT_SIG_OUT5_IDX, - .rx_sig = RMT_SIG_IN5_IDX - }, - [6] = { - .tx_sig = RMT_SIG_OUT6_IDX, - .rx_sig = RMT_SIG_IN6_IDX - }, - [7] = { - .tx_sig = RMT_SIG_OUT7_IDX, - .rx_sig = RMT_SIG_IN7_IDX + .module = PERIPH_RMT_MODULE, + .irq = ETS_RMT_INTR_SOURCE, + .channels = { + [0] = { + .tx_sig = RMT_SIG_OUT0_IDX, + .rx_sig = RMT_SIG_IN0_IDX + }, + [1] = { + .tx_sig = RMT_SIG_OUT1_IDX, + .rx_sig = RMT_SIG_IN1_IDX + }, + [2] = { + .tx_sig = RMT_SIG_OUT2_IDX, + .rx_sig = RMT_SIG_IN2_IDX + }, + [3] = { + .tx_sig = RMT_SIG_OUT3_IDX, + .rx_sig = RMT_SIG_IN3_IDX + }, + [4] = { + .tx_sig = RMT_SIG_OUT4_IDX, + .rx_sig = RMT_SIG_IN4_IDX + }, + [5] = { + .tx_sig = RMT_SIG_OUT5_IDX, + .rx_sig = RMT_SIG_IN5_IDX + }, + [6] = { + .tx_sig = RMT_SIG_OUT6_IDX, + .rx_sig = RMT_SIG_IN6_IDX + }, + [7] = { + .tx_sig = RMT_SIG_OUT7_IDX, + .rx_sig = RMT_SIG_IN7_IDX + } + } } } }; diff --git a/components/soc/esp32c3/rmt_periph.c b/components/soc/esp32c3/rmt_periph.c index 1556cf92f4..8405b76487 100644 --- a/components/soc/esp32c3/rmt_periph.c +++ b/components/soc/esp32c3/rmt_periph.c @@ -16,24 +16,28 @@ #include "soc/gpio_sig_map.h" const rmt_signal_conn_t rmt_periph_signals = { - .module = PERIPH_RMT_MODULE, - .irq = ETS_RMT_INTR_SOURCE, - .channels = { + .groups = { [0] = { - .tx_sig = RMT_SIG_OUT0_IDX, - .rx_sig = -1 - }, - [1] = { - .tx_sig = RMT_SIG_OUT1_IDX, - .rx_sig = -1 - }, - [2] = { - .tx_sig = -1, - .rx_sig = RMT_SIG_IN0_IDX - }, - [3] = { - .tx_sig = -1, - .rx_sig = RMT_SIG_IN1_IDX - }, + .module = PERIPH_RMT_MODULE, + .irq = ETS_RMT_INTR_SOURCE, + .channels = { + [0] = { + .tx_sig = RMT_SIG_OUT0_IDX, + .rx_sig = -1 + }, + [1] = { + .tx_sig = RMT_SIG_OUT1_IDX, + .rx_sig = -1 + }, + [2] = { + .tx_sig = -1, + .rx_sig = RMT_SIG_IN0_IDX + }, + [3] = { + .tx_sig = -1, + .rx_sig = RMT_SIG_IN1_IDX + }, + } + } } }; diff --git a/components/soc/esp32s2/rmt_periph.c b/components/soc/esp32s2/rmt_periph.c index 35bd844145..59ddb0613d 100644 --- a/components/soc/esp32s2/rmt_periph.c +++ b/components/soc/esp32s2/rmt_periph.c @@ -16,24 +16,28 @@ #include "soc/gpio_sig_map.h" const rmt_signal_conn_t rmt_periph_signals = { - .module = PERIPH_RMT_MODULE, - .irq = ETS_RMT_INTR_SOURCE, - .channels = { + .groups = { [0] = { - .tx_sig = RMT_SIG_OUT0_IDX, - .rx_sig = RMT_SIG_IN0_IDX - }, - [1] = { - .tx_sig = RMT_SIG_OUT1_IDX, - .rx_sig = RMT_SIG_IN1_IDX - }, - [2] = { - .tx_sig = RMT_SIG_OUT2_IDX, - .rx_sig = RMT_SIG_IN2_IDX - }, - [3] = { - .tx_sig = RMT_SIG_OUT3_IDX, - .rx_sig = RMT_SIG_IN3_IDX + .module = PERIPH_RMT_MODULE, + .irq = ETS_RMT_INTR_SOURCE, + .channels = { + [0] = { + .tx_sig = RMT_SIG_OUT0_IDX, + .rx_sig = RMT_SIG_IN0_IDX + }, + [1] = { + .tx_sig = RMT_SIG_OUT1_IDX, + .rx_sig = RMT_SIG_IN1_IDX + }, + [2] = { + .tx_sig = RMT_SIG_OUT2_IDX, + .rx_sig = RMT_SIG_IN2_IDX + }, + [3] = { + .tx_sig = RMT_SIG_OUT3_IDX, + .rx_sig = RMT_SIG_IN3_IDX + } + } } } }; diff --git a/components/soc/esp32s3/rmt_periph.c b/components/soc/esp32s3/rmt_periph.c index 611d6425f6..4581bd30a7 100644 --- a/components/soc/esp32s3/rmt_periph.c +++ b/components/soc/esp32s3/rmt_periph.c @@ -16,40 +16,44 @@ #include "soc/gpio_sig_map.h" const rmt_signal_conn_t rmt_periph_signals = { - .module = PERIPH_RMT_MODULE, - .irq = ETS_RMT_INTR_SOURCE, - .channels = { + .groups = { [0] = { - .tx_sig = RMT_SIG_OUT0_IDX, - .rx_sig = -1 - }, - [1] = { - .tx_sig = RMT_SIG_OUT1_IDX, - .rx_sig = -1 - }, - [2] = { - .tx_sig = RMT_SIG_OUT2_IDX, - .rx_sig = -1 - }, - [3] = { - .tx_sig = RMT_SIG_OUT3_IDX, - .rx_sig = -1 - }, - [4] = { - .tx_sig = -1, - .rx_sig = RMT_SIG_IN0_IDX - }, - [5] = { - .tx_sig = -1, - .rx_sig = RMT_SIG_IN1_IDX - }, - [6] = { - .tx_sig = -1, - .rx_sig = RMT_SIG_IN2_IDX - }, - [7] = { - .tx_sig = -1, - .rx_sig = RMT_SIG_IN3_IDX + .module = PERIPH_RMT_MODULE, + .irq = ETS_RMT_INTR_SOURCE, + .channels = { + [0] = { + .tx_sig = RMT_SIG_OUT0_IDX, + .rx_sig = -1 + }, + [1] = { + .tx_sig = RMT_SIG_OUT1_IDX, + .rx_sig = -1 + }, + [2] = { + .tx_sig = RMT_SIG_OUT2_IDX, + .rx_sig = -1 + }, + [3] = { + .tx_sig = RMT_SIG_OUT3_IDX, + .rx_sig = -1 + }, + [4] = { + .tx_sig = -1, + .rx_sig = RMT_SIG_IN0_IDX + }, + [5] = { + .tx_sig = -1, + .rx_sig = RMT_SIG_IN1_IDX + }, + [6] = { + .tx_sig = -1, + .rx_sig = RMT_SIG_IN2_IDX + }, + [7] = { + .tx_sig = -1, + .rx_sig = RMT_SIG_IN3_IDX + } + } } } }; diff --git a/components/soc/include/soc/rmt_periph.h b/components/soc/include/soc/rmt_periph.h index c051889262..0a2d8e2a9a 100644 --- a/components/soc/include/soc/rmt_periph.h +++ b/components/soc/include/soc/rmt_periph.h @@ -23,13 +23,15 @@ extern "C" { typedef struct { struct { + const int irq; + const periph_module_t module; struct { - const int tx_sig; - const int rx_sig; - }; - } channels[SOC_RMT_CHANNELS_PER_GROUP]; - const int irq; - const periph_module_t module; + struct { + const int tx_sig; + const int rx_sig; + }; + } channels[SOC_RMT_CHANNELS_PER_GROUP]; + } groups[SOC_RMT_GROUPS]; } rmt_signal_conn_t; extern const rmt_signal_conn_t rmt_periph_signals; From 8d9e968d3f854083149a917c4c697ec5dd77be2c Mon Sep 17 00:00:00 2001 From: morris Date: Tue, 20 Apr 2021 15:06:12 +0800 Subject: [PATCH 3/6] rmt: fix wrong macro of independent channel clock --- components/driver/rmt.c | 8 ++--- components/soc/esp32s3/include/soc/rmt_caps.h | 30 ------------------- 2 files changed, 4 insertions(+), 34 deletions(-) delete mode 100644 components/soc/esp32s3/include/soc/rmt_caps.h diff --git a/components/driver/rmt.c b/components/driver/rmt.c index 66f39929eb..86532b4b9e 100644 --- a/components/driver/rmt.c +++ b/components/driver/rmt.c @@ -114,7 +114,7 @@ static rmt_contex_t rmt_contex = { static rmt_obj_t *p_rmt_obj[RMT_CHANNEL_MAX] = {0}; -#if SOC_RMT_SOURCE_CLK_INDEPENDENT +#if SOC_RMT_CHANNEL_CLK_INDEPENDENT static uint32_t s_rmt_source_clock_hz[RMT_CHANNEL_MAX]; #else static uint32_t s_rmt_source_clock_hz; @@ -597,7 +597,7 @@ static esp_err_t rmt_internal_config(rmt_dev_t *dev, const rmt_config_t *rmt_par } RMT_EXIT_CRITICAL(); -#if SOC_RMT_SOURCE_CLK_INDEPENDENT +#if SOC_RMT_CHANNEL_CLK_INDEPENDENT s_rmt_source_clock_hz[channel] = rmt_source_clk_hz; #else if (s_rmt_source_clock_hz && rmt_source_clk_hz != s_rmt_source_clock_hz) { @@ -1316,7 +1316,7 @@ esp_err_t rmt_get_counter_clock(rmt_channel_t channel, uint32_t *clock_hz) RMT_CHECK(clock_hz, "parameter clock_hz can't be null", ESP_ERR_INVALID_ARG); RMT_ENTER_CRITICAL(); uint32_t rmt_source_clk_hz = 0; -#if SOC_RMT_SOURCE_CLK_INDEPENDENT +#if SOC_RMT_CHANNEL_CLK_INDEPENDENT rmt_source_clk_hz = s_rmt_source_clock_hz[channel]; #else rmt_source_clk_hz = s_rmt_source_clock_hz; @@ -1355,6 +1355,7 @@ esp_err_t rmt_remove_channel_from_group(rmt_channel_t channel) RMT_EXIT_CRITICAL(); return ESP_OK; } +#endif esp_err_t rmt_memory_rw_rst(rmt_channel_t channel) { @@ -1368,7 +1369,6 @@ esp_err_t rmt_memory_rw_rst(rmt_channel_t channel) RMT_EXIT_CRITICAL(); return ESP_OK; } -#endif #if SOC_RMT_SUPPORT_TX_LOOP_COUNT esp_err_t rmt_set_tx_loop_count(rmt_channel_t channel, uint32_t count) diff --git a/components/soc/esp32s3/include/soc/rmt_caps.h b/components/soc/esp32s3/include/soc/rmt_caps.h deleted file mode 100644 index 43c45b9e1b..0000000000 --- a/components/soc/esp32s3/include/soc/rmt_caps.h +++ /dev/null @@ -1,30 +0,0 @@ -// Copyright 2019-2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. - -#pragma once - -#ifdef __cplusplus -extern "C" { -#endif - -#define SOC_RMT_CHANNEL_MEM_WORDS (64) /*!< Each channel owns 64 words memory (1 word = 4 Bytes) */ -#define SOC_RMT_CHANNELS_NUM (4) /*!< Total 4 channels */ -#define SOC_RMT_SUPPORT_RX_PINGPONG (1) /*!< Support Ping-Pong mode on RX path */ -#define SOC_RMT_SUPPORT_RX_DEMODULATION (1) /*!< Support signal demodulation on RX path (i.e. remove carrier) */ -#define SOC_RMT_SUPPORT_TX_LOOP_COUNT (1) /*!< Support transmit specified number of cycles in loop mode */ -#define SOC_RMT_SUPPORT_TX_GROUP (1) /*!< Support a group of TX channels to transmit simultaneously */ - -#ifdef __cplusplus -} -#endif From 01a28add47a03f07140bdfb91390f678209efd65 Mon Sep 17 00:00:00 2001 From: morris Date: Tue, 20 Apr 2021 15:57:34 +0800 Subject: [PATCH 4/6] rmt: apply general check macro --- components/driver/rmt.c | 237 +++++++++++++++++++--------------------- 1 file changed, 114 insertions(+), 123 deletions(-) diff --git a/components/driver/rmt.c b/components/driver/rmt.c index 86532b4b9e..3165ae59af 100644 --- a/components/driver/rmt.c +++ b/components/driver/rmt.c @@ -10,6 +10,7 @@ #include "esp_compiler.h" #include "esp_intr_alloc.h" #include "esp_log.h" +#include "esp_check.h" #include "driver/gpio.h" #include "driver/periph_ctrl.h" #include "driver/rmt.h" @@ -42,12 +43,7 @@ #define RMT_TRANSLATOR_UNINIT_STR "RMT translator not init" #define RMT_PARAM_ERR_STR "RMT param error" -static const char *RMT_TAG = "rmt"; -#define RMT_CHECK(a, str, ret_val, ...) \ - if (unlikely(!(a))) { \ - ESP_LOGE(RMT_TAG, "%s(%d): "str, __FUNCTION__, __LINE__, ##__VA_ARGS__); \ - return (ret_val); \ - } +static const char *TAG = "rmt"; // Spinlock for protecting concurrent register-level access only #define RMT_ENTER_CRITICAL() portENTER_CRITICAL_SAFE(&(rmt_contex.rmt_spinlock)) @@ -145,7 +141,7 @@ static void rmt_module_disable(void) esp_err_t rmt_set_clk_div(rmt_channel_t channel, uint8_t div_cnt) { - RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG); + ESP_RETURN_ON_FALSE(channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR); RMT_ENTER_CRITICAL(); if (RMT_IS_RX_CHANNEL(channel)) { rmt_ll_rx_set_channel_clock_div(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel), div_cnt); @@ -158,8 +154,8 @@ esp_err_t rmt_set_clk_div(rmt_channel_t channel, uint8_t div_cnt) esp_err_t rmt_get_clk_div(rmt_channel_t channel, uint8_t *div_cnt) { - RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG); - RMT_CHECK(div_cnt != NULL, RMT_ADDR_ERROR_STR, ESP_ERR_INVALID_ARG); + ESP_RETURN_ON_FALSE(channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR); + ESP_RETURN_ON_FALSE(div_cnt, ESP_ERR_INVALID_ARG, TAG, RMT_ADDR_ERROR_STR); RMT_ENTER_CRITICAL(); if (RMT_IS_RX_CHANNEL(channel)) { *div_cnt = (uint8_t)rmt_ll_rx_get_channel_clock_div(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel)); @@ -172,7 +168,7 @@ esp_err_t rmt_get_clk_div(rmt_channel_t channel, uint8_t *div_cnt) esp_err_t rmt_set_rx_idle_thresh(rmt_channel_t channel, uint16_t thresh) { - RMT_CHECK(RMT_IS_RX_CHANNEL(channel) && channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG); + ESP_RETURN_ON_FALSE(RMT_IS_RX_CHANNEL(channel) && channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR); RMT_ENTER_CRITICAL(); rmt_ll_rx_set_idle_thres(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel), thresh); RMT_EXIT_CRITICAL(); @@ -181,8 +177,8 @@ esp_err_t rmt_set_rx_idle_thresh(rmt_channel_t channel, uint16_t thresh) esp_err_t rmt_get_rx_idle_thresh(rmt_channel_t channel, uint16_t *thresh) { - RMT_CHECK(RMT_IS_RX_CHANNEL(channel) && channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG); - RMT_CHECK(thresh != NULL, RMT_ADDR_ERROR_STR, ESP_ERR_INVALID_ARG); + ESP_RETURN_ON_FALSE(RMT_IS_RX_CHANNEL(channel) && channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR); + ESP_RETURN_ON_FALSE(thresh, ESP_ERR_INVALID_ARG, TAG, RMT_ADDR_ERROR_STR); RMT_ENTER_CRITICAL(); *thresh = (uint16_t)rmt_ll_rx_get_idle_thres(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel)); RMT_EXIT_CRITICAL(); @@ -191,8 +187,8 @@ esp_err_t rmt_get_rx_idle_thresh(rmt_channel_t channel, uint16_t *thresh) esp_err_t rmt_set_mem_block_num(rmt_channel_t channel, uint8_t rmt_mem_num) { - RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG); - RMT_CHECK(rmt_mem_num <= RMT_CHANNEL_MAX - channel, RMT_MEM_CNT_ERROR_STR, ESP_ERR_INVALID_ARG); + ESP_RETURN_ON_FALSE(channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR); + ESP_RETURN_ON_FALSE(rmt_mem_num <= RMT_CHANNEL_MAX - channel, ESP_ERR_INVALID_ARG, TAG, RMT_MEM_CNT_ERROR_STR); RMT_ENTER_CRITICAL(); if (RMT_IS_RX_CHANNEL(channel)) { rmt_ll_rx_set_mem_blocks(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel), rmt_mem_num); @@ -205,8 +201,8 @@ esp_err_t rmt_set_mem_block_num(rmt_channel_t channel, uint8_t rmt_mem_num) esp_err_t rmt_get_mem_block_num(rmt_channel_t channel, uint8_t *rmt_mem_num) { - RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG); - RMT_CHECK(rmt_mem_num != NULL, RMT_ADDR_ERROR_STR, ESP_ERR_INVALID_ARG); + ESP_RETURN_ON_FALSE(channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR); + ESP_RETURN_ON_FALSE(rmt_mem_num, ESP_ERR_INVALID_ARG, TAG, RMT_ADDR_ERROR_STR); RMT_ENTER_CRITICAL(); if (RMT_IS_RX_CHANNEL(channel)) { *rmt_mem_num = (uint8_t)rmt_ll_rx_get_mem_blocks(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel)); @@ -220,8 +216,8 @@ esp_err_t rmt_get_mem_block_num(rmt_channel_t channel, uint8_t *rmt_mem_num) esp_err_t rmt_set_tx_carrier(rmt_channel_t channel, bool carrier_en, uint16_t high_level, uint16_t low_level, rmt_carrier_level_t carrier_level) { - RMT_CHECK(RMT_IS_TX_CHANNEL(channel), RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG); - RMT_CHECK(carrier_level < RMT_CARRIER_LEVEL_MAX, RMT_CARRIER_ERROR_STR, ESP_ERR_INVALID_ARG); + ESP_RETURN_ON_FALSE(RMT_IS_TX_CHANNEL(channel), ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR); + ESP_RETURN_ON_FALSE(carrier_level < RMT_CARRIER_LEVEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CARRIER_ERROR_STR); RMT_ENTER_CRITICAL(); rmt_ll_tx_set_carrier_high_low_ticks(rmt_contex.hal.regs, channel, high_level, low_level); rmt_ll_tx_set_carrier_level(rmt_contex.hal.regs, channel, carrier_level); @@ -232,7 +228,7 @@ esp_err_t rmt_set_tx_carrier(rmt_channel_t channel, bool carrier_en, uint16_t hi esp_err_t rmt_set_mem_pd(rmt_channel_t channel, bool pd_en) { - RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG); + ESP_RETURN_ON_FALSE(channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR); RMT_ENTER_CRITICAL(); rmt_ll_power_down_mem(rmt_contex.hal.regs, pd_en); RMT_EXIT_CRITICAL(); @@ -241,7 +237,7 @@ esp_err_t rmt_set_mem_pd(rmt_channel_t channel, bool pd_en) esp_err_t rmt_get_mem_pd(rmt_channel_t channel, bool *pd_en) { - RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG); + ESP_RETURN_ON_FALSE(channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR); RMT_ENTER_CRITICAL(); *pd_en = rmt_ll_is_mem_power_down(rmt_contex.hal.regs); RMT_EXIT_CRITICAL(); @@ -250,7 +246,7 @@ esp_err_t rmt_get_mem_pd(rmt_channel_t channel, bool *pd_en) esp_err_t rmt_tx_start(rmt_channel_t channel, bool tx_idx_rst) { - RMT_CHECK(RMT_IS_TX_CHANNEL(channel), RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG); + ESP_RETURN_ON_FALSE(RMT_IS_TX_CHANNEL(channel), ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR); RMT_ENTER_CRITICAL(); if (tx_idx_rst) { rmt_ll_tx_reset_pointer(rmt_contex.hal.regs, channel); @@ -274,7 +270,7 @@ esp_err_t rmt_tx_start(rmt_channel_t channel, bool tx_idx_rst) esp_err_t rmt_tx_stop(rmt_channel_t channel) { - RMT_CHECK(RMT_IS_TX_CHANNEL(channel), RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG); + ESP_RETURN_ON_FALSE(RMT_IS_TX_CHANNEL(channel), ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR); RMT_ENTER_CRITICAL(); rmt_ll_tx_stop(rmt_contex.hal.regs, channel); rmt_ll_tx_reset_pointer(rmt_contex.hal.regs, channel); @@ -284,7 +280,7 @@ esp_err_t rmt_tx_stop(rmt_channel_t channel) esp_err_t rmt_rx_start(rmt_channel_t channel, bool rx_idx_rst) { - RMT_CHECK(RMT_IS_RX_CHANNEL(channel) && channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG); + ESP_RETURN_ON_FALSE(RMT_IS_RX_CHANNEL(channel) && channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR); RMT_ENTER_CRITICAL(); rmt_ll_rx_enable(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel), false); if (rx_idx_rst) { @@ -307,7 +303,7 @@ esp_err_t rmt_rx_start(rmt_channel_t channel, bool rx_idx_rst) esp_err_t rmt_rx_stop(rmt_channel_t channel) { - RMT_CHECK(RMT_IS_RX_CHANNEL(channel) && channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG); + ESP_RETURN_ON_FALSE(RMT_IS_RX_CHANNEL(channel) && channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR); RMT_ENTER_CRITICAL(); rmt_ll_enable_rx_end_interrupt(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel), false); rmt_ll_rx_enable(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel), false); @@ -321,7 +317,7 @@ esp_err_t rmt_rx_stop(rmt_channel_t channel) esp_err_t rmt_tx_memory_reset(rmt_channel_t channel) { - RMT_CHECK(RMT_IS_TX_CHANNEL(channel), RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG); + ESP_RETURN_ON_FALSE(RMT_IS_TX_CHANNEL(channel), ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR); RMT_ENTER_CRITICAL(); rmt_ll_tx_reset_pointer(rmt_contex.hal.regs, channel); RMT_EXIT_CRITICAL(); @@ -330,7 +326,7 @@ esp_err_t rmt_tx_memory_reset(rmt_channel_t channel) esp_err_t rmt_rx_memory_reset(rmt_channel_t channel) { - RMT_CHECK(RMT_IS_RX_CHANNEL(channel) && channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG); + ESP_RETURN_ON_FALSE(RMT_IS_RX_CHANNEL(channel) && channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR); RMT_ENTER_CRITICAL(); rmt_ll_rx_reset_pointer(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel)); RMT_EXIT_CRITICAL(); @@ -339,8 +335,8 @@ esp_err_t rmt_rx_memory_reset(rmt_channel_t channel) esp_err_t rmt_set_memory_owner(rmt_channel_t channel, rmt_mem_owner_t owner) { - RMT_CHECK(RMT_IS_RX_CHANNEL(channel) && channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG); - RMT_CHECK(owner < RMT_MEM_OWNER_MAX, RMT_MEM_OWNER_ERROR_STR, ESP_ERR_INVALID_ARG); + ESP_RETURN_ON_FALSE(RMT_IS_RX_CHANNEL(channel) && channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR); + ESP_RETURN_ON_FALSE(owner < RMT_MEM_OWNER_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_MEM_OWNER_ERROR_STR); RMT_ENTER_CRITICAL(); rmt_ll_rx_set_mem_owner(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel), owner); RMT_EXIT_CRITICAL(); @@ -349,8 +345,8 @@ esp_err_t rmt_set_memory_owner(rmt_channel_t channel, rmt_mem_owner_t owner) esp_err_t rmt_get_memory_owner(rmt_channel_t channel, rmt_mem_owner_t *owner) { - RMT_CHECK(RMT_IS_RX_CHANNEL(channel) && channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG); - RMT_CHECK(owner != NULL, RMT_MEM_OWNER_ERROR_STR, ESP_ERR_INVALID_ARG); + ESP_RETURN_ON_FALSE(RMT_IS_RX_CHANNEL(channel) && channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR); + ESP_RETURN_ON_FALSE(owner, ESP_ERR_INVALID_ARG, TAG, RMT_MEM_OWNER_ERROR_STR); RMT_ENTER_CRITICAL(); *owner = (rmt_mem_owner_t)rmt_ll_rx_get_mem_owner(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel)); RMT_EXIT_CRITICAL(); @@ -359,7 +355,7 @@ esp_err_t rmt_get_memory_owner(rmt_channel_t channel, rmt_mem_owner_t *owner) esp_err_t rmt_set_tx_loop_mode(rmt_channel_t channel, bool loop_en) { - RMT_CHECK(RMT_IS_TX_CHANNEL(channel), RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG); + ESP_RETURN_ON_FALSE(RMT_IS_TX_CHANNEL(channel), ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR); RMT_ENTER_CRITICAL(); rmt_ll_tx_enable_loop(rmt_contex.hal.regs, channel, loop_en); RMT_EXIT_CRITICAL(); @@ -368,7 +364,7 @@ esp_err_t rmt_set_tx_loop_mode(rmt_channel_t channel, bool loop_en) esp_err_t rmt_get_tx_loop_mode(rmt_channel_t channel, bool *loop_en) { - RMT_CHECK(RMT_IS_TX_CHANNEL(channel), RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG); + ESP_RETURN_ON_FALSE(RMT_IS_TX_CHANNEL(channel), ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR); RMT_ENTER_CRITICAL(); *loop_en = rmt_ll_is_tx_loop_enabled(rmt_contex.hal.regs, channel); RMT_EXIT_CRITICAL(); @@ -377,7 +373,7 @@ esp_err_t rmt_get_tx_loop_mode(rmt_channel_t channel, bool *loop_en) esp_err_t rmt_set_rx_filter(rmt_channel_t channel, bool rx_filter_en, uint8_t thresh) { - RMT_CHECK(RMT_IS_RX_CHANNEL(channel) && channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG); + ESP_RETURN_ON_FALSE(RMT_IS_RX_CHANNEL(channel) && channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR); RMT_ENTER_CRITICAL(); rmt_ll_rx_enable_filter(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel), rx_filter_en); rmt_ll_rx_set_filter_thres(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel), thresh); @@ -387,8 +383,8 @@ esp_err_t rmt_set_rx_filter(rmt_channel_t channel, bool rx_filter_en, uint8_t th esp_err_t rmt_set_source_clk(rmt_channel_t channel, rmt_source_clk_t base_clk) { - RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG); - RMT_CHECK(base_clk < RMT_BASECLK_MAX, RMT_BASECLK_ERROR_STR, ESP_ERR_INVALID_ARG); + ESP_RETURN_ON_FALSE(channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR); + ESP_RETURN_ON_FALSE(base_clk < RMT_BASECLK_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_BASECLK_ERROR_STR); RMT_ENTER_CRITICAL(); rmt_ll_set_group_clock_src(rmt_contex.hal.regs, channel, base_clk, 0, 0, 0); RMT_EXIT_CRITICAL(); @@ -397,7 +393,7 @@ esp_err_t rmt_set_source_clk(rmt_channel_t channel, rmt_source_clk_t base_clk) esp_err_t rmt_get_source_clk(rmt_channel_t channel, rmt_source_clk_t *src_clk) { - RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG); + ESP_RETURN_ON_FALSE(channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR); RMT_ENTER_CRITICAL(); *src_clk = (rmt_source_clk_t)rmt_ll_get_group_clock_src(rmt_contex.hal.regs, channel); RMT_EXIT_CRITICAL(); @@ -406,8 +402,8 @@ esp_err_t rmt_get_source_clk(rmt_channel_t channel, rmt_source_clk_t *src_clk) esp_err_t rmt_set_idle_level(rmt_channel_t channel, bool idle_out_en, rmt_idle_level_t level) { - RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG); - RMT_CHECK(level < RMT_IDLE_LEVEL_MAX, "RMT IDLE LEVEL ERR", ESP_ERR_INVALID_ARG); + ESP_RETURN_ON_FALSE(channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR); + ESP_RETURN_ON_FALSE(level < RMT_IDLE_LEVEL_MAX, ESP_ERR_INVALID_ARG, TAG, "RMT IDLE LEVEL ERR"); RMT_ENTER_CRITICAL(); rmt_ll_tx_enable_idle(rmt_contex.hal.regs, channel, idle_out_en); rmt_ll_tx_set_idle_level(rmt_contex.hal.regs, channel, level); @@ -417,7 +413,7 @@ esp_err_t rmt_set_idle_level(rmt_channel_t channel, bool idle_out_en, rmt_idle_l esp_err_t rmt_get_idle_level(rmt_channel_t channel, bool *idle_out_en, rmt_idle_level_t *level) { - RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG); + ESP_RETURN_ON_FALSE(channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR); RMT_ENTER_CRITICAL(); *idle_out_en = rmt_ll_is_tx_idle_enabled(rmt_contex.hal.regs, channel); *level = rmt_ll_tx_get_idle_level(rmt_contex.hal.regs, channel); @@ -427,7 +423,7 @@ esp_err_t rmt_get_idle_level(rmt_channel_t channel, bool *idle_out_en, rmt_idle_ esp_err_t rmt_get_status(rmt_channel_t channel, uint32_t *status) { - RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG); + ESP_RETURN_ON_FALSE(channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR); RMT_ENTER_CRITICAL(); if (RMT_IS_RX_CHANNEL(channel)) { *status = rmt_ll_rx_get_channel_status(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel)); @@ -454,7 +450,7 @@ void rmt_clr_intr_enable_mask(uint32_t mask) esp_err_t rmt_set_rx_intr_en(rmt_channel_t channel, bool en) { - RMT_CHECK(RMT_IS_RX_CHANNEL(channel) && channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG); + ESP_RETURN_ON_FALSE(RMT_IS_RX_CHANNEL(channel) && channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR); RMT_ENTER_CRITICAL(); rmt_ll_enable_rx_end_interrupt(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel), en); RMT_EXIT_CRITICAL(); @@ -464,10 +460,10 @@ esp_err_t rmt_set_rx_intr_en(rmt_channel_t channel, bool en) #if SOC_RMT_SUPPORT_RX_PINGPONG esp_err_t rmt_set_rx_thr_intr_en(rmt_channel_t channel, bool en, uint16_t evt_thresh) { - RMT_CHECK(RMT_IS_RX_CHANNEL(channel) && channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG); + ESP_RETURN_ON_FALSE(RMT_IS_RX_CHANNEL(channel) && channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR); if (en) { uint32_t item_block_len = rmt_ll_rx_get_mem_blocks(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel)) * RMT_MEM_ITEM_NUM; - RMT_CHECK(evt_thresh <= item_block_len, "RMT EVT THRESH ERR", ESP_ERR_INVALID_ARG); + ESP_RETURN_ON_FALSE(evt_thresh <= item_block_len, ESP_ERR_INVALID_ARG, TAG, "RMT EVT THRESH ERR"); RMT_ENTER_CRITICAL(); rmt_ll_rx_set_limit(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel), evt_thresh); rmt_ll_enable_rx_thres_interrupt(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel), true); @@ -483,7 +479,7 @@ esp_err_t rmt_set_rx_thr_intr_en(rmt_channel_t channel, bool en, uint16_t evt_th esp_err_t rmt_set_err_intr_en(rmt_channel_t channel, bool en) { - RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG); + ESP_RETURN_ON_FALSE(channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR); RMT_ENTER_CRITICAL(); if (RMT_IS_RX_CHANNEL(channel)) { rmt_ll_enable_rx_err_interrupt(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel), en); @@ -496,7 +492,7 @@ esp_err_t rmt_set_err_intr_en(rmt_channel_t channel, bool en) esp_err_t rmt_set_tx_intr_en(rmt_channel_t channel, bool en) { - RMT_CHECK(RMT_IS_TX_CHANNEL(channel), RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG); + ESP_RETURN_ON_FALSE(RMT_IS_TX_CHANNEL(channel), ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR); RMT_ENTER_CRITICAL(); rmt_ll_enable_tx_end_interrupt(rmt_contex.hal.regs, channel, en); RMT_EXIT_CRITICAL(); @@ -505,10 +501,10 @@ esp_err_t rmt_set_tx_intr_en(rmt_channel_t channel, bool en) esp_err_t rmt_set_tx_thr_intr_en(rmt_channel_t channel, bool en, uint16_t evt_thresh) { - RMT_CHECK(RMT_IS_TX_CHANNEL(channel), RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG); + ESP_RETURN_ON_FALSE(RMT_IS_TX_CHANNEL(channel), ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR); if (en) { uint32_t item_block_len = rmt_ll_tx_get_mem_blocks(rmt_contex.hal.regs, channel) * RMT_MEM_ITEM_NUM; - RMT_CHECK(evt_thresh <= item_block_len, "RMT EVT THRESH ERR", ESP_ERR_INVALID_ARG); + ESP_RETURN_ON_FALSE(evt_thresh <= item_block_len, ESP_ERR_INVALID_ARG, TAG, "RMT EVT THRESH ERR"); RMT_ENTER_CRITICAL(); rmt_ll_tx_set_limit(rmt_contex.hal.regs, channel, evt_thresh); rmt_ll_enable_tx_thres_interrupt(rmt_contex.hal.regs, channel, true); @@ -523,19 +519,18 @@ esp_err_t rmt_set_tx_thr_intr_en(rmt_channel_t channel, bool en, uint16_t evt_th esp_err_t rmt_set_gpio(rmt_channel_t channel, rmt_mode_t mode, gpio_num_t gpio_num, bool invert_signal) { - RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG); - RMT_CHECK(mode < RMT_MODE_MAX, RMT_MODE_ERROR_STR, ESP_ERR_INVALID_ARG); - RMT_CHECK(((GPIO_IS_VALID_GPIO(gpio_num) && (mode == RMT_MODE_RX)) || - (GPIO_IS_VALID_OUTPUT_GPIO(gpio_num) && (mode == RMT_MODE_TX))), - RMT_GPIO_ERROR_STR, ESP_ERR_INVALID_ARG); + ESP_RETURN_ON_FALSE(channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR); + ESP_RETURN_ON_FALSE(mode < RMT_MODE_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_MODE_ERROR_STR); + ESP_RETURN_ON_FALSE(((GPIO_IS_VALID_GPIO(gpio_num) && (mode == RMT_MODE_RX)) || + (GPIO_IS_VALID_OUTPUT_GPIO(gpio_num) && (mode == RMT_MODE_TX))), ESP_ERR_INVALID_ARG, TAG, RMT_GPIO_ERROR_STR); gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[gpio_num], PIN_FUNC_GPIO); if (mode == RMT_MODE_TX) { - RMT_CHECK(RMT_IS_TX_CHANNEL(channel), RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG); + ESP_RETURN_ON_FALSE(RMT_IS_TX_CHANNEL(channel), ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR); gpio_set_direction(gpio_num, GPIO_MODE_OUTPUT); esp_rom_gpio_connect_out_signal(gpio_num, rmt_periph_signals.groups[0].channels[channel].tx_sig, invert_signal, 0); } else { - RMT_CHECK(RMT_IS_RX_CHANNEL(channel), RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG); + ESP_RETURN_ON_FALSE(RMT_IS_RX_CHANNEL(channel), ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR); gpio_set_direction(gpio_num, GPIO_MODE_INPUT); esp_rom_gpio_connect_in_signal(gpio_num, rmt_periph_signals.groups[0].channels[channel].rx_sig, invert_signal); } @@ -569,12 +564,12 @@ static esp_err_t rmt_internal_config(rmt_dev_t *dev, const rmt_config_t *rmt_par bool carrier_en = rmt_param->tx_config.carrier_en; uint32_t rmt_source_clk_hz; - RMT_CHECK(rmt_is_channel_number_valid(channel, mode), RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG); - RMT_CHECK((mem_cnt + channel <= 8 && mem_cnt > 0), RMT_MEM_CNT_ERROR_STR, ESP_ERR_INVALID_ARG); - RMT_CHECK((clk_div > 0), RMT_CLK_DIV_ERROR_STR, ESP_ERR_INVALID_ARG); + ESP_RETURN_ON_FALSE(rmt_is_channel_number_valid(channel, mode), ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR); + ESP_RETURN_ON_FALSE(mem_cnt + channel <= 8 && mem_cnt > 0, ESP_ERR_INVALID_ARG, TAG, RMT_MEM_CNT_ERROR_STR); + ESP_RETURN_ON_FALSE(clk_div > 0, ESP_ERR_INVALID_ARG, TAG, RMT_CLK_DIV_ERROR_STR); if (mode == RMT_MODE_TX) { - RMT_CHECK((!carrier_en || carrier_freq_hz > 0), "RMT carrier frequency can't be zero", ESP_ERR_INVALID_ARG); + ESP_RETURN_ON_FALSE(!carrier_en || carrier_freq_hz > 0, ESP_ERR_INVALID_ARG, TAG, "RMT carrier frequency can't be zero"); } RMT_ENTER_CRITICAL(); @@ -601,11 +596,11 @@ static esp_err_t rmt_internal_config(rmt_dev_t *dev, const rmt_config_t *rmt_par s_rmt_source_clock_hz[channel] = rmt_source_clk_hz; #else if (s_rmt_source_clock_hz && rmt_source_clk_hz != s_rmt_source_clock_hz) { - ESP_LOGW(RMT_TAG, "RMT clock source has been configured to %d by other channel, now reconfigure it to %d", s_rmt_source_clock_hz, rmt_source_clk_hz); + ESP_LOGW(TAG, "RMT clock source has been configured to %d by other channel, now reconfigure it to %d", s_rmt_source_clock_hz, rmt_source_clk_hz); } s_rmt_source_clock_hz = rmt_source_clk_hz; #endif - ESP_LOGD(RMT_TAG, "rmt_source_clk_hz: %d\n", rmt_source_clk_hz); + ESP_LOGD(TAG, "rmt_source_clk_hz: %d\n", rmt_source_clk_hz); if (mode == RMT_MODE_TX) { uint16_t carrier_duty_percent = rmt_param->tx_config.carrier_duty_percent; @@ -642,7 +637,7 @@ static esp_err_t rmt_internal_config(rmt_dev_t *dev, const rmt_config_t *rmt_par } RMT_EXIT_CRITICAL(); - ESP_LOGD(RMT_TAG, "Rmt Tx Channel %u|Gpio %u|Sclk_Hz %u|Div %u|Carrier_Hz %u|Duty %u", + ESP_LOGD(TAG, "Rmt Tx Channel %u|Gpio %u|Sclk_Hz %u|Div %u|Carrier_Hz %u|Duty %u", channel, gpio_num, rmt_source_clk_hz, clk_div, carrier_freq_hz, carrier_duty_percent); } else if (RMT_MODE_RX == mode) { uint8_t filter_cnt = rmt_param->rx_config.filter_ticks_thresh; @@ -676,7 +671,7 @@ static esp_err_t rmt_internal_config(rmt_dev_t *dev, const rmt_config_t *rmt_par #endif RMT_EXIT_CRITICAL(); - ESP_LOGD(RMT_TAG, "Rmt Rx Channel %u|Gpio %u|Sclk_Hz %u|Div %u|Thresold %u|Filter %u", + ESP_LOGD(TAG, "Rmt Rx Channel %u|Gpio %u|Sclk_Hz %u|Div %u|Thresold %u|Filter %u", channel, gpio_num, rmt_source_clk_hz, clk_div, threshold, filter_cnt); } @@ -687,11 +682,8 @@ esp_err_t rmt_config(const rmt_config_t *rmt_param) { rmt_module_enable(); - RMT_CHECK(rmt_set_gpio(rmt_param->channel, rmt_param->rmt_mode, rmt_param->gpio_num, rmt_param->flags & RMT_CHANNEL_FLAGS_INVERT_SIG) == ESP_OK, - "set gpio for RMT driver failed", ESP_ERR_INVALID_ARG); - - RMT_CHECK(rmt_internal_config(&RMT, rmt_param) == ESP_OK, - "initialize RMT driver failed", ESP_ERR_INVALID_ARG); + ESP_RETURN_ON_ERROR(rmt_set_gpio(rmt_param->channel, rmt_param->rmt_mode, rmt_param->gpio_num, rmt_param->flags & RMT_CHANNEL_FLAGS_INVERT_SIG), TAG, "set gpio for RMT driver failed"); + ESP_RETURN_ON_ERROR(rmt_internal_config(&RMT, rmt_param), TAG, "initialize RMT driver failed"); return ESP_OK; } @@ -706,21 +698,21 @@ static void IRAM_ATTR rmt_fill_memory(rmt_channel_t channel, const rmt_item32_t esp_err_t rmt_fill_tx_items(rmt_channel_t channel, const rmt_item32_t *item, uint16_t item_num, uint16_t mem_offset) { - RMT_CHECK(RMT_IS_TX_CHANNEL(channel), RMT_CHANNEL_ERROR_STR, (0)); - RMT_CHECK((item != NULL), RMT_ADDR_ERROR_STR, ESP_ERR_INVALID_ARG); - RMT_CHECK((item_num > 0), RMT_DRIVER_LENGTH_ERROR_STR, ESP_ERR_INVALID_ARG); + ESP_RETURN_ON_FALSE(RMT_IS_TX_CHANNEL(channel), (0), TAG, RMT_CHANNEL_ERROR_STR); + ESP_RETURN_ON_FALSE(item, ESP_ERR_INVALID_ARG, TAG, RMT_ADDR_ERROR_STR); + ESP_RETURN_ON_FALSE(item_num > 0, ESP_ERR_INVALID_ARG, TAG, RMT_DRIVER_LENGTH_ERROR_STR); /*Each block has 64 x 32 bits of data*/ uint8_t mem_cnt = rmt_ll_tx_get_mem_blocks(rmt_contex.hal.regs, channel); - RMT_CHECK((mem_cnt * RMT_MEM_ITEM_NUM >= item_num), RMT_WR_MEM_OVF_ERROR_STR, ESP_ERR_INVALID_ARG); + ESP_RETURN_ON_FALSE(mem_cnt * RMT_MEM_ITEM_NUM >= item_num, ESP_ERR_INVALID_ARG, TAG, RMT_WR_MEM_OVF_ERROR_STR); rmt_fill_memory(channel, item, item_num, mem_offset); return ESP_OK; } esp_err_t rmt_isr_register(void (*fn)(void *), void *arg, int intr_alloc_flags, rmt_isr_handle_t *handle) { - RMT_CHECK((fn != NULL), RMT_ADDR_ERROR_STR, ESP_ERR_INVALID_ARG); - RMT_CHECK(rmt_contex.rmt_driver_channels == 0, "RMT driver installed, can not install generic ISR handler", ESP_FAIL); + ESP_RETURN_ON_FALSE(fn, ESP_ERR_INVALID_ARG, TAG, RMT_ADDR_ERROR_STR); + ESP_RETURN_ON_FALSE(rmt_contex.rmt_driver_channels == 0, ESP_FAIL, TAG, "RMT driver installed, can not install generic ISR handler"); return esp_intr_alloc(rmt_periph_signals.groups[0].irq, intr_alloc_flags, fn, arg, handle); } @@ -769,7 +761,7 @@ static void IRAM_ATTR rmt_driver_isr_default(void *arg) p_rmt->tx_sub_len = 0; p_rmt->sample_cur = NULL; p_rmt->translator = false; - if (rmt_contex.rmt_tx_end_callback.function != NULL) { + if (rmt_contex.rmt_tx_end_callback.function) { rmt_contex.rmt_tx_end_callback.function(channel, rmt_contex.rmt_tx_end_callback.arg); } } @@ -848,10 +840,10 @@ static void IRAM_ATTR rmt_driver_isr_default(void *arg) BaseType_t res = xRingbufferSendFromISR(p_rmt->rx_buf, (void *)addr, item_len * 4, &HPTaskAwoken); #endif if (res == pdFALSE) { - ESP_EARLY_LOGE(RMT_TAG, "RMT RX BUFFER FULL"); + ESP_EARLY_LOGE(TAG, "RMT RX BUFFER FULL"); } } else { - ESP_EARLY_LOGE(RMT_TAG, "RMT RX BUFFER ERROR"); + ESP_EARLY_LOGE(TAG, "RMT RX BUFFER ERROR"); } #if SOC_RMT_SUPPORT_RX_PINGPONG @@ -886,7 +878,7 @@ static void IRAM_ATTR rmt_driver_isr_default(void *arg) p_rmt->rx_item_start_idx = 0; } } else { - ESP_EARLY_LOGE(RMT_TAG, "---RX buffer too small: %d", sizeof(p_rmt->rx_item_buf)); + ESP_EARLY_LOGE(TAG, "---RX buffer too small: %d", sizeof(p_rmt->rx_item_buf)); } rmt_ll_clear_rx_thres_interrupt(hal->regs, channel); } @@ -901,7 +893,7 @@ static void IRAM_ATTR rmt_driver_isr_default(void *arg) rmt_obj_t *p_rmt = p_rmt_obj[channel]; if (p_rmt) { xSemaphoreGiveFromISR(p_rmt->tx_sem, &HPTaskAwoken); - if (rmt_contex.rmt_tx_end_callback.function != NULL) { + if (rmt_contex.rmt_tx_end_callback.function) { rmt_contex.rmt_tx_end_callback.function(channel, rmt_contex.rmt_tx_end_callback.arg); } } @@ -918,8 +910,8 @@ static void IRAM_ATTR rmt_driver_isr_default(void *arg) if (p_rmt) { // Reset the receiver's write/read addresses to prevent endless err interrupts. rmt_ll_rx_reset_pointer(rmt_contex.hal.regs, channel); - ESP_EARLY_LOGD(RMT_TAG, "RMT RX channel %d error", channel); - ESP_EARLY_LOGD(RMT_TAG, "status: 0x%08x", rmt_ll_rx_get_channel_status(rmt_contex.hal.regs, channel)); + ESP_EARLY_LOGD(TAG, "RMT RX channel %d error", channel); + ESP_EARLY_LOGD(TAG, "status: 0x%08x", rmt_ll_rx_get_channel_status(rmt_contex.hal.regs, channel)); } rmt_ll_clear_rx_err_interrupt(hal->regs, channel); } @@ -933,8 +925,8 @@ static void IRAM_ATTR rmt_driver_isr_default(void *arg) if (p_rmt) { // Reset the transmitter's write/read addresses to prevent endless err interrupts. rmt_ll_tx_reset_pointer(rmt_contex.hal.regs, channel); - ESP_EARLY_LOGD(RMT_TAG, "RMT TX channel %d error", channel); - ESP_EARLY_LOGD(RMT_TAG, "status: 0x%08x", rmt_ll_tx_get_channel_status(rmt_contex.hal.regs, channel)); + ESP_EARLY_LOGD(TAG, "RMT TX channel %d error", channel); + ESP_EARLY_LOGD(TAG, "status: 0x%08x", rmt_ll_tx_get_channel_status(rmt_contex.hal.regs, channel)); } rmt_ll_clear_tx_err_interrupt(hal->regs, channel); } @@ -947,8 +939,8 @@ static void IRAM_ATTR rmt_driver_isr_default(void *arg) esp_err_t rmt_driver_uninstall(rmt_channel_t channel) { esp_err_t err = ESP_OK; - RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG); - RMT_CHECK((rmt_contex.rmt_driver_channels & BIT(channel)) != 0, "No RMT driver for this channel", ESP_ERR_INVALID_STATE); + ESP_RETURN_ON_FALSE(channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR); + ESP_RETURN_ON_FALSE(rmt_contex.rmt_driver_channels & BIT(channel), ESP_ERR_INVALID_STATE, TAG, "No RMT driver for this channel"); if (p_rmt_obj[channel] == NULL) { return ESP_OK; } @@ -1016,14 +1008,13 @@ esp_err_t rmt_driver_uninstall(rmt_channel_t channel) esp_err_t rmt_driver_install(rmt_channel_t channel, size_t rx_buf_size, int intr_alloc_flags) { - RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG); - RMT_CHECK((rmt_contex.rmt_driver_channels & BIT(channel)) == 0, - "RMT driver already installed for channel", ESP_ERR_INVALID_STATE); + ESP_RETURN_ON_FALSE(channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR); + ESP_RETURN_ON_FALSE((rmt_contex.rmt_driver_channels & BIT(channel)) == 0, ESP_ERR_INVALID_STATE, TAG, "RMT driver already installed for channel"); esp_err_t err = ESP_OK; - if (p_rmt_obj[channel] != NULL) { - ESP_LOGD(RMT_TAG, "RMT driver already installed"); + if (p_rmt_obj[channel]) { + ESP_LOGD(TAG, "RMT driver already installed"); return ESP_ERR_INVALID_STATE; } @@ -1038,7 +1029,7 @@ esp_err_t rmt_driver_install(rmt_channel_t channel, size_t rx_buf_size, int intr #endif if (p_rmt_obj[channel] == NULL) { - ESP_LOGE(RMT_TAG, "RMT driver malloc error"); + ESP_LOGE(TAG, "RMT driver malloc error"); return ESP_ERR_NO_MEM; } @@ -1079,7 +1070,7 @@ esp_err_t rmt_driver_install(rmt_channel_t channel, size_t rx_buf_size, int intr } #endif if (p_rmt_obj[channel]->rx_item_buf == NULL) { - ESP_LOGE(RMT_TAG, "RMT malloc fail"); + ESP_LOGE(TAG, "RMT malloc fail"); return ESP_FAIL; } p_rmt_obj[channel]->rx_item_buf_size = rx_buf_size; @@ -1110,14 +1101,14 @@ esp_err_t rmt_driver_install(rmt_channel_t channel, size_t rx_buf_size, int intr esp_err_t rmt_write_items(rmt_channel_t channel, const rmt_item32_t *rmt_item, int item_num, bool wait_tx_done) { - RMT_CHECK(RMT_IS_TX_CHANNEL(channel), RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG); - RMT_CHECK(p_rmt_obj[channel] != NULL, RMT_DRIVER_ERROR_STR, ESP_FAIL); - RMT_CHECK(rmt_item != NULL, RMT_ADDR_ERROR_STR, ESP_FAIL); - RMT_CHECK(item_num > 0, RMT_DRIVER_LENGTH_ERROR_STR, ESP_ERR_INVALID_ARG); + ESP_RETURN_ON_FALSE(RMT_IS_TX_CHANNEL(channel), ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR); + ESP_RETURN_ON_FALSE(p_rmt_obj[channel], ESP_FAIL, TAG, RMT_DRIVER_ERROR_STR); + ESP_RETURN_ON_FALSE(rmt_item, ESP_FAIL, TAG, RMT_ADDR_ERROR_STR); + ESP_RETURN_ON_FALSE(item_num > 0, ESP_ERR_INVALID_ARG, TAG, RMT_DRIVER_LENGTH_ERROR_STR); #if CONFIG_SPIRAM_USE_MALLOC if (p_rmt_obj[channel]->intr_alloc_flags & ESP_INTR_FLAG_IRAM) { if (!esp_ptr_internal(rmt_item)) { - ESP_LOGE(RMT_TAG, RMT_PSRAM_BUFFER_WARN_STR); + ESP_LOGE(TAG, RMT_PSRAM_BUFFER_WARN_STR); return ESP_ERR_INVALID_ARG; } } @@ -1164,8 +1155,8 @@ esp_err_t rmt_write_items(rmt_channel_t channel, const rmt_item32_t *rmt_item, i esp_err_t rmt_wait_tx_done(rmt_channel_t channel, TickType_t wait_time) { - RMT_CHECK(RMT_IS_TX_CHANNEL(channel), RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG); - RMT_CHECK(p_rmt_obj[channel] != NULL, RMT_DRIVER_ERROR_STR, ESP_FAIL); + ESP_RETURN_ON_FALSE(RMT_IS_TX_CHANNEL(channel), ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR); + ESP_RETURN_ON_FALSE(p_rmt_obj[channel], ESP_FAIL, TAG, RMT_DRIVER_ERROR_STR); if (xSemaphoreTake(p_rmt_obj[channel]->tx_sem, wait_time) == pdTRUE) { p_rmt_obj[channel]->wait_done = false; xSemaphoreGive(p_rmt_obj[channel]->tx_sem); @@ -1173,7 +1164,7 @@ esp_err_t rmt_wait_tx_done(rmt_channel_t channel, TickType_t wait_time) } else { if (wait_time != 0) { // Don't emit error message if just polling. - ESP_LOGE(RMT_TAG, "Timeout on wait_tx_done"); + ESP_LOGE(TAG, "Timeout on wait_tx_done"); } return ESP_ERR_TIMEOUT; } @@ -1181,9 +1172,9 @@ esp_err_t rmt_wait_tx_done(rmt_channel_t channel, TickType_t wait_time) esp_err_t rmt_get_ringbuf_handle(rmt_channel_t channel, RingbufHandle_t *buf_handle) { - RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG); - RMT_CHECK(p_rmt_obj[channel] != NULL, RMT_DRIVER_ERROR_STR, ESP_FAIL); - RMT_CHECK(buf_handle != NULL, RMT_ADDR_ERROR_STR, ESP_ERR_INVALID_ARG); + ESP_RETURN_ON_FALSE(channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR); + ESP_RETURN_ON_FALSE(p_rmt_obj[channel], ESP_FAIL, TAG, RMT_DRIVER_ERROR_STR); + ESP_RETURN_ON_FALSE(buf_handle, ESP_ERR_INVALID_ARG, TAG, RMT_ADDR_ERROR_STR); *buf_handle = p_rmt_obj[channel]->rx_buf; return ESP_OK; } @@ -1198,9 +1189,9 @@ rmt_tx_end_callback_t rmt_register_tx_end_callback(rmt_tx_end_fn_t function, voi esp_err_t rmt_translator_init(rmt_channel_t channel, sample_to_rmt_t fn) { - RMT_CHECK(fn != NULL, RMT_TRANSLATOR_NULL_STR, ESP_ERR_INVALID_ARG); - RMT_CHECK(RMT_IS_TX_CHANNEL(channel), RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG); - RMT_CHECK(p_rmt_obj[channel] != NULL, RMT_DRIVER_ERROR_STR, ESP_FAIL); + ESP_RETURN_ON_FALSE(fn, ESP_ERR_INVALID_ARG, TAG, RMT_TRANSLATOR_NULL_STR); + ESP_RETURN_ON_FALSE(RMT_IS_TX_CHANNEL(channel), ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR); + ESP_RETURN_ON_FALSE(p_rmt_obj[channel], ESP_FAIL, TAG, RMT_DRIVER_ERROR_STR); const uint32_t block_size = rmt_ll_tx_get_mem_blocks(rmt_contex.hal.regs, channel) * RMT_MEM_ITEM_NUM * sizeof(rmt_item32_t); if (p_rmt_obj[channel]->tx_buf == NULL) { @@ -1214,7 +1205,7 @@ esp_err_t rmt_translator_init(rmt_channel_t channel, sample_to_rmt_t fn) } #endif if (p_rmt_obj[channel]->tx_buf == NULL) { - ESP_LOGE(RMT_TAG, "RMT translator buffer create fail"); + ESP_LOGE(TAG, "RMT translator buffer create fail"); return ESP_FAIL; } } @@ -1222,14 +1213,14 @@ esp_err_t rmt_translator_init(rmt_channel_t channel, sample_to_rmt_t fn) p_rmt_obj[channel]->tx_context = NULL; p_rmt_obj[channel]->sample_size_remain = 0; p_rmt_obj[channel]->sample_cur = NULL; - ESP_LOGD(RMT_TAG, "RMT translator init done"); + ESP_LOGD(TAG, "RMT translator init done"); return ESP_OK; } esp_err_t rmt_translator_set_context(rmt_channel_t channel, void *context) { - RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG); - RMT_CHECK(p_rmt_obj[channel] != NULL, RMT_DRIVER_ERROR_STR, ESP_FAIL); + ESP_RETURN_ON_FALSE(channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR); + ESP_RETURN_ON_FALSE(p_rmt_obj[channel], ESP_FAIL, TAG, RMT_DRIVER_ERROR_STR); p_rmt_obj[channel]->tx_context = context; return ESP_OK; @@ -1237,7 +1228,7 @@ esp_err_t rmt_translator_set_context(rmt_channel_t channel, void *context) esp_err_t rmt_translator_get_context(const size_t *item_num, void **context) { - RMT_CHECK(item_num && context, "invalid arguments", ESP_ERR_INVALID_ARG); + ESP_RETURN_ON_FALSE(item_num && context, ESP_ERR_INVALID_ARG, TAG, "invalid arguments"); // the address of tx_len_rem is directlly passed to the callback, // so it's possible to get the object address from that @@ -1249,13 +1240,13 @@ esp_err_t rmt_translator_get_context(const size_t *item_num, void **context) esp_err_t rmt_write_sample(rmt_channel_t channel, const uint8_t *src, size_t src_size, bool wait_tx_done) { - RMT_CHECK(RMT_IS_TX_CHANNEL(channel), RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG); - RMT_CHECK(p_rmt_obj[channel] != NULL, RMT_DRIVER_ERROR_STR, ESP_FAIL); - RMT_CHECK(p_rmt_obj[channel]->sample_to_rmt != NULL, RMT_TRANSLATOR_UNINIT_STR, ESP_FAIL); + ESP_RETURN_ON_FALSE(RMT_IS_TX_CHANNEL(channel), ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR); + ESP_RETURN_ON_FALSE(p_rmt_obj[channel], ESP_FAIL, TAG, RMT_DRIVER_ERROR_STR); + ESP_RETURN_ON_FALSE(p_rmt_obj[channel]->sample_to_rmt, ESP_FAIL, TAG, RMT_TRANSLATOR_UNINIT_STR); #if CONFIG_SPIRAM_USE_MALLOC if (p_rmt_obj[channel]->intr_alloc_flags & ESP_INTR_FLAG_IRAM) { if (!esp_ptr_internal(src)) { - ESP_LOGE(RMT_TAG, RMT_PSRAM_BUFFER_WARN_STR); + ESP_LOGE(TAG, RMT_PSRAM_BUFFER_WARN_STR); return ESP_ERR_INVALID_ARG; } } @@ -1293,11 +1284,11 @@ esp_err_t rmt_write_sample(rmt_channel_t channel, const uint8_t *src, size_t src esp_err_t rmt_get_channel_status(rmt_channel_status_result_t *channel_status) { - RMT_CHECK(channel_status != NULL, RMT_PARAM_ERR_STR, ESP_ERR_INVALID_ARG); + ESP_RETURN_ON_FALSE(channel_status, ESP_ERR_INVALID_ARG, TAG, RMT_PARAM_ERR_STR); for (int i = 0; i < RMT_CHANNEL_MAX; i++) { channel_status->status[i] = RMT_CHANNEL_UNINIT; - if (p_rmt_obj[i] != NULL) { - if (p_rmt_obj[i]->tx_sem != NULL) { + if (p_rmt_obj[i]) { + if (p_rmt_obj[i]->tx_sem) { if (xSemaphoreTake(p_rmt_obj[i]->tx_sem, (TickType_t)0) == pdTRUE) { channel_status->status[i] = RMT_CHANNEL_IDLE; xSemaphoreGive(p_rmt_obj[i]->tx_sem); @@ -1312,8 +1303,8 @@ esp_err_t rmt_get_channel_status(rmt_channel_status_result_t *channel_status) esp_err_t rmt_get_counter_clock(rmt_channel_t channel, uint32_t *clock_hz) { - RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG); - RMT_CHECK(clock_hz, "parameter clock_hz can't be null", ESP_ERR_INVALID_ARG); + ESP_RETURN_ON_FALSE(channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR); + ESP_RETURN_ON_FALSE(clock_hz, ESP_ERR_INVALID_ARG, TAG, "parameter clock_hz can't be null"); RMT_ENTER_CRITICAL(); uint32_t rmt_source_clk_hz = 0; #if SOC_RMT_CHANNEL_CLK_INDEPENDENT @@ -1333,7 +1324,7 @@ esp_err_t rmt_get_counter_clock(rmt_channel_t channel, uint32_t *clock_hz) #if SOC_RMT_SUPPORT_TX_SYNCHRO esp_err_t rmt_add_channel_to_group(rmt_channel_t channel) { - RMT_CHECK(RMT_IS_TX_CHANNEL(channel), RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG); + ESP_RETURN_ON_FALSE(RMT_IS_TX_CHANNEL(channel), ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR); RMT_ENTER_CRITICAL(); rmt_ll_tx_enable_sync(rmt_contex.hal.regs, true); rmt_contex.synchro_channel_mask |= (1 << channel); @@ -1345,7 +1336,7 @@ esp_err_t rmt_add_channel_to_group(rmt_channel_t channel) esp_err_t rmt_remove_channel_from_group(rmt_channel_t channel) { - RMT_CHECK(RMT_IS_TX_CHANNEL(channel), RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG); + ESP_RETURN_ON_FALSE(RMT_IS_TX_CHANNEL(channel), ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR); RMT_ENTER_CRITICAL(); rmt_contex.synchro_channel_mask &= ~(1 << channel); rmt_ll_tx_remove_from_sync_group(rmt_contex.hal.regs, channel); @@ -1359,7 +1350,7 @@ esp_err_t rmt_remove_channel_from_group(rmt_channel_t channel) esp_err_t rmt_memory_rw_rst(rmt_channel_t channel) { - RMT_CHECK(channel < RMT_CHANNEL_MAX, RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG); + ESP_RETURN_ON_FALSE(channel < RMT_CHANNEL_MAX, ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR); RMT_ENTER_CRITICAL(); if (RMT_IS_RX_CHANNEL(channel)) { rmt_ll_rx_reset_pointer(rmt_contex.hal.regs, RMT_DECODE_RX_CHANNEL(channel)); @@ -1373,7 +1364,7 @@ esp_err_t rmt_memory_rw_rst(rmt_channel_t channel) #if SOC_RMT_SUPPORT_TX_LOOP_COUNT esp_err_t rmt_set_tx_loop_count(rmt_channel_t channel, uint32_t count) { - RMT_CHECK(RMT_IS_TX_CHANNEL(channel), RMT_CHANNEL_ERROR_STR, ESP_ERR_INVALID_ARG); + ESP_RETURN_ON_FALSE(RMT_IS_TX_CHANNEL(channel), ESP_ERR_INVALID_ARG, TAG, RMT_CHANNEL_ERROR_STR); RMT_ENTER_CRITICAL(); rmt_ll_tx_set_loop_count(rmt_contex.hal.regs, channel, count); RMT_EXIT_CRITICAL(); From e58f53f26571a74d43a2b0d06c794aba13b658b2 Mon Sep 17 00:00:00 2001 From: morris Date: Wed, 9 Jun 2021 12:10:30 +0800 Subject: [PATCH 5/6] rmt: update doc for esp32s3 --- docs/en/api-reference/peripherals/rmt.rst | 23 ++++++++++++++++++----- 1 file changed, 18 insertions(+), 5 deletions(-) diff --git a/docs/en/api-reference/peripherals/rmt.rst b/docs/en/api-reference/peripherals/rmt.rst index 2fced3f08a..35dd8c6f13 100644 --- a/docs/en/api-reference/peripherals/rmt.rst +++ b/docs/en/api-reference/peripherals/rmt.rst @@ -103,6 +103,10 @@ There couple of typical steps to setup and operate the RMT and they are discusse The RMT has four channels numbered from zero to three. The first half (i.e. Channel 0 ~ 1) channels can only be configured for transmitting, and the other half (i.e. Channel 2 ~ 3) channels can only be configured for receiving. They are referred to using indexes defined in structure :cpp:type:`rmt_channel_t`. +.. only:: esp32s3 + + The RMT has eight channels numbered from zero to seven. The first half (i.e. Channel 0 ~ 3) channels can only be configured for transmitting, and the other half (i.e. Channel 4 ~ 7) channels can only be configured for receiving. They are referred to using indexes defined in structure :cpp:type:`rmt_channel_t`. + Configure Driver ---------------- @@ -144,7 +148,7 @@ When configuring channel in transmit mode, set **tx_config** and the following m * Level of the RMT output, when the carrier is applied - **carrier_level** * Enable the RMT output if idle - **idle_output_en** * Set the signal level on the RMT output if idle - **idle_level** - :esp32s2: * Specify maximum number of transmissions in a loop - **loop_count** + :SOC_RMT_SUPPORT_TX_LOOP_COUNT: * Specify maximum number of transmissions in a loop - **loop_count** Receive Mode ^^^^^^^^^^^^ @@ -156,10 +160,10 @@ In receive mode, set **rx_config** and the following members of :cpp:type:`rmt_r * Enable a filter on the input of the RMT receiver - **filter_en** * A threshold of the filter, set in the number of ticks - **filter_ticks_thresh**. Pulses shorter than this setting will be filtered out. Note, that the range of entered tick values is [0..255]. * A pulse length threshold that will turn the RMT receiver idle, set in number of ticks - **idle_threshold**. The receiver will ignore pulses longer than this setting. - :esp32s2: * Enable the RMT carrier demodulation - **carrier_rm** - :esp32s2: * Frequency of the carrier in Hz - **carrier_freq_hz** - :esp32s2: * Duty cycle of the carrier signal in percent (%) - **carrier_duty_percent** - :esp32s2: * Level of the RMT input, where the carrier is modulated to - **carrier_level** + :SOC_RMT_SUPPORT_RX_DEMODULATION: * Enable the RMT carrier demodulation - **carrier_rm** + :SOC_RMT_SUPPORT_RX_DEMODULATION: * Frequency of the carrier in Hz - **carrier_freq_hz** + :SOC_RMT_SUPPORT_RX_DEMODULATION: * Duty cycle of the carrier signal in percent (%) - **carrier_duty_percent** + :SOC_RMT_SUPPORT_RX_DEMODULATION: * Level of the RMT input, where the carrier is modulated to - **carrier_level** Finalize Configuration ^^^^^^^^^^^^^^^^^^^^^^ @@ -207,6 +211,11 @@ Another way to provide data for transmission is by calling :cpp:func:`rmt_fill_t Receive Data ------------ +.. only:: esp32 + + .. warning:: + RMT RX channel can't receive packet whose items are larger than its memory block size. If you set the memory block number to 1, then this RX channel can't receive packet with more than 64 items. This is a hardware limitation. + .. only:: esp32 Before starting the receiver we need some storage for incoming items. The RMT controller has 512 x 32-bits of internal RAM shared between all eight channels. @@ -219,6 +228,10 @@ Receive Data Before starting the receiver we need some storage for incoming items. The RMT controller has 192 x 32-bits of internal RAM shared between all four channels. +.. only:: esp32s3 + + Before starting the receiver we need some storage for incoming items. The RMT controller has 384 x 32-bits of internal RAM shared between all eight channels. + In typical scenarios it is not enough as an ultimate storage for all incoming (and outgoing) items. Therefore this API supports retrieval of incoming items on the fly to save them in a ring buffer of a size defined by the user. The size is provided when calling :cpp:func:`rmt_driver_install` discussed above. To get a handle to this buffer call :cpp:func:`rmt_get_ringbuf_handle`. With the above steps complete we can start the receiver by calling :cpp:func:`rmt_rx_start` and then move to checking what's inside the buffer. To do so, you can use common FreeRTOS functions that interact with the ring buffer. Please see an example how to do it in :example:`peripherals/rmt/ir_protocols`. From 40f350693f861cede36acee235c8a29f0c2ae6d7 Mon Sep 17 00:00:00 2001 From: morris Date: Fri, 18 Jun 2021 12:03:57 +0800 Subject: [PATCH 6/6] rmt: update soc data with regtool for esp32s3 --- components/hal/esp32s3/include/hal/rmt_ll.h | 132 +- components/soc/esp32s3/include/soc/rmt_reg.h | 5073 +++++++++-------- .../soc/esp32s3/include/soc/rmt_struct.h | 1400 +++-- 3 files changed, 3960 insertions(+), 2645 deletions(-) diff --git a/components/hal/esp32s3/include/hal/rmt_ll.h b/components/hal/esp32s3/include/hal/rmt_ll.h index b5ef90004d..0dc87853fa 100644 --- a/components/hal/esp32s3/include/hal/rmt_ll.h +++ b/components/hal/esp32s3/include/hal/rmt_ll.h @@ -1,4 +1,4 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// Copyright 2021 Espressif Systems (Shanghai) PTE LTD // // Licensed under the Apache License, Version 2.0 (the "License"); // you may not use this file except in compliance with the License. @@ -13,11 +13,9 @@ // limitations under the License. #pragma once -#include #include #include #include "soc/rmt_struct.h" -#include "soc/soc_caps.h" #ifdef __cplusplus extern "C" { @@ -51,7 +49,7 @@ static inline bool rmt_ll_is_mem_power_down(rmt_dev_t *dev) static inline void rmt_ll_enable_mem_access(rmt_dev_t *dev, bool enable) { - dev->sys_conf.fifo_mask = enable; + dev->sys_conf.apb_fifo_mask = enable; } static inline void rmt_ll_set_group_clock_src(rmt_dev_t *dev, uint32_t channel, uint8_t src, uint8_t div_num, uint8_t div_a, uint8_t div_b) @@ -87,132 +85,132 @@ static inline void rmt_ll_rx_reset_channel_clock_div(rmt_dev_t *dev, uint32_t ch static inline void rmt_ll_tx_reset_pointer(rmt_dev_t *dev, uint32_t channel) { - dev->tx_conf[channel].mem_rd_rst = 1; - dev->tx_conf[channel].mem_rd_rst = 0; - dev->tx_conf[channel].mem_rst = 1; - dev->tx_conf[channel].mem_rst = 0; + dev->chnconf0[channel].mem_rd_rst_n = 1; + dev->chnconf0[channel].mem_rd_rst_n = 0; + dev->chnconf0[channel].apb_mem_rst_n = 1; + dev->chnconf0[channel].apb_mem_rst_n = 0; } static inline void rmt_ll_rx_reset_pointer(rmt_dev_t *dev, uint32_t channel) { - dev->rx_conf[channel].conf1.mem_wr_rst = 1; - dev->rx_conf[channel].conf1.mem_wr_rst = 0; - dev->rx_conf[channel].conf1.mem_rst = 1; - dev->rx_conf[channel].conf1.mem_rst = 0; + dev->chmconf[channel].conf1.mem_wr_rst_m = 1; + dev->chmconf[channel].conf1.mem_wr_rst_m = 0; + dev->chmconf[channel].conf1.apb_mem_rst_m = 1; + dev->chmconf[channel].conf1.apb_mem_rst_m = 0; } static inline void rmt_ll_tx_start(rmt_dev_t *dev, uint32_t channel) { - dev->tx_conf[channel].conf_update = 1; - dev->tx_conf[channel].tx_start = 1; + dev->chnconf0[channel].conf_update_n = 1; + dev->chnconf0[channel].tx_start_n = 1; } static inline void rmt_ll_tx_stop(rmt_dev_t *dev, uint32_t channel) { - dev->tx_conf[channel].tx_stop = 1; - dev->tx_conf[channel].conf_update = 1; + dev->chnconf0[channel].tx_stop_n = 1; + dev->chnconf0[channel].conf_update_n = 1; } static inline void rmt_ll_rx_enable(rmt_dev_t *dev, uint32_t channel, bool enable) { - dev->rx_conf[channel].conf1.rx_en = enable; - dev->rx_conf[channel].conf1.conf_update = 1; + dev->chmconf[channel].conf1.rx_en_m = enable; + dev->chmconf[channel].conf1.conf_update_m = 1; } static inline void rmt_ll_tx_set_mem_blocks(rmt_dev_t *dev, uint32_t channel, uint8_t block_num) { - dev->tx_conf[channel].mem_size = block_num; + dev->chnconf0[channel].mem_size_n = block_num; } static inline void rmt_ll_rx_set_mem_blocks(rmt_dev_t *dev, uint32_t channel, uint8_t block_num) { - dev->rx_conf[channel].conf0.mem_size = block_num; + dev->chmconf[channel].conf0.mem_size_m = block_num; } static inline uint32_t rmt_ll_tx_get_mem_blocks(rmt_dev_t *dev, uint32_t channel) { - return dev->tx_conf[channel].mem_size; + return dev->chnconf0[channel].mem_size_n; } static inline uint32_t rmt_ll_rx_get_mem_blocks(rmt_dev_t *dev, uint32_t channel) { - return dev->rx_conf[channel].conf0.mem_size; + return dev->chmconf[channel].conf0.mem_size_m; } static inline void rmt_ll_tx_set_channel_clock_div(rmt_dev_t *dev, uint32_t channel, uint32_t div) { - dev->tx_conf[channel].div_cnt = div; + dev->chnconf0[channel].div_cnt_n = div; } static inline void rmt_ll_rx_set_channel_clock_div(rmt_dev_t *dev, uint32_t channel, uint32_t div) { - dev->rx_conf[channel].conf0.div_cnt = div; + dev->chmconf[channel].conf0.div_cnt_m = div; } static inline uint32_t rmt_ll_tx_get_channel_clock_div(rmt_dev_t *dev, uint32_t channel) { - return dev->tx_conf[channel].div_cnt; + return dev->chnconf0[channel].div_cnt_n; } static inline uint32_t rmt_ll_rx_get_channel_clock_div(rmt_dev_t *dev, uint32_t channel) { - return dev->rx_conf[channel].conf0.div_cnt; + return dev->chmconf[channel].conf0.div_cnt_m; } static inline void rmt_ll_tx_enable_pingpong(rmt_dev_t *dev, uint32_t channel, bool enable) { - dev->tx_conf[channel].mem_tx_wrap_en = enable; + dev->chnconf0[channel].mem_tx_wrap_en_n = enable; } static inline void rmt_ll_rx_set_idle_thres(rmt_dev_t *dev, uint32_t channel, uint32_t thres) { - dev->rx_conf[channel].conf0.idle_thres = thres; + dev->chmconf[channel].conf0.idle_thres_m = thres; } static inline uint32_t rmt_ll_rx_get_idle_thres(rmt_dev_t *dev, uint32_t channel) { - return dev->rx_conf[channel].conf0.idle_thres; + return dev->chmconf[channel].conf0.idle_thres_m; } static inline void rmt_ll_rx_set_mem_owner(rmt_dev_t *dev, uint32_t channel, uint8_t owner) { - dev->rx_conf[channel].conf1.mem_owner = owner; + dev->chmconf[channel].conf1.mem_owner_m = owner; } static inline uint32_t rmt_ll_rx_get_mem_owner(rmt_dev_t *dev, uint32_t channel) { - return dev->rx_conf[channel].conf1.mem_owner; + return dev->chmconf[channel].conf1.mem_owner_m; } static inline void rmt_ll_tx_enable_loop(rmt_dev_t *dev, uint32_t channel, bool enable) { - dev->tx_conf[channel].tx_conti_mode = enable; + dev->chnconf0[channel].tx_conti_mode_n = enable; } static inline bool rmt_ll_is_tx_loop_enabled(rmt_dev_t *dev, uint32_t channel) { - return dev->tx_conf[channel].tx_conti_mode; + return dev->chnconf0[channel].tx_conti_mode_n; } static inline void rmt_ll_tx_set_loop_count(rmt_dev_t *dev, uint32_t channel, uint32_t count) { - dev->tx_lim[channel].tx_loop_num = count; + dev->chn_tx_lim[channel].tx_loop_num_chn = count; } static inline void rmt_ll_tx_reset_loop(rmt_dev_t *dev, uint32_t channel) { - dev->tx_lim[channel].loop_count_reset = 1; - dev->tx_lim[channel].loop_count_reset = 0; + dev->chn_tx_lim[channel].loop_count_reset_chn = 1; + dev->chn_tx_lim[channel].loop_count_reset_chn = 0; } static inline void rmt_ll_tx_enable_loop_count(rmt_dev_t *dev, uint32_t channel, bool enable) { - dev->tx_lim[channel].tx_loop_cnt_en = enable; + dev->chn_tx_lim[channel].tx_loop_cnt_en_chn = enable; } static inline void rmt_ll_tx_enable_sync(rmt_dev_t *dev, bool enable) { - dev->tx_sim.en = enable; + dev->tx_sim.tx_sim_en = enable; } static inline void rmt_ll_tx_add_to_sync_group(rmt_dev_t *dev, uint32_t channel) @@ -227,57 +225,57 @@ static inline void rmt_ll_tx_remove_from_sync_group(rmt_dev_t *dev, uint32_t cha static inline void rmt_ll_rx_enable_filter(rmt_dev_t *dev, uint32_t channel, bool enable) { - dev->rx_conf[channel].conf1.rx_filter_en = enable; + dev->chmconf[channel].conf1.rx_filter_en_m = enable; } static inline void rmt_ll_rx_set_filter_thres(rmt_dev_t *dev, uint32_t channel, uint32_t thres) { - dev->rx_conf[channel].conf1.rx_filter_thres = thres; + dev->chmconf[channel].conf1.rx_filter_thres_m = thres; } static inline void rmt_ll_tx_enable_idle(rmt_dev_t *dev, uint32_t channel, bool enable) { - dev->tx_conf[channel].idle_out_en = enable; + dev->chnconf0[channel].idle_out_en_n = enable; } static inline bool rmt_ll_is_tx_idle_enabled(rmt_dev_t *dev, uint32_t channel) { - return dev->tx_conf[channel].idle_out_en; + return dev->chnconf0[channel].idle_out_en_n; } static inline void rmt_ll_tx_set_idle_level(rmt_dev_t *dev, uint32_t channel, uint8_t level) { - dev->tx_conf[channel].idle_out_lv = level; + dev->chnconf0[channel].idle_out_lv_n = level; } static inline uint32_t rmt_ll_tx_get_idle_level(rmt_dev_t *dev, uint32_t channel) { - return dev->tx_conf[channel].idle_out_lv; + return dev->chnconf0[channel].idle_out_lv_n; } static inline uint32_t rmt_ll_rx_get_channel_status(rmt_dev_t *dev, uint32_t channel) { - return dev->rx_status[channel].val; + return dev->chmstatus[channel].val; } static inline uint32_t rmt_ll_tx_get_channel_status(rmt_dev_t *dev, uint32_t channel) { - return dev->tx_status[channel].val; + return dev->chnstatus[channel].val; } static inline void rmt_ll_tx_set_limit(rmt_dev_t *dev, uint32_t channel, uint32_t limit) { - dev->tx_lim[channel].limit = limit; + dev->chn_tx_lim[channel].tx_lim_chn = limit; } static inline void rmt_ll_rx_set_limit(rmt_dev_t *dev, uint32_t channel, uint32_t limit) { - dev->rx_lim[channel].rx_lim = limit; + dev->chm_rx_lim[channel].chm_rx_lim_reg = limit; } static inline uint32_t rmt_ll_rx_get_limit(rmt_dev_t *dev, uint32_t channel) { - return dev->rx_lim[channel].rx_lim; + return dev->chm_rx_lim[channel].chm_rx_lim_reg; } static inline void rmt_ll_enable_interrupt(rmt_dev_t *dev, uint32_t mask, bool enable) @@ -426,57 +424,57 @@ static inline void rmt_ll_tx_set_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t { // In case the compiler optimise a 32bit instruction (e.g. s32i) into two 16bit instruction (e.g. s16i, which is not allowed to access a register) // We take care of the "read-modify-write" procedure by ourselves. - typeof(dev->tx_carrier[0]) reg; - reg.high = high_ticks; - reg.low = low_ticks; - dev->tx_carrier[channel].val = reg.val; + rmt_chncarrier_duty_reg_t reg; + reg.carrier_high_chn = high_ticks; + reg.carrier_low_chn = low_ticks; + dev->chncarrier_duty[channel].val = reg.val; } static inline void rmt_ll_rx_set_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t channel, uint32_t high_ticks, uint32_t low_ticks) { - typeof(dev->rx_carrier[0]) reg; - reg.high_thres = high_ticks; - reg.low_thres = low_ticks; - dev->rx_carrier[channel].val = reg.val; + rmt_chm_rx_carrier_rm_reg_t reg; + reg.carrier_high_thres_chm = high_ticks; + reg.carrier_low_thres_chm = low_ticks; + dev->chm_rx_carrier_rm[channel].val = reg.val; } static inline void rmt_ll_tx_get_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t channel, uint32_t *high_ticks, uint32_t *low_ticks ) { - *high_ticks = dev->tx_carrier[channel].high; - *low_ticks = dev->tx_carrier[channel].low; + *high_ticks = dev->chncarrier_duty[channel].carrier_high_chn; + *low_ticks = dev->chncarrier_duty[channel].carrier_low_chn; } static inline void rmt_ll_rx_get_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t channel, uint32_t *high_ticks, uint32_t *low_ticks) { - *high_ticks = dev->rx_carrier[channel].high_thres; - *low_ticks = dev->rx_carrier[channel].low_thres; + *high_ticks = dev->chm_rx_carrier_rm[channel].carrier_high_thres_chm; + *low_ticks = dev->chm_rx_carrier_rm[channel].carrier_low_thres_chm; } static inline void rmt_ll_tx_enable_carrier_modulation(rmt_dev_t *dev, uint32_t channel, bool enable) { - dev->tx_conf[channel].carrier_en = enable; + dev->chnconf0[channel].carrier_en_n = enable; } static inline void rmt_ll_rx_enable_carrier_demodulation(rmt_dev_t *dev, uint32_t channel, bool enable) { - dev->rx_conf[channel].conf0.carrier_en = enable; + dev->chmconf[channel].conf0.carrier_en_m = enable; } static inline void rmt_ll_tx_set_carrier_level(rmt_dev_t *dev, uint32_t channel, uint8_t level) { - dev->tx_conf[channel].carrier_out_lv = level; + dev->chnconf0[channel].carrier_out_lv_n = level; } static inline void rmt_ll_rx_set_carrier_level(rmt_dev_t *dev, uint32_t channel, uint8_t level) { - dev->rx_conf[channel].conf0.carrier_out_lv = level; + dev->chmconf[channel].conf0.carrier_out_lv_m = level; } // set true, enable carrier in all RMT state (idle, reading, sending) // set false, enable carrier only in sending state (i.e. there're effective data in RAM to be sent) static inline void rmt_ll_tx_set_carrier_always_on(rmt_dev_t *dev, uint32_t channel, bool enable) { - dev->tx_conf[channel].carrier_eff_en = !enable; + dev->chnconf0[channel].carrier_eff_en_n = !enable; } //Writes items to the specified TX channel memory with the given offset and length. @@ -492,7 +490,7 @@ static inline void rmt_ll_write_memory(rmt_mem_t *mem, uint32_t channel, const v static inline void rmt_ll_rx_enable_pingpong(rmt_dev_t *dev, uint32_t channel, bool enable) { - dev->rx_conf[channel].conf1.mem_rx_wrap_en = enable; + dev->chmconf[channel].conf1.mem_rx_wrap_en_m = enable; } #ifdef __cplusplus diff --git a/components/soc/esp32s3/include/soc/rmt_reg.h b/components/soc/esp32s3/include/soc/rmt_reg.h index 8c7e0c4518..55513e5e97 100644 --- a/components/soc/esp32s3/include/soc/rmt_reg.h +++ b/components/soc/esp32s3/include/soc/rmt_reg.h @@ -1,2347 +1,2900 @@ -// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -#ifndef _SOC_RMT_REG_H_ -#define _SOC_RMT_REG_H_ +/** Copyright 2021 Espressif Systems (Shanghai) PTE LTD + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once - -#include "soc.h" +#include +#include "soc/soc.h" #ifdef __cplusplus extern "C" { #endif -#define RMT_CH0DATA_REG (DR_REG_RMT_BASE + 0x0) +/** RMT_CH0DATA_REG register + * The read and write data register for CHANNEL0 by apb fifo access. + */ +#define RMT_CH0DATA_REG (DR_REG_RMT_BASE + 0x0) +/** RMT_CH0DATA : RO; bitpos: [31:0]; default: 0; + * Read and write data for channel 0 via APB FIFO. + */ +#define RMT_CH0DATA 0xFFFFFFFFU +#define RMT_CH0DATA_M (RMT_CH0DATA_V << RMT_CH0DATA_S) +#define RMT_CH0DATA_V 0xFFFFFFFFU +#define RMT_CH0DATA_S 0 -#define RMT_CH1DATA_REG (DR_REG_RMT_BASE + 0x4) +/** RMT_CH1DATA_REG register + * The read and write data register for CHANNEL1 by apb fifo access. + */ +#define RMT_CH1DATA_REG (DR_REG_RMT_BASE + 0x4) +/** RMT_CH1DATA : RO; bitpos: [31:0]; default: 0; + * Read and write data for channel 1 via APB FIFO. + */ +#define RMT_CH1DATA 0xFFFFFFFFU +#define RMT_CH1DATA_M (RMT_CH1DATA_V << RMT_CH1DATA_S) +#define RMT_CH1DATA_V 0xFFFFFFFFU +#define RMT_CH1DATA_S 0 -#define RMT_CH2DATA_REG (DR_REG_RMT_BASE + 0x8) +/** RMT_CH2DATA_REG register + * The read and write data register for CHANNEL2 by apb fifo access. + */ +#define RMT_CH2DATA_REG (DR_REG_RMT_BASE + 0x8) +/** RMT_CH2DATA : RO; bitpos: [31:0]; default: 0; + * Read and write data for channel 2 via APB FIFO. + */ +#define RMT_CH2DATA 0xFFFFFFFFU +#define RMT_CH2DATA_M (RMT_CH2DATA_V << RMT_CH2DATA_S) +#define RMT_CH2DATA_V 0xFFFFFFFFU +#define RMT_CH2DATA_S 0 -#define RMT_CH3DATA_REG (DR_REG_RMT_BASE + 0xC) +/** RMT_CH3DATA_REG register + * The read and write data register for CHANNEL3 by apb fifo access. + */ +#define RMT_CH3DATA_REG (DR_REG_RMT_BASE + 0xc) +/** RMT_CH3DATA : RO; bitpos: [31:0]; default: 0; + * Read and write data for channel 3 via APB FIFO. + */ +#define RMT_CH3DATA 0xFFFFFFFFU +#define RMT_CH3DATA_M (RMT_CH3DATA_V << RMT_CH3DATA_S) +#define RMT_CH3DATA_V 0xFFFFFFFFU +#define RMT_CH3DATA_S 0 -#define RMT_CH4DATA_REG (DR_REG_RMT_BASE + 0x10) +/** RMT_CH4DATA_REG register + * The read and write data register for CHANNEL$n by apb fifo access. + */ +#define RMT_CH4DATA_REG (DR_REG_RMT_BASE + 0x10) +/** RMT_CH4DATA : RO; bitpos: [31:0]; default: 0; + * Read and write data for channel $n via APB FIFO. + */ +#define RMT_CH4DATA 0xFFFFFFFFU +#define RMT_CH4DATA_M (RMT_CH4DATA_V << RMT_CH4DATA_S) +#define RMT_CH4DATA_V 0xFFFFFFFFU +#define RMT_CH4DATA_S 0 -#define RMT_CH5DATA_REG (DR_REG_RMT_BASE + 0x14) +/** RMT_CH5DATA_REG register + * The read and write data register for CHANNEL$n by apb fifo access. + */ +#define RMT_CH5DATA_REG (DR_REG_RMT_BASE + 0x14) +/** RMT_CH5DATA : RO; bitpos: [31:0]; default: 0; + * Read and write data for channel $n via APB FIFO. + */ +#define RMT_CH5DATA 0xFFFFFFFFU +#define RMT_CH5DATA_M (RMT_CH5DATA_V << RMT_CH5DATA_S) +#define RMT_CH5DATA_V 0xFFFFFFFFU +#define RMT_CH5DATA_S 0 -#define RMT_CH6DATA_REG (DR_REG_RMT_BASE + 0x18) +/** RMT_CH6DATA_REG register + * The read and write data register for CHANNEL$n by apb fifo access. + */ +#define RMT_CH6DATA_REG (DR_REG_RMT_BASE + 0x18) +/** RMT_CH6DATA : RO; bitpos: [31:0]; default: 0; + * Read and write data for channel $n via APB FIFO. + */ +#define RMT_CH6DATA 0xFFFFFFFFU +#define RMT_CH6DATA_M (RMT_CH6DATA_V << RMT_CH6DATA_S) +#define RMT_CH6DATA_V 0xFFFFFFFFU +#define RMT_CH6DATA_S 0 -#define RMT_CH7DATA_REG (DR_REG_RMT_BASE + 0x1C) +/** RMT_CH7DATA_REG register + * The read and write data register for CHANNEL$n by apb fifo access. + */ +#define RMT_CH7DATA_REG (DR_REG_RMT_BASE + 0x1c) +/** RMT_CH7DATA : RO; bitpos: [31:0]; default: 0; + * Read and write data for channel $n via APB FIFO. + */ +#define RMT_CH7DATA 0xFFFFFFFFU +#define RMT_CH7DATA_M (RMT_CH7DATA_V << RMT_CH7DATA_S) +#define RMT_CH7DATA_V 0xFFFFFFFFU +#define RMT_CH7DATA_S 0 -#define RMT_CH0CONF0_REG (DR_REG_RMT_BASE + 0x20) -/* RMT_CONF_UPDATE_CH0 : WT ;bitpos:[24] ;default: 1'b0 ; */ -/*description: synchronization bit for CHANNEL$n.*/ -#define RMT_CONF_UPDATE_CH0 (BIT(24)) -#define RMT_CONF_UPDATE_CH0_M (BIT(24)) -#define RMT_CONF_UPDATE_CH0_V 0x1 -#define RMT_CONF_UPDATE_CH0_S 24 -/* RMT_AFIFO_RST_CH0 : WT ;bitpos:[23] ;default: 1'b0 ; */ -/*description: Reserved.*/ -#define RMT_AFIFO_RST_CH0 (BIT(23)) -#define RMT_AFIFO_RST_CH0_M (BIT(23)) -#define RMT_AFIFO_RST_CH0_V 0x1 -#define RMT_AFIFO_RST_CH0_S 23 -/* RMT_CARRIER_OUT_LV_CH0 : R/W ;bitpos:[22] ;default: 1'b1 ; */ -/*description: This bit is used to configure the position of carrier wave for CHANNEL$n.; ; 1'h -0: add carrier wave on low level.; ; 1'h1: add carrier wave on high level..*/ -#define RMT_CARRIER_OUT_LV_CH0 (BIT(22)) -#define RMT_CARRIER_OUT_LV_CH0_M (BIT(22)) -#define RMT_CARRIER_OUT_LV_CH0_V 0x1 -#define RMT_CARRIER_OUT_LV_CH0_S 22 -/* RMT_CARRIER_EN_CH0 : R/W ;bitpos:[21] ;default: 1'b1 ; */ -/*description: This is the carrier modulation enable-control bit for CHANNEL$n. 1: Add carrier -modulation in the output signal. 0: No carrier modulation in sig_out..*/ -#define RMT_CARRIER_EN_CH0 (BIT(21)) -#define RMT_CARRIER_EN_CH0_M (BIT(21)) -#define RMT_CARRIER_EN_CH0_V 0x1 -#define RMT_CARRIER_EN_CH0_S 21 -/* RMT_CARRIER_EFF_EN_CH0 : R/W ;bitpos:[20] ;default: 1'b1 ; */ -/*description: 1: Add carrier modulation on the output signal only at the send data state for C -HANNEL$n. 0: Add carrier modulation on the output signal at all state for CHANNE -L$n. Only valid when RMT_CARRIER_EN_CH$n is 1..*/ -#define RMT_CARRIER_EFF_EN_CH0 (BIT(20)) -#define RMT_CARRIER_EFF_EN_CH0_M (BIT(20)) -#define RMT_CARRIER_EFF_EN_CH0_V 0x1 -#define RMT_CARRIER_EFF_EN_CH0_S 20 -/* RMT_MEM_SIZE_CH0 : R/W ;bitpos:[19:16] ;default: 4'h1 ; */ -/*description: This register is used to configure the maximum size of memory allocated to CHANN -EL$n..*/ -#define RMT_MEM_SIZE_CH0 0x0000000F -#define RMT_MEM_SIZE_CH0_M ((RMT_MEM_SIZE_CH0_V)<<(RMT_MEM_SIZE_CH0_S)) -#define RMT_MEM_SIZE_CH0_V 0xF -#define RMT_MEM_SIZE_CH0_S 16 -/* RMT_DIV_CNT_CH0 : R/W ;bitpos:[15:8] ;default: 8'h2 ; */ -/*description: This register is used to configure the divider for clock of CHANNEL$n..*/ -#define RMT_DIV_CNT_CH0 0x000000FF -#define RMT_DIV_CNT_CH0_M ((RMT_DIV_CNT_CH0_V)<<(RMT_DIV_CNT_CH0_S)) -#define RMT_DIV_CNT_CH0_V 0xFF -#define RMT_DIV_CNT_CH0_S 8 -/* RMT_TX_STOP_CH0 : R/W/SC ;bitpos:[7] ;default: 1'b0 ; */ -/*description: Set this bit to stop the transmitter of CHANNEL$n sending data out..*/ -#define RMT_TX_STOP_CH0 (BIT(7)) -#define RMT_TX_STOP_CH0_M (BIT(7)) -#define RMT_TX_STOP_CH0_V 0x1 -#define RMT_TX_STOP_CH0_S 7 -/* RMT_IDLE_OUT_EN_CH0 : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: This is the output enable-control bit for CHANNEL$n in IDLE state..*/ -#define RMT_IDLE_OUT_EN_CH0 (BIT(6)) -#define RMT_IDLE_OUT_EN_CH0_M (BIT(6)) -#define RMT_IDLE_OUT_EN_CH0_V 0x1 -#define RMT_IDLE_OUT_EN_CH0_S 6 -/* RMT_IDLE_OUT_LV_CH0 : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: This bit configures the level of output signal in CHANNEL$n when the latter is i -n IDLE state..*/ -#define RMT_IDLE_OUT_LV_CH0 (BIT(5)) -#define RMT_IDLE_OUT_LV_CH0_M (BIT(5)) -#define RMT_IDLE_OUT_LV_CH0_V 0x1 -#define RMT_IDLE_OUT_LV_CH0_S 5 -/* RMT_MEM_TX_WRAP_EN_CH0 : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: This is the channel $n enable bit for wraparound mode: it will resume sending at - the start when the data to be sent is more than its memory size..*/ -#define RMT_MEM_TX_WRAP_EN_CH0 (BIT(4)) -#define RMT_MEM_TX_WRAP_EN_CH0_M (BIT(4)) -#define RMT_MEM_TX_WRAP_EN_CH0_V 0x1 -#define RMT_MEM_TX_WRAP_EN_CH0_S 4 -/* RMT_TX_CONTI_MODE_CH0 : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: Set this bit to restart transmission from the first data to the last data in CH -ANNEL$n..*/ -#define RMT_TX_CONTI_MODE_CH0 (BIT(3)) -#define RMT_TX_CONTI_MODE_CH0_M (BIT(3)) -#define RMT_TX_CONTI_MODE_CH0_V 0x1 -#define RMT_TX_CONTI_MODE_CH0_S 3 -/* RMT_APB_MEM_RST_CH0 : WT ;bitpos:[2] ;default: 1'b0 ; */ -/*description: Set this bit to reset W/R ram address for CHANNEL$n by accessing apb fifo..*/ -#define RMT_APB_MEM_RST_CH0 (BIT(2)) -#define RMT_APB_MEM_RST_CH0_M (BIT(2)) -#define RMT_APB_MEM_RST_CH0_V 0x1 -#define RMT_APB_MEM_RST_CH0_S 2 -/* RMT_MEM_RD_RST_CH0 : WT ;bitpos:[1] ;default: 1'b0 ; */ -/*description: Set this bit to reset read ram address for CHANNEL$n by accessing transmitter..*/ -#define RMT_MEM_RD_RST_CH0 (BIT(1)) -#define RMT_MEM_RD_RST_CH0_M (BIT(1)) -#define RMT_MEM_RD_RST_CH0_V 0x1 -#define RMT_MEM_RD_RST_CH0_S 1 -/* RMT_TX_START_CH0 : WT ;bitpos:[0] ;default: 1'h0 ; */ -/*description: Set this bit to start sending data on CHANNEL$n..*/ -#define RMT_TX_START_CH0 (BIT(0)) -#define RMT_TX_START_CH0_M (BIT(0)) -#define RMT_TX_START_CH0_V 0x1 -#define RMT_TX_START_CH0_S 0 +/** RMT_CH0CONF0_REG register + * Channel 0 configure register 0 + */ +#define RMT_CH0CONF0_REG (DR_REG_RMT_BASE + 0x20) +/** RMT_TX_START_0 : WT; bitpos: [0]; default: 0; + * Set this bit to start sending data on CHANNEL0. + */ +#define RMT_TX_START_0 (BIT(0)) +#define RMT_TX_START_0_M (RMT_TX_START_0_V << RMT_TX_START_0_S) +#define RMT_TX_START_0_V 0x00000001U +#define RMT_TX_START_0_S 0 +/** RMT_MEM_RD_RST_0 : WT; bitpos: [1]; default: 0; + * Set this bit to reset read ram address for CHANNEL0 by accessing transmitter. + */ +#define RMT_MEM_RD_RST_0 (BIT(1)) +#define RMT_MEM_RD_RST_0_M (RMT_MEM_RD_RST_0_V << RMT_MEM_RD_RST_0_S) +#define RMT_MEM_RD_RST_0_V 0x00000001U +#define RMT_MEM_RD_RST_0_S 1 +/** RMT_APB_MEM_RST_0 : WT; bitpos: [2]; default: 0; + * Set this bit to reset W/R ram address for CHANNEL0 by accessing apb fifo. + */ +#define RMT_APB_MEM_RST_0 (BIT(2)) +#define RMT_APB_MEM_RST_0_M (RMT_APB_MEM_RST_0_V << RMT_APB_MEM_RST_0_S) +#define RMT_APB_MEM_RST_0_V 0x00000001U +#define RMT_APB_MEM_RST_0_S 2 +/** RMT_TX_CONTI_MODE_0 : R/W; bitpos: [3]; default: 0; + * Set this bit to restart transmission from the first data to the last data in + * CHANNEL0. + */ +#define RMT_TX_CONTI_MODE_0 (BIT(3)) +#define RMT_TX_CONTI_MODE_0_M (RMT_TX_CONTI_MODE_0_V << RMT_TX_CONTI_MODE_0_S) +#define RMT_TX_CONTI_MODE_0_V 0x00000001U +#define RMT_TX_CONTI_MODE_0_S 3 +/** RMT_MEM_TX_WRAP_EN_0 : R/W; bitpos: [4]; default: 0; + * This is the channel 0 enable bit for wraparound mode: it will resume sending at the + * start when the data to be sent is more than its memory size. + */ +#define RMT_MEM_TX_WRAP_EN_0 (BIT(4)) +#define RMT_MEM_TX_WRAP_EN_0_M (RMT_MEM_TX_WRAP_EN_0_V << RMT_MEM_TX_WRAP_EN_0_S) +#define RMT_MEM_TX_WRAP_EN_0_V 0x00000001U +#define RMT_MEM_TX_WRAP_EN_0_S 4 +/** RMT_IDLE_OUT_LV_0 : R/W; bitpos: [5]; default: 0; + * This bit configures the level of output signal in CHANNEL0 when the latter is in + * IDLE state. + */ +#define RMT_IDLE_OUT_LV_0 (BIT(5)) +#define RMT_IDLE_OUT_LV_0_M (RMT_IDLE_OUT_LV_0_V << RMT_IDLE_OUT_LV_0_S) +#define RMT_IDLE_OUT_LV_0_V 0x00000001U +#define RMT_IDLE_OUT_LV_0_S 5 +/** RMT_IDLE_OUT_EN_0 : R/W; bitpos: [6]; default: 0; + * This is the output enable-control bit for CHANNEL0 in IDLE state. + */ +#define RMT_IDLE_OUT_EN_0 (BIT(6)) +#define RMT_IDLE_OUT_EN_0_M (RMT_IDLE_OUT_EN_0_V << RMT_IDLE_OUT_EN_0_S) +#define RMT_IDLE_OUT_EN_0_V 0x00000001U +#define RMT_IDLE_OUT_EN_0_S 6 +/** RMT_TX_STOP_0 : R/W/SC; bitpos: [7]; default: 0; + * Set this bit to stop the transmitter of CHANNEL0 sending data out. + */ +#define RMT_TX_STOP_0 (BIT(7)) +#define RMT_TX_STOP_0_M (RMT_TX_STOP_0_V << RMT_TX_STOP_0_S) +#define RMT_TX_STOP_0_V 0x00000001U +#define RMT_TX_STOP_0_S 7 +/** RMT_DIV_CNT_0 : R/W; bitpos: [15:8]; default: 2; + * This register is used to configure the divider for clock of CHANNEL0. + */ +#define RMT_DIV_CNT_0 0x000000FFU +#define RMT_DIV_CNT_0_M (RMT_DIV_CNT_0_V << RMT_DIV_CNT_0_S) +#define RMT_DIV_CNT_0_V 0x000000FFU +#define RMT_DIV_CNT_0_S 8 +/** RMT_MEM_SIZE_0 : R/W; bitpos: [19:16]; default: 1; + * This register is used to configure the maximum size of memory allocated to CHANNEL0. + */ +#define RMT_MEM_SIZE_0 0x0000000FU +#define RMT_MEM_SIZE_0_M (RMT_MEM_SIZE_0_V << RMT_MEM_SIZE_0_S) +#define RMT_MEM_SIZE_0_V 0x0000000FU +#define RMT_MEM_SIZE_0_S 16 +/** RMT_CARRIER_EFF_EN_0 : R/W; bitpos: [20]; default: 1; + * 1: Add carrier modulation on the output signal only at the send data state for + * CHANNEL0. 0: Add carrier modulation on the output signal at all state for CHANNEL0. + * Only valid when RMT_CARRIER_EN_CH0 is 1. + */ +#define RMT_CARRIER_EFF_EN_0 (BIT(20)) +#define RMT_CARRIER_EFF_EN_0_M (RMT_CARRIER_EFF_EN_0_V << RMT_CARRIER_EFF_EN_0_S) +#define RMT_CARRIER_EFF_EN_0_V 0x00000001U +#define RMT_CARRIER_EFF_EN_0_S 20 +/** RMT_CARRIER_EN_0 : R/W; bitpos: [21]; default: 1; + * This is the carrier modulation enable-control bit for CHANNEL0. 1: Add carrier + * modulation in the output signal. 0: No carrier modulation in sig_out. + */ +#define RMT_CARRIER_EN_0 (BIT(21)) +#define RMT_CARRIER_EN_0_M (RMT_CARRIER_EN_0_V << RMT_CARRIER_EN_0_S) +#define RMT_CARRIER_EN_0_V 0x00000001U +#define RMT_CARRIER_EN_0_S 21 +/** RMT_CARRIER_OUT_LV_0 : R/W; bitpos: [22]; default: 1; + * This bit is used to configure the position of carrier wave for CHANNEL0. + * + * 1'h0: add carrier wave on low level. + * + * 1'h1: add carrier wave on high level. + */ +#define RMT_CARRIER_OUT_LV_0 (BIT(22)) +#define RMT_CARRIER_OUT_LV_0_M (RMT_CARRIER_OUT_LV_0_V << RMT_CARRIER_OUT_LV_0_S) +#define RMT_CARRIER_OUT_LV_0_V 0x00000001U +#define RMT_CARRIER_OUT_LV_0_S 22 +/** RMT_AFIFO_RST_0 : WT; bitpos: [23]; default: 0; + * Reserved + */ +#define RMT_AFIFO_RST_0 (BIT(23)) +#define RMT_AFIFO_RST_0_M (RMT_AFIFO_RST_0_V << RMT_AFIFO_RST_0_S) +#define RMT_AFIFO_RST_0_V 0x00000001U +#define RMT_AFIFO_RST_0_S 23 +/** RMT_CONF_UPDATE_0 : WT; bitpos: [24]; default: 0; + * synchronization bit for CHANNEL0 + */ +#define RMT_CONF_UPDATE_0 (BIT(24)) +#define RMT_CONF_UPDATE_0_M (RMT_CONF_UPDATE_0_V << RMT_CONF_UPDATE_0_S) +#define RMT_CONF_UPDATE_0_V 0x00000001U +#define RMT_CONF_UPDATE_0_S 24 -#define RMT_CH1CONF0_REG (DR_REG_RMT_BASE + 0x24) -/* RMT_CONF_UPDATE_CH1 : WT ;bitpos:[24] ;default: 1'b0 ; */ -/*description: synchronization bit for CHANNEL$n.*/ -#define RMT_CONF_UPDATE_CH1 (BIT(24)) -#define RMT_CONF_UPDATE_CH1_M (BIT(24)) -#define RMT_CONF_UPDATE_CH1_V 0x1 -#define RMT_CONF_UPDATE_CH1_S 24 -/* RMT_AFIFO_RST_CH1 : WT ;bitpos:[23] ;default: 1'b0 ; */ -/*description: Reserved.*/ -#define RMT_AFIFO_RST_CH1 (BIT(23)) -#define RMT_AFIFO_RST_CH1_M (BIT(23)) -#define RMT_AFIFO_RST_CH1_V 0x1 -#define RMT_AFIFO_RST_CH1_S 23 -/* RMT_CARRIER_OUT_LV_CH1 : R/W ;bitpos:[22] ;default: 1'b1 ; */ -/*description: This bit is used to configure the position of carrier wave for CHANNEL$n.; ; 1'h -0: add carrier wave on low level.; ; 1'h1: add carrier wave on high level..*/ -#define RMT_CARRIER_OUT_LV_CH1 (BIT(22)) -#define RMT_CARRIER_OUT_LV_CH1_M (BIT(22)) -#define RMT_CARRIER_OUT_LV_CH1_V 0x1 -#define RMT_CARRIER_OUT_LV_CH1_S 22 -/* RMT_CARRIER_EN_CH1 : R/W ;bitpos:[21] ;default: 1'b1 ; */ -/*description: This is the carrier modulation enable-control bit for CHANNEL$n. 1: Add carrier -modulation in the output signal. 0: No carrier modulation in sig_out..*/ -#define RMT_CARRIER_EN_CH1 (BIT(21)) -#define RMT_CARRIER_EN_CH1_M (BIT(21)) -#define RMT_CARRIER_EN_CH1_V 0x1 -#define RMT_CARRIER_EN_CH1_S 21 -/* RMT_CARRIER_EFF_EN_CH1 : R/W ;bitpos:[20] ;default: 1'b1 ; */ -/*description: 1: Add carrier modulation on the output signal only at the send data state for C -HANNEL$n. 0: Add carrier modulation on the output signal at all state for CHANNE -L$n. Only valid when RMT_CARRIER_EN_CH$n is 1..*/ -#define RMT_CARRIER_EFF_EN_CH1 (BIT(20)) -#define RMT_CARRIER_EFF_EN_CH1_M (BIT(20)) -#define RMT_CARRIER_EFF_EN_CH1_V 0x1 -#define RMT_CARRIER_EFF_EN_CH1_S 20 -/* RMT_MEM_SIZE_CH1 : R/W ;bitpos:[19:16] ;default: 4'h1 ; */ -/*description: This register is used to configure the maximum size of memory allocated to CHANN -EL$n..*/ -#define RMT_MEM_SIZE_CH1 0x0000000F -#define RMT_MEM_SIZE_CH1_M ((RMT_MEM_SIZE_CH1_V)<<(RMT_MEM_SIZE_CH1_S)) -#define RMT_MEM_SIZE_CH1_V 0xF -#define RMT_MEM_SIZE_CH1_S 16 -/* RMT_DIV_CNT_CH1 : R/W ;bitpos:[15:8] ;default: 8'h2 ; */ -/*description: This register is used to configure the divider for clock of CHANNEL$n..*/ -#define RMT_DIV_CNT_CH1 0x000000FF -#define RMT_DIV_CNT_CH1_M ((RMT_DIV_CNT_CH1_V)<<(RMT_DIV_CNT_CH1_S)) -#define RMT_DIV_CNT_CH1_V 0xFF -#define RMT_DIV_CNT_CH1_S 8 -/* RMT_TX_STOP_CH1 : R/W/SC ;bitpos:[7] ;default: 1'b0 ; */ -/*description: Set this bit to stop the transmitter of CHANNEL$n sending data out..*/ -#define RMT_TX_STOP_CH1 (BIT(7)) -#define RMT_TX_STOP_CH1_M (BIT(7)) -#define RMT_TX_STOP_CH1_V 0x1 -#define RMT_TX_STOP_CH1_S 7 -/* RMT_IDLE_OUT_EN_CH1 : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: This is the output enable-control bit for CHANNEL$n in IDLE state..*/ -#define RMT_IDLE_OUT_EN_CH1 (BIT(6)) -#define RMT_IDLE_OUT_EN_CH1_M (BIT(6)) -#define RMT_IDLE_OUT_EN_CH1_V 0x1 -#define RMT_IDLE_OUT_EN_CH1_S 6 -/* RMT_IDLE_OUT_LV_CH1 : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: This bit configures the level of output signal in CHANNEL$n when the latter is i -n IDLE state..*/ -#define RMT_IDLE_OUT_LV_CH1 (BIT(5)) -#define RMT_IDLE_OUT_LV_CH1_M (BIT(5)) -#define RMT_IDLE_OUT_LV_CH1_V 0x1 -#define RMT_IDLE_OUT_LV_CH1_S 5 -/* RMT_MEM_TX_WRAP_EN_CH1 : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: This is the channel $n enable bit for wraparound mode: it will resume sending at - the start when the data to be sent is more than its memory size..*/ -#define RMT_MEM_TX_WRAP_EN_CH1 (BIT(4)) -#define RMT_MEM_TX_WRAP_EN_CH1_M (BIT(4)) -#define RMT_MEM_TX_WRAP_EN_CH1_V 0x1 -#define RMT_MEM_TX_WRAP_EN_CH1_S 4 -/* RMT_TX_CONTI_MODE_CH1 : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: Set this bit to restart transmission from the first data to the last data in CH -ANNEL$n..*/ -#define RMT_TX_CONTI_MODE_CH1 (BIT(3)) -#define RMT_TX_CONTI_MODE_CH1_M (BIT(3)) -#define RMT_TX_CONTI_MODE_CH1_V 0x1 -#define RMT_TX_CONTI_MODE_CH1_S 3 -/* RMT_APB_MEM_RST_CH1 : WT ;bitpos:[2] ;default: 1'b0 ; */ -/*description: Set this bit to reset W/R ram address for CHANNEL$n by accessing apb fifo..*/ -#define RMT_APB_MEM_RST_CH1 (BIT(2)) -#define RMT_APB_MEM_RST_CH1_M (BIT(2)) -#define RMT_APB_MEM_RST_CH1_V 0x1 -#define RMT_APB_MEM_RST_CH1_S 2 -/* RMT_MEM_RD_RST_CH1 : WT ;bitpos:[1] ;default: 1'b0 ; */ -/*description: Set this bit to reset read ram address for CHANNEL$n by accessing transmitter..*/ -#define RMT_MEM_RD_RST_CH1 (BIT(1)) -#define RMT_MEM_RD_RST_CH1_M (BIT(1)) -#define RMT_MEM_RD_RST_CH1_V 0x1 -#define RMT_MEM_RD_RST_CH1_S 1 -/* RMT_TX_START_CH1 : WT ;bitpos:[0] ;default: 1'h0 ; */ -/*description: Set this bit to start sending data on CHANNEL$n..*/ -#define RMT_TX_START_CH1 (BIT(0)) -#define RMT_TX_START_CH1_M (BIT(0)) -#define RMT_TX_START_CH1_V 0x1 -#define RMT_TX_START_CH1_S 0 +/** RMT_CH1CONF0_REG register + * Channel 1 configure register 0 + */ +#define RMT_CH1CONF0_REG (DR_REG_RMT_BASE + 0x24) +/** RMT_TX_START_1 : WT; bitpos: [0]; default: 0; + * Set this bit to start sending data on CHANNEL1. + */ +#define RMT_TX_START_1 (BIT(0)) +#define RMT_TX_START_1_M (RMT_TX_START_1_V << RMT_TX_START_1_S) +#define RMT_TX_START_1_V 0x00000001U +#define RMT_TX_START_1_S 0 +/** RMT_MEM_RD_RST_1 : WT; bitpos: [1]; default: 0; + * Set this bit to reset read ram address for CHANNEL1 by accessing transmitter. + */ +#define RMT_MEM_RD_RST_1 (BIT(1)) +#define RMT_MEM_RD_RST_1_M (RMT_MEM_RD_RST_1_V << RMT_MEM_RD_RST_1_S) +#define RMT_MEM_RD_RST_1_V 0x00000001U +#define RMT_MEM_RD_RST_1_S 1 +/** RMT_APB_MEM_RST_1 : WT; bitpos: [2]; default: 0; + * Set this bit to reset W/R ram address for CHANNEL1 by accessing apb fifo. + */ +#define RMT_APB_MEM_RST_1 (BIT(2)) +#define RMT_APB_MEM_RST_1_M (RMT_APB_MEM_RST_1_V << RMT_APB_MEM_RST_1_S) +#define RMT_APB_MEM_RST_1_V 0x00000001U +#define RMT_APB_MEM_RST_1_S 2 +/** RMT_TX_CONTI_MODE_1 : R/W; bitpos: [3]; default: 0; + * Set this bit to restart transmission from the first data to the last data in + * CHANNEL1. + */ +#define RMT_TX_CONTI_MODE_1 (BIT(3)) +#define RMT_TX_CONTI_MODE_1_M (RMT_TX_CONTI_MODE_1_V << RMT_TX_CONTI_MODE_1_S) +#define RMT_TX_CONTI_MODE_1_V 0x00000001U +#define RMT_TX_CONTI_MODE_1_S 3 +/** RMT_MEM_TX_WRAP_EN_1 : R/W; bitpos: [4]; default: 0; + * This is the channel 1 enable bit for wraparound mode: it will resume sending at the + * start when the data to be sent is more than its memory size. + */ +#define RMT_MEM_TX_WRAP_EN_1 (BIT(4)) +#define RMT_MEM_TX_WRAP_EN_1_M (RMT_MEM_TX_WRAP_EN_1_V << RMT_MEM_TX_WRAP_EN_1_S) +#define RMT_MEM_TX_WRAP_EN_1_V 0x00000001U +#define RMT_MEM_TX_WRAP_EN_1_S 4 +/** RMT_IDLE_OUT_LV_1 : R/W; bitpos: [5]; default: 0; + * This bit configures the level of output signal in CHANNEL1 when the latter is in + * IDLE state. + */ +#define RMT_IDLE_OUT_LV_1 (BIT(5)) +#define RMT_IDLE_OUT_LV_1_M (RMT_IDLE_OUT_LV_1_V << RMT_IDLE_OUT_LV_1_S) +#define RMT_IDLE_OUT_LV_1_V 0x00000001U +#define RMT_IDLE_OUT_LV_1_S 5 +/** RMT_IDLE_OUT_EN_1 : R/W; bitpos: [6]; default: 0; + * This is the output enable-control bit for CHANNEL1 in IDLE state. + */ +#define RMT_IDLE_OUT_EN_1 (BIT(6)) +#define RMT_IDLE_OUT_EN_1_M (RMT_IDLE_OUT_EN_1_V << RMT_IDLE_OUT_EN_1_S) +#define RMT_IDLE_OUT_EN_1_V 0x00000001U +#define RMT_IDLE_OUT_EN_1_S 6 +/** RMT_TX_STOP_1 : R/W/SC; bitpos: [7]; default: 0; + * Set this bit to stop the transmitter of CHANNEL1 sending data out. + */ +#define RMT_TX_STOP_1 (BIT(7)) +#define RMT_TX_STOP_1_M (RMT_TX_STOP_1_V << RMT_TX_STOP_1_S) +#define RMT_TX_STOP_1_V 0x00000001U +#define RMT_TX_STOP_1_S 7 +/** RMT_DIV_CNT_1 : R/W; bitpos: [15:8]; default: 2; + * This register is used to configure the divider for clock of CHANNEL1. + */ +#define RMT_DIV_CNT_1 0x000000FFU +#define RMT_DIV_CNT_1_M (RMT_DIV_CNT_1_V << RMT_DIV_CNT_1_S) +#define RMT_DIV_CNT_1_V 0x000000FFU +#define RMT_DIV_CNT_1_S 8 +/** RMT_MEM_SIZE_1 : R/W; bitpos: [19:16]; default: 1; + * This register is used to configure the maximum size of memory allocated to CHANNEL1. + */ +#define RMT_MEM_SIZE_1 0x0000000FU +#define RMT_MEM_SIZE_1_M (RMT_MEM_SIZE_1_V << RMT_MEM_SIZE_1_S) +#define RMT_MEM_SIZE_1_V 0x0000000FU +#define RMT_MEM_SIZE_1_S 16 +/** RMT_CARRIER_EFF_EN_1 : R/W; bitpos: [20]; default: 1; + * 1: Add carrier modulation on the output signal only at the send data state for + * CHANNEL1. 0: Add carrier modulation on the output signal at all state for CHANNEL1. + * Only valid when RMT_CARRIER_EN_CH1 is 1. + */ +#define RMT_CARRIER_EFF_EN_1 (BIT(20)) +#define RMT_CARRIER_EFF_EN_1_M (RMT_CARRIER_EFF_EN_1_V << RMT_CARRIER_EFF_EN_1_S) +#define RMT_CARRIER_EFF_EN_1_V 0x00000001U +#define RMT_CARRIER_EFF_EN_1_S 20 +/** RMT_CARRIER_EN_1 : R/W; bitpos: [21]; default: 1; + * This is the carrier modulation enable-control bit for CHANNEL1. 1: Add carrier + * modulation in the output signal. 0: No carrier modulation in sig_out. + */ +#define RMT_CARRIER_EN_1 (BIT(21)) +#define RMT_CARRIER_EN_1_M (RMT_CARRIER_EN_1_V << RMT_CARRIER_EN_1_S) +#define RMT_CARRIER_EN_1_V 0x00000001U +#define RMT_CARRIER_EN_1_S 21 +/** RMT_CARRIER_OUT_LV_1 : R/W; bitpos: [22]; default: 1; + * This bit is used to configure the position of carrier wave for CHANNEL1. + * + * 1'h0: add carrier wave on low level. + * + * 1'h1: add carrier wave on high level. + */ +#define RMT_CARRIER_OUT_LV_1 (BIT(22)) +#define RMT_CARRIER_OUT_LV_1_M (RMT_CARRIER_OUT_LV_1_V << RMT_CARRIER_OUT_LV_1_S) +#define RMT_CARRIER_OUT_LV_1_V 0x00000001U +#define RMT_CARRIER_OUT_LV_1_S 22 +/** RMT_AFIFO_RST_1 : WT; bitpos: [23]; default: 0; + * Reserved + */ +#define RMT_AFIFO_RST_1 (BIT(23)) +#define RMT_AFIFO_RST_1_M (RMT_AFIFO_RST_1_V << RMT_AFIFO_RST_1_S) +#define RMT_AFIFO_RST_1_V 0x00000001U +#define RMT_AFIFO_RST_1_S 23 +/** RMT_CONF_UPDATE_1 : WT; bitpos: [24]; default: 0; + * synchronization bit for CHANNEL1 + */ +#define RMT_CONF_UPDATE_1 (BIT(24)) +#define RMT_CONF_UPDATE_1_M (RMT_CONF_UPDATE_1_V << RMT_CONF_UPDATE_1_S) +#define RMT_CONF_UPDATE_1_V 0x00000001U +#define RMT_CONF_UPDATE_1_S 24 -#define RMT_CH2CONF0_REG (DR_REG_RMT_BASE + 0x28) -/* RMT_CONF_UPDATE_CH2 : WT ;bitpos:[24] ;default: 1'b0 ; */ -/*description: synchronization bit for CHANNEL$n.*/ -#define RMT_CONF_UPDATE_CH2 (BIT(24)) -#define RMT_CONF_UPDATE_CH2_M (BIT(24)) -#define RMT_CONF_UPDATE_CH2_V 0x1 -#define RMT_CONF_UPDATE_CH2_S 24 -/* RMT_AFIFO_RST_CH2 : WT ;bitpos:[23] ;default: 1'b0 ; */ -/*description: Reserved.*/ -#define RMT_AFIFO_RST_CH2 (BIT(23)) -#define RMT_AFIFO_RST_CH2_M (BIT(23)) -#define RMT_AFIFO_RST_CH2_V 0x1 -#define RMT_AFIFO_RST_CH2_S 23 -/* RMT_CARRIER_OUT_LV_CH2 : R/W ;bitpos:[22] ;default: 1'b1 ; */ -/*description: This bit is used to configure the position of carrier wave for CHANNEL$n.; ; 1'h -0: add carrier wave on low level.; ; 1'h1: add carrier wave on high level..*/ -#define RMT_CARRIER_OUT_LV_CH2 (BIT(22)) -#define RMT_CARRIER_OUT_LV_CH2_M (BIT(22)) -#define RMT_CARRIER_OUT_LV_CH2_V 0x1 -#define RMT_CARRIER_OUT_LV_CH2_S 22 -/* RMT_CARRIER_EN_CH2 : R/W ;bitpos:[21] ;default: 1'b1 ; */ -/*description: This is the carrier modulation enable-control bit for CHANNEL$n. 1: Add carrier -modulation in the output signal. 0: No carrier modulation in sig_out..*/ -#define RMT_CARRIER_EN_CH2 (BIT(21)) -#define RMT_CARRIER_EN_CH2_M (BIT(21)) -#define RMT_CARRIER_EN_CH2_V 0x1 -#define RMT_CARRIER_EN_CH2_S 21 -/* RMT_CARRIER_EFF_EN_CH2 : R/W ;bitpos:[20] ;default: 1'b1 ; */ -/*description: 1: Add carrier modulation on the output signal only at the send data state for C -HANNEL$n. 0: Add carrier modulation on the output signal at all state for CHANNE -L$n. Only valid when RMT_CARRIER_EN_CH$n is 1..*/ -#define RMT_CARRIER_EFF_EN_CH2 (BIT(20)) -#define RMT_CARRIER_EFF_EN_CH2_M (BIT(20)) -#define RMT_CARRIER_EFF_EN_CH2_V 0x1 -#define RMT_CARRIER_EFF_EN_CH2_S 20 -/* RMT_MEM_SIZE_CH2 : R/W ;bitpos:[19:16] ;default: 4'h1 ; */ -/*description: This register is used to configure the maximum size of memory allocated to CHANN -EL$n..*/ -#define RMT_MEM_SIZE_CH2 0x0000000F -#define RMT_MEM_SIZE_CH2_M ((RMT_MEM_SIZE_CH2_V)<<(RMT_MEM_SIZE_CH2_S)) -#define RMT_MEM_SIZE_CH2_V 0xF -#define RMT_MEM_SIZE_CH2_S 16 -/* RMT_DIV_CNT_CH2 : R/W ;bitpos:[15:8] ;default: 8'h2 ; */ -/*description: This register is used to configure the divider for clock of CHANNEL$n..*/ -#define RMT_DIV_CNT_CH2 0x000000FF -#define RMT_DIV_CNT_CH2_M ((RMT_DIV_CNT_CH2_V)<<(RMT_DIV_CNT_CH2_S)) -#define RMT_DIV_CNT_CH2_V 0xFF -#define RMT_DIV_CNT_CH2_S 8 -/* RMT_TX_STOP_CH2 : R/W/SC ;bitpos:[7] ;default: 1'b0 ; */ -/*description: Set this bit to stop the transmitter of CHANNEL$n sending data out..*/ -#define RMT_TX_STOP_CH2 (BIT(7)) -#define RMT_TX_STOP_CH2_M (BIT(7)) -#define RMT_TX_STOP_CH2_V 0x1 -#define RMT_TX_STOP_CH2_S 7 -/* RMT_IDLE_OUT_EN_CH2 : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: This is the output enable-control bit for CHANNEL$n in IDLE state..*/ -#define RMT_IDLE_OUT_EN_CH2 (BIT(6)) -#define RMT_IDLE_OUT_EN_CH2_M (BIT(6)) -#define RMT_IDLE_OUT_EN_CH2_V 0x1 -#define RMT_IDLE_OUT_EN_CH2_S 6 -/* RMT_IDLE_OUT_LV_CH2 : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: This bit configures the level of output signal in CHANNEL$n when the latter is i -n IDLE state..*/ -#define RMT_IDLE_OUT_LV_CH2 (BIT(5)) -#define RMT_IDLE_OUT_LV_CH2_M (BIT(5)) -#define RMT_IDLE_OUT_LV_CH2_V 0x1 -#define RMT_IDLE_OUT_LV_CH2_S 5 -/* RMT_MEM_TX_WRAP_EN_CH2 : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: This is the channel $n enable bit for wraparound mode: it will resume sending at - the start when the data to be sent is more than its memory size..*/ -#define RMT_MEM_TX_WRAP_EN_CH2 (BIT(4)) -#define RMT_MEM_TX_WRAP_EN_CH2_M (BIT(4)) -#define RMT_MEM_TX_WRAP_EN_CH2_V 0x1 -#define RMT_MEM_TX_WRAP_EN_CH2_S 4 -/* RMT_TX_CONTI_MODE_CH2 : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: Set this bit to restart transmission from the first data to the last data in CH -ANNEL$n..*/ -#define RMT_TX_CONTI_MODE_CH2 (BIT(3)) -#define RMT_TX_CONTI_MODE_CH2_M (BIT(3)) -#define RMT_TX_CONTI_MODE_CH2_V 0x1 -#define RMT_TX_CONTI_MODE_CH2_S 3 -/* RMT_APB_MEM_RST_CH2 : WT ;bitpos:[2] ;default: 1'b0 ; */ -/*description: Set this bit to reset W/R ram address for CHANNEL$n by accessing apb fifo..*/ -#define RMT_APB_MEM_RST_CH2 (BIT(2)) -#define RMT_APB_MEM_RST_CH2_M (BIT(2)) -#define RMT_APB_MEM_RST_CH2_V 0x1 -#define RMT_APB_MEM_RST_CH2_S 2 -/* RMT_MEM_RD_RST_CH2 : WT ;bitpos:[1] ;default: 1'b0 ; */ -/*description: Set this bit to reset read ram address for CHANNEL$n by accessing transmitter..*/ -#define RMT_MEM_RD_RST_CH2 (BIT(1)) -#define RMT_MEM_RD_RST_CH2_M (BIT(1)) -#define RMT_MEM_RD_RST_CH2_V 0x1 -#define RMT_MEM_RD_RST_CH2_S 1 -/* RMT_TX_START_CH2 : WT ;bitpos:[0] ;default: 1'h0 ; */ -/*description: Set this bit to start sending data on CHANNEL$n..*/ -#define RMT_TX_START_CH2 (BIT(0)) -#define RMT_TX_START_CH2_M (BIT(0)) -#define RMT_TX_START_CH2_V 0x1 -#define RMT_TX_START_CH2_S 0 +/** RMT_CH2CONF0_REG register + * Channel 2 configure register 0 + */ +#define RMT_CH2CONF0_REG (DR_REG_RMT_BASE + 0x28) +/** RMT_TX_START_2 : WT; bitpos: [0]; default: 0; + * Set this bit to start sending data on CHANNEL2. + */ +#define RMT_TX_START_2 (BIT(0)) +#define RMT_TX_START_2_M (RMT_TX_START_2_V << RMT_TX_START_2_S) +#define RMT_TX_START_2_V 0x00000001U +#define RMT_TX_START_2_S 0 +/** RMT_MEM_RD_RST_2 : WT; bitpos: [1]; default: 0; + * Set this bit to reset read ram address for CHANNEL2 by accessing transmitter. + */ +#define RMT_MEM_RD_RST_2 (BIT(1)) +#define RMT_MEM_RD_RST_2_M (RMT_MEM_RD_RST_2_V << RMT_MEM_RD_RST_2_S) +#define RMT_MEM_RD_RST_2_V 0x00000001U +#define RMT_MEM_RD_RST_2_S 1 +/** RMT_APB_MEM_RST_2 : WT; bitpos: [2]; default: 0; + * Set this bit to reset W/R ram address for CHANNEL2 by accessing apb fifo. + */ +#define RMT_APB_MEM_RST_2 (BIT(2)) +#define RMT_APB_MEM_RST_2_M (RMT_APB_MEM_RST_2_V << RMT_APB_MEM_RST_2_S) +#define RMT_APB_MEM_RST_2_V 0x00000001U +#define RMT_APB_MEM_RST_2_S 2 +/** RMT_TX_CONTI_MODE_2 : R/W; bitpos: [3]; default: 0; + * Set this bit to restart transmission from the first data to the last data in + * CHANNEL2. + */ +#define RMT_TX_CONTI_MODE_2 (BIT(3)) +#define RMT_TX_CONTI_MODE_2_M (RMT_TX_CONTI_MODE_2_V << RMT_TX_CONTI_MODE_2_S) +#define RMT_TX_CONTI_MODE_2_V 0x00000001U +#define RMT_TX_CONTI_MODE_2_S 3 +/** RMT_MEM_TX_WRAP_EN_2 : R/W; bitpos: [4]; default: 0; + * This is the channel 2 enable bit for wraparound mode: it will resume sending at the + * start when the data to be sent is more than its memory size. + */ +#define RMT_MEM_TX_WRAP_EN_2 (BIT(4)) +#define RMT_MEM_TX_WRAP_EN_2_M (RMT_MEM_TX_WRAP_EN_2_V << RMT_MEM_TX_WRAP_EN_2_S) +#define RMT_MEM_TX_WRAP_EN_2_V 0x00000001U +#define RMT_MEM_TX_WRAP_EN_2_S 4 +/** RMT_IDLE_OUT_LV_2 : R/W; bitpos: [5]; default: 0; + * This bit configures the level of output signal in CHANNEL2 when the latter is in + * IDLE state. + */ +#define RMT_IDLE_OUT_LV_2 (BIT(5)) +#define RMT_IDLE_OUT_LV_2_M (RMT_IDLE_OUT_LV_2_V << RMT_IDLE_OUT_LV_2_S) +#define RMT_IDLE_OUT_LV_2_V 0x00000001U +#define RMT_IDLE_OUT_LV_2_S 5 +/** RMT_IDLE_OUT_EN_2 : R/W; bitpos: [6]; default: 0; + * This is the output enable-control bit for CHANNEL2 in IDLE state. + */ +#define RMT_IDLE_OUT_EN_2 (BIT(6)) +#define RMT_IDLE_OUT_EN_2_M (RMT_IDLE_OUT_EN_2_V << RMT_IDLE_OUT_EN_2_S) +#define RMT_IDLE_OUT_EN_2_V 0x00000001U +#define RMT_IDLE_OUT_EN_2_S 6 +/** RMT_TX_STOP_2 : R/W/SC; bitpos: [7]; default: 0; + * Set this bit to stop the transmitter of CHANNEL2 sending data out. + */ +#define RMT_TX_STOP_2 (BIT(7)) +#define RMT_TX_STOP_2_M (RMT_TX_STOP_2_V << RMT_TX_STOP_2_S) +#define RMT_TX_STOP_2_V 0x00000001U +#define RMT_TX_STOP_2_S 7 +/** RMT_DIV_CNT_2 : R/W; bitpos: [15:8]; default: 2; + * This register is used to configure the divider for clock of CHANNEL2. + */ +#define RMT_DIV_CNT_2 0x000000FFU +#define RMT_DIV_CNT_2_M (RMT_DIV_CNT_2_V << RMT_DIV_CNT_2_S) +#define RMT_DIV_CNT_2_V 0x000000FFU +#define RMT_DIV_CNT_2_S 8 +/** RMT_MEM_SIZE_2 : R/W; bitpos: [19:16]; default: 1; + * This register is used to configure the maximum size of memory allocated to CHANNEL2. + */ +#define RMT_MEM_SIZE_2 0x0000000FU +#define RMT_MEM_SIZE_2_M (RMT_MEM_SIZE_2_V << RMT_MEM_SIZE_2_S) +#define RMT_MEM_SIZE_2_V 0x0000000FU +#define RMT_MEM_SIZE_2_S 16 +/** RMT_CARRIER_EFF_EN_2 : R/W; bitpos: [20]; default: 1; + * 1: Add carrier modulation on the output signal only at the send data state for + * CHANNEL2. 0: Add carrier modulation on the output signal at all state for CHANNEL2. + * Only valid when RMT_CARRIER_EN_CH2 is 1. + */ +#define RMT_CARRIER_EFF_EN_2 (BIT(20)) +#define RMT_CARRIER_EFF_EN_2_M (RMT_CARRIER_EFF_EN_2_V << RMT_CARRIER_EFF_EN_2_S) +#define RMT_CARRIER_EFF_EN_2_V 0x00000001U +#define RMT_CARRIER_EFF_EN_2_S 20 +/** RMT_CARRIER_EN_2 : R/W; bitpos: [21]; default: 1; + * This is the carrier modulation enable-control bit for CHANNEL2. 1: Add carrier + * modulation in the output signal. 0: No carrier modulation in sig_out. + */ +#define RMT_CARRIER_EN_2 (BIT(21)) +#define RMT_CARRIER_EN_2_M (RMT_CARRIER_EN_2_V << RMT_CARRIER_EN_2_S) +#define RMT_CARRIER_EN_2_V 0x00000001U +#define RMT_CARRIER_EN_2_S 21 +/** RMT_CARRIER_OUT_LV_2 : R/W; bitpos: [22]; default: 1; + * This bit is used to configure the position of carrier wave for CHANNEL2. + * + * 1'h0: add carrier wave on low level. + * + * 1'h1: add carrier wave on high level. + */ +#define RMT_CARRIER_OUT_LV_2 (BIT(22)) +#define RMT_CARRIER_OUT_LV_2_M (RMT_CARRIER_OUT_LV_2_V << RMT_CARRIER_OUT_LV_2_S) +#define RMT_CARRIER_OUT_LV_2_V 0x00000001U +#define RMT_CARRIER_OUT_LV_2_S 22 +/** RMT_AFIFO_RST_2 : WT; bitpos: [23]; default: 0; + * Reserved + */ +#define RMT_AFIFO_RST_2 (BIT(23)) +#define RMT_AFIFO_RST_2_M (RMT_AFIFO_RST_2_V << RMT_AFIFO_RST_2_S) +#define RMT_AFIFO_RST_2_V 0x00000001U +#define RMT_AFIFO_RST_2_S 23 +/** RMT_CONF_UPDATE_2 : WT; bitpos: [24]; default: 0; + * synchronization bit for CHANNEL2 + */ +#define RMT_CONF_UPDATE_2 (BIT(24)) +#define RMT_CONF_UPDATE_2_M (RMT_CONF_UPDATE_2_V << RMT_CONF_UPDATE_2_S) +#define RMT_CONF_UPDATE_2_V 0x00000001U +#define RMT_CONF_UPDATE_2_S 24 -#define RMT_CH3CONF0_REG (DR_REG_RMT_BASE + 0x2C) -/* RMT_DMA_ACCESS_EN_CH3 : R/W ;bitpos:[25] ;default: 1'b0 ; */ -/*description: This bit is used to enable the dma access function for CHANNEL$n..*/ -#define RMT_DMA_ACCESS_EN_CH3 (BIT(25)) -#define RMT_DMA_ACCESS_EN_CH3_M (BIT(25)) -#define RMT_DMA_ACCESS_EN_CH3_V 0x1 -#define RMT_DMA_ACCESS_EN_CH3_S 25 -/* RMT_CONF_UPDATE_CH3 : WT ;bitpos:[24] ;default: 1'b0 ; */ -/*description: synchronization bit for CHANNEL$n.*/ -#define RMT_CONF_UPDATE_CH3 (BIT(24)) -#define RMT_CONF_UPDATE_CH3_M (BIT(24)) -#define RMT_CONF_UPDATE_CH3_V 0x1 -#define RMT_CONF_UPDATE_CH3_S 24 -/* RMT_AFIFO_RST_CH3 : WT ;bitpos:[23] ;default: 1'b0 ; */ -/*description: Reserved.*/ -#define RMT_AFIFO_RST_CH3 (BIT(23)) -#define RMT_AFIFO_RST_CH3_M (BIT(23)) -#define RMT_AFIFO_RST_CH3_V 0x1 -#define RMT_AFIFO_RST_CH3_S 23 -/* RMT_CARRIER_OUT_LV_CH3 : R/W ;bitpos:[22] ;default: 1'b1 ; */ -/*description: This bit is used to configure the position of carrier wave for CHANNEL$n.; ; 1'h -0: add carrier wave on low level.; ; 1'h1: add carrier wave on high level..*/ -#define RMT_CARRIER_OUT_LV_CH3 (BIT(22)) -#define RMT_CARRIER_OUT_LV_CH3_M (BIT(22)) -#define RMT_CARRIER_OUT_LV_CH3_V 0x1 -#define RMT_CARRIER_OUT_LV_CH3_S 22 -/* RMT_CARRIER_EN_CH3 : R/W ;bitpos:[21] ;default: 1'b1 ; */ -/*description: This is the carrier modulation enable-control bit for CHANNEL$n. 1: Add carrier -modulation in the output signal. 0: No carrier modulation in sig_out..*/ -#define RMT_CARRIER_EN_CH3 (BIT(21)) -#define RMT_CARRIER_EN_CH3_M (BIT(21)) -#define RMT_CARRIER_EN_CH3_V 0x1 -#define RMT_CARRIER_EN_CH3_S 21 -/* RMT_CARRIER_EFF_EN_CH3 : R/W ;bitpos:[20] ;default: 1'b1 ; */ -/*description: 1: Add carrier modulation on the output signal only at the send data state for C -HANNEL$n. 0: Add carrier modulation on the output signal at all state for CHANNE -L$n. Only valid when RMT_CARRIER_EN_CH$n is 1..*/ -#define RMT_CARRIER_EFF_EN_CH3 (BIT(20)) -#define RMT_CARRIER_EFF_EN_CH3_M (BIT(20)) -#define RMT_CARRIER_EFF_EN_CH3_V 0x1 -#define RMT_CARRIER_EFF_EN_CH3_S 20 -/* RMT_MEM_SIZE_CH3 : R/W ;bitpos:[19:16] ;default: 4'h1 ; */ -/*description: This register is used to configure the maximum size of memory allocated to CHANN -EL$n..*/ -#define RMT_MEM_SIZE_CH3 0x0000000F -#define RMT_MEM_SIZE_CH3_M ((RMT_MEM_SIZE_CH3_V)<<(RMT_MEM_SIZE_CH3_S)) -#define RMT_MEM_SIZE_CH3_V 0xF -#define RMT_MEM_SIZE_CH3_S 16 -/* RMT_DIV_CNT_CH3 : R/W ;bitpos:[15:8] ;default: 8'h2 ; */ -/*description: This register is used to configure the divider for clock of CHANNEL$n..*/ -#define RMT_DIV_CNT_CH3 0x000000FF -#define RMT_DIV_CNT_CH3_M ((RMT_DIV_CNT_CH3_V)<<(RMT_DIV_CNT_CH3_S)) -#define RMT_DIV_CNT_CH3_V 0xFF -#define RMT_DIV_CNT_CH3_S 8 -/* RMT_TX_STOP_CH3 : R/W/SC ;bitpos:[7] ;default: 1'b0 ; */ -/*description: Set this bit to stop the transmitter of CHANNEL$n sending data out..*/ -#define RMT_TX_STOP_CH3 (BIT(7)) -#define RMT_TX_STOP_CH3_M (BIT(7)) -#define RMT_TX_STOP_CH3_V 0x1 -#define RMT_TX_STOP_CH3_S 7 -/* RMT_IDLE_OUT_EN_CH3 : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: This is the output enable-control bit for CHANNEL$n in IDLE state..*/ -#define RMT_IDLE_OUT_EN_CH3 (BIT(6)) -#define RMT_IDLE_OUT_EN_CH3_M (BIT(6)) -#define RMT_IDLE_OUT_EN_CH3_V 0x1 -#define RMT_IDLE_OUT_EN_CH3_S 6 -/* RMT_IDLE_OUT_LV_CH3 : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: This bit configures the level of output signal in CHANNEL$n when the latter is i -n IDLE state..*/ -#define RMT_IDLE_OUT_LV_CH3 (BIT(5)) -#define RMT_IDLE_OUT_LV_CH3_M (BIT(5)) -#define RMT_IDLE_OUT_LV_CH3_V 0x1 -#define RMT_IDLE_OUT_LV_CH3_S 5 -/* RMT_MEM_TX_WRAP_EN_CH3 : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: This is the channel $n enable bit for wraparound mode: it will resume sending at - the start when the data to be sent is more than its memory size..*/ -#define RMT_MEM_TX_WRAP_EN_CH3 (BIT(4)) -#define RMT_MEM_TX_WRAP_EN_CH3_M (BIT(4)) -#define RMT_MEM_TX_WRAP_EN_CH3_V 0x1 -#define RMT_MEM_TX_WRAP_EN_CH3_S 4 -/* RMT_TX_CONTI_MODE_CH3 : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: Set this bit to restart transmission from the first data to the last data in CH -ANNEL$n..*/ -#define RMT_TX_CONTI_MODE_CH3 (BIT(3)) -#define RMT_TX_CONTI_MODE_CH3_M (BIT(3)) -#define RMT_TX_CONTI_MODE_CH3_V 0x1 -#define RMT_TX_CONTI_MODE_CH3_S 3 -/* RMT_APB_MEM_RST_CH3 : WT ;bitpos:[2] ;default: 1'b0 ; */ -/*description: Set this bit to reset W/R ram address for CHANNEL$n by accessing apb fifo..*/ -#define RMT_APB_MEM_RST_CH3 (BIT(2)) -#define RMT_APB_MEM_RST_CH3_M (BIT(2)) -#define RMT_APB_MEM_RST_CH3_V 0x1 -#define RMT_APB_MEM_RST_CH3_S 2 -/* RMT_MEM_RD_RST_CH3 : WT ;bitpos:[1] ;default: 1'b0 ; */ -/*description: Set this bit to reset read ram address for CHANNEL$n by accessing transmitter..*/ -#define RMT_MEM_RD_RST_CH3 (BIT(1)) -#define RMT_MEM_RD_RST_CH3_M (BIT(1)) -#define RMT_MEM_RD_RST_CH3_V 0x1 -#define RMT_MEM_RD_RST_CH3_S 1 -/* RMT_TX_START_CH3 : WT ;bitpos:[0] ;default: 1'h0 ; */ -/*description: Set this bit to start sending data on CHANNEL$n..*/ -#define RMT_TX_START_CH3 (BIT(0)) -#define RMT_TX_START_CH3_M (BIT(0)) -#define RMT_TX_START_CH3_V 0x1 -#define RMT_TX_START_CH3_S 0 +/** RMT_CH3CONF0_REG register + * Channel 3 configure register 0 + */ +#define RMT_CH3CONF0_REG (DR_REG_RMT_BASE + 0x2c) +/** RMT_TX_START_3 : WT; bitpos: [0]; default: 0; + * Set this bit to start sending data on CHANNEL3. + */ +#define RMT_TX_START_3 (BIT(0)) +#define RMT_TX_START_3_M (RMT_TX_START_3_V << RMT_TX_START_3_S) +#define RMT_TX_START_3_V 0x00000001U +#define RMT_TX_START_3_S 0 +/** RMT_MEM_RD_RST_3 : WT; bitpos: [1]; default: 0; + * Set this bit to reset read ram address for CHANNEL3 by accessing transmitter. + */ +#define RMT_MEM_RD_RST_3 (BIT(1)) +#define RMT_MEM_RD_RST_3_M (RMT_MEM_RD_RST_3_V << RMT_MEM_RD_RST_3_S) +#define RMT_MEM_RD_RST_3_V 0x00000001U +#define RMT_MEM_RD_RST_3_S 1 +/** RMT_APB_MEM_RST_3 : WT; bitpos: [2]; default: 0; + * Set this bit to reset W/R ram address for CHANNEL3 by accessing apb fifo. + */ +#define RMT_APB_MEM_RST_3 (BIT(2)) +#define RMT_APB_MEM_RST_3_M (RMT_APB_MEM_RST_3_V << RMT_APB_MEM_RST_3_S) +#define RMT_APB_MEM_RST_3_V 0x00000001U +#define RMT_APB_MEM_RST_3_S 2 +/** RMT_TX_CONTI_MODE_3 : R/W; bitpos: [3]; default: 0; + * Set this bit to restart transmission from the first data to the last data in + * CHANNEL3. + */ +#define RMT_TX_CONTI_MODE_3 (BIT(3)) +#define RMT_TX_CONTI_MODE_3_M (RMT_TX_CONTI_MODE_3_V << RMT_TX_CONTI_MODE_3_S) +#define RMT_TX_CONTI_MODE_3_V 0x00000001U +#define RMT_TX_CONTI_MODE_3_S 3 +/** RMT_MEM_TX_WRAP_EN_3 : R/W; bitpos: [4]; default: 0; + * This is the channel 3 enable bit for wraparound mode: it will resume sending at the + * start when the data to be sent is more than its memory size. + */ +#define RMT_MEM_TX_WRAP_EN_3 (BIT(4)) +#define RMT_MEM_TX_WRAP_EN_3_M (RMT_MEM_TX_WRAP_EN_3_V << RMT_MEM_TX_WRAP_EN_3_S) +#define RMT_MEM_TX_WRAP_EN_3_V 0x00000001U +#define RMT_MEM_TX_WRAP_EN_3_S 4 +/** RMT_IDLE_OUT_LV_3 : R/W; bitpos: [5]; default: 0; + * This bit configures the level of output signal in CHANNEL3 when the latter is in + * IDLE state. + */ +#define RMT_IDLE_OUT_LV_3 (BIT(5)) +#define RMT_IDLE_OUT_LV_3_M (RMT_IDLE_OUT_LV_3_V << RMT_IDLE_OUT_LV_3_S) +#define RMT_IDLE_OUT_LV_3_V 0x00000001U +#define RMT_IDLE_OUT_LV_3_S 5 +/** RMT_IDLE_OUT_EN_3 : R/W; bitpos: [6]; default: 0; + * This is the output enable-control bit for CHANNEL3 in IDLE state. + */ +#define RMT_IDLE_OUT_EN_3 (BIT(6)) +#define RMT_IDLE_OUT_EN_3_M (RMT_IDLE_OUT_EN_3_V << RMT_IDLE_OUT_EN_3_S) +#define RMT_IDLE_OUT_EN_3_V 0x00000001U +#define RMT_IDLE_OUT_EN_3_S 6 +/** RMT_TX_STOP_3 : R/W/SC; bitpos: [7]; default: 0; + * Set this bit to stop the transmitter of CHANNEL3 sending data out. + */ +#define RMT_TX_STOP_3 (BIT(7)) +#define RMT_TX_STOP_3_M (RMT_TX_STOP_3_V << RMT_TX_STOP_3_S) +#define RMT_TX_STOP_3_V 0x00000001U +#define RMT_TX_STOP_3_S 7 +/** RMT_DIV_CNT_3 : R/W; bitpos: [15:8]; default: 2; + * This register is used to configure the divider for clock of CHANNEL3. + */ +#define RMT_DIV_CNT_3 0x000000FFU +#define RMT_DIV_CNT_3_M (RMT_DIV_CNT_3_V << RMT_DIV_CNT_3_S) +#define RMT_DIV_CNT_3_V 0x000000FFU +#define RMT_DIV_CNT_3_S 8 +/** RMT_MEM_SIZE_3 : R/W; bitpos: [19:16]; default: 1; + * This register is used to configure the maximum size of memory allocated to CHANNEL3. + */ +#define RMT_MEM_SIZE_3 0x0000000FU +#define RMT_MEM_SIZE_3_M (RMT_MEM_SIZE_3_V << RMT_MEM_SIZE_3_S) +#define RMT_MEM_SIZE_3_V 0x0000000FU +#define RMT_MEM_SIZE_3_S 16 +/** RMT_CARRIER_EFF_EN_3 : R/W; bitpos: [20]; default: 1; + * 1: Add carrier modulation on the output signal only at the send data state for + * CHANNEL3. 0: Add carrier modulation on the output signal at all state for CHANNEL3. + * Only valid when RMT_CARRIER_EN_CH3 is 1. + */ +#define RMT_CARRIER_EFF_EN_3 (BIT(20)) +#define RMT_CARRIER_EFF_EN_3_M (RMT_CARRIER_EFF_EN_3_V << RMT_CARRIER_EFF_EN_3_S) +#define RMT_CARRIER_EFF_EN_3_V 0x00000001U +#define RMT_CARRIER_EFF_EN_3_S 20 +/** RMT_CARRIER_EN_3 : R/W; bitpos: [21]; default: 1; + * This is the carrier modulation enable-control bit for CHANNEL3. 1: Add carrier + * modulation in the output signal. 0: No carrier modulation in sig_out. + */ +#define RMT_CARRIER_EN_3 (BIT(21)) +#define RMT_CARRIER_EN_3_M (RMT_CARRIER_EN_3_V << RMT_CARRIER_EN_3_S) +#define RMT_CARRIER_EN_3_V 0x00000001U +#define RMT_CARRIER_EN_3_S 21 +/** RMT_CARRIER_OUT_LV_3 : R/W; bitpos: [22]; default: 1; + * This bit is used to configure the position of carrier wave for CHANNEL3. + * + * 1'h0: add carrier wave on low level. + * + * 1'h1: add carrier wave on high level. + */ +#define RMT_CARRIER_OUT_LV_3 (BIT(22)) +#define RMT_CARRIER_OUT_LV_3_M (RMT_CARRIER_OUT_LV_3_V << RMT_CARRIER_OUT_LV_3_S) +#define RMT_CARRIER_OUT_LV_3_V 0x00000001U +#define RMT_CARRIER_OUT_LV_3_S 22 +/** RMT_AFIFO_RST_3 : WT; bitpos: [23]; default: 0; + * Reserved + */ +#define RMT_AFIFO_RST_3 (BIT(23)) +#define RMT_AFIFO_RST_3_M (RMT_AFIFO_RST_3_V << RMT_AFIFO_RST_3_S) +#define RMT_AFIFO_RST_3_V 0x00000001U +#define RMT_AFIFO_RST_3_S 23 +/** RMT_CONF_UPDATE_3 : WT; bitpos: [24]; default: 0; + * synchronization bit for CHANNEL3 + */ +#define RMT_CONF_UPDATE_3 (BIT(24)) +#define RMT_CONF_UPDATE_3_M (RMT_CONF_UPDATE_3_V << RMT_CONF_UPDATE_3_S) +#define RMT_CONF_UPDATE_3_V 0x00000001U +#define RMT_CONF_UPDATE_3_S 24 -#define RMT_CH4CONF0_REG (DR_REG_RMT_BASE + 0x30) -/* RMT_CARRIER_OUT_LV_CH4 : R/W ;bitpos:[29] ;default: 1'b1 ; */ -/*description: This bit is used to configure the position of carrier wave for CHANNEL$m.; ; 1'h -0: add carrier wave on low level.; ; 1'h1: add carrier wave on high level..*/ -#define RMT_CARRIER_OUT_LV_CH4 (BIT(29)) -#define RMT_CARRIER_OUT_LV_CH4_M (BIT(29)) -#define RMT_CARRIER_OUT_LV_CH4_V 0x1 -#define RMT_CARRIER_OUT_LV_CH4_S 29 -/* RMT_CARRIER_EN_CH4 : R/W ;bitpos:[28] ;default: 1'b1 ; */ -/*description: This is the carrier modulation enable-control bit for CHANNEL$m. 1: Add carrier -modulation in the output signal. 0: No carrier modulation in sig_out..*/ -#define RMT_CARRIER_EN_CH4 (BIT(28)) -#define RMT_CARRIER_EN_CH4_M (BIT(28)) -#define RMT_CARRIER_EN_CH4_V 0x1 -#define RMT_CARRIER_EN_CH4_S 28 -/* RMT_MEM_SIZE_CH4 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */ -/*description: This register is used to configure the maximum size of memory allocated to CHANN -EL$m..*/ -#define RMT_MEM_SIZE_CH4 0x0000000F -#define RMT_MEM_SIZE_CH4_M ((RMT_MEM_SIZE_CH4_V)<<(RMT_MEM_SIZE_CH4_S)) -#define RMT_MEM_SIZE_CH4_V 0xF -#define RMT_MEM_SIZE_CH4_S 24 -/* RMT_IDLE_THRES_CH4 : R/W ;bitpos:[22:8] ;default: 15'h7fff ; */ -/*description: When no edge is detected on the input signal and continuous clock cycles is long -er than this register value, received process is finished..*/ -#define RMT_IDLE_THRES_CH4 0x00007FFF -#define RMT_IDLE_THRES_CH4_M ((RMT_IDLE_THRES_CH4_V)<<(RMT_IDLE_THRES_CH4_S)) -#define RMT_IDLE_THRES_CH4_V 0x7FFF -#define RMT_IDLE_THRES_CH4_S 8 -/* RMT_DIV_CNT_CH4 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */ -/*description: This register is used to configure the divider for clock of CHANNEL$m..*/ -#define RMT_DIV_CNT_CH4 0x000000FF -#define RMT_DIV_CNT_CH4_M ((RMT_DIV_CNT_CH4_V)<<(RMT_DIV_CNT_CH4_S)) -#define RMT_DIV_CNT_CH4_V 0xFF -#define RMT_DIV_CNT_CH4_S 0 +/** RMT_CH4CONF0_REG register + * Channel 4 configure register 0 + */ +#define RMT_CH4CONF0_REG (DR_REG_RMT_BASE + 0x30) +/** RMT_DIV_CNT_4 : R/W; bitpos: [7:0]; default: 2; + * This register is used to configure the divider for clock of CHANNEL4. + */ +#define RMT_DIV_CNT_4 0x000000FFU +#define RMT_DIV_CNT_4_M (RMT_DIV_CNT_4_V << RMT_DIV_CNT_4_S) +#define RMT_DIV_CNT_4_V 0x000000FFU +#define RMT_DIV_CNT_4_S 0 +/** RMT_IDLE_THRES_4 : R/W; bitpos: [22:8]; default: 32767; + * When no edge is detected on the input signal and continuous clock cycles is longer + * than this register value, received process is finished. + */ +#define RMT_IDLE_THRES_4 0x00007FFFU +#define RMT_IDLE_THRES_4_M (RMT_IDLE_THRES_4_V << RMT_IDLE_THRES_4_S) +#define RMT_IDLE_THRES_4_V 0x00007FFFU +#define RMT_IDLE_THRES_4_S 8 +/** RMT_MEM_SIZE_4 : R/W; bitpos: [27:24]; default: 1; + * This register is used to configure the maximum size of memory allocated to CHANNEL4. + */ +#define RMT_MEM_SIZE_4 0x0000000FU +#define RMT_MEM_SIZE_4_M (RMT_MEM_SIZE_4_V << RMT_MEM_SIZE_4_S) +#define RMT_MEM_SIZE_4_V 0x0000000FU +#define RMT_MEM_SIZE_4_S 24 +/** RMT_CARRIER_EN_4 : R/W; bitpos: [28]; default: 1; + * This is the carrier modulation enable-control bit for CHANNEL4. 1: Add carrier + * modulation in the output signal. 0: No carrier modulation in sig_out. + */ +#define RMT_CARRIER_EN_4 (BIT(28)) +#define RMT_CARRIER_EN_4_M (RMT_CARRIER_EN_4_V << RMT_CARRIER_EN_4_S) +#define RMT_CARRIER_EN_4_V 0x00000001U +#define RMT_CARRIER_EN_4_S 28 +/** RMT_CARRIER_OUT_LV_4 : R/W; bitpos: [29]; default: 1; + * This bit is used to configure the position of carrier wave for CHANNEL4. + * + * 1'h0: add carrier wave on low level. + * + * 1'h1: add carrier wave on high level. + */ +#define RMT_CARRIER_OUT_LV_4 (BIT(29)) +#define RMT_CARRIER_OUT_LV_4_M (RMT_CARRIER_OUT_LV_4_V << RMT_CARRIER_OUT_LV_4_S) +#define RMT_CARRIER_OUT_LV_4_V 0x00000001U +#define RMT_CARRIER_OUT_LV_4_S 29 -#define RMT_CH4CONF1_REG (DR_REG_RMT_BASE + 0x34) -/* RMT_CONF_UPDATE_CH4 : WT ;bitpos:[15] ;default: 1'b0 ; */ -/*description: synchronization bit for CHANNEL$m.*/ -#define RMT_CONF_UPDATE_CH4 (BIT(15)) -#define RMT_CONF_UPDATE_CH4_M (BIT(15)) -#define RMT_CONF_UPDATE_CH4_V 0x1 -#define RMT_CONF_UPDATE_CH4_S 15 -/* RMT_AFIFO_RST_CH4 : WT ;bitpos:[14] ;default: 1'b0 ; */ -/*description: Reserved.*/ -#define RMT_AFIFO_RST_CH4 (BIT(14)) -#define RMT_AFIFO_RST_CH4_M (BIT(14)) -#define RMT_AFIFO_RST_CH4_V 0x1 -#define RMT_AFIFO_RST_CH4_S 14 -/* RMT_MEM_RX_WRAP_EN_CH4 : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: This is the channel $m enable bit for wraparound mode: it will resume receiving -at the start when the data to be received is more than its memory size..*/ -#define RMT_MEM_RX_WRAP_EN_CH4 (BIT(13)) -#define RMT_MEM_RX_WRAP_EN_CH4_M (BIT(13)) -#define RMT_MEM_RX_WRAP_EN_CH4_V 0x1 -#define RMT_MEM_RX_WRAP_EN_CH4_S 13 -/* RMT_RX_FILTER_THRES_CH4 : R/W ;bitpos:[12:5] ;default: 8'hf ; */ -/*description: Ignores the input pulse when its width is smaller than this register value in AP -B clock periods (in receive mode)..*/ -#define RMT_RX_FILTER_THRES_CH4 0x000000FF -#define RMT_RX_FILTER_THRES_CH4_M ((RMT_RX_FILTER_THRES_CH4_V)<<(RMT_RX_FILTER_THRES_CH4_S)) -#define RMT_RX_FILTER_THRES_CH4_V 0xFF -#define RMT_RX_FILTER_THRES_CH4_S 5 -/* RMT_RX_FILTER_EN_CH4 : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: This is the receive filter's enable bit for CHANNEL$m..*/ -#define RMT_RX_FILTER_EN_CH4 (BIT(4)) -#define RMT_RX_FILTER_EN_CH4_M (BIT(4)) -#define RMT_RX_FILTER_EN_CH4_V 0x1 -#define RMT_RX_FILTER_EN_CH4_S 4 -/* RMT_MEM_OWNER_CH4 : R/W/SC ;bitpos:[3] ;default: 1'b1 ; */ -/*description: This register marks the ownership of CHANNEL$m's ram block.; ; 1'h1: Receiver is - using the ram. ; ; 1'h0: APB bus is using the ram..*/ -#define RMT_MEM_OWNER_CH4 (BIT(3)) -#define RMT_MEM_OWNER_CH4_M (BIT(3)) -#define RMT_MEM_OWNER_CH4_V 0x1 -#define RMT_MEM_OWNER_CH4_S 3 -/* RMT_APB_MEM_RST_CH4 : WT ;bitpos:[2] ;default: 1'b0 ; */ -/*description: Set this bit to reset W/R ram address for CHANNEL$m by accessing apb fifo..*/ -#define RMT_APB_MEM_RST_CH4 (BIT(2)) -#define RMT_APB_MEM_RST_CH4_M (BIT(2)) -#define RMT_APB_MEM_RST_CH4_V 0x1 -#define RMT_APB_MEM_RST_CH4_S 2 -/* RMT_MEM_WR_RST_CH4 : WT ;bitpos:[1] ;default: 1'h0 ; */ -/*description: Set this bit to reset write ram address for CHANNEL$m by accessing receiver..*/ -#define RMT_MEM_WR_RST_CH4 (BIT(1)) -#define RMT_MEM_WR_RST_CH4_M (BIT(1)) -#define RMT_MEM_WR_RST_CH4_V 0x1 -#define RMT_MEM_WR_RST_CH4_S 1 -/* RMT_RX_EN_CH4 : R/W ;bitpos:[0] ;default: 1'h0 ; */ -/*description: Set this bit to enable receiver to receive data on CHANNEL$m..*/ -#define RMT_RX_EN_CH4 (BIT(0)) -#define RMT_RX_EN_CH4_M (BIT(0)) -#define RMT_RX_EN_CH4_V 0x1 -#define RMT_RX_EN_CH4_S 0 +/** RMT_CH4CONF1_REG register + * Channel 4 configure register 1 + */ +#define RMT_CH4CONF1_REG (DR_REG_RMT_BASE + 0x34) +/** RMT_RX_EN_4 : R/W; bitpos: [0]; default: 0; + * Set this bit to enable receiver to receive data on CHANNEL4. + */ +#define RMT_RX_EN_4 (BIT(0)) +#define RMT_RX_EN_4_M (RMT_RX_EN_4_V << RMT_RX_EN_4_S) +#define RMT_RX_EN_4_V 0x00000001U +#define RMT_RX_EN_4_S 0 +/** RMT_MEM_WR_RST_4 : WT; bitpos: [1]; default: 0; + * Set this bit to reset write ram address for CHANNEL4 by accessing receiver. + */ +#define RMT_MEM_WR_RST_4 (BIT(1)) +#define RMT_MEM_WR_RST_4_M (RMT_MEM_WR_RST_4_V << RMT_MEM_WR_RST_4_S) +#define RMT_MEM_WR_RST_4_V 0x00000001U +#define RMT_MEM_WR_RST_4_S 1 +/** RMT_APB_MEM_RST_4 : WT; bitpos: [2]; default: 0; + * Set this bit to reset W/R ram address for CHANNEL4 by accessing apb fifo. + */ +#define RMT_APB_MEM_RST_4 (BIT(2)) +#define RMT_APB_MEM_RST_4_M (RMT_APB_MEM_RST_4_V << RMT_APB_MEM_RST_4_S) +#define RMT_APB_MEM_RST_4_V 0x00000001U +#define RMT_APB_MEM_RST_4_S 2 +/** RMT_MEM_OWNER_4 : R/W/SC; bitpos: [3]; default: 1; + * This register marks the ownership of CHANNEL4's ram block. + * + * 1'h1: Receiver is using the ram. + * + * 1'h0: APB bus is using the ram. + */ +#define RMT_MEM_OWNER_4 (BIT(3)) +#define RMT_MEM_OWNER_4_M (RMT_MEM_OWNER_4_V << RMT_MEM_OWNER_4_S) +#define RMT_MEM_OWNER_4_V 0x00000001U +#define RMT_MEM_OWNER_4_S 3 +/** RMT_RX_FILTER_EN_4 : R/W; bitpos: [4]; default: 0; + * This is the receive filter's enable bit for CHANNEL4. + */ +#define RMT_RX_FILTER_EN_4 (BIT(4)) +#define RMT_RX_FILTER_EN_4_M (RMT_RX_FILTER_EN_4_V << RMT_RX_FILTER_EN_4_S) +#define RMT_RX_FILTER_EN_4_V 0x00000001U +#define RMT_RX_FILTER_EN_4_S 4 +/** RMT_RX_FILTER_THRES_4 : R/W; bitpos: [12:5]; default: 15; + * Ignores the input pulse when its width is smaller than this register value in APB + * clock periods (in receive mode). + */ +#define RMT_RX_FILTER_THRES_4 0x000000FFU +#define RMT_RX_FILTER_THRES_4_M (RMT_RX_FILTER_THRES_4_V << RMT_RX_FILTER_THRES_4_S) +#define RMT_RX_FILTER_THRES_4_V 0x000000FFU +#define RMT_RX_FILTER_THRES_4_S 5 +/** RMT_MEM_RX_WRAP_EN_4 : R/W; bitpos: [13]; default: 0; + * This is the channel 4 enable bit for wraparound mode: it will resume receiving at + * the start when the data to be received is more than its memory size. + */ +#define RMT_MEM_RX_WRAP_EN_4 (BIT(13)) +#define RMT_MEM_RX_WRAP_EN_4_M (RMT_MEM_RX_WRAP_EN_4_V << RMT_MEM_RX_WRAP_EN_4_S) +#define RMT_MEM_RX_WRAP_EN_4_V 0x00000001U +#define RMT_MEM_RX_WRAP_EN_4_S 13 +/** RMT_AFIFO_RST_4 : WT; bitpos: [14]; default: 0; + * Reserved + */ +#define RMT_AFIFO_RST_4 (BIT(14)) +#define RMT_AFIFO_RST_4_M (RMT_AFIFO_RST_4_V << RMT_AFIFO_RST_4_S) +#define RMT_AFIFO_RST_4_V 0x00000001U +#define RMT_AFIFO_RST_4_S 14 +/** RMT_CONF_UPDATE_4 : WT; bitpos: [15]; default: 0; + * synchronization bit for CHANNEL4 + */ +#define RMT_CONF_UPDATE_4 (BIT(15)) +#define RMT_CONF_UPDATE_4_M (RMT_CONF_UPDATE_4_V << RMT_CONF_UPDATE_4_S) +#define RMT_CONF_UPDATE_4_V 0x00000001U +#define RMT_CONF_UPDATE_4_S 15 -#define RMT_CH5CONF0_REG (DR_REG_RMT_BASE + 0x38) -/* RMT_CARRIER_OUT_LV_CH5 : R/W ;bitpos:[29] ;default: 1'b1 ; */ -/*description: This bit is used to configure the position of carrier wave for CHANNEL$m.; ; 1'h -0: add carrier wave on low level.; ; 1'h1: add carrier wave on high level..*/ -#define RMT_CARRIER_OUT_LV_CH5 (BIT(29)) -#define RMT_CARRIER_OUT_LV_CH5_M (BIT(29)) -#define RMT_CARRIER_OUT_LV_CH5_V 0x1 -#define RMT_CARRIER_OUT_LV_CH5_S 29 -/* RMT_CARRIER_EN_CH5 : R/W ;bitpos:[28] ;default: 1'b1 ; */ -/*description: This is the carrier modulation enable-control bit for CHANNEL$m. 1: Add carrier -modulation in the output signal. 0: No carrier modulation in sig_out..*/ -#define RMT_CARRIER_EN_CH5 (BIT(28)) -#define RMT_CARRIER_EN_CH5_M (BIT(28)) -#define RMT_CARRIER_EN_CH5_V 0x1 -#define RMT_CARRIER_EN_CH5_S 28 -/* RMT_MEM_SIZE_CH5 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */ -/*description: This register is used to configure the maximum size of memory allocated to CHANN -EL$m..*/ -#define RMT_MEM_SIZE_CH5 0x0000000F -#define RMT_MEM_SIZE_CH5_M ((RMT_MEM_SIZE_CH5_V)<<(RMT_MEM_SIZE_CH5_S)) -#define RMT_MEM_SIZE_CH5_V 0xF -#define RMT_MEM_SIZE_CH5_S 24 -/* RMT_IDLE_THRES_CH5 : R/W ;bitpos:[22:8] ;default: 15'h7fff ; */ -/*description: When no edge is detected on the input signal and continuous clock cycles is long -er than this register value, received process is finished..*/ -#define RMT_IDLE_THRES_CH5 0x00007FFF -#define RMT_IDLE_THRES_CH5_M ((RMT_IDLE_THRES_CH5_V)<<(RMT_IDLE_THRES_CH5_S)) -#define RMT_IDLE_THRES_CH5_V 0x7FFF -#define RMT_IDLE_THRES_CH5_S 8 -/* RMT_DIV_CNT_CH5 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */ -/*description: This register is used to configure the divider for clock of CHANNEL$m..*/ -#define RMT_DIV_CNT_CH5 0x000000FF -#define RMT_DIV_CNT_CH5_M ((RMT_DIV_CNT_CH5_V)<<(RMT_DIV_CNT_CH5_S)) -#define RMT_DIV_CNT_CH5_V 0xFF -#define RMT_DIV_CNT_CH5_S 0 +/** RMT_CH5CONF0_REG register + * Channel 5 configure register 0 + */ +#define RMT_CH5CONF0_REG (DR_REG_RMT_BASE + 0x38) +/** RMT_DIV_CNT_5 : R/W; bitpos: [7:0]; default: 2; + * This register is used to configure the divider for clock of CHANNEL5. + */ +#define RMT_DIV_CNT_5 0x000000FFU +#define RMT_DIV_CNT_5_M (RMT_DIV_CNT_5_V << RMT_DIV_CNT_5_S) +#define RMT_DIV_CNT_5_V 0x000000FFU +#define RMT_DIV_CNT_5_S 0 +/** RMT_IDLE_THRES_5 : R/W; bitpos: [22:8]; default: 32767; + * When no edge is detected on the input signal and continuous clock cycles is longer + * than this register value, received process is finished. + */ +#define RMT_IDLE_THRES_5 0x00007FFFU +#define RMT_IDLE_THRES_5_M (RMT_IDLE_THRES_5_V << RMT_IDLE_THRES_5_S) +#define RMT_IDLE_THRES_5_V 0x00007FFFU +#define RMT_IDLE_THRES_5_S 8 +/** RMT_MEM_SIZE_5 : R/W; bitpos: [27:24]; default: 1; + * This register is used to configure the maximum size of memory allocated to CHANNEL5. + */ +#define RMT_MEM_SIZE_5 0x0000000FU +#define RMT_MEM_SIZE_5_M (RMT_MEM_SIZE_5_V << RMT_MEM_SIZE_5_S) +#define RMT_MEM_SIZE_5_V 0x0000000FU +#define RMT_MEM_SIZE_5_S 24 +/** RMT_CARRIER_EN_5 : R/W; bitpos: [28]; default: 1; + * This is the carrier modulation enable-control bit for CHANNEL5. 1: Add carrier + * modulation in the output signal. 0: No carrier modulation in sig_out. + */ +#define RMT_CARRIER_EN_5 (BIT(28)) +#define RMT_CARRIER_EN_5_M (RMT_CARRIER_EN_5_V << RMT_CARRIER_EN_5_S) +#define RMT_CARRIER_EN_5_V 0x00000001U +#define RMT_CARRIER_EN_5_S 28 +/** RMT_CARRIER_OUT_LV_5 : R/W; bitpos: [29]; default: 1; + * This bit is used to configure the position of carrier wave for CHANNEL5. + * + * 1'h0: add carrier wave on low level. + * + * 1'h1: add carrier wave on high level. + */ +#define RMT_CARRIER_OUT_LV_5 (BIT(29)) +#define RMT_CARRIER_OUT_LV_5_M (RMT_CARRIER_OUT_LV_5_V << RMT_CARRIER_OUT_LV_5_S) +#define RMT_CARRIER_OUT_LV_5_V 0x00000001U +#define RMT_CARRIER_OUT_LV_5_S 29 -#define RMT_CH5CONF1_REG (DR_REG_RMT_BASE + 0x3C) -/* RMT_CONF_UPDATE_CH5 : WT ;bitpos:[15] ;default: 1'b0 ; */ -/*description: synchronization bit for CHANNEL$m.*/ -#define RMT_CONF_UPDATE_CH5 (BIT(15)) -#define RMT_CONF_UPDATE_CH5_M (BIT(15)) -#define RMT_CONF_UPDATE_CH5_V 0x1 -#define RMT_CONF_UPDATE_CH5_S 15 -/* RMT_AFIFO_RST_CH5 : WT ;bitpos:[14] ;default: 1'b0 ; */ -/*description: Reserved.*/ -#define RMT_AFIFO_RST_CH5 (BIT(14)) -#define RMT_AFIFO_RST_CH5_M (BIT(14)) -#define RMT_AFIFO_RST_CH5_V 0x1 -#define RMT_AFIFO_RST_CH5_S 14 -/* RMT_MEM_RX_WRAP_EN_CH5 : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: This is the channel $m enable bit for wraparound mode: it will resume receiving -at the start when the data to be received is more than its memory size..*/ -#define RMT_MEM_RX_WRAP_EN_CH5 (BIT(13)) -#define RMT_MEM_RX_WRAP_EN_CH5_M (BIT(13)) -#define RMT_MEM_RX_WRAP_EN_CH5_V 0x1 -#define RMT_MEM_RX_WRAP_EN_CH5_S 13 -/* RMT_RX_FILTER_THRES_CH5 : R/W ;bitpos:[12:5] ;default: 8'hf ; */ -/*description: Ignores the input pulse when its width is smaller than this register value in AP -B clock periods (in receive mode)..*/ -#define RMT_RX_FILTER_THRES_CH5 0x000000FF -#define RMT_RX_FILTER_THRES_CH5_M ((RMT_RX_FILTER_THRES_CH5_V)<<(RMT_RX_FILTER_THRES_CH5_S)) -#define RMT_RX_FILTER_THRES_CH5_V 0xFF -#define RMT_RX_FILTER_THRES_CH5_S 5 -/* RMT_RX_FILTER_EN_CH5 : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: This is the receive filter's enable bit for CHANNEL$m..*/ -#define RMT_RX_FILTER_EN_CH5 (BIT(4)) -#define RMT_RX_FILTER_EN_CH5_M (BIT(4)) -#define RMT_RX_FILTER_EN_CH5_V 0x1 -#define RMT_RX_FILTER_EN_CH5_S 4 -/* RMT_MEM_OWNER_CH5 : R/W/SC ;bitpos:[3] ;default: 1'b1 ; */ -/*description: This register marks the ownership of CHANNEL$m's ram block.; ; 1'h1: Receiver is - using the ram. ; ; 1'h0: APB bus is using the ram..*/ -#define RMT_MEM_OWNER_CH5 (BIT(3)) -#define RMT_MEM_OWNER_CH5_M (BIT(3)) -#define RMT_MEM_OWNER_CH5_V 0x1 -#define RMT_MEM_OWNER_CH5_S 3 -/* RMT_APB_MEM_RST_CH5 : WT ;bitpos:[2] ;default: 1'b0 ; */ -/*description: Set this bit to reset W/R ram address for CHANNEL$m by accessing apb fifo..*/ -#define RMT_APB_MEM_RST_CH5 (BIT(2)) -#define RMT_APB_MEM_RST_CH5_M (BIT(2)) -#define RMT_APB_MEM_RST_CH5_V 0x1 -#define RMT_APB_MEM_RST_CH5_S 2 -/* RMT_MEM_WR_RST_CH5 : WT ;bitpos:[1] ;default: 1'h0 ; */ -/*description: Set this bit to reset write ram address for CHANNEL$m by accessing receiver..*/ -#define RMT_MEM_WR_RST_CH5 (BIT(1)) -#define RMT_MEM_WR_RST_CH5_M (BIT(1)) -#define RMT_MEM_WR_RST_CH5_V 0x1 -#define RMT_MEM_WR_RST_CH5_S 1 -/* RMT_RX_EN_CH5 : R/W ;bitpos:[0] ;default: 1'h0 ; */ -/*description: Set this bit to enable receiver to receive data on CHANNEL$m..*/ -#define RMT_RX_EN_CH5 (BIT(0)) -#define RMT_RX_EN_CH5_M (BIT(0)) -#define RMT_RX_EN_CH5_V 0x1 -#define RMT_RX_EN_CH5_S 0 +/** RMT_CH5CONF1_REG register + * Channel 5 configure register 1 + */ +#define RMT_CH5CONF1_REG (DR_REG_RMT_BASE + 0x3c) +/** RMT_RX_EN_5 : R/W; bitpos: [0]; default: 0; + * Set this bit to enable receiver to receive data on CHANNEL5. + */ +#define RMT_RX_EN_5 (BIT(0)) +#define RMT_RX_EN_5_M (RMT_RX_EN_5_V << RMT_RX_EN_5_S) +#define RMT_RX_EN_5_V 0x00000001U +#define RMT_RX_EN_5_S 0 +/** RMT_MEM_WR_RST_5 : WT; bitpos: [1]; default: 0; + * Set this bit to reset write ram address for CHANNEL5 by accessing receiver. + */ +#define RMT_MEM_WR_RST_5 (BIT(1)) +#define RMT_MEM_WR_RST_5_M (RMT_MEM_WR_RST_5_V << RMT_MEM_WR_RST_5_S) +#define RMT_MEM_WR_RST_5_V 0x00000001U +#define RMT_MEM_WR_RST_5_S 1 +/** RMT_APB_MEM_RST_5 : WT; bitpos: [2]; default: 0; + * Set this bit to reset W/R ram address for CHANNEL5 by accessing apb fifo. + */ +#define RMT_APB_MEM_RST_5 (BIT(2)) +#define RMT_APB_MEM_RST_5_M (RMT_APB_MEM_RST_5_V << RMT_APB_MEM_RST_5_S) +#define RMT_APB_MEM_RST_5_V 0x00000001U +#define RMT_APB_MEM_RST_5_S 2 +/** RMT_MEM_OWNER_5 : R/W/SC; bitpos: [3]; default: 1; + * This register marks the ownership of CHANNEL5's ram block. + * + * 1'h1: Receiver is using the ram. + * + * 1'h0: APB bus is using the ram. + */ +#define RMT_MEM_OWNER_5 (BIT(3)) +#define RMT_MEM_OWNER_5_M (RMT_MEM_OWNER_5_V << RMT_MEM_OWNER_5_S) +#define RMT_MEM_OWNER_5_V 0x00000001U +#define RMT_MEM_OWNER_5_S 3 +/** RMT_RX_FILTER_EN_5 : R/W; bitpos: [4]; default: 0; + * This is the receive filter's enable bit for CHANNEL5. + */ +#define RMT_RX_FILTER_EN_5 (BIT(4)) +#define RMT_RX_FILTER_EN_5_M (RMT_RX_FILTER_EN_5_V << RMT_RX_FILTER_EN_5_S) +#define RMT_RX_FILTER_EN_5_V 0x00000001U +#define RMT_RX_FILTER_EN_5_S 4 +/** RMT_RX_FILTER_THRES_5 : R/W; bitpos: [12:5]; default: 15; + * Ignores the input pulse when its width is smaller than this register value in APB + * clock periods (in receive mode). + */ +#define RMT_RX_FILTER_THRES_5 0x000000FFU +#define RMT_RX_FILTER_THRES_5_M (RMT_RX_FILTER_THRES_5_V << RMT_RX_FILTER_THRES_5_S) +#define RMT_RX_FILTER_THRES_5_V 0x000000FFU +#define RMT_RX_FILTER_THRES_5_S 5 +/** RMT_MEM_RX_WRAP_EN_5 : R/W; bitpos: [13]; default: 0; + * This is the channel 5 enable bit for wraparound mode: it will resume receiving at + * the start when the data to be received is more than its memory size. + */ +#define RMT_MEM_RX_WRAP_EN_5 (BIT(13)) +#define RMT_MEM_RX_WRAP_EN_5_M (RMT_MEM_RX_WRAP_EN_5_V << RMT_MEM_RX_WRAP_EN_5_S) +#define RMT_MEM_RX_WRAP_EN_5_V 0x00000001U +#define RMT_MEM_RX_WRAP_EN_5_S 13 +/** RMT_AFIFO_RST_5 : WT; bitpos: [14]; default: 0; + * Reserved + */ +#define RMT_AFIFO_RST_5 (BIT(14)) +#define RMT_AFIFO_RST_5_M (RMT_AFIFO_RST_5_V << RMT_AFIFO_RST_5_S) +#define RMT_AFIFO_RST_5_V 0x00000001U +#define RMT_AFIFO_RST_5_S 14 +/** RMT_CONF_UPDATE_5 : WT; bitpos: [15]; default: 0; + * synchronization bit for CHANNEL5 + */ +#define RMT_CONF_UPDATE_5 (BIT(15)) +#define RMT_CONF_UPDATE_5_M (RMT_CONF_UPDATE_5_V << RMT_CONF_UPDATE_5_S) +#define RMT_CONF_UPDATE_5_V 0x00000001U +#define RMT_CONF_UPDATE_5_S 15 -#define RMT_CH6CONF0_REG (DR_REG_RMT_BASE + 0x40) -/* RMT_CARRIER_OUT_LV_CH6 : R/W ;bitpos:[29] ;default: 1'b1 ; */ -/*description: This bit is used to configure the position of carrier wave for CHANNEL$m.; ; 1'h -0: add carrier wave on low level.; ; 1'h1: add carrier wave on high level..*/ -#define RMT_CARRIER_OUT_LV_CH6 (BIT(29)) -#define RMT_CARRIER_OUT_LV_CH6_M (BIT(29)) -#define RMT_CARRIER_OUT_LV_CH6_V 0x1 -#define RMT_CARRIER_OUT_LV_CH6_S 29 -/* RMT_CARRIER_EN_CH6 : R/W ;bitpos:[28] ;default: 1'b1 ; */ -/*description: This is the carrier modulation enable-control bit for CHANNEL$m. 1: Add carrier -modulation in the output signal. 0: No carrier modulation in sig_out..*/ -#define RMT_CARRIER_EN_CH6 (BIT(28)) -#define RMT_CARRIER_EN_CH6_M (BIT(28)) -#define RMT_CARRIER_EN_CH6_V 0x1 -#define RMT_CARRIER_EN_CH6_S 28 -/* RMT_MEM_SIZE_CH6 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */ -/*description: This register is used to configure the maximum size of memory allocated to CHANN -EL$m..*/ -#define RMT_MEM_SIZE_CH6 0x0000000F -#define RMT_MEM_SIZE_CH6_M ((RMT_MEM_SIZE_CH6_V)<<(RMT_MEM_SIZE_CH6_S)) -#define RMT_MEM_SIZE_CH6_V 0xF -#define RMT_MEM_SIZE_CH6_S 24 -/* RMT_IDLE_THRES_CH6 : R/W ;bitpos:[22:8] ;default: 15'h7fff ; */ -/*description: When no edge is detected on the input signal and continuous clock cycles is long -er than this register value, received process is finished..*/ -#define RMT_IDLE_THRES_CH6 0x00007FFF -#define RMT_IDLE_THRES_CH6_M ((RMT_IDLE_THRES_CH6_V)<<(RMT_IDLE_THRES_CH6_S)) -#define RMT_IDLE_THRES_CH6_V 0x7FFF -#define RMT_IDLE_THRES_CH6_S 8 -/* RMT_DIV_CNT_CH6 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */ -/*description: This register is used to configure the divider for clock of CHANNEL$m..*/ -#define RMT_DIV_CNT_CH6 0x000000FF -#define RMT_DIV_CNT_CH6_M ((RMT_DIV_CNT_CH6_V)<<(RMT_DIV_CNT_CH6_S)) -#define RMT_DIV_CNT_CH6_V 0xFF -#define RMT_DIV_CNT_CH6_S 0 +/** RMT_CH6CONF0_REG register + * Channel 6 configure register 0 + */ +#define RMT_CH6CONF0_REG (DR_REG_RMT_BASE + 0x40) +/** RMT_DIV_CNT_6 : R/W; bitpos: [7:0]; default: 2; + * This register is used to configure the divider for clock of CHANNEL6. + */ +#define RMT_DIV_CNT_6 0x000000FFU +#define RMT_DIV_CNT_6_M (RMT_DIV_CNT_6_V << RMT_DIV_CNT_6_S) +#define RMT_DIV_CNT_6_V 0x000000FFU +#define RMT_DIV_CNT_6_S 0 +/** RMT_IDLE_THRES_6 : R/W; bitpos: [22:8]; default: 32767; + * When no edge is detected on the input signal and continuous clock cycles is longer + * than this register value, received process is finished. + */ +#define RMT_IDLE_THRES_6 0x00007FFFU +#define RMT_IDLE_THRES_6_M (RMT_IDLE_THRES_6_V << RMT_IDLE_THRES_6_S) +#define RMT_IDLE_THRES_6_V 0x00007FFFU +#define RMT_IDLE_THRES_6_S 8 +/** RMT_MEM_SIZE_6 : R/W; bitpos: [27:24]; default: 1; + * This register is used to configure the maximum size of memory allocated to CHANNEL6. + */ +#define RMT_MEM_SIZE_6 0x0000000FU +#define RMT_MEM_SIZE_6_M (RMT_MEM_SIZE_6_V << RMT_MEM_SIZE_6_S) +#define RMT_MEM_SIZE_6_V 0x0000000FU +#define RMT_MEM_SIZE_6_S 24 +/** RMT_CARRIER_EN_6 : R/W; bitpos: [28]; default: 1; + * This is the carrier modulation enable-control bit for CHANNEL6. 1: Add carrier + * modulation in the output signal. 0: No carrier modulation in sig_out. + */ +#define RMT_CARRIER_EN_6 (BIT(28)) +#define RMT_CARRIER_EN_6_M (RMT_CARRIER_EN_6_V << RMT_CARRIER_EN_6_S) +#define RMT_CARRIER_EN_6_V 0x00000001U +#define RMT_CARRIER_EN_6_S 28 +/** RMT_CARRIER_OUT_LV_6 : R/W; bitpos: [29]; default: 1; + * This bit is used to configure the position of carrier wave for CHANNEL6. + * + * 1'h0: add carrier wave on low level. + * + * 1'h1: add carrier wave on high level. + */ +#define RMT_CARRIER_OUT_LV_6 (BIT(29)) +#define RMT_CARRIER_OUT_LV_6_M (RMT_CARRIER_OUT_LV_6_V << RMT_CARRIER_OUT_LV_6_S) +#define RMT_CARRIER_OUT_LV_6_V 0x00000001U +#define RMT_CARRIER_OUT_LV_6_S 29 -#define RMT_CH6CONF1_REG (DR_REG_RMT_BASE + 0x44) -/* RMT_CONF_UPDATE_CH6 : WT ;bitpos:[15] ;default: 1'b0 ; */ -/*description: synchronization bit for CHANNEL$m.*/ -#define RMT_CONF_UPDATE_CH6 (BIT(15)) -#define RMT_CONF_UPDATE_CH6_M (BIT(15)) -#define RMT_CONF_UPDATE_CH6_V 0x1 -#define RMT_CONF_UPDATE_CH6_S 15 -/* RMT_AFIFO_RST_CH6 : WT ;bitpos:[14] ;default: 1'b0 ; */ -/*description: Reserved.*/ -#define RMT_AFIFO_RST_CH6 (BIT(14)) -#define RMT_AFIFO_RST_CH6_M (BIT(14)) -#define RMT_AFIFO_RST_CH6_V 0x1 -#define RMT_AFIFO_RST_CH6_S 14 -/* RMT_MEM_RX_WRAP_EN_CH6 : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: This is the channel $m enable bit for wraparound mode: it will resume receiving -at the start when the data to be received is more than its memory size..*/ -#define RMT_MEM_RX_WRAP_EN_CH6 (BIT(13)) -#define RMT_MEM_RX_WRAP_EN_CH6_M (BIT(13)) -#define RMT_MEM_RX_WRAP_EN_CH6_V 0x1 -#define RMT_MEM_RX_WRAP_EN_CH6_S 13 -/* RMT_RX_FILTER_THRES_CH6 : R/W ;bitpos:[12:5] ;default: 8'hf ; */ -/*description: Ignores the input pulse when its width is smaller than this register value in AP -B clock periods (in receive mode)..*/ -#define RMT_RX_FILTER_THRES_CH6 0x000000FF -#define RMT_RX_FILTER_THRES_CH6_M ((RMT_RX_FILTER_THRES_CH6_V)<<(RMT_RX_FILTER_THRES_CH6_S)) -#define RMT_RX_FILTER_THRES_CH6_V 0xFF -#define RMT_RX_FILTER_THRES_CH6_S 5 -/* RMT_RX_FILTER_EN_CH6 : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: This is the receive filter's enable bit for CHANNEL$m..*/ -#define RMT_RX_FILTER_EN_CH6 (BIT(4)) -#define RMT_RX_FILTER_EN_CH6_M (BIT(4)) -#define RMT_RX_FILTER_EN_CH6_V 0x1 -#define RMT_RX_FILTER_EN_CH6_S 4 -/* RMT_MEM_OWNER_CH6 : R/W/SC ;bitpos:[3] ;default: 1'b1 ; */ -/*description: This register marks the ownership of CHANNEL$m's ram block.; ; 1'h1: Receiver is - using the ram. ; ; 1'h0: APB bus is using the ram..*/ -#define RMT_MEM_OWNER_CH6 (BIT(3)) -#define RMT_MEM_OWNER_CH6_M (BIT(3)) -#define RMT_MEM_OWNER_CH6_V 0x1 -#define RMT_MEM_OWNER_CH6_S 3 -/* RMT_APB_MEM_RST_CH6 : WT ;bitpos:[2] ;default: 1'b0 ; */ -/*description: Set this bit to reset W/R ram address for CHANNEL$m by accessing apb fifo..*/ -#define RMT_APB_MEM_RST_CH6 (BIT(2)) -#define RMT_APB_MEM_RST_CH6_M (BIT(2)) -#define RMT_APB_MEM_RST_CH6_V 0x1 -#define RMT_APB_MEM_RST_CH6_S 2 -/* RMT_MEM_WR_RST_CH6 : WT ;bitpos:[1] ;default: 1'h0 ; */ -/*description: Set this bit to reset write ram address for CHANNEL$m by accessing receiver..*/ -#define RMT_MEM_WR_RST_CH6 (BIT(1)) -#define RMT_MEM_WR_RST_CH6_M (BIT(1)) -#define RMT_MEM_WR_RST_CH6_V 0x1 -#define RMT_MEM_WR_RST_CH6_S 1 -/* RMT_RX_EN_CH6 : R/W ;bitpos:[0] ;default: 1'h0 ; */ -/*description: Set this bit to enable receiver to receive data on CHANNEL$m..*/ -#define RMT_RX_EN_CH6 (BIT(0)) -#define RMT_RX_EN_CH6_M (BIT(0)) -#define RMT_RX_EN_CH6_V 0x1 -#define RMT_RX_EN_CH6_S 0 +/** RMT_CH6CONF1_REG register + * Channel 6 configure register 1 + */ +#define RMT_CH6CONF1_REG (DR_REG_RMT_BASE + 0x44) +/** RMT_RX_EN_6 : R/W; bitpos: [0]; default: 0; + * Set this bit to enable receiver to receive data on CHANNEL6. + */ +#define RMT_RX_EN_6 (BIT(0)) +#define RMT_RX_EN_6_M (RMT_RX_EN_6_V << RMT_RX_EN_6_S) +#define RMT_RX_EN_6_V 0x00000001U +#define RMT_RX_EN_6_S 0 +/** RMT_MEM_WR_RST_6 : WT; bitpos: [1]; default: 0; + * Set this bit to reset write ram address for CHANNEL6 by accessing receiver. + */ +#define RMT_MEM_WR_RST_6 (BIT(1)) +#define RMT_MEM_WR_RST_6_M (RMT_MEM_WR_RST_6_V << RMT_MEM_WR_RST_6_S) +#define RMT_MEM_WR_RST_6_V 0x00000001U +#define RMT_MEM_WR_RST_6_S 1 +/** RMT_APB_MEM_RST_6 : WT; bitpos: [2]; default: 0; + * Set this bit to reset W/R ram address for CHANNEL6 by accessing apb fifo. + */ +#define RMT_APB_MEM_RST_6 (BIT(2)) +#define RMT_APB_MEM_RST_6_M (RMT_APB_MEM_RST_6_V << RMT_APB_MEM_RST_6_S) +#define RMT_APB_MEM_RST_6_V 0x00000001U +#define RMT_APB_MEM_RST_6_S 2 +/** RMT_MEM_OWNER_6 : R/W/SC; bitpos: [3]; default: 1; + * This register marks the ownership of CHANNEL6's ram block. + * + * 1'h1: Receiver is using the ram. + * + * 1'h0: APB bus is using the ram. + */ +#define RMT_MEM_OWNER_6 (BIT(3)) +#define RMT_MEM_OWNER_6_M (RMT_MEM_OWNER_6_V << RMT_MEM_OWNER_6_S) +#define RMT_MEM_OWNER_6_V 0x00000001U +#define RMT_MEM_OWNER_6_S 3 +/** RMT_RX_FILTER_EN_6 : R/W; bitpos: [4]; default: 0; + * This is the receive filter's enable bit for CHANNEL6. + */ +#define RMT_RX_FILTER_EN_6 (BIT(4)) +#define RMT_RX_FILTER_EN_6_M (RMT_RX_FILTER_EN_6_V << RMT_RX_FILTER_EN_6_S) +#define RMT_RX_FILTER_EN_6_V 0x00000001U +#define RMT_RX_FILTER_EN_6_S 4 +/** RMT_RX_FILTER_THRES_6 : R/W; bitpos: [12:5]; default: 15; + * Ignores the input pulse when its width is smaller than this register value in APB + * clock periods (in receive mode). + */ +#define RMT_RX_FILTER_THRES_6 0x000000FFU +#define RMT_RX_FILTER_THRES_6_M (RMT_RX_FILTER_THRES_6_V << RMT_RX_FILTER_THRES_6_S) +#define RMT_RX_FILTER_THRES_6_V 0x000000FFU +#define RMT_RX_FILTER_THRES_6_S 5 +/** RMT_MEM_RX_WRAP_EN_6 : R/W; bitpos: [13]; default: 0; + * This is the channel 6 enable bit for wraparound mode: it will resume receiving at + * the start when the data to be received is more than its memory size. + */ +#define RMT_MEM_RX_WRAP_EN_6 (BIT(13)) +#define RMT_MEM_RX_WRAP_EN_6_M (RMT_MEM_RX_WRAP_EN_6_V << RMT_MEM_RX_WRAP_EN_6_S) +#define RMT_MEM_RX_WRAP_EN_6_V 0x00000001U +#define RMT_MEM_RX_WRAP_EN_6_S 13 +/** RMT_AFIFO_RST_6 : WT; bitpos: [14]; default: 0; + * Reserved + */ +#define RMT_AFIFO_RST_6 (BIT(14)) +#define RMT_AFIFO_RST_6_M (RMT_AFIFO_RST_6_V << RMT_AFIFO_RST_6_S) +#define RMT_AFIFO_RST_6_V 0x00000001U +#define RMT_AFIFO_RST_6_S 14 +/** RMT_CONF_UPDATE_6 : WT; bitpos: [15]; default: 0; + * synchronization bit for CHANNEL6 + */ +#define RMT_CONF_UPDATE_6 (BIT(15)) +#define RMT_CONF_UPDATE_6_M (RMT_CONF_UPDATE_6_V << RMT_CONF_UPDATE_6_S) +#define RMT_CONF_UPDATE_6_V 0x00000001U +#define RMT_CONF_UPDATE_6_S 15 -#define RMT_CH7CONF0_REG (DR_REG_RMT_BASE + 0x48) -/* RMT_CARRIER_OUT_LV_CH7 : R/W ;bitpos:[29] ;default: 1'b1 ; */ -/*description: This bit is used to configure the position of carrier wave for CHANNEL$m.; ; 1'h -0: add carrier wave on low level.; ; 1'h1: add carrier wave on high level..*/ -#define RMT_CARRIER_OUT_LV_CH7 (BIT(29)) -#define RMT_CARRIER_OUT_LV_CH7_M (BIT(29)) -#define RMT_CARRIER_OUT_LV_CH7_V 0x1 -#define RMT_CARRIER_OUT_LV_CH7_S 29 -/* RMT_CARRIER_EN_CH7 : R/W ;bitpos:[28] ;default: 1'b1 ; */ -/*description: This is the carrier modulation enable-control bit for CHANNEL$m. 1: Add carrier -modulation in the output signal. 0: No carrier modulation in sig_out..*/ -#define RMT_CARRIER_EN_CH7 (BIT(28)) -#define RMT_CARRIER_EN_CH7_M (BIT(28)) -#define RMT_CARRIER_EN_CH7_V 0x1 -#define RMT_CARRIER_EN_CH7_S 28 -/* RMT_MEM_SIZE_CH7 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */ -/*description: This register is used to configure the maximum size of memory allocated to CHANN -EL$m..*/ -#define RMT_MEM_SIZE_CH7 0x0000000F -#define RMT_MEM_SIZE_CH7_M ((RMT_MEM_SIZE_CH7_V)<<(RMT_MEM_SIZE_CH7_S)) -#define RMT_MEM_SIZE_CH7_V 0xF -#define RMT_MEM_SIZE_CH7_S 24 -/* RMT_DMA_ACCESS_EN_CH7 : R/W ;bitpos:[23] ;default: 1'b0 ; */ -/*description: This bit is used to enable the dma access function for CHANNEL$m..*/ -#define RMT_DMA_ACCESS_EN_CH7 (BIT(23)) -#define RMT_DMA_ACCESS_EN_CH7_M (BIT(23)) -#define RMT_DMA_ACCESS_EN_CH7_V 0x1 -#define RMT_DMA_ACCESS_EN_CH7_S 23 -/* RMT_IDLE_THRES_CH7 : R/W ;bitpos:[22:8] ;default: 15'h7fff ; */ -/*description: When no edge is detected on the input signal and continuous clock cycles is long -er than this register value, received process is finished..*/ -#define RMT_IDLE_THRES_CH7 0x00007FFF -#define RMT_IDLE_THRES_CH7_M ((RMT_IDLE_THRES_CH7_V)<<(RMT_IDLE_THRES_CH7_S)) -#define RMT_IDLE_THRES_CH7_V 0x7FFF -#define RMT_IDLE_THRES_CH7_S 8 -/* RMT_DIV_CNT_CH7 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */ -/*description: This register is used to configure the divider for clock of CHANNEL$m..*/ -#define RMT_DIV_CNT_CH7 0x000000FF -#define RMT_DIV_CNT_CH7_M ((RMT_DIV_CNT_CH7_V)<<(RMT_DIV_CNT_CH7_S)) -#define RMT_DIV_CNT_CH7_V 0xFF -#define RMT_DIV_CNT_CH7_S 0 +/** RMT_CH7CONF0_REG register + * Channel 7 configure register 0 + */ +#define RMT_CH7CONF0_REG (DR_REG_RMT_BASE + 0x48) +/** RMT_DIV_CNT_7 : R/W; bitpos: [7:0]; default: 2; + * This register is used to configure the divider for clock of CHANNEL7. + */ +#define RMT_DIV_CNT_7 0x000000FFU +#define RMT_DIV_CNT_7_M (RMT_DIV_CNT_7_V << RMT_DIV_CNT_7_S) +#define RMT_DIV_CNT_7_V 0x000000FFU +#define RMT_DIV_CNT_7_S 0 +/** RMT_IDLE_THRES_7 : R/W; bitpos: [22:8]; default: 32767; + * When no edge is detected on the input signal and continuous clock cycles is longer + * than this register value, received process is finished. + */ +#define RMT_IDLE_THRES_7 0x00007FFFU +#define RMT_IDLE_THRES_7_M (RMT_IDLE_THRES_7_V << RMT_IDLE_THRES_7_S) +#define RMT_IDLE_THRES_7_V 0x00007FFFU +#define RMT_IDLE_THRES_7_S 8 +/** RMT_MEM_SIZE_7 : R/W; bitpos: [27:24]; default: 1; + * This register is used to configure the maximum size of memory allocated to CHANNEL7. + */ +#define RMT_MEM_SIZE_7 0x0000000FU +#define RMT_MEM_SIZE_7_M (RMT_MEM_SIZE_7_V << RMT_MEM_SIZE_7_S) +#define RMT_MEM_SIZE_7_V 0x0000000FU +#define RMT_MEM_SIZE_7_S 24 +/** RMT_CARRIER_EN_7 : R/W; bitpos: [28]; default: 1; + * This is the carrier modulation enable-control bit for CHANNEL7. 1: Add carrier + * modulation in the output signal. 0: No carrier modulation in sig_out. + */ +#define RMT_CARRIER_EN_7 (BIT(28)) +#define RMT_CARRIER_EN_7_M (RMT_CARRIER_EN_7_V << RMT_CARRIER_EN_7_S) +#define RMT_CARRIER_EN_7_V 0x00000001U +#define RMT_CARRIER_EN_7_S 28 +/** RMT_CARRIER_OUT_LV_7 : R/W; bitpos: [29]; default: 1; + * This bit is used to configure the position of carrier wave for CHANNEL7. + * + * 1'h0: add carrier wave on low level. + * + * 1'h1: add carrier wave on high level. + */ +#define RMT_CARRIER_OUT_LV_7 (BIT(29)) +#define RMT_CARRIER_OUT_LV_7_M (RMT_CARRIER_OUT_LV_7_V << RMT_CARRIER_OUT_LV_7_S) +#define RMT_CARRIER_OUT_LV_7_V 0x00000001U +#define RMT_CARRIER_OUT_LV_7_S 29 -#define RMT_CH7CONF1_REG (DR_REG_RMT_BASE + 0x4C) -/* RMT_CONF_UPDATE_CH7 : WT ;bitpos:[15] ;default: 1'b0 ; */ -/*description: synchronization bit for CHANNEL$m.*/ -#define RMT_CONF_UPDATE_CH7 (BIT(15)) -#define RMT_CONF_UPDATE_CH7_M (BIT(15)) -#define RMT_CONF_UPDATE_CH7_V 0x1 -#define RMT_CONF_UPDATE_CH7_S 15 -/* RMT_AFIFO_RST_CH7 : WT ;bitpos:[14] ;default: 1'b0 ; */ -/*description: Reserved.*/ -#define RMT_AFIFO_RST_CH7 (BIT(14)) -#define RMT_AFIFO_RST_CH7_M (BIT(14)) -#define RMT_AFIFO_RST_CH7_V 0x1 -#define RMT_AFIFO_RST_CH7_S 14 -/* RMT_MEM_RX_WRAP_EN_CH7 : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: This is the channel $m enable bit for wraparound mode: it will resume receiving -at the start when the data to be received is more than its memory size..*/ -#define RMT_MEM_RX_WRAP_EN_CH7 (BIT(13)) -#define RMT_MEM_RX_WRAP_EN_CH7_M (BIT(13)) -#define RMT_MEM_RX_WRAP_EN_CH7_V 0x1 -#define RMT_MEM_RX_WRAP_EN_CH7_S 13 -/* RMT_RX_FILTER_THRES_CH7 : R/W ;bitpos:[12:5] ;default: 8'hf ; */ -/*description: Ignores the input pulse when its width is smaller than this register value in AP -B clock periods (in receive mode)..*/ -#define RMT_RX_FILTER_THRES_CH7 0x000000FF -#define RMT_RX_FILTER_THRES_CH7_M ((RMT_RX_FILTER_THRES_CH7_V)<<(RMT_RX_FILTER_THRES_CH7_S)) -#define RMT_RX_FILTER_THRES_CH7_V 0xFF -#define RMT_RX_FILTER_THRES_CH7_S 5 -/* RMT_RX_FILTER_EN_CH7 : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: This is the receive filter's enable bit for CHANNEL$m..*/ -#define RMT_RX_FILTER_EN_CH7 (BIT(4)) -#define RMT_RX_FILTER_EN_CH7_M (BIT(4)) -#define RMT_RX_FILTER_EN_CH7_V 0x1 -#define RMT_RX_FILTER_EN_CH7_S 4 -/* RMT_MEM_OWNER_CH7 : R/W/SC ;bitpos:[3] ;default: 1'b1 ; */ -/*description: This register marks the ownership of CHANNEL$m's ram block.; ; 1'h1: Receiver is - using the ram. ; ; 1'h0: APB bus is using the ram..*/ -#define RMT_MEM_OWNER_CH7 (BIT(3)) -#define RMT_MEM_OWNER_CH7_M (BIT(3)) -#define RMT_MEM_OWNER_CH7_V 0x1 -#define RMT_MEM_OWNER_CH7_S 3 -/* RMT_APB_MEM_RST_CH7 : WT ;bitpos:[2] ;default: 1'b0 ; */ -/*description: Set this bit to reset W/R ram address for CHANNEL$m by accessing apb fifo..*/ -#define RMT_APB_MEM_RST_CH7 (BIT(2)) -#define RMT_APB_MEM_RST_CH7_M (BIT(2)) -#define RMT_APB_MEM_RST_CH7_V 0x1 -#define RMT_APB_MEM_RST_CH7_S 2 -/* RMT_MEM_WR_RST_CH7 : WT ;bitpos:[1] ;default: 1'h0 ; */ -/*description: Set this bit to reset write ram address for CHANNEL$m by accessing receiver..*/ -#define RMT_MEM_WR_RST_CH7 (BIT(1)) -#define RMT_MEM_WR_RST_CH7_M (BIT(1)) -#define RMT_MEM_WR_RST_CH7_V 0x1 -#define RMT_MEM_WR_RST_CH7_S 1 -/* RMT_RX_EN_CH7 : R/W ;bitpos:[0] ;default: 1'h0 ; */ -/*description: Set this bit to enable receiver to receive data on CHANNEL$m..*/ -#define RMT_RX_EN_CH7 (BIT(0)) -#define RMT_RX_EN_CH7_M (BIT(0)) -#define RMT_RX_EN_CH7_V 0x1 -#define RMT_RX_EN_CH7_S 0 +/** RMT_CH7CONF1_REG register + * Channel 7 configure register 1 + */ +#define RMT_CH7CONF1_REG (DR_REG_RMT_BASE + 0x4c) +/** RMT_RX_EN_7 : R/W; bitpos: [0]; default: 0; + * Set this bit to enable receiver to receive data on CHANNEL7. + */ +#define RMT_RX_EN_7 (BIT(0)) +#define RMT_RX_EN_7_M (RMT_RX_EN_7_V << RMT_RX_EN_7_S) +#define RMT_RX_EN_7_V 0x00000001U +#define RMT_RX_EN_7_S 0 +/** RMT_MEM_WR_RST_7 : WT; bitpos: [1]; default: 0; + * Set this bit to reset write ram address for CHANNEL7 by accessing receiver. + */ +#define RMT_MEM_WR_RST_7 (BIT(1)) +#define RMT_MEM_WR_RST_7_M (RMT_MEM_WR_RST_7_V << RMT_MEM_WR_RST_7_S) +#define RMT_MEM_WR_RST_7_V 0x00000001U +#define RMT_MEM_WR_RST_7_S 1 +/** RMT_APB_MEM_RST_7 : WT; bitpos: [2]; default: 0; + * Set this bit to reset W/R ram address for CHANNEL7 by accessing apb fifo. + */ +#define RMT_APB_MEM_RST_7 (BIT(2)) +#define RMT_APB_MEM_RST_7_M (RMT_APB_MEM_RST_7_V << RMT_APB_MEM_RST_7_S) +#define RMT_APB_MEM_RST_7_V 0x00000001U +#define RMT_APB_MEM_RST_7_S 2 +/** RMT_MEM_OWNER_7 : R/W/SC; bitpos: [3]; default: 1; + * This register marks the ownership of CHANNEL7's ram block. + * + * 1'h1: Receiver is using the ram. + * + * 1'h0: APB bus is using the ram. + */ +#define RMT_MEM_OWNER_7 (BIT(3)) +#define RMT_MEM_OWNER_7_M (RMT_MEM_OWNER_7_V << RMT_MEM_OWNER_7_S) +#define RMT_MEM_OWNER_7_V 0x00000001U +#define RMT_MEM_OWNER_7_S 3 +/** RMT_RX_FILTER_EN_7 : R/W; bitpos: [4]; default: 0; + * This is the receive filter's enable bit for CHANNEL7. + */ +#define RMT_RX_FILTER_EN_7 (BIT(4)) +#define RMT_RX_FILTER_EN_7_M (RMT_RX_FILTER_EN_7_V << RMT_RX_FILTER_EN_7_S) +#define RMT_RX_FILTER_EN_7_V 0x00000001U +#define RMT_RX_FILTER_EN_7_S 4 +/** RMT_RX_FILTER_THRES_7 : R/W; bitpos: [12:5]; default: 15; + * Ignores the input pulse when its width is smaller than this register value in APB + * clock periods (in receive mode). + */ +#define RMT_RX_FILTER_THRES_7 0x000000FFU +#define RMT_RX_FILTER_THRES_7_M (RMT_RX_FILTER_THRES_7_V << RMT_RX_FILTER_THRES_7_S) +#define RMT_RX_FILTER_THRES_7_V 0x000000FFU +#define RMT_RX_FILTER_THRES_7_S 5 +/** RMT_MEM_RX_WRAP_EN_7 : R/W; bitpos: [13]; default: 0; + * This is the channel 7 enable bit for wraparound mode: it will resume receiving at + * the start when the data to be received is more than its memory size. + */ +#define RMT_MEM_RX_WRAP_EN_7 (BIT(13)) +#define RMT_MEM_RX_WRAP_EN_7_M (RMT_MEM_RX_WRAP_EN_7_V << RMT_MEM_RX_WRAP_EN_7_S) +#define RMT_MEM_RX_WRAP_EN_7_V 0x00000001U +#define RMT_MEM_RX_WRAP_EN_7_S 13 +/** RMT_AFIFO_RST_7 : WT; bitpos: [14]; default: 0; + * Reserved + */ +#define RMT_AFIFO_RST_7 (BIT(14)) +#define RMT_AFIFO_RST_7_M (RMT_AFIFO_RST_7_V << RMT_AFIFO_RST_7_S) +#define RMT_AFIFO_RST_7_V 0x00000001U +#define RMT_AFIFO_RST_7_S 14 +/** RMT_CONF_UPDATE_7 : WT; bitpos: [15]; default: 0; + * synchronization bit for CHANNEL7 + */ +#define RMT_CONF_UPDATE_7 (BIT(15)) +#define RMT_CONF_UPDATE_7_M (RMT_CONF_UPDATE_7_V << RMT_CONF_UPDATE_7_S) +#define RMT_CONF_UPDATE_7_V 0x00000001U +#define RMT_CONF_UPDATE_7_S 15 -#define RMT_CH0STATUS_REG (DR_REG_RMT_BASE + 0x50) -/* RMT_APB_MEM_WR_ERR_CH0 : RO ;bitpos:[26] ;default: 1'b0 ; */ -/*description: This status bit will be set if the offset address out of memory size when writes - via APB bus..*/ -#define RMT_APB_MEM_WR_ERR_CH0 (BIT(26)) -#define RMT_APB_MEM_WR_ERR_CH0_M (BIT(26)) -#define RMT_APB_MEM_WR_ERR_CH0_V 0x1 -#define RMT_APB_MEM_WR_ERR_CH0_S 26 -/* RMT_MEM_EMPTY_CH0 : RO ;bitpos:[25] ;default: 1'b0 ; */ -/*description: This status bit will be set when the data to be set is more than memory size and - the wraparound mode is disabled..*/ -#define RMT_MEM_EMPTY_CH0 (BIT(25)) -#define RMT_MEM_EMPTY_CH0_M (BIT(25)) -#define RMT_MEM_EMPTY_CH0_V 0x1 -#define RMT_MEM_EMPTY_CH0_S 25 -/* RMT_STATE_CH0 : RO ;bitpos:[24:22] ;default: 3'b0 ; */ -/*description: This register records the FSM status of CHANNEL$n..*/ -#define RMT_STATE_CH0 0x00000007 -#define RMT_STATE_CH0_M ((RMT_STATE_CH0_V)<<(RMT_STATE_CH0_S)) -#define RMT_STATE_CH0_V 0x7 -#define RMT_STATE_CH0_S 22 -/* RMT_APB_MEM_WADDR_CH0 : RO ;bitpos:[20:11] ;default: 10'b0 ; */ -/*description: This register records the memory address offset when writes RAM over APB bus..*/ -#define RMT_APB_MEM_WADDR_CH0 0x000003FF -#define RMT_APB_MEM_WADDR_CH0_M ((RMT_APB_MEM_WADDR_CH0_V)<<(RMT_APB_MEM_WADDR_CH0_S)) -#define RMT_APB_MEM_WADDR_CH0_V 0x3FF -#define RMT_APB_MEM_WADDR_CH0_S 11 -/* RMT_MEM_RADDR_EX_CH0 : RO ;bitpos:[9:0] ;default: 10'b0 ; */ -/*description: This register records the memory address offset when transmitter of CHANNEL$n is - using the RAM..*/ -#define RMT_MEM_RADDR_EX_CH0 0x000003FF -#define RMT_MEM_RADDR_EX_CH0_M ((RMT_MEM_RADDR_EX_CH0_V)<<(RMT_MEM_RADDR_EX_CH0_S)) -#define RMT_MEM_RADDR_EX_CH0_V 0x3FF -#define RMT_MEM_RADDR_EX_CH0_S 0 +/** RMT_CH0STATUS_REG register + * Channel 0 status register + */ +#define RMT_CH0STATUS_REG (DR_REG_RMT_BASE + 0x50) +/** RMT_MEM_RADDR_EX_0 : RO; bitpos: [9:0]; default: 0; + * This register records the memory address offset when transmitter of CHANNEL0 is + * using the RAM. + */ +#define RMT_MEM_RADDR_EX_0 0x000003FFU +#define RMT_MEM_RADDR_EX_0_M (RMT_MEM_RADDR_EX_0_V << RMT_MEM_RADDR_EX_0_S) +#define RMT_MEM_RADDR_EX_0_V 0x000003FFU +#define RMT_MEM_RADDR_EX_0_S 0 +/** RMT_APB_MEM_WADDR_0 : RO; bitpos: [20:11]; default: 0; + * This register records the memory address offset when writes RAM over APB bus. + */ +#define RMT_APB_MEM_WADDR_0 0x000003FFU +#define RMT_APB_MEM_WADDR_0_M (RMT_APB_MEM_WADDR_0_V << RMT_APB_MEM_WADDR_0_S) +#define RMT_APB_MEM_WADDR_0_V 0x000003FFU +#define RMT_APB_MEM_WADDR_0_S 11 +/** RMT_STATE_0 : RO; bitpos: [24:22]; default: 0; + * This register records the FSM status of CHANNEL0. + */ +#define RMT_STATE_0 0x00000007U +#define RMT_STATE_0_M (RMT_STATE_0_V << RMT_STATE_0_S) +#define RMT_STATE_0_V 0x00000007U +#define RMT_STATE_0_S 22 +/** RMT_MEM_EMPTY_0 : RO; bitpos: [25]; default: 0; + * This status bit will be set when the data to be set is more than memory size and + * the wraparound mode is disabled. + */ +#define RMT_MEM_EMPTY_0 (BIT(25)) +#define RMT_MEM_EMPTY_0_M (RMT_MEM_EMPTY_0_V << RMT_MEM_EMPTY_0_S) +#define RMT_MEM_EMPTY_0_V 0x00000001U +#define RMT_MEM_EMPTY_0_S 25 +/** RMT_APB_MEM_WR_ERR_0 : RO; bitpos: [26]; default: 0; + * This status bit will be set if the offset address out of memory size when writes + * via APB bus. + */ +#define RMT_APB_MEM_WR_ERR_0 (BIT(26)) +#define RMT_APB_MEM_WR_ERR_0_M (RMT_APB_MEM_WR_ERR_0_V << RMT_APB_MEM_WR_ERR_0_S) +#define RMT_APB_MEM_WR_ERR_0_V 0x00000001U +#define RMT_APB_MEM_WR_ERR_0_S 26 -#define RMT_CH1STATUS_REG (DR_REG_RMT_BASE + 0x54) -/* RMT_APB_MEM_WR_ERR_CH1 : RO ;bitpos:[26] ;default: 1'b0 ; */ -/*description: This status bit will be set if the offset address out of memory size when writes - via APB bus..*/ -#define RMT_APB_MEM_WR_ERR_CH1 (BIT(26)) -#define RMT_APB_MEM_WR_ERR_CH1_M (BIT(26)) -#define RMT_APB_MEM_WR_ERR_CH1_V 0x1 -#define RMT_APB_MEM_WR_ERR_CH1_S 26 -/* RMT_MEM_EMPTY_CH1 : RO ;bitpos:[25] ;default: 1'b0 ; */ -/*description: This status bit will be set when the data to be set is more than memory size and - the wraparound mode is disabled..*/ -#define RMT_MEM_EMPTY_CH1 (BIT(25)) -#define RMT_MEM_EMPTY_CH1_M (BIT(25)) -#define RMT_MEM_EMPTY_CH1_V 0x1 -#define RMT_MEM_EMPTY_CH1_S 25 -/* RMT_STATE_CH1 : RO ;bitpos:[24:22] ;default: 3'b0 ; */ -/*description: This register records the FSM status of CHANNEL$n..*/ -#define RMT_STATE_CH1 0x00000007 -#define RMT_STATE_CH1_M ((RMT_STATE_CH1_V)<<(RMT_STATE_CH1_S)) -#define RMT_STATE_CH1_V 0x7 -#define RMT_STATE_CH1_S 22 -/* RMT_APB_MEM_WADDR_CH1 : RO ;bitpos:[20:11] ;default: 10'h30 ; */ -/*description: This register records the memory address offset when writes RAM over APB bus..*/ -#define RMT_APB_MEM_WADDR_CH1 0x000003FF -#define RMT_APB_MEM_WADDR_CH1_M ((RMT_APB_MEM_WADDR_CH1_V)<<(RMT_APB_MEM_WADDR_CH1_S)) -#define RMT_APB_MEM_WADDR_CH1_V 0x3FF -#define RMT_APB_MEM_WADDR_CH1_S 11 -/* RMT_MEM_RADDR_EX_CH1 : RO ;bitpos:[9:0] ;default: 10'h30 ; */ -/*description: This register records the memory address offset when transmitter of CHANNEL$n is - using the RAM..*/ -#define RMT_MEM_RADDR_EX_CH1 0x000003FF -#define RMT_MEM_RADDR_EX_CH1_M ((RMT_MEM_RADDR_EX_CH1_V)<<(RMT_MEM_RADDR_EX_CH1_S)) -#define RMT_MEM_RADDR_EX_CH1_V 0x3FF -#define RMT_MEM_RADDR_EX_CH1_S 0 +/** RMT_CH1STATUS_REG register + * Channel 1 status register + */ +#define RMT_CH1STATUS_REG (DR_REG_RMT_BASE + 0x54) +/** RMT_MEM_RADDR_EX_1 : RO; bitpos: [9:0]; default: 0; + * This register records the memory address offset when transmitter of CHANNEL1 is + * using the RAM. + */ +#define RMT_MEM_RADDR_EX_1 0x000003FFU +#define RMT_MEM_RADDR_EX_1_M (RMT_MEM_RADDR_EX_1_V << RMT_MEM_RADDR_EX_1_S) +#define RMT_MEM_RADDR_EX_1_V 0x000003FFU +#define RMT_MEM_RADDR_EX_1_S 0 +/** RMT_APB_MEM_WADDR_1 : RO; bitpos: [20:11]; default: 0; + * This register records the memory address offset when writes RAM over APB bus. + */ +#define RMT_APB_MEM_WADDR_1 0x000003FFU +#define RMT_APB_MEM_WADDR_1_M (RMT_APB_MEM_WADDR_1_V << RMT_APB_MEM_WADDR_1_S) +#define RMT_APB_MEM_WADDR_1_V 0x000003FFU +#define RMT_APB_MEM_WADDR_1_S 11 +/** RMT_STATE_1 : RO; bitpos: [24:22]; default: 0; + * This register records the FSM status of CHANNEL1. + */ +#define RMT_STATE_1 0x00000007U +#define RMT_STATE_1_M (RMT_STATE_1_V << RMT_STATE_1_S) +#define RMT_STATE_1_V 0x00000007U +#define RMT_STATE_1_S 22 +/** RMT_MEM_EMPTY_1 : RO; bitpos: [25]; default: 0; + * This status bit will be set when the data to be set is more than memory size and + * the wraparound mode is disabled. + */ +#define RMT_MEM_EMPTY_1 (BIT(25)) +#define RMT_MEM_EMPTY_1_M (RMT_MEM_EMPTY_1_V << RMT_MEM_EMPTY_1_S) +#define RMT_MEM_EMPTY_1_V 0x00000001U +#define RMT_MEM_EMPTY_1_S 25 +/** RMT_APB_MEM_WR_ERR_1 : RO; bitpos: [26]; default: 0; + * This status bit will be set if the offset address out of memory size when writes + * via APB bus. + */ +#define RMT_APB_MEM_WR_ERR_1 (BIT(26)) +#define RMT_APB_MEM_WR_ERR_1_M (RMT_APB_MEM_WR_ERR_1_V << RMT_APB_MEM_WR_ERR_1_S) +#define RMT_APB_MEM_WR_ERR_1_V 0x00000001U +#define RMT_APB_MEM_WR_ERR_1_S 26 -#define RMT_CH2STATUS_REG (DR_REG_RMT_BASE + 0x58) -/* RMT_APB_MEM_WR_ERR_CH2 : RO ;bitpos:[26] ;default: 1'b0 ; */ -/*description: This status bit will be set if the offset address out of memory size when writes - via APB bus..*/ -#define RMT_APB_MEM_WR_ERR_CH2 (BIT(26)) -#define RMT_APB_MEM_WR_ERR_CH2_M (BIT(26)) -#define RMT_APB_MEM_WR_ERR_CH2_V 0x1 -#define RMT_APB_MEM_WR_ERR_CH2_S 26 -/* RMT_MEM_EMPTY_CH2 : RO ;bitpos:[25] ;default: 1'b0 ; */ -/*description: This status bit will be set when the data to be set is more than memory size and - the wraparound mode is disabled..*/ -#define RMT_MEM_EMPTY_CH2 (BIT(25)) -#define RMT_MEM_EMPTY_CH2_M (BIT(25)) -#define RMT_MEM_EMPTY_CH2_V 0x1 -#define RMT_MEM_EMPTY_CH2_S 25 -/* RMT_STATE_CH2 : RO ;bitpos:[24:22] ;default: 3'b0 ; */ -/*description: This register records the FSM status of CHANNEL$n..*/ -#define RMT_STATE_CH2 0x00000007 -#define RMT_STATE_CH2_M ((RMT_STATE_CH2_V)<<(RMT_STATE_CH2_S)) -#define RMT_STATE_CH2_V 0x7 -#define RMT_STATE_CH2_S 22 -/* RMT_APB_MEM_WADDR_CH2 : RO ;bitpos:[20:11] ;default: 10'h60 ; */ -/*description: This register records the memory address offset when writes RAM over APB bus..*/ -#define RMT_APB_MEM_WADDR_CH2 0x000003FF -#define RMT_APB_MEM_WADDR_CH2_M ((RMT_APB_MEM_WADDR_CH2_V)<<(RMT_APB_MEM_WADDR_CH2_S)) -#define RMT_APB_MEM_WADDR_CH2_V 0x3FF -#define RMT_APB_MEM_WADDR_CH2_S 11 -/* RMT_MEM_RADDR_EX_CH2 : RO ;bitpos:[9:0] ;default: 10'h60 ; */ -/*description: This register records the memory address offset when transmitter of CHANNEL$n is - using the RAM..*/ -#define RMT_MEM_RADDR_EX_CH2 0x000003FF -#define RMT_MEM_RADDR_EX_CH2_M ((RMT_MEM_RADDR_EX_CH2_V)<<(RMT_MEM_RADDR_EX_CH2_S)) -#define RMT_MEM_RADDR_EX_CH2_V 0x3FF -#define RMT_MEM_RADDR_EX_CH2_S 0 +/** RMT_CH2STATUS_REG register + * Channel 2 status register + */ +#define RMT_CH2STATUS_REG (DR_REG_RMT_BASE + 0x58) +/** RMT_MEM_RADDR_EX_2 : RO; bitpos: [9:0]; default: 0; + * This register records the memory address offset when transmitter of CHANNEL2 is + * using the RAM. + */ +#define RMT_MEM_RADDR_EX_2 0x000003FFU +#define RMT_MEM_RADDR_EX_2_M (RMT_MEM_RADDR_EX_2_V << RMT_MEM_RADDR_EX_2_S) +#define RMT_MEM_RADDR_EX_2_V 0x000003FFU +#define RMT_MEM_RADDR_EX_2_S 0 +/** RMT_APB_MEM_WADDR_2 : RO; bitpos: [20:11]; default: 0; + * This register records the memory address offset when writes RAM over APB bus. + */ +#define RMT_APB_MEM_WADDR_2 0x000003FFU +#define RMT_APB_MEM_WADDR_2_M (RMT_APB_MEM_WADDR_2_V << RMT_APB_MEM_WADDR_2_S) +#define RMT_APB_MEM_WADDR_2_V 0x000003FFU +#define RMT_APB_MEM_WADDR_2_S 11 +/** RMT_STATE_2 : RO; bitpos: [24:22]; default: 0; + * This register records the FSM status of CHANNEL2. + */ +#define RMT_STATE_2 0x00000007U +#define RMT_STATE_2_M (RMT_STATE_2_V << RMT_STATE_2_S) +#define RMT_STATE_2_V 0x00000007U +#define RMT_STATE_2_S 22 +/** RMT_MEM_EMPTY_2 : RO; bitpos: [25]; default: 0; + * This status bit will be set when the data to be set is more than memory size and + * the wraparound mode is disabled. + */ +#define RMT_MEM_EMPTY_2 (BIT(25)) +#define RMT_MEM_EMPTY_2_M (RMT_MEM_EMPTY_2_V << RMT_MEM_EMPTY_2_S) +#define RMT_MEM_EMPTY_2_V 0x00000001U +#define RMT_MEM_EMPTY_2_S 25 +/** RMT_APB_MEM_WR_ERR_2 : RO; bitpos: [26]; default: 0; + * This status bit will be set if the offset address out of memory size when writes + * via APB bus. + */ +#define RMT_APB_MEM_WR_ERR_2 (BIT(26)) +#define RMT_APB_MEM_WR_ERR_2_M (RMT_APB_MEM_WR_ERR_2_V << RMT_APB_MEM_WR_ERR_2_S) +#define RMT_APB_MEM_WR_ERR_2_V 0x00000001U +#define RMT_APB_MEM_WR_ERR_2_S 26 -#define RMT_CH3STATUS_REG (DR_REG_RMT_BASE + 0x5C) -/* RMT_APB_MEM_WR_ERR_CH3 : RO ;bitpos:[26] ;default: 1'b0 ; */ -/*description: This status bit will be set if the offset address out of memory size when writes - via APB bus..*/ -#define RMT_APB_MEM_WR_ERR_CH3 (BIT(26)) -#define RMT_APB_MEM_WR_ERR_CH3_M (BIT(26)) -#define RMT_APB_MEM_WR_ERR_CH3_V 0x1 -#define RMT_APB_MEM_WR_ERR_CH3_S 26 -/* RMT_MEM_EMPTY_CH3 : RO ;bitpos:[25] ;default: 1'b0 ; */ -/*description: This status bit will be set when the data to be set is more than memory size and - the wraparound mode is disabled..*/ -#define RMT_MEM_EMPTY_CH3 (BIT(25)) -#define RMT_MEM_EMPTY_CH3_M (BIT(25)) -#define RMT_MEM_EMPTY_CH3_V 0x1 -#define RMT_MEM_EMPTY_CH3_S 25 -/* RMT_STATE_CH3 : RO ;bitpos:[24:22] ;default: 3'b0 ; */ -/*description: This register records the FSM status of CHANNEL$n..*/ -#define RMT_STATE_CH3 0x00000007 -#define RMT_STATE_CH3_M ((RMT_STATE_CH3_V)<<(RMT_STATE_CH3_S)) -#define RMT_STATE_CH3_V 0x7 -#define RMT_STATE_CH3_S 22 -/* RMT_APB_MEM_WADDR_CH3 : RO ;bitpos:[20:11] ;default: 10'h90 ; */ -/*description: This register records the memory address offset when writes RAM over APB bus..*/ -#define RMT_APB_MEM_WADDR_CH3 0x000003FF -#define RMT_APB_MEM_WADDR_CH3_M ((RMT_APB_MEM_WADDR_CH3_V)<<(RMT_APB_MEM_WADDR_CH3_S)) -#define RMT_APB_MEM_WADDR_CH3_V 0x3FF -#define RMT_APB_MEM_WADDR_CH3_S 11 -/* RMT_MEM_RADDR_EX_CH3 : RO ;bitpos:[9:0] ;default: 10'h90 ; */ -/*description: This register records the memory address offset when transmitter of CHANNEL$n is - using the RAM..*/ -#define RMT_MEM_RADDR_EX_CH3 0x000003FF -#define RMT_MEM_RADDR_EX_CH3_M ((RMT_MEM_RADDR_EX_CH3_V)<<(RMT_MEM_RADDR_EX_CH3_S)) -#define RMT_MEM_RADDR_EX_CH3_V 0x3FF -#define RMT_MEM_RADDR_EX_CH3_S 0 +/** RMT_CH3STATUS_REG register + * Channel 3 status register + */ +#define RMT_CH3STATUS_REG (DR_REG_RMT_BASE + 0x5c) +/** RMT_MEM_RADDR_EX_3 : RO; bitpos: [9:0]; default: 0; + * This register records the memory address offset when transmitter of CHANNEL3 is + * using the RAM. + */ +#define RMT_MEM_RADDR_EX_3 0x000003FFU +#define RMT_MEM_RADDR_EX_3_M (RMT_MEM_RADDR_EX_3_V << RMT_MEM_RADDR_EX_3_S) +#define RMT_MEM_RADDR_EX_3_V 0x000003FFU +#define RMT_MEM_RADDR_EX_3_S 0 +/** RMT_APB_MEM_WADDR_3 : RO; bitpos: [20:11]; default: 0; + * This register records the memory address offset when writes RAM over APB bus. + */ +#define RMT_APB_MEM_WADDR_3 0x000003FFU +#define RMT_APB_MEM_WADDR_3_M (RMT_APB_MEM_WADDR_3_V << RMT_APB_MEM_WADDR_3_S) +#define RMT_APB_MEM_WADDR_3_V 0x000003FFU +#define RMT_APB_MEM_WADDR_3_S 11 +/** RMT_STATE_3 : RO; bitpos: [24:22]; default: 0; + * This register records the FSM status of CHANNEL3. + */ +#define RMT_STATE_3 0x00000007U +#define RMT_STATE_3_M (RMT_STATE_3_V << RMT_STATE_3_S) +#define RMT_STATE_3_V 0x00000007U +#define RMT_STATE_3_S 22 +/** RMT_MEM_EMPTY_3 : RO; bitpos: [25]; default: 0; + * This status bit will be set when the data to be set is more than memory size and + * the wraparound mode is disabled. + */ +#define RMT_MEM_EMPTY_3 (BIT(25)) +#define RMT_MEM_EMPTY_3_M (RMT_MEM_EMPTY_3_V << RMT_MEM_EMPTY_3_S) +#define RMT_MEM_EMPTY_3_V 0x00000001U +#define RMT_MEM_EMPTY_3_S 25 +/** RMT_APB_MEM_WR_ERR_3 : RO; bitpos: [26]; default: 0; + * This status bit will be set if the offset address out of memory size when writes + * via APB bus. + */ +#define RMT_APB_MEM_WR_ERR_3 (BIT(26)) +#define RMT_APB_MEM_WR_ERR_3_M (RMT_APB_MEM_WR_ERR_3_V << RMT_APB_MEM_WR_ERR_3_S) +#define RMT_APB_MEM_WR_ERR_3_V 0x00000001U +#define RMT_APB_MEM_WR_ERR_3_S 26 -#define RMT_CH4STATUS_REG (DR_REG_RMT_BASE + 0x60) -/* RMT_APB_MEM_RD_ERR_CH4 : RO ;bitpos:[27] ;default: 1'b0 ; */ -/*description: This status bit will be set if the offset address out of memory size when reads -via APB bus..*/ -#define RMT_APB_MEM_RD_ERR_CH4 (BIT(27)) -#define RMT_APB_MEM_RD_ERR_CH4_M (BIT(27)) -#define RMT_APB_MEM_RD_ERR_CH4_V 0x1 -#define RMT_APB_MEM_RD_ERR_CH4_S 27 -/* RMT_MEM_FULL_CH4 : RO ;bitpos:[26] ;default: 1'b0 ; */ -/*description: This status bit will be set if the receiver receives more data than the memory s -ize..*/ -#define RMT_MEM_FULL_CH4 (BIT(26)) -#define RMT_MEM_FULL_CH4_M (BIT(26)) -#define RMT_MEM_FULL_CH4_V 0x1 -#define RMT_MEM_FULL_CH4_S 26 -/* RMT_MEM_OWNER_ERR_CH4 : RO ;bitpos:[25] ;default: 1'b0 ; */ -/*description: This status bit will be set when the ownership of memory block is wrong..*/ -#define RMT_MEM_OWNER_ERR_CH4 (BIT(25)) -#define RMT_MEM_OWNER_ERR_CH4_M (BIT(25)) -#define RMT_MEM_OWNER_ERR_CH4_V 0x1 -#define RMT_MEM_OWNER_ERR_CH4_S 25 -/* RMT_STATE_CH4 : RO ;bitpos:[24:22] ;default: 3'b0 ; */ -/*description: This register records the FSM status of CHANNEL$m..*/ -#define RMT_STATE_CH4 0x00000007 -#define RMT_STATE_CH4_M ((RMT_STATE_CH4_V)<<(RMT_STATE_CH4_S)) -#define RMT_STATE_CH4_V 0x7 -#define RMT_STATE_CH4_S 22 -/* RMT_APB_MEM_RADDR_CH4 : RO ;bitpos:[20:11] ;default: 10'hc0 ; */ -/*description: This register records the memory address offset when reads RAM over APB bus..*/ -#define RMT_APB_MEM_RADDR_CH4 0x000003FF -#define RMT_APB_MEM_RADDR_CH4_M ((RMT_APB_MEM_RADDR_CH4_V)<<(RMT_APB_MEM_RADDR_CH4_S)) -#define RMT_APB_MEM_RADDR_CH4_V 0x3FF -#define RMT_APB_MEM_RADDR_CH4_S 11 -/* RMT_MEM_WADDR_EX_CH4 : RO ;bitpos:[9:0] ;default: 10'hc0 ; */ -/*description: This register records the memory address offset when receiver of CHANNEL$m is us -ing the RAM..*/ -#define RMT_MEM_WADDR_EX_CH4 0x000003FF -#define RMT_MEM_WADDR_EX_CH4_M ((RMT_MEM_WADDR_EX_CH4_V)<<(RMT_MEM_WADDR_EX_CH4_S)) -#define RMT_MEM_WADDR_EX_CH4_V 0x3FF -#define RMT_MEM_WADDR_EX_CH4_S 0 +/** RMT_CH4STATUS_REG register + * Channel 4 status register + */ +#define RMT_CH4STATUS_REG (DR_REG_RMT_BASE + 0x60) +/** RMT_MEM_WADDR_EX_4 : RO; bitpos: [9:0]; default: 192; + * This register records the memory address offset when receiver of CHANNEL4 is using + * the RAM. + */ +#define RMT_MEM_WADDR_EX_4 0x000003FFU +#define RMT_MEM_WADDR_EX_4_M (RMT_MEM_WADDR_EX_4_V << RMT_MEM_WADDR_EX_4_S) +#define RMT_MEM_WADDR_EX_4_V 0x000003FFU +#define RMT_MEM_WADDR_EX_4_S 0 +/** RMT_APB_MEM_RADDR_4 : RO; bitpos: [20:11]; default: 192; + * This register records the memory address offset when reads RAM over APB bus. + */ +#define RMT_APB_MEM_RADDR_4 0x000003FFU +#define RMT_APB_MEM_RADDR_4_M (RMT_APB_MEM_RADDR_4_V << RMT_APB_MEM_RADDR_4_S) +#define RMT_APB_MEM_RADDR_4_V 0x000003FFU +#define RMT_APB_MEM_RADDR_4_S 11 +/** RMT_STATE_4 : RO; bitpos: [24:22]; default: 0; + * This register records the FSM status of CHANNEL4. + */ +#define RMT_STATE_4 0x00000007U +#define RMT_STATE_4_M (RMT_STATE_4_V << RMT_STATE_4_S) +#define RMT_STATE_4_V 0x00000007U +#define RMT_STATE_4_S 22 +/** RMT_MEM_OWNER_ERR_4 : RO; bitpos: [25]; default: 0; + * This status bit will be set when the ownership of memory block is wrong. + */ +#define RMT_MEM_OWNER_ERR_4 (BIT(25)) +#define RMT_MEM_OWNER_ERR_4_M (RMT_MEM_OWNER_ERR_4_V << RMT_MEM_OWNER_ERR_4_S) +#define RMT_MEM_OWNER_ERR_4_V 0x00000001U +#define RMT_MEM_OWNER_ERR_4_S 25 +/** RMT_MEM_FULL_4 : RO; bitpos: [26]; default: 0; + * This status bit will be set if the receiver receives more data than the memory size. + */ +#define RMT_MEM_FULL_4 (BIT(26)) +#define RMT_MEM_FULL_4_M (RMT_MEM_FULL_4_V << RMT_MEM_FULL_4_S) +#define RMT_MEM_FULL_4_V 0x00000001U +#define RMT_MEM_FULL_4_S 26 +/** RMT_APB_MEM_RD_ERR_4 : RO; bitpos: [27]; default: 0; + * This status bit will be set if the offset address out of memory size when reads via + * APB bus. + */ +#define RMT_APB_MEM_RD_ERR_4 (BIT(27)) +#define RMT_APB_MEM_RD_ERR_4_M (RMT_APB_MEM_RD_ERR_4_V << RMT_APB_MEM_RD_ERR_4_S) +#define RMT_APB_MEM_RD_ERR_4_V 0x00000001U +#define RMT_APB_MEM_RD_ERR_4_S 27 -#define RMT_CH5STATUS_REG (DR_REG_RMT_BASE + 0x64) -/* RMT_APB_MEM_RD_ERR_CH5 : RO ;bitpos:[27] ;default: 1'b0 ; */ -/*description: This status bit will be set if the offset address out of memory size when reads -via APB bus..*/ -#define RMT_APB_MEM_RD_ERR_CH5 (BIT(27)) -#define RMT_APB_MEM_RD_ERR_CH5_M (BIT(27)) -#define RMT_APB_MEM_RD_ERR_CH5_V 0x1 -#define RMT_APB_MEM_RD_ERR_CH5_S 27 -/* RMT_MEM_FULL_CH5 : RO ;bitpos:[26] ;default: 1'b0 ; */ -/*description: This status bit will be set if the receiver receives more data than the memory s -ize..*/ -#define RMT_MEM_FULL_CH5 (BIT(26)) -#define RMT_MEM_FULL_CH5_M (BIT(26)) -#define RMT_MEM_FULL_CH5_V 0x1 -#define RMT_MEM_FULL_CH5_S 26 -/* RMT_MEM_OWNER_ERR_CH5 : RO ;bitpos:[25] ;default: 1'b0 ; */ -/*description: This status bit will be set when the ownership of memory block is wrong..*/ -#define RMT_MEM_OWNER_ERR_CH5 (BIT(25)) -#define RMT_MEM_OWNER_ERR_CH5_M (BIT(25)) -#define RMT_MEM_OWNER_ERR_CH5_V 0x1 -#define RMT_MEM_OWNER_ERR_CH5_S 25 -/* RMT_STATE_CH5 : RO ;bitpos:[24:22] ;default: 3'b0 ; */ -/*description: This register records the FSM status of CHANNEL$m..*/ -#define RMT_STATE_CH5 0x00000007 -#define RMT_STATE_CH5_M ((RMT_STATE_CH5_V)<<(RMT_STATE_CH5_S)) -#define RMT_STATE_CH5_V 0x7 -#define RMT_STATE_CH5_S 22 -/* RMT_APB_MEM_RADDR_CH5 : RO ;bitpos:[20:11] ;default: 10'hf0 ; */ -/*description: This register records the memory address offset when reads RAM over APB bus..*/ -#define RMT_APB_MEM_RADDR_CH5 0x000003FF -#define RMT_APB_MEM_RADDR_CH5_M ((RMT_APB_MEM_RADDR_CH5_V)<<(RMT_APB_MEM_RADDR_CH5_S)) -#define RMT_APB_MEM_RADDR_CH5_V 0x3FF -#define RMT_APB_MEM_RADDR_CH5_S 11 -/* RMT_MEM_WADDR_EX_CH5 : RO ;bitpos:[9:0] ;default: 10'hf0 ; */ -/*description: This register records the memory address offset when receiver of CHANNEL$m is us -ing the RAM..*/ -#define RMT_MEM_WADDR_EX_CH5 0x000003FF -#define RMT_MEM_WADDR_EX_CH5_M ((RMT_MEM_WADDR_EX_CH5_V)<<(RMT_MEM_WADDR_EX_CH5_S)) -#define RMT_MEM_WADDR_EX_CH5_V 0x3FF -#define RMT_MEM_WADDR_EX_CH5_S 0 +/** RMT_CH5STATUS_REG register + * Channel 5 status register + */ +#define RMT_CH5STATUS_REG (DR_REG_RMT_BASE + 0x64) +/** RMT_MEM_WADDR_EX_5 : RO; bitpos: [9:0]; default: 192; + * This register records the memory address offset when receiver of CHANNEL5 is using + * the RAM. + */ +#define RMT_MEM_WADDR_EX_5 0x000003FFU +#define RMT_MEM_WADDR_EX_5_M (RMT_MEM_WADDR_EX_5_V << RMT_MEM_WADDR_EX_5_S) +#define RMT_MEM_WADDR_EX_5_V 0x000003FFU +#define RMT_MEM_WADDR_EX_5_S 0 +/** RMT_APB_MEM_RADDR_5 : RO; bitpos: [20:11]; default: 192; + * This register records the memory address offset when reads RAM over APB bus. + */ +#define RMT_APB_MEM_RADDR_5 0x000003FFU +#define RMT_APB_MEM_RADDR_5_M (RMT_APB_MEM_RADDR_5_V << RMT_APB_MEM_RADDR_5_S) +#define RMT_APB_MEM_RADDR_5_V 0x000003FFU +#define RMT_APB_MEM_RADDR_5_S 11 +/** RMT_STATE_5 : RO; bitpos: [24:22]; default: 0; + * This register records the FSM status of CHANNEL5. + */ +#define RMT_STATE_5 0x00000007U +#define RMT_STATE_5_M (RMT_STATE_5_V << RMT_STATE_5_S) +#define RMT_STATE_5_V 0x00000007U +#define RMT_STATE_5_S 22 +/** RMT_MEM_OWNER_ERR_5 : RO; bitpos: [25]; default: 0; + * This status bit will be set when the ownership of memory block is wrong. + */ +#define RMT_MEM_OWNER_ERR_5 (BIT(25)) +#define RMT_MEM_OWNER_ERR_5_M (RMT_MEM_OWNER_ERR_5_V << RMT_MEM_OWNER_ERR_5_S) +#define RMT_MEM_OWNER_ERR_5_V 0x00000001U +#define RMT_MEM_OWNER_ERR_5_S 25 +/** RMT_MEM_FULL_5 : RO; bitpos: [26]; default: 0; + * This status bit will be set if the receiver receives more data than the memory size. + */ +#define RMT_MEM_FULL_5 (BIT(26)) +#define RMT_MEM_FULL_5_M (RMT_MEM_FULL_5_V << RMT_MEM_FULL_5_S) +#define RMT_MEM_FULL_5_V 0x00000001U +#define RMT_MEM_FULL_5_S 26 +/** RMT_APB_MEM_RD_ERR_5 : RO; bitpos: [27]; default: 0; + * This status bit will be set if the offset address out of memory size when reads via + * APB bus. + */ +#define RMT_APB_MEM_RD_ERR_5 (BIT(27)) +#define RMT_APB_MEM_RD_ERR_5_M (RMT_APB_MEM_RD_ERR_5_V << RMT_APB_MEM_RD_ERR_5_S) +#define RMT_APB_MEM_RD_ERR_5_V 0x00000001U +#define RMT_APB_MEM_RD_ERR_5_S 27 -#define RMT_CH6STATUS_REG (DR_REG_RMT_BASE + 0x68) -/* RMT_APB_MEM_RD_ERR_CH6 : RO ;bitpos:[27] ;default: 1'b0 ; */ -/*description: This status bit will be set if the offset address out of memory size when reads -via APB bus..*/ -#define RMT_APB_MEM_RD_ERR_CH6 (BIT(27)) -#define RMT_APB_MEM_RD_ERR_CH6_M (BIT(27)) -#define RMT_APB_MEM_RD_ERR_CH6_V 0x1 -#define RMT_APB_MEM_RD_ERR_CH6_S 27 -/* RMT_MEM_FULL_CH6 : RO ;bitpos:[26] ;default: 1'b0 ; */ -/*description: This status bit will be set if the receiver receives more data than the memory s -ize..*/ -#define RMT_MEM_FULL_CH6 (BIT(26)) -#define RMT_MEM_FULL_CH6_M (BIT(26)) -#define RMT_MEM_FULL_CH6_V 0x1 -#define RMT_MEM_FULL_CH6_S 26 -/* RMT_MEM_OWNER_ERR_CH6 : RO ;bitpos:[25] ;default: 1'b0 ; */ -/*description: This status bit will be set when the ownership of memory block is wrong..*/ -#define RMT_MEM_OWNER_ERR_CH6 (BIT(25)) -#define RMT_MEM_OWNER_ERR_CH6_M (BIT(25)) -#define RMT_MEM_OWNER_ERR_CH6_V 0x1 -#define RMT_MEM_OWNER_ERR_CH6_S 25 -/* RMT_STATE_CH6 : RO ;bitpos:[24:22] ;default: 3'b0 ; */ -/*description: This register records the FSM status of CHANNEL$m..*/ -#define RMT_STATE_CH6 0x00000007 -#define RMT_STATE_CH6_M ((RMT_STATE_CH6_V)<<(RMT_STATE_CH6_S)) -#define RMT_STATE_CH6_V 0x7 -#define RMT_STATE_CH6_S 22 -/* RMT_APB_MEM_RADDR_CH6 : RO ;bitpos:[20:11] ;default: 10'h120 ; */ -/*description: This register records the memory address offset when reads RAM over APB bus..*/ -#define RMT_APB_MEM_RADDR_CH6 0x000003FF -#define RMT_APB_MEM_RADDR_CH6_M ((RMT_APB_MEM_RADDR_CH6_V)<<(RMT_APB_MEM_RADDR_CH6_S)) -#define RMT_APB_MEM_RADDR_CH6_V 0x3FF -#define RMT_APB_MEM_RADDR_CH6_S 11 -/* RMT_MEM_WADDR_EX_CH6 : RO ;bitpos:[9:0] ;default: 10'h120 ; */ -/*description: This register records the memory address offset when receiver of CHANNEL$m is us -ing the RAM..*/ -#define RMT_MEM_WADDR_EX_CH6 0x000003FF -#define RMT_MEM_WADDR_EX_CH6_M ((RMT_MEM_WADDR_EX_CH6_V)<<(RMT_MEM_WADDR_EX_CH6_S)) -#define RMT_MEM_WADDR_EX_CH6_V 0x3FF -#define RMT_MEM_WADDR_EX_CH6_S 0 +/** RMT_CH6STATUS_REG register + * Channel 6 status register + */ +#define RMT_CH6STATUS_REG (DR_REG_RMT_BASE + 0x68) +/** RMT_MEM_WADDR_EX_6 : RO; bitpos: [9:0]; default: 192; + * This register records the memory address offset when receiver of CHANNEL6 is using + * the RAM. + */ +#define RMT_MEM_WADDR_EX_6 0x000003FFU +#define RMT_MEM_WADDR_EX_6_M (RMT_MEM_WADDR_EX_6_V << RMT_MEM_WADDR_EX_6_S) +#define RMT_MEM_WADDR_EX_6_V 0x000003FFU +#define RMT_MEM_WADDR_EX_6_S 0 +/** RMT_APB_MEM_RADDR_6 : RO; bitpos: [20:11]; default: 192; + * This register records the memory address offset when reads RAM over APB bus. + */ +#define RMT_APB_MEM_RADDR_6 0x000003FFU +#define RMT_APB_MEM_RADDR_6_M (RMT_APB_MEM_RADDR_6_V << RMT_APB_MEM_RADDR_6_S) +#define RMT_APB_MEM_RADDR_6_V 0x000003FFU +#define RMT_APB_MEM_RADDR_6_S 11 +/** RMT_STATE_6 : RO; bitpos: [24:22]; default: 0; + * This register records the FSM status of CHANNEL6. + */ +#define RMT_STATE_6 0x00000007U +#define RMT_STATE_6_M (RMT_STATE_6_V << RMT_STATE_6_S) +#define RMT_STATE_6_V 0x00000007U +#define RMT_STATE_6_S 22 +/** RMT_MEM_OWNER_ERR_6 : RO; bitpos: [25]; default: 0; + * This status bit will be set when the ownership of memory block is wrong. + */ +#define RMT_MEM_OWNER_ERR_6 (BIT(25)) +#define RMT_MEM_OWNER_ERR_6_M (RMT_MEM_OWNER_ERR_6_V << RMT_MEM_OWNER_ERR_6_S) +#define RMT_MEM_OWNER_ERR_6_V 0x00000001U +#define RMT_MEM_OWNER_ERR_6_S 25 +/** RMT_MEM_FULL_6 : RO; bitpos: [26]; default: 0; + * This status bit will be set if the receiver receives more data than the memory size. + */ +#define RMT_MEM_FULL_6 (BIT(26)) +#define RMT_MEM_FULL_6_M (RMT_MEM_FULL_6_V << RMT_MEM_FULL_6_S) +#define RMT_MEM_FULL_6_V 0x00000001U +#define RMT_MEM_FULL_6_S 26 +/** RMT_APB_MEM_RD_ERR_6 : RO; bitpos: [27]; default: 0; + * This status bit will be set if the offset address out of memory size when reads via + * APB bus. + */ +#define RMT_APB_MEM_RD_ERR_6 (BIT(27)) +#define RMT_APB_MEM_RD_ERR_6_M (RMT_APB_MEM_RD_ERR_6_V << RMT_APB_MEM_RD_ERR_6_S) +#define RMT_APB_MEM_RD_ERR_6_V 0x00000001U +#define RMT_APB_MEM_RD_ERR_6_S 27 -#define RMT_CH7STATUS_REG (DR_REG_RMT_BASE + 0x6C) -/* RMT_APB_MEM_RD_ERR_CH7 : RO ;bitpos:[27] ;default: 1'b0 ; */ -/*description: This status bit will be set if the offset address out of memory size when reads -via APB bus..*/ -#define RMT_APB_MEM_RD_ERR_CH7 (BIT(27)) -#define RMT_APB_MEM_RD_ERR_CH7_M (BIT(27)) -#define RMT_APB_MEM_RD_ERR_CH7_V 0x1 -#define RMT_APB_MEM_RD_ERR_CH7_S 27 -/* RMT_MEM_FULL_CH7 : RO ;bitpos:[26] ;default: 1'b0 ; */ -/*description: This status bit will be set if the receiver receives more data than the memory s -ize..*/ -#define RMT_MEM_FULL_CH7 (BIT(26)) -#define RMT_MEM_FULL_CH7_M (BIT(26)) -#define RMT_MEM_FULL_CH7_V 0x1 -#define RMT_MEM_FULL_CH7_S 26 -/* RMT_MEM_OWNER_ERR_CH7 : RO ;bitpos:[25] ;default: 1'b0 ; */ -/*description: This status bit will be set when the ownership of memory block is wrong..*/ -#define RMT_MEM_OWNER_ERR_CH7 (BIT(25)) -#define RMT_MEM_OWNER_ERR_CH7_M (BIT(25)) -#define RMT_MEM_OWNER_ERR_CH7_V 0x1 -#define RMT_MEM_OWNER_ERR_CH7_S 25 -/* RMT_STATE_CH7 : RO ;bitpos:[24:22] ;default: 3'b0 ; */ -/*description: This register records the FSM status of CHANNEL$m..*/ -#define RMT_STATE_CH7 0x00000007 -#define RMT_STATE_CH7_M ((RMT_STATE_CH7_V)<<(RMT_STATE_CH7_S)) -#define RMT_STATE_CH7_V 0x7 -#define RMT_STATE_CH7_S 22 -/* RMT_APB_MEM_RADDR_CH7 : RO ;bitpos:[20:11] ;default: 10'h150 ; */ -/*description: This register records the memory address offset when reads RAM over APB bus..*/ -#define RMT_APB_MEM_RADDR_CH7 0x000003FF -#define RMT_APB_MEM_RADDR_CH7_M ((RMT_APB_MEM_RADDR_CH7_V)<<(RMT_APB_MEM_RADDR_CH7_S)) -#define RMT_APB_MEM_RADDR_CH7_V 0x3FF -#define RMT_APB_MEM_RADDR_CH7_S 11 -/* RMT_MEM_WADDR_EX_CH7 : RO ;bitpos:[9:0] ;default: 10'h150 ; */ -/*description: This register records the memory address offset when receiver of CHANNEL$m is us -ing the RAM..*/ -#define RMT_MEM_WADDR_EX_CH7 0x000003FF -#define RMT_MEM_WADDR_EX_CH7_M ((RMT_MEM_WADDR_EX_CH7_V)<<(RMT_MEM_WADDR_EX_CH7_S)) -#define RMT_MEM_WADDR_EX_CH7_V 0x3FF -#define RMT_MEM_WADDR_EX_CH7_S 0 +/** RMT_CH7STATUS_REG register + * Channel 7 status register + */ +#define RMT_CH7STATUS_REG (DR_REG_RMT_BASE + 0x6c) +/** RMT_MEM_WADDR_EX_7 : RO; bitpos: [9:0]; default: 192; + * This register records the memory address offset when receiver of CHANNEL7 is using + * the RAM. + */ +#define RMT_MEM_WADDR_EX_7 0x000003FFU +#define RMT_MEM_WADDR_EX_7_M (RMT_MEM_WADDR_EX_7_V << RMT_MEM_WADDR_EX_7_S) +#define RMT_MEM_WADDR_EX_7_V 0x000003FFU +#define RMT_MEM_WADDR_EX_7_S 0 +/** RMT_APB_MEM_RADDR_7 : RO; bitpos: [20:11]; default: 192; + * This register records the memory address offset when reads RAM over APB bus. + */ +#define RMT_APB_MEM_RADDR_7 0x000003FFU +#define RMT_APB_MEM_RADDR_7_M (RMT_APB_MEM_RADDR_7_V << RMT_APB_MEM_RADDR_7_S) +#define RMT_APB_MEM_RADDR_7_V 0x000003FFU +#define RMT_APB_MEM_RADDR_7_S 11 +/** RMT_STATE_7 : RO; bitpos: [24:22]; default: 0; + * This register records the FSM status of CHANNEL7. + */ +#define RMT_STATE_7 0x00000007U +#define RMT_STATE_7_M (RMT_STATE_7_V << RMT_STATE_7_S) +#define RMT_STATE_7_V 0x00000007U +#define RMT_STATE_7_S 22 +/** RMT_MEM_OWNER_ERR_7 : RO; bitpos: [25]; default: 0; + * This status bit will be set when the ownership of memory block is wrong. + */ +#define RMT_MEM_OWNER_ERR_7 (BIT(25)) +#define RMT_MEM_OWNER_ERR_7_M (RMT_MEM_OWNER_ERR_7_V << RMT_MEM_OWNER_ERR_7_S) +#define RMT_MEM_OWNER_ERR_7_V 0x00000001U +#define RMT_MEM_OWNER_ERR_7_S 25 +/** RMT_MEM_FULL_7 : RO; bitpos: [26]; default: 0; + * This status bit will be set if the receiver receives more data than the memory size. + */ +#define RMT_MEM_FULL_7 (BIT(26)) +#define RMT_MEM_FULL_7_M (RMT_MEM_FULL_7_V << RMT_MEM_FULL_7_S) +#define RMT_MEM_FULL_7_V 0x00000001U +#define RMT_MEM_FULL_7_S 26 +/** RMT_APB_MEM_RD_ERR_7 : RO; bitpos: [27]; default: 0; + * This status bit will be set if the offset address out of memory size when reads via + * APB bus. + */ +#define RMT_APB_MEM_RD_ERR_7 (BIT(27)) +#define RMT_APB_MEM_RD_ERR_7_M (RMT_APB_MEM_RD_ERR_7_V << RMT_APB_MEM_RD_ERR_7_S) +#define RMT_APB_MEM_RD_ERR_7_V 0x00000001U +#define RMT_APB_MEM_RD_ERR_7_S 27 -#define RMT_INT_RAW_REG (DR_REG_RMT_BASE + 0x70) -/* RMT_CH7_DMA_ACCESS_FAIL_INT_RAW : R/WTC/SS ;bitpos:[29] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for CHANNEL$m. Triggered when dma accessing CHANNEL$m fail -s..*/ -#define RMT_CH7_DMA_ACCESS_FAIL_INT_RAW (BIT(29)) -#define RMT_CH7_DMA_ACCESS_FAIL_INT_RAW_M (BIT(29)) -#define RMT_CH7_DMA_ACCESS_FAIL_INT_RAW_V 0x1 -#define RMT_CH7_DMA_ACCESS_FAIL_INT_RAW_S 29 -/* RMT_CH3_DMA_ACCESS_FAIL_INT_RAW : R/WTC/SS ;bitpos:[28] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for CHANNEL$n. Triggered when dma accessing CHANNEL$n fail -s..*/ -#define RMT_CH3_DMA_ACCESS_FAIL_INT_RAW (BIT(28)) -#define RMT_CH3_DMA_ACCESS_FAIL_INT_RAW_M (BIT(28)) -#define RMT_CH3_DMA_ACCESS_FAIL_INT_RAW_V 0x1 -#define RMT_CH3_DMA_ACCESS_FAIL_INT_RAW_S 28 -/* RMT_CH7_RX_THR_EVENT_INT_RAW : R/WTC/SS ;bitpos:[27] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for CHANNEL$m. Triggered when receiver receive more data t -han configured value..*/ -#define RMT_CH7_RX_THR_EVENT_INT_RAW (BIT(27)) -#define RMT_CH7_RX_THR_EVENT_INT_RAW_M (BIT(27)) -#define RMT_CH7_RX_THR_EVENT_INT_RAW_V 0x1 -#define RMT_CH7_RX_THR_EVENT_INT_RAW_S 27 -/* RMT_CH6_RX_THR_EVENT_INT_RAW : R/WTC/SS ;bitpos:[26] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for CHANNEL$m. Triggered when receiver receive more data t -han configured value..*/ -#define RMT_CH6_RX_THR_EVENT_INT_RAW (BIT(26)) -#define RMT_CH6_RX_THR_EVENT_INT_RAW_M (BIT(26)) -#define RMT_CH6_RX_THR_EVENT_INT_RAW_V 0x1 -#define RMT_CH6_RX_THR_EVENT_INT_RAW_S 26 -/* RMT_CH5_RX_THR_EVENT_INT_RAW : R/WTC/SS ;bitpos:[25] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for CHANNEL$m. Triggered when receiver receive more data t -han configured value..*/ -#define RMT_CH5_RX_THR_EVENT_INT_RAW (BIT(25)) -#define RMT_CH5_RX_THR_EVENT_INT_RAW_M (BIT(25)) -#define RMT_CH5_RX_THR_EVENT_INT_RAW_V 0x1 -#define RMT_CH5_RX_THR_EVENT_INT_RAW_S 25 -/* RMT_CH4_RX_THR_EVENT_INT_RAW : R/WTC/SS ;bitpos:[24] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for CHANNEL$m. Triggered when receiver receive more data t -han configured value..*/ -#define RMT_CH4_RX_THR_EVENT_INT_RAW (BIT(24)) -#define RMT_CH4_RX_THR_EVENT_INT_RAW_M (BIT(24)) -#define RMT_CH4_RX_THR_EVENT_INT_RAW_V 0x1 -#define RMT_CH4_RX_THR_EVENT_INT_RAW_S 24 -/* RMT_CH7_ERR_INT_RAW : R/WTC/SS ;bitpos:[23] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for CHANNEL$m. Triggered when error occurs..*/ -#define RMT_CH7_ERR_INT_RAW (BIT(23)) -#define RMT_CH7_ERR_INT_RAW_M (BIT(23)) -#define RMT_CH7_ERR_INT_RAW_V 0x1 -#define RMT_CH7_ERR_INT_RAW_S 23 -/* RMT_CH6_ERR_INT_RAW : R/WTC/SS ;bitpos:[22] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for CHANNEL$m. Triggered when error occurs..*/ -#define RMT_CH6_ERR_INT_RAW (BIT(22)) -#define RMT_CH6_ERR_INT_RAW_M (BIT(22)) -#define RMT_CH6_ERR_INT_RAW_V 0x1 -#define RMT_CH6_ERR_INT_RAW_S 22 -/* RMT_CH5_ERR_INT_RAW : R/WTC/SS ;bitpos:[21] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for CHANNEL$m. Triggered when error occurs..*/ -#define RMT_CH5_ERR_INT_RAW (BIT(21)) -#define RMT_CH5_ERR_INT_RAW_M (BIT(21)) -#define RMT_CH5_ERR_INT_RAW_V 0x1 -#define RMT_CH5_ERR_INT_RAW_S 21 -/* RMT_CH4_ERR_INT_RAW : R/WTC/SS ;bitpos:[20] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for CHANNEL$m. Triggered when error occurs..*/ -#define RMT_CH4_ERR_INT_RAW (BIT(20)) -#define RMT_CH4_ERR_INT_RAW_M (BIT(20)) -#define RMT_CH4_ERR_INT_RAW_V 0x1 -#define RMT_CH4_ERR_INT_RAW_S 20 -/* RMT_CH7_RX_END_INT_RAW : R/WTC/SS ;bitpos:[19] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for CHANNEL$m. Triggered when reception done..*/ -#define RMT_CH7_RX_END_INT_RAW (BIT(19)) -#define RMT_CH7_RX_END_INT_RAW_M (BIT(19)) -#define RMT_CH7_RX_END_INT_RAW_V 0x1 -#define RMT_CH7_RX_END_INT_RAW_S 19 -/* RMT_CH6_RX_END_INT_RAW : R/WTC/SS ;bitpos:[18] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for CHANNEL$m. Triggered when reception done..*/ -#define RMT_CH6_RX_END_INT_RAW (BIT(18)) -#define RMT_CH6_RX_END_INT_RAW_M (BIT(18)) -#define RMT_CH6_RX_END_INT_RAW_V 0x1 -#define RMT_CH6_RX_END_INT_RAW_S 18 -/* RMT_CH5_RX_END_INT_RAW : R/WTC/SS ;bitpos:[17] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for CHANNEL$m. Triggered when reception done..*/ -#define RMT_CH5_RX_END_INT_RAW (BIT(17)) -#define RMT_CH5_RX_END_INT_RAW_M (BIT(17)) -#define RMT_CH5_RX_END_INT_RAW_V 0x1 -#define RMT_CH5_RX_END_INT_RAW_S 17 -/* RMT_CH4_RX_END_INT_RAW : R/WTC/SS ;bitpos:[16] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for CHANNEL$m. Triggered when reception done..*/ -#define RMT_CH4_RX_END_INT_RAW (BIT(16)) -#define RMT_CH4_RX_END_INT_RAW_M (BIT(16)) -#define RMT_CH4_RX_END_INT_RAW_V 0x1 -#define RMT_CH4_RX_END_INT_RAW_S 16 -/* RMT_CH3_TX_LOOP_INT_RAW : R/WTC/SS ;bitpos:[15] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for CHANNEL$n. Triggered when the loop count reaches the c -onfigured threshold value..*/ -#define RMT_CH3_TX_LOOP_INT_RAW (BIT(15)) -#define RMT_CH3_TX_LOOP_INT_RAW_M (BIT(15)) -#define RMT_CH3_TX_LOOP_INT_RAW_V 0x1 -#define RMT_CH3_TX_LOOP_INT_RAW_S 15 -/* RMT_CH2_TX_LOOP_INT_RAW : R/WTC/SS ;bitpos:[14] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for CHANNEL$n. Triggered when the loop count reaches the c -onfigured threshold value..*/ -#define RMT_CH2_TX_LOOP_INT_RAW (BIT(14)) -#define RMT_CH2_TX_LOOP_INT_RAW_M (BIT(14)) -#define RMT_CH2_TX_LOOP_INT_RAW_V 0x1 -#define RMT_CH2_TX_LOOP_INT_RAW_S 14 -/* RMT_CH1_TX_LOOP_INT_RAW : R/WTC/SS ;bitpos:[13] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for CHANNEL$n. Triggered when the loop count reaches the c -onfigured threshold value..*/ -#define RMT_CH1_TX_LOOP_INT_RAW (BIT(13)) -#define RMT_CH1_TX_LOOP_INT_RAW_M (BIT(13)) -#define RMT_CH1_TX_LOOP_INT_RAW_V 0x1 -#define RMT_CH1_TX_LOOP_INT_RAW_S 13 -/* RMT_CH0_TX_LOOP_INT_RAW : R/WTC/SS ;bitpos:[12] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for CHANNEL$n. Triggered when the loop count reaches the c -onfigured threshold value..*/ -#define RMT_CH0_TX_LOOP_INT_RAW (BIT(12)) -#define RMT_CH0_TX_LOOP_INT_RAW_M (BIT(12)) -#define RMT_CH0_TX_LOOP_INT_RAW_V 0x1 -#define RMT_CH0_TX_LOOP_INT_RAW_S 12 -/* RMT_CH3_TX_THR_EVENT_INT_RAW : R/WTC/SS ;bitpos:[11] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for CHANNEL$n. Triggered when transmitter sent more data t -han configured value..*/ -#define RMT_CH3_TX_THR_EVENT_INT_RAW (BIT(11)) -#define RMT_CH3_TX_THR_EVENT_INT_RAW_M (BIT(11)) -#define RMT_CH3_TX_THR_EVENT_INT_RAW_V 0x1 -#define RMT_CH3_TX_THR_EVENT_INT_RAW_S 11 -/* RMT_CH2_TX_THR_EVENT_INT_RAW : R/WTC/SS ;bitpos:[10] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for CHANNEL$n. Triggered when transmitter sent more data t -han configured value..*/ -#define RMT_CH2_TX_THR_EVENT_INT_RAW (BIT(10)) -#define RMT_CH2_TX_THR_EVENT_INT_RAW_M (BIT(10)) -#define RMT_CH2_TX_THR_EVENT_INT_RAW_V 0x1 -#define RMT_CH2_TX_THR_EVENT_INT_RAW_S 10 -/* RMT_CH1_TX_THR_EVENT_INT_RAW : R/WTC/SS ;bitpos:[9] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for CHANNEL$n. Triggered when transmitter sent more data t -han configured value..*/ -#define RMT_CH1_TX_THR_EVENT_INT_RAW (BIT(9)) -#define RMT_CH1_TX_THR_EVENT_INT_RAW_M (BIT(9)) -#define RMT_CH1_TX_THR_EVENT_INT_RAW_V 0x1 -#define RMT_CH1_TX_THR_EVENT_INT_RAW_S 9 -/* RMT_CH0_TX_THR_EVENT_INT_RAW : R/WTC/SS ;bitpos:[8] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for CHANNEL$n. Triggered when transmitter sent more data t -han configured value..*/ -#define RMT_CH0_TX_THR_EVENT_INT_RAW (BIT(8)) -#define RMT_CH0_TX_THR_EVENT_INT_RAW_M (BIT(8)) -#define RMT_CH0_TX_THR_EVENT_INT_RAW_V 0x1 -#define RMT_CH0_TX_THR_EVENT_INT_RAW_S 8 -/* RMT_CH3_ERR_INT_RAW : R/WTC/SS ;bitpos:[7] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for CHANNEL$n. Triggered when error occurs..*/ -#define RMT_CH3_ERR_INT_RAW (BIT(7)) -#define RMT_CH3_ERR_INT_RAW_M (BIT(7)) -#define RMT_CH3_ERR_INT_RAW_V 0x1 -#define RMT_CH3_ERR_INT_RAW_S 7 -/* RMT_CH2_ERR_INT_RAW : R/WTC/SS ;bitpos:[6] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for CHANNEL$n. Triggered when error occurs..*/ -#define RMT_CH2_ERR_INT_RAW (BIT(6)) -#define RMT_CH2_ERR_INT_RAW_M (BIT(6)) -#define RMT_CH2_ERR_INT_RAW_V 0x1 -#define RMT_CH2_ERR_INT_RAW_S 6 -/* RMT_CH1_ERR_INT_RAW : R/WTC/SS ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for CHANNEL$n. Triggered when error occurs..*/ -#define RMT_CH1_ERR_INT_RAW (BIT(5)) -#define RMT_CH1_ERR_INT_RAW_M (BIT(5)) -#define RMT_CH1_ERR_INT_RAW_V 0x1 -#define RMT_CH1_ERR_INT_RAW_S 5 -/* RMT_CH0_ERR_INT_RAW : R/WTC/SS ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for CHANNEL$n. Triggered when error occurs..*/ -#define RMT_CH0_ERR_INT_RAW (BIT(4)) -#define RMT_CH0_ERR_INT_RAW_M (BIT(4)) -#define RMT_CH0_ERR_INT_RAW_V 0x1 -#define RMT_CH0_ERR_INT_RAW_S 4 -/* RMT_CH3_TX_END_INT_RAW : R/WTC/SS ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for CHANNEL$n. Triggered when transmission done..*/ -#define RMT_CH3_TX_END_INT_RAW (BIT(3)) -#define RMT_CH3_TX_END_INT_RAW_M (BIT(3)) -#define RMT_CH3_TX_END_INT_RAW_V 0x1 -#define RMT_CH3_TX_END_INT_RAW_S 3 -/* RMT_CH2_TX_END_INT_RAW : R/WTC/SS ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for CHANNEL$n. Triggered when transmission done..*/ -#define RMT_CH2_TX_END_INT_RAW (BIT(2)) -#define RMT_CH2_TX_END_INT_RAW_M (BIT(2)) -#define RMT_CH2_TX_END_INT_RAW_V 0x1 -#define RMT_CH2_TX_END_INT_RAW_S 2 -/* RMT_CH1_TX_END_INT_RAW : R/WTC/SS ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for CHANNEL$n. Triggered when transmission done..*/ -#define RMT_CH1_TX_END_INT_RAW (BIT(1)) -#define RMT_CH1_TX_END_INT_RAW_M (BIT(1)) -#define RMT_CH1_TX_END_INT_RAW_V 0x1 -#define RMT_CH1_TX_END_INT_RAW_S 1 -/* RMT_CH0_TX_END_INT_RAW : R/WTC/SS ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The interrupt raw bit for CHANNEL$n. Triggered when transmission done..*/ +/** RMT_INT_RAW_REG register + * Raw interrupt status + */ +#define RMT_INT_RAW_REG (DR_REG_RMT_BASE + 0x70) +/** RMT_CH0_TX_END_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0; + * The interrupt raw bit for CHANNEL0. Triggered when transmission done. + */ #define RMT_CH0_TX_END_INT_RAW (BIT(0)) -#define RMT_CH0_TX_END_INT_RAW_M (BIT(0)) -#define RMT_CH0_TX_END_INT_RAW_V 0x1 +#define RMT_CH0_TX_END_INT_RAW_M (RMT_CH0_TX_END_INT_RAW_V << RMT_CH0_TX_END_INT_RAW_S) +#define RMT_CH0_TX_END_INT_RAW_V 0x00000001U #define RMT_CH0_TX_END_INT_RAW_S 0 +/** RMT_CH1_TX_END_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0; + * The interrupt raw bit for CHANNEL1. Triggered when transmission done. + */ +#define RMT_CH1_TX_END_INT_RAW (BIT(1)) +#define RMT_CH1_TX_END_INT_RAW_M (RMT_CH1_TX_END_INT_RAW_V << RMT_CH1_TX_END_INT_RAW_S) +#define RMT_CH1_TX_END_INT_RAW_V 0x00000001U +#define RMT_CH1_TX_END_INT_RAW_S 1 +/** RMT_CH2_TX_END_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0; + * The interrupt raw bit for CHANNEL2. Triggered when transmission done. + */ +#define RMT_CH2_TX_END_INT_RAW (BIT(2)) +#define RMT_CH2_TX_END_INT_RAW_M (RMT_CH2_TX_END_INT_RAW_V << RMT_CH2_TX_END_INT_RAW_S) +#define RMT_CH2_TX_END_INT_RAW_V 0x00000001U +#define RMT_CH2_TX_END_INT_RAW_S 2 +/** RMT_CH3_TX_END_INT_RAW : R/WTC/SS; bitpos: [3]; default: 0; + * The interrupt raw bit for CHANNEL3. Triggered when transmission done. + */ +#define RMT_CH3_TX_END_INT_RAW (BIT(3)) +#define RMT_CH3_TX_END_INT_RAW_M (RMT_CH3_TX_END_INT_RAW_V << RMT_CH3_TX_END_INT_RAW_S) +#define RMT_CH3_TX_END_INT_RAW_V 0x00000001U +#define RMT_CH3_TX_END_INT_RAW_S 3 +/** RMT_CH0_ERR_INT_RAW : R/WTC/SS; bitpos: [4]; default: 0; + * The interrupt raw bit for CHANNEL0. Triggered when error occurs. + */ +#define RMT_CH0_ERR_INT_RAW (BIT(4)) +#define RMT_CH0_ERR_INT_RAW_M (RMT_CH0_ERR_INT_RAW_V << RMT_CH0_ERR_INT_RAW_S) +#define RMT_CH0_ERR_INT_RAW_V 0x00000001U +#define RMT_CH0_ERR_INT_RAW_S 4 +/** RMT_CH1_ERR_INT_RAW : R/WTC/SS; bitpos: [5]; default: 0; + * The interrupt raw bit for CHANNEL1. Triggered when error occurs. + */ +#define RMT_CH1_ERR_INT_RAW (BIT(5)) +#define RMT_CH1_ERR_INT_RAW_M (RMT_CH1_ERR_INT_RAW_V << RMT_CH1_ERR_INT_RAW_S) +#define RMT_CH1_ERR_INT_RAW_V 0x00000001U +#define RMT_CH1_ERR_INT_RAW_S 5 +/** RMT_CH2_ERR_INT_RAW : R/WTC/SS; bitpos: [6]; default: 0; + * The interrupt raw bit for CHANNEL2. Triggered when error occurs. + */ +#define RMT_CH2_ERR_INT_RAW (BIT(6)) +#define RMT_CH2_ERR_INT_RAW_M (RMT_CH2_ERR_INT_RAW_V << RMT_CH2_ERR_INT_RAW_S) +#define RMT_CH2_ERR_INT_RAW_V 0x00000001U +#define RMT_CH2_ERR_INT_RAW_S 6 +/** RMT_CH3_ERR_INT_RAW : R/WTC/SS; bitpos: [7]; default: 0; + * The interrupt raw bit for CHANNEL3. Triggered when error occurs. + */ +#define RMT_CH3_ERR_INT_RAW (BIT(7)) +#define RMT_CH3_ERR_INT_RAW_M (RMT_CH3_ERR_INT_RAW_V << RMT_CH3_ERR_INT_RAW_S) +#define RMT_CH3_ERR_INT_RAW_V 0x00000001U +#define RMT_CH3_ERR_INT_RAW_S 7 +/** RMT_CH0_TX_THR_EVENT_INT_RAW : R/WTC/SS; bitpos: [8]; default: 0; + * The interrupt raw bit for CHANNEL0. Triggered when transmitter sent more data than + * configured value. + */ +#define RMT_CH0_TX_THR_EVENT_INT_RAW (BIT(8)) +#define RMT_CH0_TX_THR_EVENT_INT_RAW_M (RMT_CH0_TX_THR_EVENT_INT_RAW_V << RMT_CH0_TX_THR_EVENT_INT_RAW_S) +#define RMT_CH0_TX_THR_EVENT_INT_RAW_V 0x00000001U +#define RMT_CH0_TX_THR_EVENT_INT_RAW_S 8 +/** RMT_CH1_TX_THR_EVENT_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0; + * The interrupt raw bit for CHANNEL1. Triggered when transmitter sent more data than + * configured value. + */ +#define RMT_CH1_TX_THR_EVENT_INT_RAW (BIT(9)) +#define RMT_CH1_TX_THR_EVENT_INT_RAW_M (RMT_CH1_TX_THR_EVENT_INT_RAW_V << RMT_CH1_TX_THR_EVENT_INT_RAW_S) +#define RMT_CH1_TX_THR_EVENT_INT_RAW_V 0x00000001U +#define RMT_CH1_TX_THR_EVENT_INT_RAW_S 9 +/** RMT_CH2_TX_THR_EVENT_INT_RAW : R/WTC/SS; bitpos: [10]; default: 0; + * The interrupt raw bit for CHANNEL2. Triggered when transmitter sent more data than + * configured value. + */ +#define RMT_CH2_TX_THR_EVENT_INT_RAW (BIT(10)) +#define RMT_CH2_TX_THR_EVENT_INT_RAW_M (RMT_CH2_TX_THR_EVENT_INT_RAW_V << RMT_CH2_TX_THR_EVENT_INT_RAW_S) +#define RMT_CH2_TX_THR_EVENT_INT_RAW_V 0x00000001U +#define RMT_CH2_TX_THR_EVENT_INT_RAW_S 10 +/** RMT_CH3_TX_THR_EVENT_INT_RAW : R/WTC/SS; bitpos: [11]; default: 0; + * The interrupt raw bit for CHANNEL3. Triggered when transmitter sent more data than + * configured value. + */ +#define RMT_CH3_TX_THR_EVENT_INT_RAW (BIT(11)) +#define RMT_CH3_TX_THR_EVENT_INT_RAW_M (RMT_CH3_TX_THR_EVENT_INT_RAW_V << RMT_CH3_TX_THR_EVENT_INT_RAW_S) +#define RMT_CH3_TX_THR_EVENT_INT_RAW_V 0x00000001U +#define RMT_CH3_TX_THR_EVENT_INT_RAW_S 11 +/** RMT_CH0_TX_LOOP_INT_RAW : R/WTC/SS; bitpos: [12]; default: 0; + * The interrupt raw bit for CHANNEL0. Triggered when the loop count reaches the + * configured threshold value. + */ +#define RMT_CH0_TX_LOOP_INT_RAW (BIT(12)) +#define RMT_CH0_TX_LOOP_INT_RAW_M (RMT_CH0_TX_LOOP_INT_RAW_V << RMT_CH0_TX_LOOP_INT_RAW_S) +#define RMT_CH0_TX_LOOP_INT_RAW_V 0x00000001U +#define RMT_CH0_TX_LOOP_INT_RAW_S 12 +/** RMT_CH1_TX_LOOP_INT_RAW : R/WTC/SS; bitpos: [13]; default: 0; + * The interrupt raw bit for CHANNEL1. Triggered when the loop count reaches the + * configured threshold value. + */ +#define RMT_CH1_TX_LOOP_INT_RAW (BIT(13)) +#define RMT_CH1_TX_LOOP_INT_RAW_M (RMT_CH1_TX_LOOP_INT_RAW_V << RMT_CH1_TX_LOOP_INT_RAW_S) +#define RMT_CH1_TX_LOOP_INT_RAW_V 0x00000001U +#define RMT_CH1_TX_LOOP_INT_RAW_S 13 +/** RMT_CH2_TX_LOOP_INT_RAW : R/WTC/SS; bitpos: [14]; default: 0; + * The interrupt raw bit for CHANNEL2. Triggered when the loop count reaches the + * configured threshold value. + */ +#define RMT_CH2_TX_LOOP_INT_RAW (BIT(14)) +#define RMT_CH2_TX_LOOP_INT_RAW_M (RMT_CH2_TX_LOOP_INT_RAW_V << RMT_CH2_TX_LOOP_INT_RAW_S) +#define RMT_CH2_TX_LOOP_INT_RAW_V 0x00000001U +#define RMT_CH2_TX_LOOP_INT_RAW_S 14 +/** RMT_CH3_TX_LOOP_INT_RAW : R/WTC/SS; bitpos: [15]; default: 0; + * The interrupt raw bit for CHANNEL3. Triggered when the loop count reaches the + * configured threshold value. + */ +#define RMT_CH3_TX_LOOP_INT_RAW (BIT(15)) +#define RMT_CH3_TX_LOOP_INT_RAW_M (RMT_CH3_TX_LOOP_INT_RAW_V << RMT_CH3_TX_LOOP_INT_RAW_S) +#define RMT_CH3_TX_LOOP_INT_RAW_V 0x00000001U +#define RMT_CH3_TX_LOOP_INT_RAW_S 15 +/** RMT_CH4_RX_END_INT_RAW : R/WTC/SS; bitpos: [16]; default: 0; + * The interrupt raw bit for CHANNEL4. Triggered when reception done. + */ +#define RMT_CH4_RX_END_INT_RAW (BIT(16)) +#define RMT_CH4_RX_END_INT_RAW_M (RMT_CH4_RX_END_INT_RAW_V << RMT_CH4_RX_END_INT_RAW_S) +#define RMT_CH4_RX_END_INT_RAW_V 0x00000001U +#define RMT_CH4_RX_END_INT_RAW_S 16 +/** RMT_CH5_RX_END_INT_RAW : R/WTC/SS; bitpos: [17]; default: 0; + * The interrupt raw bit for CHANNEL5. Triggered when reception done. + */ +#define RMT_CH5_RX_END_INT_RAW (BIT(17)) +#define RMT_CH5_RX_END_INT_RAW_M (RMT_CH5_RX_END_INT_RAW_V << RMT_CH5_RX_END_INT_RAW_S) +#define RMT_CH5_RX_END_INT_RAW_V 0x00000001U +#define RMT_CH5_RX_END_INT_RAW_S 17 +/** RMT_CH6_RX_END_INT_RAW : R/WTC/SS; bitpos: [18]; default: 0; + * The interrupt raw bit for CHANNEL6. Triggered when reception done. + */ +#define RMT_CH6_RX_END_INT_RAW (BIT(18)) +#define RMT_CH6_RX_END_INT_RAW_M (RMT_CH6_RX_END_INT_RAW_V << RMT_CH6_RX_END_INT_RAW_S) +#define RMT_CH6_RX_END_INT_RAW_V 0x00000001U +#define RMT_CH6_RX_END_INT_RAW_S 18 +/** RMT_CH7_RX_END_INT_RAW : R/WTC/SS; bitpos: [19]; default: 0; + * The interrupt raw bit for CHANNEL7. Triggered when reception done. + */ +#define RMT_CH7_RX_END_INT_RAW (BIT(19)) +#define RMT_CH7_RX_END_INT_RAW_M (RMT_CH7_RX_END_INT_RAW_V << RMT_CH7_RX_END_INT_RAW_S) +#define RMT_CH7_RX_END_INT_RAW_V 0x00000001U +#define RMT_CH7_RX_END_INT_RAW_S 19 +/** RMT_CH4_ERR_INT_RAW : R/WTC/SS; bitpos: [20]; default: 0; + * The interrupt raw bit for CHANNEL4. Triggered when error occurs. + */ +#define RMT_CH4_ERR_INT_RAW (BIT(20)) +#define RMT_CH4_ERR_INT_RAW_M (RMT_CH4_ERR_INT_RAW_V << RMT_CH4_ERR_INT_RAW_S) +#define RMT_CH4_ERR_INT_RAW_V 0x00000001U +#define RMT_CH4_ERR_INT_RAW_S 20 +/** RMT_CH5_ERR_INT_RAW : R/WTC/SS; bitpos: [21]; default: 0; + * The interrupt raw bit for CHANNEL5. Triggered when error occurs. + */ +#define RMT_CH5_ERR_INT_RAW (BIT(21)) +#define RMT_CH5_ERR_INT_RAW_M (RMT_CH5_ERR_INT_RAW_V << RMT_CH5_ERR_INT_RAW_S) +#define RMT_CH5_ERR_INT_RAW_V 0x00000001U +#define RMT_CH5_ERR_INT_RAW_S 21 +/** RMT_CH6_ERR_INT_RAW : R/WTC/SS; bitpos: [22]; default: 0; + * The interrupt raw bit for CHANNEL6. Triggered when error occurs. + */ +#define RMT_CH6_ERR_INT_RAW (BIT(22)) +#define RMT_CH6_ERR_INT_RAW_M (RMT_CH6_ERR_INT_RAW_V << RMT_CH6_ERR_INT_RAW_S) +#define RMT_CH6_ERR_INT_RAW_V 0x00000001U +#define RMT_CH6_ERR_INT_RAW_S 22 +/** RMT_CH7_ERR_INT_RAW : R/WTC/SS; bitpos: [23]; default: 0; + * The interrupt raw bit for CHANNEL7. Triggered when error occurs. + */ +#define RMT_CH7_ERR_INT_RAW (BIT(23)) +#define RMT_CH7_ERR_INT_RAW_M (RMT_CH7_ERR_INT_RAW_V << RMT_CH7_ERR_INT_RAW_S) +#define RMT_CH7_ERR_INT_RAW_V 0x00000001U +#define RMT_CH7_ERR_INT_RAW_S 23 +/** RMT_CH4_RX_THR_EVENT_INT_RAW : R/WTC/SS; bitpos: [24]; default: 0; + * The interrupt raw bit for CHANNEL4. Triggered when receiver receive more data than + * configured value. + */ +#define RMT_CH4_RX_THR_EVENT_INT_RAW (BIT(24)) +#define RMT_CH4_RX_THR_EVENT_INT_RAW_M (RMT_CH4_RX_THR_EVENT_INT_RAW_V << RMT_CH4_RX_THR_EVENT_INT_RAW_S) +#define RMT_CH4_RX_THR_EVENT_INT_RAW_V 0x00000001U +#define RMT_CH4_RX_THR_EVENT_INT_RAW_S 24 +/** RMT_CH5_RX_THR_EVENT_INT_RAW : R/WTC/SS; bitpos: [25]; default: 0; + * The interrupt raw bit for CHANNEL5. Triggered when receiver receive more data than + * configured value. + */ +#define RMT_CH5_RX_THR_EVENT_INT_RAW (BIT(25)) +#define RMT_CH5_RX_THR_EVENT_INT_RAW_M (RMT_CH5_RX_THR_EVENT_INT_RAW_V << RMT_CH5_RX_THR_EVENT_INT_RAW_S) +#define RMT_CH5_RX_THR_EVENT_INT_RAW_V 0x00000001U +#define RMT_CH5_RX_THR_EVENT_INT_RAW_S 25 +/** RMT_CH6_RX_THR_EVENT_INT_RAW : R/WTC/SS; bitpos: [26]; default: 0; + * The interrupt raw bit for CHANNEL6. Triggered when receiver receive more data than + * configured value. + */ +#define RMT_CH6_RX_THR_EVENT_INT_RAW (BIT(26)) +#define RMT_CH6_RX_THR_EVENT_INT_RAW_M (RMT_CH6_RX_THR_EVENT_INT_RAW_V << RMT_CH6_RX_THR_EVENT_INT_RAW_S) +#define RMT_CH6_RX_THR_EVENT_INT_RAW_V 0x00000001U +#define RMT_CH6_RX_THR_EVENT_INT_RAW_S 26 +/** RMT_CH7_RX_THR_EVENT_INT_RAW : R/WTC/SS; bitpos: [27]; default: 0; + * The interrupt raw bit for CHANNEL7. Triggered when receiver receive more data than + * configured value. + */ +#define RMT_CH7_RX_THR_EVENT_INT_RAW (BIT(27)) +#define RMT_CH7_RX_THR_EVENT_INT_RAW_M (RMT_CH7_RX_THR_EVENT_INT_RAW_V << RMT_CH7_RX_THR_EVENT_INT_RAW_S) +#define RMT_CH7_RX_THR_EVENT_INT_RAW_V 0x00000001U +#define RMT_CH7_RX_THR_EVENT_INT_RAW_S 27 +/** RMT_CH3_DMA_ACCESS_FAIL_INT_RAW : R/WTC/SS; bitpos: [28]; default: 0; + * The interrupt raw bit for CHANNEL3. Triggered when dma accessing CHANNEL3 fails. + */ +#define RMT_CH3_DMA_ACCESS_FAIL_INT_RAW (BIT(28)) +#define RMT_CH3_DMA_ACCESS_FAIL_INT_RAW_M (RMT_CH3_DMA_ACCESS_FAIL_INT_RAW_V << RMT_CH3_DMA_ACCESS_FAIL_INT_RAW_S) +#define RMT_CH3_DMA_ACCESS_FAIL_INT_RAW_V 0x00000001U +#define RMT_CH3_DMA_ACCESS_FAIL_INT_RAW_S 28 +/** RMT_CH7_DMA_ACCESS_FAIL_INT_RAW : R/WTC/SS; bitpos: [29]; default: 0; + * The interrupt raw bit for CHANNEL7. Triggered when dma accessing CHANNEL7 fails. + */ +#define RMT_CH7_DMA_ACCESS_FAIL_INT_RAW (BIT(29)) +#define RMT_CH7_DMA_ACCESS_FAIL_INT_RAW_M (RMT_CH7_DMA_ACCESS_FAIL_INT_RAW_V << RMT_CH7_DMA_ACCESS_FAIL_INT_RAW_S) +#define RMT_CH7_DMA_ACCESS_FAIL_INT_RAW_V 0x00000001U +#define RMT_CH7_DMA_ACCESS_FAIL_INT_RAW_S 29 -#define RMT_INT_ST_REG (DR_REG_RMT_BASE + 0x74) -/* RMT_CH7_DMA_ACCESS_FAIL_INT_ST : RO ;bitpos:[29] ;default: 1'b0 ; */ -/*description: The masked interrupt status bit for CH$m_DMA_ACCESS_FAIL_INT..*/ -#define RMT_CH7_DMA_ACCESS_FAIL_INT_ST (BIT(29)) -#define RMT_CH7_DMA_ACCESS_FAIL_INT_ST_M (BIT(29)) -#define RMT_CH7_DMA_ACCESS_FAIL_INT_ST_V 0x1 -#define RMT_CH7_DMA_ACCESS_FAIL_INT_ST_S 29 -/* RMT_CH3_DMA_ACCESS_FAIL_INT_ST : RO ;bitpos:[28] ;default: 1'b0 ; */ -/*description: The masked interrupt status bit for CH$n_DMA_ACCESS_FAIL_INT..*/ -#define RMT_CH3_DMA_ACCESS_FAIL_INT_ST (BIT(28)) -#define RMT_CH3_DMA_ACCESS_FAIL_INT_ST_M (BIT(28)) -#define RMT_CH3_DMA_ACCESS_FAIL_INT_ST_V 0x1 -#define RMT_CH3_DMA_ACCESS_FAIL_INT_ST_S 28 -/* RMT_CH7_RX_THR_EVENT_INT_ST : RO ;bitpos:[27] ;default: 1'b0 ; */ -/*description: The masked interrupt status bit for CH$m_RX_THR_EVENT_INT..*/ -#define RMT_CH7_RX_THR_EVENT_INT_ST (BIT(27)) -#define RMT_CH7_RX_THR_EVENT_INT_ST_M (BIT(27)) -#define RMT_CH7_RX_THR_EVENT_INT_ST_V 0x1 -#define RMT_CH7_RX_THR_EVENT_INT_ST_S 27 -/* RMT_CH6_RX_THR_EVENT_INT_ST : RO ;bitpos:[26] ;default: 1'b0 ; */ -/*description: The masked interrupt status bit for CH$m_RX_THR_EVENT_INT..*/ -#define RMT_CH6_RX_THR_EVENT_INT_ST (BIT(26)) -#define RMT_CH6_RX_THR_EVENT_INT_ST_M (BIT(26)) -#define RMT_CH6_RX_THR_EVENT_INT_ST_V 0x1 -#define RMT_CH6_RX_THR_EVENT_INT_ST_S 26 -/* RMT_CH5_RX_THR_EVENT_INT_ST : RO ;bitpos:[25] ;default: 1'b0 ; */ -/*description: The masked interrupt status bit for CH$m_RX_THR_EVENT_INT..*/ -#define RMT_CH5_RX_THR_EVENT_INT_ST (BIT(25)) -#define RMT_CH5_RX_THR_EVENT_INT_ST_M (BIT(25)) -#define RMT_CH5_RX_THR_EVENT_INT_ST_V 0x1 -#define RMT_CH5_RX_THR_EVENT_INT_ST_S 25 -/* RMT_CH4_RX_THR_EVENT_INT_ST : RO ;bitpos:[24] ;default: 1'b0 ; */ -/*description: The masked interrupt status bit for CH$m_RX_THR_EVENT_INT..*/ -#define RMT_CH4_RX_THR_EVENT_INT_ST (BIT(24)) -#define RMT_CH4_RX_THR_EVENT_INT_ST_M (BIT(24)) -#define RMT_CH4_RX_THR_EVENT_INT_ST_V 0x1 -#define RMT_CH4_RX_THR_EVENT_INT_ST_S 24 -/* RMT_CH7_ERR_INT_ST : RO ;bitpos:[23] ;default: 1'b0 ; */ -/*description: The masked interrupt status bit for CH$m_ERR_INT..*/ -#define RMT_CH7_ERR_INT_ST (BIT(23)) -#define RMT_CH7_ERR_INT_ST_M (BIT(23)) -#define RMT_CH7_ERR_INT_ST_V 0x1 -#define RMT_CH7_ERR_INT_ST_S 23 -/* RMT_CH6_ERR_INT_ST : RO ;bitpos:[22] ;default: 1'b0 ; */ -/*description: The masked interrupt status bit for CH$m_ERR_INT..*/ -#define RMT_CH6_ERR_INT_ST (BIT(22)) -#define RMT_CH6_ERR_INT_ST_M (BIT(22)) -#define RMT_CH6_ERR_INT_ST_V 0x1 -#define RMT_CH6_ERR_INT_ST_S 22 -/* RMT_CH5_ERR_INT_ST : RO ;bitpos:[21] ;default: 1'b0 ; */ -/*description: The masked interrupt status bit for CH$m_ERR_INT..*/ -#define RMT_CH5_ERR_INT_ST (BIT(21)) -#define RMT_CH5_ERR_INT_ST_M (BIT(21)) -#define RMT_CH5_ERR_INT_ST_V 0x1 -#define RMT_CH5_ERR_INT_ST_S 21 -/* RMT_CH4_ERR_INT_ST : RO ;bitpos:[20] ;default: 1'b0 ; */ -/*description: The masked interrupt status bit for CH$m_ERR_INT..*/ -#define RMT_CH4_ERR_INT_ST (BIT(20)) -#define RMT_CH4_ERR_INT_ST_M (BIT(20)) -#define RMT_CH4_ERR_INT_ST_V 0x1 -#define RMT_CH4_ERR_INT_ST_S 20 -/* RMT_CH7_RX_END_INT_ST : RO ;bitpos:[19] ;default: 1'b0 ; */ -/*description: The masked interrupt status bit for CH$m_RX_END_INT..*/ -#define RMT_CH7_RX_END_INT_ST (BIT(19)) -#define RMT_CH7_RX_END_INT_ST_M (BIT(19)) -#define RMT_CH7_RX_END_INT_ST_V 0x1 -#define RMT_CH7_RX_END_INT_ST_S 19 -/* RMT_CH6_RX_END_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */ -/*description: The masked interrupt status bit for CH$m_RX_END_INT..*/ -#define RMT_CH6_RX_END_INT_ST (BIT(18)) -#define RMT_CH6_RX_END_INT_ST_M (BIT(18)) -#define RMT_CH6_RX_END_INT_ST_V 0x1 -#define RMT_CH6_RX_END_INT_ST_S 18 -/* RMT_CH5_RX_END_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */ -/*description: The masked interrupt status bit for CH$m_RX_END_INT..*/ -#define RMT_CH5_RX_END_INT_ST (BIT(17)) -#define RMT_CH5_RX_END_INT_ST_M (BIT(17)) -#define RMT_CH5_RX_END_INT_ST_V 0x1 -#define RMT_CH5_RX_END_INT_ST_S 17 -/* RMT_CH4_RX_END_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */ -/*description: The masked interrupt status bit for CH$m_RX_END_INT..*/ -#define RMT_CH4_RX_END_INT_ST (BIT(16)) -#define RMT_CH4_RX_END_INT_ST_M (BIT(16)) -#define RMT_CH4_RX_END_INT_ST_V 0x1 -#define RMT_CH4_RX_END_INT_ST_S 16 -/* RMT_CH3_TX_LOOP_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */ -/*description: The masked interrupt status bit for CH$n_TX_LOOP_INT..*/ -#define RMT_CH3_TX_LOOP_INT_ST (BIT(15)) -#define RMT_CH3_TX_LOOP_INT_ST_M (BIT(15)) -#define RMT_CH3_TX_LOOP_INT_ST_V 0x1 -#define RMT_CH3_TX_LOOP_INT_ST_S 15 -/* RMT_CH2_TX_LOOP_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */ -/*description: The masked interrupt status bit for CH$n_TX_LOOP_INT..*/ -#define RMT_CH2_TX_LOOP_INT_ST (BIT(14)) -#define RMT_CH2_TX_LOOP_INT_ST_M (BIT(14)) -#define RMT_CH2_TX_LOOP_INT_ST_V 0x1 -#define RMT_CH2_TX_LOOP_INT_ST_S 14 -/* RMT_CH1_TX_LOOP_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */ -/*description: The masked interrupt status bit for CH$n_TX_LOOP_INT..*/ -#define RMT_CH1_TX_LOOP_INT_ST (BIT(13)) -#define RMT_CH1_TX_LOOP_INT_ST_M (BIT(13)) -#define RMT_CH1_TX_LOOP_INT_ST_V 0x1 -#define RMT_CH1_TX_LOOP_INT_ST_S 13 -/* RMT_CH0_TX_LOOP_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */ -/*description: The masked interrupt status bit for CH$n_TX_LOOP_INT..*/ -#define RMT_CH0_TX_LOOP_INT_ST (BIT(12)) -#define RMT_CH0_TX_LOOP_INT_ST_M (BIT(12)) -#define RMT_CH0_TX_LOOP_INT_ST_V 0x1 -#define RMT_CH0_TX_LOOP_INT_ST_S 12 -/* RMT_CH3_TX_THR_EVENT_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ -/*description: The masked interrupt status bit for CH$n_TX_THR_EVENT_INT..*/ -#define RMT_CH3_TX_THR_EVENT_INT_ST (BIT(11)) -#define RMT_CH3_TX_THR_EVENT_INT_ST_M (BIT(11)) -#define RMT_CH3_TX_THR_EVENT_INT_ST_V 0x1 -#define RMT_CH3_TX_THR_EVENT_INT_ST_S 11 -/* RMT_CH2_TX_THR_EVENT_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ -/*description: The masked interrupt status bit for CH$n_TX_THR_EVENT_INT..*/ -#define RMT_CH2_TX_THR_EVENT_INT_ST (BIT(10)) -#define RMT_CH2_TX_THR_EVENT_INT_ST_M (BIT(10)) -#define RMT_CH2_TX_THR_EVENT_INT_ST_V 0x1 -#define RMT_CH2_TX_THR_EVENT_INT_ST_S 10 -/* RMT_CH1_TX_THR_EVENT_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ -/*description: The masked interrupt status bit for CH$n_TX_THR_EVENT_INT..*/ -#define RMT_CH1_TX_THR_EVENT_INT_ST (BIT(9)) -#define RMT_CH1_TX_THR_EVENT_INT_ST_M (BIT(9)) -#define RMT_CH1_TX_THR_EVENT_INT_ST_V 0x1 -#define RMT_CH1_TX_THR_EVENT_INT_ST_S 9 -/* RMT_CH0_TX_THR_EVENT_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ -/*description: The masked interrupt status bit for CH$n_TX_THR_EVENT_INT..*/ -#define RMT_CH0_TX_THR_EVENT_INT_ST (BIT(8)) -#define RMT_CH0_TX_THR_EVENT_INT_ST_M (BIT(8)) -#define RMT_CH0_TX_THR_EVENT_INT_ST_V 0x1 -#define RMT_CH0_TX_THR_EVENT_INT_ST_S 8 -/* RMT_CH3_ERR_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ -/*description: The masked interrupt status bit for CH$n_ERR_INT..*/ -#define RMT_CH3_ERR_INT_ST (BIT(7)) -#define RMT_CH3_ERR_INT_ST_M (BIT(7)) -#define RMT_CH3_ERR_INT_ST_V 0x1 -#define RMT_CH3_ERR_INT_ST_S 7 -/* RMT_CH2_ERR_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ -/*description: The masked interrupt status bit for CH$n_ERR_INT..*/ -#define RMT_CH2_ERR_INT_ST (BIT(6)) -#define RMT_CH2_ERR_INT_ST_M (BIT(6)) -#define RMT_CH2_ERR_INT_ST_V 0x1 -#define RMT_CH2_ERR_INT_ST_S 6 -/* RMT_CH1_ERR_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The masked interrupt status bit for CH$n_ERR_INT..*/ -#define RMT_CH1_ERR_INT_ST (BIT(5)) -#define RMT_CH1_ERR_INT_ST_M (BIT(5)) -#define RMT_CH1_ERR_INT_ST_V 0x1 -#define RMT_CH1_ERR_INT_ST_S 5 -/* RMT_CH0_ERR_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The masked interrupt status bit for CH$n_ERR_INT..*/ -#define RMT_CH0_ERR_INT_ST (BIT(4)) -#define RMT_CH0_ERR_INT_ST_M (BIT(4)) -#define RMT_CH0_ERR_INT_ST_V 0x1 -#define RMT_CH0_ERR_INT_ST_S 4 -/* RMT_CH3_TX_END_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The masked interrupt status bit for CH$n_TX_END_INT..*/ -#define RMT_CH3_TX_END_INT_ST (BIT(3)) -#define RMT_CH3_TX_END_INT_ST_M (BIT(3)) -#define RMT_CH3_TX_END_INT_ST_V 0x1 -#define RMT_CH3_TX_END_INT_ST_S 3 -/* RMT_CH2_TX_END_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The masked interrupt status bit for CH$n_TX_END_INT..*/ -#define RMT_CH2_TX_END_INT_ST (BIT(2)) -#define RMT_CH2_TX_END_INT_ST_M (BIT(2)) -#define RMT_CH2_TX_END_INT_ST_V 0x1 -#define RMT_CH2_TX_END_INT_ST_S 2 -/* RMT_CH1_TX_END_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The masked interrupt status bit for CH$n_TX_END_INT..*/ -#define RMT_CH1_TX_END_INT_ST (BIT(1)) -#define RMT_CH1_TX_END_INT_ST_M (BIT(1)) -#define RMT_CH1_TX_END_INT_ST_V 0x1 -#define RMT_CH1_TX_END_INT_ST_S 1 -/* RMT_CH0_TX_END_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The masked interrupt status bit for CH$n_TX_END_INT..*/ +/** RMT_INT_ST_REG register + * Masked interrupt status + */ +#define RMT_INT_ST_REG (DR_REG_RMT_BASE + 0x74) +/** RMT_CH0_TX_END_INT_ST : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for CH0_TX_END_INT. + */ #define RMT_CH0_TX_END_INT_ST (BIT(0)) -#define RMT_CH0_TX_END_INT_ST_M (BIT(0)) -#define RMT_CH0_TX_END_INT_ST_V 0x1 +#define RMT_CH0_TX_END_INT_ST_M (RMT_CH0_TX_END_INT_ST_V << RMT_CH0_TX_END_INT_ST_S) +#define RMT_CH0_TX_END_INT_ST_V 0x00000001U #define RMT_CH0_TX_END_INT_ST_S 0 +/** RMT_CH1_TX_END_INT_ST : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit for CH1_TX_END_INT. + */ +#define RMT_CH1_TX_END_INT_ST (BIT(1)) +#define RMT_CH1_TX_END_INT_ST_M (RMT_CH1_TX_END_INT_ST_V << RMT_CH1_TX_END_INT_ST_S) +#define RMT_CH1_TX_END_INT_ST_V 0x00000001U +#define RMT_CH1_TX_END_INT_ST_S 1 +/** RMT_CH2_TX_END_INT_ST : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit for CH2_TX_END_INT. + */ +#define RMT_CH2_TX_END_INT_ST (BIT(2)) +#define RMT_CH2_TX_END_INT_ST_M (RMT_CH2_TX_END_INT_ST_V << RMT_CH2_TX_END_INT_ST_S) +#define RMT_CH2_TX_END_INT_ST_V 0x00000001U +#define RMT_CH2_TX_END_INT_ST_S 2 +/** RMT_CH3_TX_END_INT_ST : RO; bitpos: [3]; default: 0; + * The masked interrupt status bit for CH3_TX_END_INT. + */ +#define RMT_CH3_TX_END_INT_ST (BIT(3)) +#define RMT_CH3_TX_END_INT_ST_M (RMT_CH3_TX_END_INT_ST_V << RMT_CH3_TX_END_INT_ST_S) +#define RMT_CH3_TX_END_INT_ST_V 0x00000001U +#define RMT_CH3_TX_END_INT_ST_S 3 +/** RMT_CH0_ERR_INT_ST : RO; bitpos: [4]; default: 0; + * The masked interrupt status bit for CH0_ERR_INT. + */ +#define RMT_CH0_ERR_INT_ST (BIT(4)) +#define RMT_CH0_ERR_INT_ST_M (RMT_CH0_ERR_INT_ST_V << RMT_CH0_ERR_INT_ST_S) +#define RMT_CH0_ERR_INT_ST_V 0x00000001U +#define RMT_CH0_ERR_INT_ST_S 4 +/** RMT_CH1_ERR_INT_ST : RO; bitpos: [5]; default: 0; + * The masked interrupt status bit for CH1_ERR_INT. + */ +#define RMT_CH1_ERR_INT_ST (BIT(5)) +#define RMT_CH1_ERR_INT_ST_M (RMT_CH1_ERR_INT_ST_V << RMT_CH1_ERR_INT_ST_S) +#define RMT_CH1_ERR_INT_ST_V 0x00000001U +#define RMT_CH1_ERR_INT_ST_S 5 +/** RMT_CH2_ERR_INT_ST : RO; bitpos: [6]; default: 0; + * The masked interrupt status bit for CH2_ERR_INT. + */ +#define RMT_CH2_ERR_INT_ST (BIT(6)) +#define RMT_CH2_ERR_INT_ST_M (RMT_CH2_ERR_INT_ST_V << RMT_CH2_ERR_INT_ST_S) +#define RMT_CH2_ERR_INT_ST_V 0x00000001U +#define RMT_CH2_ERR_INT_ST_S 6 +/** RMT_CH3_ERR_INT_ST : RO; bitpos: [7]; default: 0; + * The masked interrupt status bit for CH3_ERR_INT. + */ +#define RMT_CH3_ERR_INT_ST (BIT(7)) +#define RMT_CH3_ERR_INT_ST_M (RMT_CH3_ERR_INT_ST_V << RMT_CH3_ERR_INT_ST_S) +#define RMT_CH3_ERR_INT_ST_V 0x00000001U +#define RMT_CH3_ERR_INT_ST_S 7 +/** RMT_CH0_TX_THR_EVENT_INT_ST : RO; bitpos: [8]; default: 0; + * The masked interrupt status bit for CH0_TX_THR_EVENT_INT. + */ +#define RMT_CH0_TX_THR_EVENT_INT_ST (BIT(8)) +#define RMT_CH0_TX_THR_EVENT_INT_ST_M (RMT_CH0_TX_THR_EVENT_INT_ST_V << RMT_CH0_TX_THR_EVENT_INT_ST_S) +#define RMT_CH0_TX_THR_EVENT_INT_ST_V 0x00000001U +#define RMT_CH0_TX_THR_EVENT_INT_ST_S 8 +/** RMT_CH1_TX_THR_EVENT_INT_ST : RO; bitpos: [9]; default: 0; + * The masked interrupt status bit for CH1_TX_THR_EVENT_INT. + */ +#define RMT_CH1_TX_THR_EVENT_INT_ST (BIT(9)) +#define RMT_CH1_TX_THR_EVENT_INT_ST_M (RMT_CH1_TX_THR_EVENT_INT_ST_V << RMT_CH1_TX_THR_EVENT_INT_ST_S) +#define RMT_CH1_TX_THR_EVENT_INT_ST_V 0x00000001U +#define RMT_CH1_TX_THR_EVENT_INT_ST_S 9 +/** RMT_CH2_TX_THR_EVENT_INT_ST : RO; bitpos: [10]; default: 0; + * The masked interrupt status bit for CH2_TX_THR_EVENT_INT. + */ +#define RMT_CH2_TX_THR_EVENT_INT_ST (BIT(10)) +#define RMT_CH2_TX_THR_EVENT_INT_ST_M (RMT_CH2_TX_THR_EVENT_INT_ST_V << RMT_CH2_TX_THR_EVENT_INT_ST_S) +#define RMT_CH2_TX_THR_EVENT_INT_ST_V 0x00000001U +#define RMT_CH2_TX_THR_EVENT_INT_ST_S 10 +/** RMT_CH3_TX_THR_EVENT_INT_ST : RO; bitpos: [11]; default: 0; + * The masked interrupt status bit for CH3_TX_THR_EVENT_INT. + */ +#define RMT_CH3_TX_THR_EVENT_INT_ST (BIT(11)) +#define RMT_CH3_TX_THR_EVENT_INT_ST_M (RMT_CH3_TX_THR_EVENT_INT_ST_V << RMT_CH3_TX_THR_EVENT_INT_ST_S) +#define RMT_CH3_TX_THR_EVENT_INT_ST_V 0x00000001U +#define RMT_CH3_TX_THR_EVENT_INT_ST_S 11 +/** RMT_CH0_TX_LOOP_INT_ST : RO; bitpos: [12]; default: 0; + * The masked interrupt status bit for CH0_TX_LOOP_INT. + */ +#define RMT_CH0_TX_LOOP_INT_ST (BIT(12)) +#define RMT_CH0_TX_LOOP_INT_ST_M (RMT_CH0_TX_LOOP_INT_ST_V << RMT_CH0_TX_LOOP_INT_ST_S) +#define RMT_CH0_TX_LOOP_INT_ST_V 0x00000001U +#define RMT_CH0_TX_LOOP_INT_ST_S 12 +/** RMT_CH1_TX_LOOP_INT_ST : RO; bitpos: [13]; default: 0; + * The masked interrupt status bit for CH1_TX_LOOP_INT. + */ +#define RMT_CH1_TX_LOOP_INT_ST (BIT(13)) +#define RMT_CH1_TX_LOOP_INT_ST_M (RMT_CH1_TX_LOOP_INT_ST_V << RMT_CH1_TX_LOOP_INT_ST_S) +#define RMT_CH1_TX_LOOP_INT_ST_V 0x00000001U +#define RMT_CH1_TX_LOOP_INT_ST_S 13 +/** RMT_CH2_TX_LOOP_INT_ST : RO; bitpos: [14]; default: 0; + * The masked interrupt status bit for CH2_TX_LOOP_INT. + */ +#define RMT_CH2_TX_LOOP_INT_ST (BIT(14)) +#define RMT_CH2_TX_LOOP_INT_ST_M (RMT_CH2_TX_LOOP_INT_ST_V << RMT_CH2_TX_LOOP_INT_ST_S) +#define RMT_CH2_TX_LOOP_INT_ST_V 0x00000001U +#define RMT_CH2_TX_LOOP_INT_ST_S 14 +/** RMT_CH3_TX_LOOP_INT_ST : RO; bitpos: [15]; default: 0; + * The masked interrupt status bit for CH3_TX_LOOP_INT. + */ +#define RMT_CH3_TX_LOOP_INT_ST (BIT(15)) +#define RMT_CH3_TX_LOOP_INT_ST_M (RMT_CH3_TX_LOOP_INT_ST_V << RMT_CH3_TX_LOOP_INT_ST_S) +#define RMT_CH3_TX_LOOP_INT_ST_V 0x00000001U +#define RMT_CH3_TX_LOOP_INT_ST_S 15 +/** RMT_CH4_RX_END_INT_ST : RO; bitpos: [16]; default: 0; + * The masked interrupt status bit for CH4_RX_END_INT. + */ +#define RMT_CH4_RX_END_INT_ST (BIT(16)) +#define RMT_CH4_RX_END_INT_ST_M (RMT_CH4_RX_END_INT_ST_V << RMT_CH4_RX_END_INT_ST_S) +#define RMT_CH4_RX_END_INT_ST_V 0x00000001U +#define RMT_CH4_RX_END_INT_ST_S 16 +/** RMT_CH5_RX_END_INT_ST : RO; bitpos: [17]; default: 0; + * The masked interrupt status bit for CH5_RX_END_INT. + */ +#define RMT_CH5_RX_END_INT_ST (BIT(17)) +#define RMT_CH5_RX_END_INT_ST_M (RMT_CH5_RX_END_INT_ST_V << RMT_CH5_RX_END_INT_ST_S) +#define RMT_CH5_RX_END_INT_ST_V 0x00000001U +#define RMT_CH5_RX_END_INT_ST_S 17 +/** RMT_CH6_RX_END_INT_ST : RO; bitpos: [18]; default: 0; + * The masked interrupt status bit for CH6_RX_END_INT. + */ +#define RMT_CH6_RX_END_INT_ST (BIT(18)) +#define RMT_CH6_RX_END_INT_ST_M (RMT_CH6_RX_END_INT_ST_V << RMT_CH6_RX_END_INT_ST_S) +#define RMT_CH6_RX_END_INT_ST_V 0x00000001U +#define RMT_CH6_RX_END_INT_ST_S 18 +/** RMT_CH7_RX_END_INT_ST : RO; bitpos: [19]; default: 0; + * The masked interrupt status bit for CH7_RX_END_INT. + */ +#define RMT_CH7_RX_END_INT_ST (BIT(19)) +#define RMT_CH7_RX_END_INT_ST_M (RMT_CH7_RX_END_INT_ST_V << RMT_CH7_RX_END_INT_ST_S) +#define RMT_CH7_RX_END_INT_ST_V 0x00000001U +#define RMT_CH7_RX_END_INT_ST_S 19 +/** RMT_CH4_ERR_INT_ST : RO; bitpos: [20]; default: 0; + * The masked interrupt status bit for CH4_ERR_INT. + */ +#define RMT_CH4_ERR_INT_ST (BIT(20)) +#define RMT_CH4_ERR_INT_ST_M (RMT_CH4_ERR_INT_ST_V << RMT_CH4_ERR_INT_ST_S) +#define RMT_CH4_ERR_INT_ST_V 0x00000001U +#define RMT_CH4_ERR_INT_ST_S 20 +/** RMT_CH5_ERR_INT_ST : RO; bitpos: [21]; default: 0; + * The masked interrupt status bit for CH5_ERR_INT. + */ +#define RMT_CH5_ERR_INT_ST (BIT(21)) +#define RMT_CH5_ERR_INT_ST_M (RMT_CH5_ERR_INT_ST_V << RMT_CH5_ERR_INT_ST_S) +#define RMT_CH5_ERR_INT_ST_V 0x00000001U +#define RMT_CH5_ERR_INT_ST_S 21 +/** RMT_CH6_ERR_INT_ST : RO; bitpos: [22]; default: 0; + * The masked interrupt status bit for CH6_ERR_INT. + */ +#define RMT_CH6_ERR_INT_ST (BIT(22)) +#define RMT_CH6_ERR_INT_ST_M (RMT_CH6_ERR_INT_ST_V << RMT_CH6_ERR_INT_ST_S) +#define RMT_CH6_ERR_INT_ST_V 0x00000001U +#define RMT_CH6_ERR_INT_ST_S 22 +/** RMT_CH7_ERR_INT_ST : RO; bitpos: [23]; default: 0; + * The masked interrupt status bit for CH7_ERR_INT. + */ +#define RMT_CH7_ERR_INT_ST (BIT(23)) +#define RMT_CH7_ERR_INT_ST_M (RMT_CH7_ERR_INT_ST_V << RMT_CH7_ERR_INT_ST_S) +#define RMT_CH7_ERR_INT_ST_V 0x00000001U +#define RMT_CH7_ERR_INT_ST_S 23 +/** RMT_CH4_RX_THR_EVENT_INT_ST : RO; bitpos: [24]; default: 0; + * The masked interrupt status bit for CH4_RX_THR_EVENT_INT. + */ +#define RMT_CH4_RX_THR_EVENT_INT_ST (BIT(24)) +#define RMT_CH4_RX_THR_EVENT_INT_ST_M (RMT_CH4_RX_THR_EVENT_INT_ST_V << RMT_CH4_RX_THR_EVENT_INT_ST_S) +#define RMT_CH4_RX_THR_EVENT_INT_ST_V 0x00000001U +#define RMT_CH4_RX_THR_EVENT_INT_ST_S 24 +/** RMT_CH5_RX_THR_EVENT_INT_ST : RO; bitpos: [25]; default: 0; + * The masked interrupt status bit for CH5_RX_THR_EVENT_INT. + */ +#define RMT_CH5_RX_THR_EVENT_INT_ST (BIT(25)) +#define RMT_CH5_RX_THR_EVENT_INT_ST_M (RMT_CH5_RX_THR_EVENT_INT_ST_V << RMT_CH5_RX_THR_EVENT_INT_ST_S) +#define RMT_CH5_RX_THR_EVENT_INT_ST_V 0x00000001U +#define RMT_CH5_RX_THR_EVENT_INT_ST_S 25 +/** RMT_CH6_RX_THR_EVENT_INT_ST : RO; bitpos: [26]; default: 0; + * The masked interrupt status bit for CH6_RX_THR_EVENT_INT. + */ +#define RMT_CH6_RX_THR_EVENT_INT_ST (BIT(26)) +#define RMT_CH6_RX_THR_EVENT_INT_ST_M (RMT_CH6_RX_THR_EVENT_INT_ST_V << RMT_CH6_RX_THR_EVENT_INT_ST_S) +#define RMT_CH6_RX_THR_EVENT_INT_ST_V 0x00000001U +#define RMT_CH6_RX_THR_EVENT_INT_ST_S 26 +/** RMT_CH7_RX_THR_EVENT_INT_ST : RO; bitpos: [27]; default: 0; + * The masked interrupt status bit for CH7_RX_THR_EVENT_INT. + */ +#define RMT_CH7_RX_THR_EVENT_INT_ST (BIT(27)) +#define RMT_CH7_RX_THR_EVENT_INT_ST_M (RMT_CH7_RX_THR_EVENT_INT_ST_V << RMT_CH7_RX_THR_EVENT_INT_ST_S) +#define RMT_CH7_RX_THR_EVENT_INT_ST_V 0x00000001U +#define RMT_CH7_RX_THR_EVENT_INT_ST_S 27 +/** RMT_CH3_DMA_ACCESS_FAIL_INT_ST : RO; bitpos: [28]; default: 0; + * The masked interrupt status bit for CH3_DMA_ACCESS_FAIL_INT. + */ +#define RMT_CH3_DMA_ACCESS_FAIL_INT_ST (BIT(28)) +#define RMT_CH3_DMA_ACCESS_FAIL_INT_ST_M (RMT_CH3_DMA_ACCESS_FAIL_INT_ST_V << RMT_CH3_DMA_ACCESS_FAIL_INT_ST_S) +#define RMT_CH3_DMA_ACCESS_FAIL_INT_ST_V 0x00000001U +#define RMT_CH3_DMA_ACCESS_FAIL_INT_ST_S 28 +/** RMT_CH7_DMA_ACCESS_FAIL_INT_ST : RO; bitpos: [29]; default: 0; + * The masked interrupt status bit for CH7_DMA_ACCESS_FAIL_INT. + */ +#define RMT_CH7_DMA_ACCESS_FAIL_INT_ST (BIT(29)) +#define RMT_CH7_DMA_ACCESS_FAIL_INT_ST_M (RMT_CH7_DMA_ACCESS_FAIL_INT_ST_V << RMT_CH7_DMA_ACCESS_FAIL_INT_ST_S) +#define RMT_CH7_DMA_ACCESS_FAIL_INT_ST_V 0x00000001U +#define RMT_CH7_DMA_ACCESS_FAIL_INT_ST_S 29 -#define RMT_INT_ENA_REG (DR_REG_RMT_BASE + 0x78) -/* RMT_CH7_DMA_ACCESS_FAIL_INT_ENA : R/W ;bitpos:[29] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for CH$m_DMA_ACCESS_FAIL_INT..*/ -#define RMT_CH7_DMA_ACCESS_FAIL_INT_ENA (BIT(29)) -#define RMT_CH7_DMA_ACCESS_FAIL_INT_ENA_M (BIT(29)) -#define RMT_CH7_DMA_ACCESS_FAIL_INT_ENA_V 0x1 -#define RMT_CH7_DMA_ACCESS_FAIL_INT_ENA_S 29 -/* RMT_CH3_DMA_ACCESS_FAIL_INT_ENA : R/W ;bitpos:[28] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for CH$n_DMA_ACCESS_FAIL_INT..*/ -#define RMT_CH3_DMA_ACCESS_FAIL_INT_ENA (BIT(28)) -#define RMT_CH3_DMA_ACCESS_FAIL_INT_ENA_M (BIT(28)) -#define RMT_CH3_DMA_ACCESS_FAIL_INT_ENA_V 0x1 -#define RMT_CH3_DMA_ACCESS_FAIL_INT_ENA_S 28 -/* RMT_CH7_RX_THR_EVENT_INT_ENA : R/W ;bitpos:[27] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for CH$m_RX_THR_EVENT_INT..*/ -#define RMT_CH7_RX_THR_EVENT_INT_ENA (BIT(27)) -#define RMT_CH7_RX_THR_EVENT_INT_ENA_M (BIT(27)) -#define RMT_CH7_RX_THR_EVENT_INT_ENA_V 0x1 -#define RMT_CH7_RX_THR_EVENT_INT_ENA_S 27 -/* RMT_CH6_RX_THR_EVENT_INT_ENA : R/W ;bitpos:[26] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for CH$m_RX_THR_EVENT_INT..*/ -#define RMT_CH6_RX_THR_EVENT_INT_ENA (BIT(26)) -#define RMT_CH6_RX_THR_EVENT_INT_ENA_M (BIT(26)) -#define RMT_CH6_RX_THR_EVENT_INT_ENA_V 0x1 -#define RMT_CH6_RX_THR_EVENT_INT_ENA_S 26 -/* RMT_CH5_RX_THR_EVENT_INT_ENA : R/W ;bitpos:[25] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for CH$m_RX_THR_EVENT_INT..*/ -#define RMT_CH5_RX_THR_EVENT_INT_ENA (BIT(25)) -#define RMT_CH5_RX_THR_EVENT_INT_ENA_M (BIT(25)) -#define RMT_CH5_RX_THR_EVENT_INT_ENA_V 0x1 -#define RMT_CH5_RX_THR_EVENT_INT_ENA_S 25 -/* RMT_CH4_RX_THR_EVENT_INT_ENA : R/W ;bitpos:[24] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for CH$m_RX_THR_EVENT_INT..*/ -#define RMT_CH4_RX_THR_EVENT_INT_ENA (BIT(24)) -#define RMT_CH4_RX_THR_EVENT_INT_ENA_M (BIT(24)) -#define RMT_CH4_RX_THR_EVENT_INT_ENA_V 0x1 -#define RMT_CH4_RX_THR_EVENT_INT_ENA_S 24 -/* RMT_CH7_ERR_INT_ENA : R/W ;bitpos:[23] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for CH$m_ERR_INT..*/ -#define RMT_CH7_ERR_INT_ENA (BIT(23)) -#define RMT_CH7_ERR_INT_ENA_M (BIT(23)) -#define RMT_CH7_ERR_INT_ENA_V 0x1 -#define RMT_CH7_ERR_INT_ENA_S 23 -/* RMT_CH6_ERR_INT_ENA : R/W ;bitpos:[22] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for CH$m_ERR_INT..*/ -#define RMT_CH6_ERR_INT_ENA (BIT(22)) -#define RMT_CH6_ERR_INT_ENA_M (BIT(22)) -#define RMT_CH6_ERR_INT_ENA_V 0x1 -#define RMT_CH6_ERR_INT_ENA_S 22 -/* RMT_CH5_ERR_INT_ENA : R/W ;bitpos:[21] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for CH$m_ERR_INT..*/ -#define RMT_CH5_ERR_INT_ENA (BIT(21)) -#define RMT_CH5_ERR_INT_ENA_M (BIT(21)) -#define RMT_CH5_ERR_INT_ENA_V 0x1 -#define RMT_CH5_ERR_INT_ENA_S 21 -/* RMT_CH4_ERR_INT_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for CH$m_ERR_INT..*/ -#define RMT_CH4_ERR_INT_ENA (BIT(20)) -#define RMT_CH4_ERR_INT_ENA_M (BIT(20)) -#define RMT_CH4_ERR_INT_ENA_V 0x1 -#define RMT_CH4_ERR_INT_ENA_S 20 -/* RMT_CH7_RX_END_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for CH$m_RX_END_INT..*/ -#define RMT_CH7_RX_END_INT_ENA (BIT(19)) -#define RMT_CH7_RX_END_INT_ENA_M (BIT(19)) -#define RMT_CH7_RX_END_INT_ENA_V 0x1 -#define RMT_CH7_RX_END_INT_ENA_S 19 -/* RMT_CH6_RX_END_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for CH$m_RX_END_INT..*/ -#define RMT_CH6_RX_END_INT_ENA (BIT(18)) -#define RMT_CH6_RX_END_INT_ENA_M (BIT(18)) -#define RMT_CH6_RX_END_INT_ENA_V 0x1 -#define RMT_CH6_RX_END_INT_ENA_S 18 -/* RMT_CH5_RX_END_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for CH$m_RX_END_INT..*/ -#define RMT_CH5_RX_END_INT_ENA (BIT(17)) -#define RMT_CH5_RX_END_INT_ENA_M (BIT(17)) -#define RMT_CH5_RX_END_INT_ENA_V 0x1 -#define RMT_CH5_RX_END_INT_ENA_S 17 -/* RMT_CH4_RX_END_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for CH$m_RX_END_INT..*/ -#define RMT_CH4_RX_END_INT_ENA (BIT(16)) -#define RMT_CH4_RX_END_INT_ENA_M (BIT(16)) -#define RMT_CH4_RX_END_INT_ENA_V 0x1 -#define RMT_CH4_RX_END_INT_ENA_S 16 -/* RMT_CH3_TX_LOOP_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for CH$n_TX_LOOP_INT..*/ -#define RMT_CH3_TX_LOOP_INT_ENA (BIT(15)) -#define RMT_CH3_TX_LOOP_INT_ENA_M (BIT(15)) -#define RMT_CH3_TX_LOOP_INT_ENA_V 0x1 -#define RMT_CH3_TX_LOOP_INT_ENA_S 15 -/* RMT_CH2_TX_LOOP_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for CH$n_TX_LOOP_INT..*/ -#define RMT_CH2_TX_LOOP_INT_ENA (BIT(14)) -#define RMT_CH2_TX_LOOP_INT_ENA_M (BIT(14)) -#define RMT_CH2_TX_LOOP_INT_ENA_V 0x1 -#define RMT_CH2_TX_LOOP_INT_ENA_S 14 -/* RMT_CH1_TX_LOOP_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for CH$n_TX_LOOP_INT..*/ -#define RMT_CH1_TX_LOOP_INT_ENA (BIT(13)) -#define RMT_CH1_TX_LOOP_INT_ENA_M (BIT(13)) -#define RMT_CH1_TX_LOOP_INT_ENA_V 0x1 -#define RMT_CH1_TX_LOOP_INT_ENA_S 13 -/* RMT_CH0_TX_LOOP_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for CH$n_TX_LOOP_INT..*/ -#define RMT_CH0_TX_LOOP_INT_ENA (BIT(12)) -#define RMT_CH0_TX_LOOP_INT_ENA_M (BIT(12)) -#define RMT_CH0_TX_LOOP_INT_ENA_V 0x1 -#define RMT_CH0_TX_LOOP_INT_ENA_S 12 -/* RMT_CH3_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for CH$n_TX_THR_EVENT_INT..*/ -#define RMT_CH3_TX_THR_EVENT_INT_ENA (BIT(11)) -#define RMT_CH3_TX_THR_EVENT_INT_ENA_M (BIT(11)) -#define RMT_CH3_TX_THR_EVENT_INT_ENA_V 0x1 -#define RMT_CH3_TX_THR_EVENT_INT_ENA_S 11 -/* RMT_CH2_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for CH$n_TX_THR_EVENT_INT..*/ -#define RMT_CH2_TX_THR_EVENT_INT_ENA (BIT(10)) -#define RMT_CH2_TX_THR_EVENT_INT_ENA_M (BIT(10)) -#define RMT_CH2_TX_THR_EVENT_INT_ENA_V 0x1 -#define RMT_CH2_TX_THR_EVENT_INT_ENA_S 10 -/* RMT_CH1_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for CH$n_TX_THR_EVENT_INT..*/ -#define RMT_CH1_TX_THR_EVENT_INT_ENA (BIT(9)) -#define RMT_CH1_TX_THR_EVENT_INT_ENA_M (BIT(9)) -#define RMT_CH1_TX_THR_EVENT_INT_ENA_V 0x1 -#define RMT_CH1_TX_THR_EVENT_INT_ENA_S 9 -/* RMT_CH0_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for CH$n_TX_THR_EVENT_INT..*/ -#define RMT_CH0_TX_THR_EVENT_INT_ENA (BIT(8)) -#define RMT_CH0_TX_THR_EVENT_INT_ENA_M (BIT(8)) -#define RMT_CH0_TX_THR_EVENT_INT_ENA_V 0x1 -#define RMT_CH0_TX_THR_EVENT_INT_ENA_S 8 -/* RMT_CH3_ERR_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for CH$n_ERR_INT..*/ -#define RMT_CH3_ERR_INT_ENA (BIT(7)) -#define RMT_CH3_ERR_INT_ENA_M (BIT(7)) -#define RMT_CH3_ERR_INT_ENA_V 0x1 -#define RMT_CH3_ERR_INT_ENA_S 7 -/* RMT_CH2_ERR_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for CH$n_ERR_INT..*/ -#define RMT_CH2_ERR_INT_ENA (BIT(6)) -#define RMT_CH2_ERR_INT_ENA_M (BIT(6)) -#define RMT_CH2_ERR_INT_ENA_V 0x1 -#define RMT_CH2_ERR_INT_ENA_S 6 -/* RMT_CH1_ERR_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for CH$n_ERR_INT..*/ -#define RMT_CH1_ERR_INT_ENA (BIT(5)) -#define RMT_CH1_ERR_INT_ENA_M (BIT(5)) -#define RMT_CH1_ERR_INT_ENA_V 0x1 -#define RMT_CH1_ERR_INT_ENA_S 5 -/* RMT_CH0_ERR_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for CH$n_ERR_INT..*/ -#define RMT_CH0_ERR_INT_ENA (BIT(4)) -#define RMT_CH0_ERR_INT_ENA_M (BIT(4)) -#define RMT_CH0_ERR_INT_ENA_V 0x1 -#define RMT_CH0_ERR_INT_ENA_S 4 -/* RMT_CH3_TX_END_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for CH$n_TX_END_INT..*/ -#define RMT_CH3_TX_END_INT_ENA (BIT(3)) -#define RMT_CH3_TX_END_INT_ENA_M (BIT(3)) -#define RMT_CH3_TX_END_INT_ENA_V 0x1 -#define RMT_CH3_TX_END_INT_ENA_S 3 -/* RMT_CH2_TX_END_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for CH$n_TX_END_INT..*/ -#define RMT_CH2_TX_END_INT_ENA (BIT(2)) -#define RMT_CH2_TX_END_INT_ENA_M (BIT(2)) -#define RMT_CH2_TX_END_INT_ENA_V 0x1 -#define RMT_CH2_TX_END_INT_ENA_S 2 -/* RMT_CH1_TX_END_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for CH$n_TX_END_INT..*/ -#define RMT_CH1_TX_END_INT_ENA (BIT(1)) -#define RMT_CH1_TX_END_INT_ENA_M (BIT(1)) -#define RMT_CH1_TX_END_INT_ENA_V 0x1 -#define RMT_CH1_TX_END_INT_ENA_S 1 -/* RMT_CH0_TX_END_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: The interrupt enable bit for CH$n_TX_END_INT..*/ +/** RMT_INT_ENA_REG register + * Interrupt enable bits + */ +#define RMT_INT_ENA_REG (DR_REG_RMT_BASE + 0x78) +/** RMT_CH0_TX_END_INT_ENA : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for CH0_TX_END_INT. + */ #define RMT_CH0_TX_END_INT_ENA (BIT(0)) -#define RMT_CH0_TX_END_INT_ENA_M (BIT(0)) -#define RMT_CH0_TX_END_INT_ENA_V 0x1 +#define RMT_CH0_TX_END_INT_ENA_M (RMT_CH0_TX_END_INT_ENA_V << RMT_CH0_TX_END_INT_ENA_S) +#define RMT_CH0_TX_END_INT_ENA_V 0x00000001U #define RMT_CH0_TX_END_INT_ENA_S 0 +/** RMT_CH1_TX_END_INT_ENA : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for CH1_TX_END_INT. + */ +#define RMT_CH1_TX_END_INT_ENA (BIT(1)) +#define RMT_CH1_TX_END_INT_ENA_M (RMT_CH1_TX_END_INT_ENA_V << RMT_CH1_TX_END_INT_ENA_S) +#define RMT_CH1_TX_END_INT_ENA_V 0x00000001U +#define RMT_CH1_TX_END_INT_ENA_S 1 +/** RMT_CH2_TX_END_INT_ENA : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for CH2_TX_END_INT. + */ +#define RMT_CH2_TX_END_INT_ENA (BIT(2)) +#define RMT_CH2_TX_END_INT_ENA_M (RMT_CH2_TX_END_INT_ENA_V << RMT_CH2_TX_END_INT_ENA_S) +#define RMT_CH2_TX_END_INT_ENA_V 0x00000001U +#define RMT_CH2_TX_END_INT_ENA_S 2 +/** RMT_CH3_TX_END_INT_ENA : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for CH3_TX_END_INT. + */ +#define RMT_CH3_TX_END_INT_ENA (BIT(3)) +#define RMT_CH3_TX_END_INT_ENA_M (RMT_CH3_TX_END_INT_ENA_V << RMT_CH3_TX_END_INT_ENA_S) +#define RMT_CH3_TX_END_INT_ENA_V 0x00000001U +#define RMT_CH3_TX_END_INT_ENA_S 3 +/** RMT_CH0_ERR_INT_ENA : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for CH0_ERR_INT. + */ +#define RMT_CH0_ERR_INT_ENA (BIT(4)) +#define RMT_CH0_ERR_INT_ENA_M (RMT_CH0_ERR_INT_ENA_V << RMT_CH0_ERR_INT_ENA_S) +#define RMT_CH0_ERR_INT_ENA_V 0x00000001U +#define RMT_CH0_ERR_INT_ENA_S 4 +/** RMT_CH1_ERR_INT_ENA : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for CH1_ERR_INT. + */ +#define RMT_CH1_ERR_INT_ENA (BIT(5)) +#define RMT_CH1_ERR_INT_ENA_M (RMT_CH1_ERR_INT_ENA_V << RMT_CH1_ERR_INT_ENA_S) +#define RMT_CH1_ERR_INT_ENA_V 0x00000001U +#define RMT_CH1_ERR_INT_ENA_S 5 +/** RMT_CH2_ERR_INT_ENA : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit for CH2_ERR_INT. + */ +#define RMT_CH2_ERR_INT_ENA (BIT(6)) +#define RMT_CH2_ERR_INT_ENA_M (RMT_CH2_ERR_INT_ENA_V << RMT_CH2_ERR_INT_ENA_S) +#define RMT_CH2_ERR_INT_ENA_V 0x00000001U +#define RMT_CH2_ERR_INT_ENA_S 6 +/** RMT_CH3_ERR_INT_ENA : R/W; bitpos: [7]; default: 0; + * The interrupt enable bit for CH3_ERR_INT. + */ +#define RMT_CH3_ERR_INT_ENA (BIT(7)) +#define RMT_CH3_ERR_INT_ENA_M (RMT_CH3_ERR_INT_ENA_V << RMT_CH3_ERR_INT_ENA_S) +#define RMT_CH3_ERR_INT_ENA_V 0x00000001U +#define RMT_CH3_ERR_INT_ENA_S 7 +/** RMT_CH0_TX_THR_EVENT_INT_ENA : R/W; bitpos: [8]; default: 0; + * The interrupt enable bit for CH0_TX_THR_EVENT_INT. + */ +#define RMT_CH0_TX_THR_EVENT_INT_ENA (BIT(8)) +#define RMT_CH0_TX_THR_EVENT_INT_ENA_M (RMT_CH0_TX_THR_EVENT_INT_ENA_V << RMT_CH0_TX_THR_EVENT_INT_ENA_S) +#define RMT_CH0_TX_THR_EVENT_INT_ENA_V 0x00000001U +#define RMT_CH0_TX_THR_EVENT_INT_ENA_S 8 +/** RMT_CH1_TX_THR_EVENT_INT_ENA : R/W; bitpos: [9]; default: 0; + * The interrupt enable bit for CH1_TX_THR_EVENT_INT. + */ +#define RMT_CH1_TX_THR_EVENT_INT_ENA (BIT(9)) +#define RMT_CH1_TX_THR_EVENT_INT_ENA_M (RMT_CH1_TX_THR_EVENT_INT_ENA_V << RMT_CH1_TX_THR_EVENT_INT_ENA_S) +#define RMT_CH1_TX_THR_EVENT_INT_ENA_V 0x00000001U +#define RMT_CH1_TX_THR_EVENT_INT_ENA_S 9 +/** RMT_CH2_TX_THR_EVENT_INT_ENA : R/W; bitpos: [10]; default: 0; + * The interrupt enable bit for CH2_TX_THR_EVENT_INT. + */ +#define RMT_CH2_TX_THR_EVENT_INT_ENA (BIT(10)) +#define RMT_CH2_TX_THR_EVENT_INT_ENA_M (RMT_CH2_TX_THR_EVENT_INT_ENA_V << RMT_CH2_TX_THR_EVENT_INT_ENA_S) +#define RMT_CH2_TX_THR_EVENT_INT_ENA_V 0x00000001U +#define RMT_CH2_TX_THR_EVENT_INT_ENA_S 10 +/** RMT_CH3_TX_THR_EVENT_INT_ENA : R/W; bitpos: [11]; default: 0; + * The interrupt enable bit for CH3_TX_THR_EVENT_INT. + */ +#define RMT_CH3_TX_THR_EVENT_INT_ENA (BIT(11)) +#define RMT_CH3_TX_THR_EVENT_INT_ENA_M (RMT_CH3_TX_THR_EVENT_INT_ENA_V << RMT_CH3_TX_THR_EVENT_INT_ENA_S) +#define RMT_CH3_TX_THR_EVENT_INT_ENA_V 0x00000001U +#define RMT_CH3_TX_THR_EVENT_INT_ENA_S 11 +/** RMT_CH0_TX_LOOP_INT_ENA : R/W; bitpos: [12]; default: 0; + * The interrupt enable bit for CH0_TX_LOOP_INT. + */ +#define RMT_CH0_TX_LOOP_INT_ENA (BIT(12)) +#define RMT_CH0_TX_LOOP_INT_ENA_M (RMT_CH0_TX_LOOP_INT_ENA_V << RMT_CH0_TX_LOOP_INT_ENA_S) +#define RMT_CH0_TX_LOOP_INT_ENA_V 0x00000001U +#define RMT_CH0_TX_LOOP_INT_ENA_S 12 +/** RMT_CH1_TX_LOOP_INT_ENA : R/W; bitpos: [13]; default: 0; + * The interrupt enable bit for CH1_TX_LOOP_INT. + */ +#define RMT_CH1_TX_LOOP_INT_ENA (BIT(13)) +#define RMT_CH1_TX_LOOP_INT_ENA_M (RMT_CH1_TX_LOOP_INT_ENA_V << RMT_CH1_TX_LOOP_INT_ENA_S) +#define RMT_CH1_TX_LOOP_INT_ENA_V 0x00000001U +#define RMT_CH1_TX_LOOP_INT_ENA_S 13 +/** RMT_CH2_TX_LOOP_INT_ENA : R/W; bitpos: [14]; default: 0; + * The interrupt enable bit for CH2_TX_LOOP_INT. + */ +#define RMT_CH2_TX_LOOP_INT_ENA (BIT(14)) +#define RMT_CH2_TX_LOOP_INT_ENA_M (RMT_CH2_TX_LOOP_INT_ENA_V << RMT_CH2_TX_LOOP_INT_ENA_S) +#define RMT_CH2_TX_LOOP_INT_ENA_V 0x00000001U +#define RMT_CH2_TX_LOOP_INT_ENA_S 14 +/** RMT_CH3_TX_LOOP_INT_ENA : R/W; bitpos: [15]; default: 0; + * The interrupt enable bit for CH3_TX_LOOP_INT. + */ +#define RMT_CH3_TX_LOOP_INT_ENA (BIT(15)) +#define RMT_CH3_TX_LOOP_INT_ENA_M (RMT_CH3_TX_LOOP_INT_ENA_V << RMT_CH3_TX_LOOP_INT_ENA_S) +#define RMT_CH3_TX_LOOP_INT_ENA_V 0x00000001U +#define RMT_CH3_TX_LOOP_INT_ENA_S 15 +/** RMT_CH4_RX_END_INT_ENA : R/W; bitpos: [16]; default: 0; + * The interrupt enable bit for CH4_RX_END_INT. + */ +#define RMT_CH4_RX_END_INT_ENA (BIT(16)) +#define RMT_CH4_RX_END_INT_ENA_M (RMT_CH4_RX_END_INT_ENA_V << RMT_CH4_RX_END_INT_ENA_S) +#define RMT_CH4_RX_END_INT_ENA_V 0x00000001U +#define RMT_CH4_RX_END_INT_ENA_S 16 +/** RMT_CH5_RX_END_INT_ENA : R/W; bitpos: [17]; default: 0; + * The interrupt enable bit for CH5_RX_END_INT. + */ +#define RMT_CH5_RX_END_INT_ENA (BIT(17)) +#define RMT_CH5_RX_END_INT_ENA_M (RMT_CH5_RX_END_INT_ENA_V << RMT_CH5_RX_END_INT_ENA_S) +#define RMT_CH5_RX_END_INT_ENA_V 0x00000001U +#define RMT_CH5_RX_END_INT_ENA_S 17 +/** RMT_CH6_RX_END_INT_ENA : R/W; bitpos: [18]; default: 0; + * The interrupt enable bit for CH6_RX_END_INT. + */ +#define RMT_CH6_RX_END_INT_ENA (BIT(18)) +#define RMT_CH6_RX_END_INT_ENA_M (RMT_CH6_RX_END_INT_ENA_V << RMT_CH6_RX_END_INT_ENA_S) +#define RMT_CH6_RX_END_INT_ENA_V 0x00000001U +#define RMT_CH6_RX_END_INT_ENA_S 18 +/** RMT_CH7_RX_END_INT_ENA : R/W; bitpos: [19]; default: 0; + * The interrupt enable bit for CH7_RX_END_INT. + */ +#define RMT_CH7_RX_END_INT_ENA (BIT(19)) +#define RMT_CH7_RX_END_INT_ENA_M (RMT_CH7_RX_END_INT_ENA_V << RMT_CH7_RX_END_INT_ENA_S) +#define RMT_CH7_RX_END_INT_ENA_V 0x00000001U +#define RMT_CH7_RX_END_INT_ENA_S 19 +/** RMT_CH4_ERR_INT_ENA : R/W; bitpos: [20]; default: 0; + * The interrupt enable bit for CH4_ERR_INT. + */ +#define RMT_CH4_ERR_INT_ENA (BIT(20)) +#define RMT_CH4_ERR_INT_ENA_M (RMT_CH4_ERR_INT_ENA_V << RMT_CH4_ERR_INT_ENA_S) +#define RMT_CH4_ERR_INT_ENA_V 0x00000001U +#define RMT_CH4_ERR_INT_ENA_S 20 +/** RMT_CH5_ERR_INT_ENA : R/W; bitpos: [21]; default: 0; + * The interrupt enable bit for CH5_ERR_INT. + */ +#define RMT_CH5_ERR_INT_ENA (BIT(21)) +#define RMT_CH5_ERR_INT_ENA_M (RMT_CH5_ERR_INT_ENA_V << RMT_CH5_ERR_INT_ENA_S) +#define RMT_CH5_ERR_INT_ENA_V 0x00000001U +#define RMT_CH5_ERR_INT_ENA_S 21 +/** RMT_CH6_ERR_INT_ENA : R/W; bitpos: [22]; default: 0; + * The interrupt enable bit for CH6_ERR_INT. + */ +#define RMT_CH6_ERR_INT_ENA (BIT(22)) +#define RMT_CH6_ERR_INT_ENA_M (RMT_CH6_ERR_INT_ENA_V << RMT_CH6_ERR_INT_ENA_S) +#define RMT_CH6_ERR_INT_ENA_V 0x00000001U +#define RMT_CH6_ERR_INT_ENA_S 22 +/** RMT_CH7_ERR_INT_ENA : R/W; bitpos: [23]; default: 0; + * The interrupt enable bit for CH7_ERR_INT. + */ +#define RMT_CH7_ERR_INT_ENA (BIT(23)) +#define RMT_CH7_ERR_INT_ENA_M (RMT_CH7_ERR_INT_ENA_V << RMT_CH7_ERR_INT_ENA_S) +#define RMT_CH7_ERR_INT_ENA_V 0x00000001U +#define RMT_CH7_ERR_INT_ENA_S 23 +/** RMT_CH4_RX_THR_EVENT_INT_ENA : R/W; bitpos: [24]; default: 0; + * The interrupt enable bit for CH4_RX_THR_EVENT_INT. + */ +#define RMT_CH4_RX_THR_EVENT_INT_ENA (BIT(24)) +#define RMT_CH4_RX_THR_EVENT_INT_ENA_M (RMT_CH4_RX_THR_EVENT_INT_ENA_V << RMT_CH4_RX_THR_EVENT_INT_ENA_S) +#define RMT_CH4_RX_THR_EVENT_INT_ENA_V 0x00000001U +#define RMT_CH4_RX_THR_EVENT_INT_ENA_S 24 +/** RMT_CH5_RX_THR_EVENT_INT_ENA : R/W; bitpos: [25]; default: 0; + * The interrupt enable bit for CH5_RX_THR_EVENT_INT. + */ +#define RMT_CH5_RX_THR_EVENT_INT_ENA (BIT(25)) +#define RMT_CH5_RX_THR_EVENT_INT_ENA_M (RMT_CH5_RX_THR_EVENT_INT_ENA_V << RMT_CH5_RX_THR_EVENT_INT_ENA_S) +#define RMT_CH5_RX_THR_EVENT_INT_ENA_V 0x00000001U +#define RMT_CH5_RX_THR_EVENT_INT_ENA_S 25 +/** RMT_CH6_RX_THR_EVENT_INT_ENA : R/W; bitpos: [26]; default: 0; + * The interrupt enable bit for CH6_RX_THR_EVENT_INT. + */ +#define RMT_CH6_RX_THR_EVENT_INT_ENA (BIT(26)) +#define RMT_CH6_RX_THR_EVENT_INT_ENA_M (RMT_CH6_RX_THR_EVENT_INT_ENA_V << RMT_CH6_RX_THR_EVENT_INT_ENA_S) +#define RMT_CH6_RX_THR_EVENT_INT_ENA_V 0x00000001U +#define RMT_CH6_RX_THR_EVENT_INT_ENA_S 26 +/** RMT_CH7_RX_THR_EVENT_INT_ENA : R/W; bitpos: [27]; default: 0; + * The interrupt enable bit for CH7_RX_THR_EVENT_INT. + */ +#define RMT_CH7_RX_THR_EVENT_INT_ENA (BIT(27)) +#define RMT_CH7_RX_THR_EVENT_INT_ENA_M (RMT_CH7_RX_THR_EVENT_INT_ENA_V << RMT_CH7_RX_THR_EVENT_INT_ENA_S) +#define RMT_CH7_RX_THR_EVENT_INT_ENA_V 0x00000001U +#define RMT_CH7_RX_THR_EVENT_INT_ENA_S 27 +/** RMT_CH3_DMA_ACCESS_FAIL_INT_ENA : R/W; bitpos: [28]; default: 0; + * The interrupt enable bit for CH3_DMA_ACCESS_FAIL_INT. + */ +#define RMT_CH3_DMA_ACCESS_FAIL_INT_ENA (BIT(28)) +#define RMT_CH3_DMA_ACCESS_FAIL_INT_ENA_M (RMT_CH3_DMA_ACCESS_FAIL_INT_ENA_V << RMT_CH3_DMA_ACCESS_FAIL_INT_ENA_S) +#define RMT_CH3_DMA_ACCESS_FAIL_INT_ENA_V 0x00000001U +#define RMT_CH3_DMA_ACCESS_FAIL_INT_ENA_S 28 +/** RMT_CH7_DMA_ACCESS_FAIL_INT_ENA : R/W; bitpos: [29]; default: 0; + * The interrupt enable bit for CH7_DMA_ACCESS_FAIL_INT. + */ +#define RMT_CH7_DMA_ACCESS_FAIL_INT_ENA (BIT(29)) +#define RMT_CH7_DMA_ACCESS_FAIL_INT_ENA_M (RMT_CH7_DMA_ACCESS_FAIL_INT_ENA_V << RMT_CH7_DMA_ACCESS_FAIL_INT_ENA_S) +#define RMT_CH7_DMA_ACCESS_FAIL_INT_ENA_V 0x00000001U +#define RMT_CH7_DMA_ACCESS_FAIL_INT_ENA_S 29 -#define RMT_INT_CLR_REG (DR_REG_RMT_BASE + 0x7C) -/* RMT_CH7_DMA_ACCESS_FAIL_INT_CLR : WT ;bitpos:[29] ;default: 1'b0 ; */ -/*description: Set this bit to clear the CH$m_DMA_ACCESS_FAIL_INT interrupt..*/ -#define RMT_CH7_DMA_ACCESS_FAIL_INT_CLR (BIT(29)) -#define RMT_CH7_DMA_ACCESS_FAIL_INT_CLR_M (BIT(29)) -#define RMT_CH7_DMA_ACCESS_FAIL_INT_CLR_V 0x1 -#define RMT_CH7_DMA_ACCESS_FAIL_INT_CLR_S 29 -/* RMT_CH3_DMA_ACCESS_FAIL_INT_CLR : WT ;bitpos:[28] ;default: 1'b0 ; */ -/*description: Set this bit to clear the CH$n_DMA_ACCESS_FAIL_INT interrupt..*/ -#define RMT_CH3_DMA_ACCESS_FAIL_INT_CLR (BIT(28)) -#define RMT_CH3_DMA_ACCESS_FAIL_INT_CLR_M (BIT(28)) -#define RMT_CH3_DMA_ACCESS_FAIL_INT_CLR_V 0x1 -#define RMT_CH3_DMA_ACCESS_FAIL_INT_CLR_S 28 -/* RMT_CH7_RX_THR_EVENT_INT_CLR : WT ;bitpos:[27] ;default: 1'b0 ; */ -/*description: Set this bit to clear theCH$m_RX_THR_EVENT_INT interrupt..*/ -#define RMT_CH7_RX_THR_EVENT_INT_CLR (BIT(27)) -#define RMT_CH7_RX_THR_EVENT_INT_CLR_M (BIT(27)) -#define RMT_CH7_RX_THR_EVENT_INT_CLR_V 0x1 -#define RMT_CH7_RX_THR_EVENT_INT_CLR_S 27 -/* RMT_CH6_RX_THR_EVENT_INT_CLR : WT ;bitpos:[26] ;default: 1'b0 ; */ -/*description: Set this bit to clear theCH$m_RX_THR_EVENT_INT interrupt..*/ -#define RMT_CH6_RX_THR_EVENT_INT_CLR (BIT(26)) -#define RMT_CH6_RX_THR_EVENT_INT_CLR_M (BIT(26)) -#define RMT_CH6_RX_THR_EVENT_INT_CLR_V 0x1 -#define RMT_CH6_RX_THR_EVENT_INT_CLR_S 26 -/* RMT_CH5_RX_THR_EVENT_INT_CLR : WT ;bitpos:[25] ;default: 1'b0 ; */ -/*description: Set this bit to clear theCH$m_RX_THR_EVENT_INT interrupt..*/ -#define RMT_CH5_RX_THR_EVENT_INT_CLR (BIT(25)) -#define RMT_CH5_RX_THR_EVENT_INT_CLR_M (BIT(25)) -#define RMT_CH5_RX_THR_EVENT_INT_CLR_V 0x1 -#define RMT_CH5_RX_THR_EVENT_INT_CLR_S 25 -/* RMT_CH4_RX_THR_EVENT_INT_CLR : WT ;bitpos:[24] ;default: 1'b0 ; */ -/*description: Set this bit to clear theCH$m_RX_THR_EVENT_INT interrupt..*/ -#define RMT_CH4_RX_THR_EVENT_INT_CLR (BIT(24)) -#define RMT_CH4_RX_THR_EVENT_INT_CLR_M (BIT(24)) -#define RMT_CH4_RX_THR_EVENT_INT_CLR_V 0x1 -#define RMT_CH4_RX_THR_EVENT_INT_CLR_S 24 -/* RMT_CH7_ERR_INT_CLR : WT ;bitpos:[23] ;default: 1'b0 ; */ -/*description: Set this bit to clear theCH$m_ERR_INT interrupt..*/ -#define RMT_CH7_ERR_INT_CLR (BIT(23)) -#define RMT_CH7_ERR_INT_CLR_M (BIT(23)) -#define RMT_CH7_ERR_INT_CLR_V 0x1 -#define RMT_CH7_ERR_INT_CLR_S 23 -/* RMT_CH6_ERR_INT_CLR : WT ;bitpos:[22] ;default: 1'b0 ; */ -/*description: Set this bit to clear theCH$m_ERR_INT interrupt..*/ -#define RMT_CH6_ERR_INT_CLR (BIT(22)) -#define RMT_CH6_ERR_INT_CLR_M (BIT(22)) -#define RMT_CH6_ERR_INT_CLR_V 0x1 -#define RMT_CH6_ERR_INT_CLR_S 22 -/* RMT_CH5_ERR_INT_CLR : WT ;bitpos:[21] ;default: 1'b0 ; */ -/*description: Set this bit to clear theCH$m_ERR_INT interrupt..*/ -#define RMT_CH5_ERR_INT_CLR (BIT(21)) -#define RMT_CH5_ERR_INT_CLR_M (BIT(21)) -#define RMT_CH5_ERR_INT_CLR_V 0x1 -#define RMT_CH5_ERR_INT_CLR_S 21 -/* RMT_CH4_ERR_INT_CLR : WT ;bitpos:[20] ;default: 1'b0 ; */ -/*description: Set this bit to clear theCH$m_ERR_INT interrupt..*/ -#define RMT_CH4_ERR_INT_CLR (BIT(20)) -#define RMT_CH4_ERR_INT_CLR_M (BIT(20)) -#define RMT_CH4_ERR_INT_CLR_V 0x1 -#define RMT_CH4_ERR_INT_CLR_S 20 -/* RMT_CH7_RX_END_INT_CLR : WT ;bitpos:[19] ;default: 1'b0 ; */ -/*description: Set this bit to clear theCH$m_RX_END_INT interrupt..*/ -#define RMT_CH7_RX_END_INT_CLR (BIT(19)) -#define RMT_CH7_RX_END_INT_CLR_M (BIT(19)) -#define RMT_CH7_RX_END_INT_CLR_V 0x1 -#define RMT_CH7_RX_END_INT_CLR_S 19 -/* RMT_CH6_RX_END_INT_CLR : WT ;bitpos:[18] ;default: 1'b0 ; */ -/*description: Set this bit to clear theCH$m_RX_END_INT interrupt..*/ -#define RMT_CH6_RX_END_INT_CLR (BIT(18)) -#define RMT_CH6_RX_END_INT_CLR_M (BIT(18)) -#define RMT_CH6_RX_END_INT_CLR_V 0x1 -#define RMT_CH6_RX_END_INT_CLR_S 18 -/* RMT_CH5_RX_END_INT_CLR : WT ;bitpos:[17] ;default: 1'b0 ; */ -/*description: Set this bit to clear theCH$m_RX_END_INT interrupt..*/ -#define RMT_CH5_RX_END_INT_CLR (BIT(17)) -#define RMT_CH5_RX_END_INT_CLR_M (BIT(17)) -#define RMT_CH5_RX_END_INT_CLR_V 0x1 -#define RMT_CH5_RX_END_INT_CLR_S 17 -/* RMT_CH4_RX_END_INT_CLR : WT ;bitpos:[16] ;default: 1'b0 ; */ -/*description: Set this bit to clear theCH$m_RX_END_INT interrupt..*/ -#define RMT_CH4_RX_END_INT_CLR (BIT(16)) -#define RMT_CH4_RX_END_INT_CLR_M (BIT(16)) -#define RMT_CH4_RX_END_INT_CLR_V 0x1 -#define RMT_CH4_RX_END_INT_CLR_S 16 -/* RMT_CH3_TX_LOOP_INT_CLR : WT ;bitpos:[15] ;default: 1'b0 ; */ -/*description: Set this bit to clear theCH$n_TX_LOOP_INT interrupt..*/ -#define RMT_CH3_TX_LOOP_INT_CLR (BIT(15)) -#define RMT_CH3_TX_LOOP_INT_CLR_M (BIT(15)) -#define RMT_CH3_TX_LOOP_INT_CLR_V 0x1 -#define RMT_CH3_TX_LOOP_INT_CLR_S 15 -/* RMT_CH2_TX_LOOP_INT_CLR : WT ;bitpos:[14] ;default: 1'b0 ; */ -/*description: Set this bit to clear theCH$n_TX_LOOP_INT interrupt..*/ -#define RMT_CH2_TX_LOOP_INT_CLR (BIT(14)) -#define RMT_CH2_TX_LOOP_INT_CLR_M (BIT(14)) -#define RMT_CH2_TX_LOOP_INT_CLR_V 0x1 -#define RMT_CH2_TX_LOOP_INT_CLR_S 14 -/* RMT_CH1_TX_LOOP_INT_CLR : WT ;bitpos:[13] ;default: 1'b0 ; */ -/*description: Set this bit to clear theCH$n_TX_LOOP_INT interrupt..*/ -#define RMT_CH1_TX_LOOP_INT_CLR (BIT(13)) -#define RMT_CH1_TX_LOOP_INT_CLR_M (BIT(13)) -#define RMT_CH1_TX_LOOP_INT_CLR_V 0x1 -#define RMT_CH1_TX_LOOP_INT_CLR_S 13 -/* RMT_CH0_TX_LOOP_INT_CLR : WT ;bitpos:[12] ;default: 1'b0 ; */ -/*description: Set this bit to clear theCH$n_TX_LOOP_INT interrupt..*/ -#define RMT_CH0_TX_LOOP_INT_CLR (BIT(12)) -#define RMT_CH0_TX_LOOP_INT_CLR_M (BIT(12)) -#define RMT_CH0_TX_LOOP_INT_CLR_V 0x1 -#define RMT_CH0_TX_LOOP_INT_CLR_S 12 -/* RMT_CH3_TX_THR_EVENT_INT_CLR : WT ;bitpos:[11] ;default: 1'b0 ; */ -/*description: Set this bit to clear theCH$n_TX_THR_EVENT_INT interrupt..*/ -#define RMT_CH3_TX_THR_EVENT_INT_CLR (BIT(11)) -#define RMT_CH3_TX_THR_EVENT_INT_CLR_M (BIT(11)) -#define RMT_CH3_TX_THR_EVENT_INT_CLR_V 0x1 -#define RMT_CH3_TX_THR_EVENT_INT_CLR_S 11 -/* RMT_CH2_TX_THR_EVENT_INT_CLR : WT ;bitpos:[10] ;default: 1'b0 ; */ -/*description: Set this bit to clear theCH$n_TX_THR_EVENT_INT interrupt..*/ -#define RMT_CH2_TX_THR_EVENT_INT_CLR (BIT(10)) -#define RMT_CH2_TX_THR_EVENT_INT_CLR_M (BIT(10)) -#define RMT_CH2_TX_THR_EVENT_INT_CLR_V 0x1 -#define RMT_CH2_TX_THR_EVENT_INT_CLR_S 10 -/* RMT_CH1_TX_THR_EVENT_INT_CLR : WT ;bitpos:[9] ;default: 1'b0 ; */ -/*description: Set this bit to clear theCH$n_TX_THR_EVENT_INT interrupt..*/ -#define RMT_CH1_TX_THR_EVENT_INT_CLR (BIT(9)) -#define RMT_CH1_TX_THR_EVENT_INT_CLR_M (BIT(9)) -#define RMT_CH1_TX_THR_EVENT_INT_CLR_V 0x1 -#define RMT_CH1_TX_THR_EVENT_INT_CLR_S 9 -/* RMT_CH0_TX_THR_EVENT_INT_CLR : WT ;bitpos:[8] ;default: 1'b0 ; */ -/*description: Set this bit to clear theCH$n_TX_THR_EVENT_INT interrupt..*/ -#define RMT_CH0_TX_THR_EVENT_INT_CLR (BIT(8)) -#define RMT_CH0_TX_THR_EVENT_INT_CLR_M (BIT(8)) -#define RMT_CH0_TX_THR_EVENT_INT_CLR_V 0x1 -#define RMT_CH0_TX_THR_EVENT_INT_CLR_S 8 -/* RMT_CH3_ERR_INT_CLR : WT ;bitpos:[7] ;default: 1'b0 ; */ -/*description: Set this bit to clear theCH$n_ERR_INT interrupt..*/ -#define RMT_CH3_ERR_INT_CLR (BIT(7)) -#define RMT_CH3_ERR_INT_CLR_M (BIT(7)) -#define RMT_CH3_ERR_INT_CLR_V 0x1 -#define RMT_CH3_ERR_INT_CLR_S 7 -/* RMT_CH2_ERR_INT_CLR : WT ;bitpos:[6] ;default: 1'b0 ; */ -/*description: Set this bit to clear theCH$n_ERR_INT interrupt..*/ -#define RMT_CH2_ERR_INT_CLR (BIT(6)) -#define RMT_CH2_ERR_INT_CLR_M (BIT(6)) -#define RMT_CH2_ERR_INT_CLR_V 0x1 -#define RMT_CH2_ERR_INT_CLR_S 6 -/* RMT_CH1_ERR_INT_CLR : WT ;bitpos:[5] ;default: 1'b0 ; */ -/*description: Set this bit to clear theCH$n_ERR_INT interrupt..*/ -#define RMT_CH1_ERR_INT_CLR (BIT(5)) -#define RMT_CH1_ERR_INT_CLR_M (BIT(5)) -#define RMT_CH1_ERR_INT_CLR_V 0x1 -#define RMT_CH1_ERR_INT_CLR_S 5 -/* RMT_CH0_ERR_INT_CLR : WT ;bitpos:[4] ;default: 1'b0 ; */ -/*description: Set this bit to clear theCH$n_ERR_INT interrupt..*/ -#define RMT_CH0_ERR_INT_CLR (BIT(4)) -#define RMT_CH0_ERR_INT_CLR_M (BIT(4)) -#define RMT_CH0_ERR_INT_CLR_V 0x1 -#define RMT_CH0_ERR_INT_CLR_S 4 -/* RMT_CH3_TX_END_INT_CLR : WT ;bitpos:[3] ;default: 1'b0 ; */ -/*description: Set this bit to clear theCH$n_TX_END_INT interrupt..*/ -#define RMT_CH3_TX_END_INT_CLR (BIT(3)) -#define RMT_CH3_TX_END_INT_CLR_M (BIT(3)) -#define RMT_CH3_TX_END_INT_CLR_V 0x1 -#define RMT_CH3_TX_END_INT_CLR_S 3 -/* RMT_CH2_TX_END_INT_CLR : WT ;bitpos:[2] ;default: 1'b0 ; */ -/*description: Set this bit to clear theCH$n_TX_END_INT interrupt..*/ -#define RMT_CH2_TX_END_INT_CLR (BIT(2)) -#define RMT_CH2_TX_END_INT_CLR_M (BIT(2)) -#define RMT_CH2_TX_END_INT_CLR_V 0x1 -#define RMT_CH2_TX_END_INT_CLR_S 2 -/* RMT_CH1_TX_END_INT_CLR : WT ;bitpos:[1] ;default: 1'b0 ; */ -/*description: Set this bit to clear theCH$n_TX_END_INT interrupt..*/ -#define RMT_CH1_TX_END_INT_CLR (BIT(1)) -#define RMT_CH1_TX_END_INT_CLR_M (BIT(1)) -#define RMT_CH1_TX_END_INT_CLR_V 0x1 -#define RMT_CH1_TX_END_INT_CLR_S 1 -/* RMT_CH0_TX_END_INT_CLR : WT ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Set this bit to clear theCH$n_TX_END_INT interrupt..*/ +/** RMT_INT_CLR_REG register + * Interrupt clear bits + */ +#define RMT_INT_CLR_REG (DR_REG_RMT_BASE + 0x7c) +/** RMT_CH0_TX_END_INT_CLR : WT; bitpos: [0]; default: 0; + * Set this bit to clear theCH0_TX_END_INT interrupt. + */ #define RMT_CH0_TX_END_INT_CLR (BIT(0)) -#define RMT_CH0_TX_END_INT_CLR_M (BIT(0)) -#define RMT_CH0_TX_END_INT_CLR_V 0x1 +#define RMT_CH0_TX_END_INT_CLR_M (RMT_CH0_TX_END_INT_CLR_V << RMT_CH0_TX_END_INT_CLR_S) +#define RMT_CH0_TX_END_INT_CLR_V 0x00000001U #define RMT_CH0_TX_END_INT_CLR_S 0 +/** RMT_CH1_TX_END_INT_CLR : WT; bitpos: [1]; default: 0; + * Set this bit to clear theCH1_TX_END_INT interrupt. + */ +#define RMT_CH1_TX_END_INT_CLR (BIT(1)) +#define RMT_CH1_TX_END_INT_CLR_M (RMT_CH1_TX_END_INT_CLR_V << RMT_CH1_TX_END_INT_CLR_S) +#define RMT_CH1_TX_END_INT_CLR_V 0x00000001U +#define RMT_CH1_TX_END_INT_CLR_S 1 +/** RMT_CH2_TX_END_INT_CLR : WT; bitpos: [2]; default: 0; + * Set this bit to clear theCH2_TX_END_INT interrupt. + */ +#define RMT_CH2_TX_END_INT_CLR (BIT(2)) +#define RMT_CH2_TX_END_INT_CLR_M (RMT_CH2_TX_END_INT_CLR_V << RMT_CH2_TX_END_INT_CLR_S) +#define RMT_CH2_TX_END_INT_CLR_V 0x00000001U +#define RMT_CH2_TX_END_INT_CLR_S 2 +/** RMT_CH3_TX_END_INT_CLR : WT; bitpos: [3]; default: 0; + * Set this bit to clear theCH3_TX_END_INT interrupt. + */ +#define RMT_CH3_TX_END_INT_CLR (BIT(3)) +#define RMT_CH3_TX_END_INT_CLR_M (RMT_CH3_TX_END_INT_CLR_V << RMT_CH3_TX_END_INT_CLR_S) +#define RMT_CH3_TX_END_INT_CLR_V 0x00000001U +#define RMT_CH3_TX_END_INT_CLR_S 3 +/** RMT_CH0_ERR_INT_CLR : WT; bitpos: [4]; default: 0; + * Set this bit to clear theCH0_ERR_INT interrupt. + */ +#define RMT_CH0_ERR_INT_CLR (BIT(4)) +#define RMT_CH0_ERR_INT_CLR_M (RMT_CH0_ERR_INT_CLR_V << RMT_CH0_ERR_INT_CLR_S) +#define RMT_CH0_ERR_INT_CLR_V 0x00000001U +#define RMT_CH0_ERR_INT_CLR_S 4 +/** RMT_CH1_ERR_INT_CLR : WT; bitpos: [5]; default: 0; + * Set this bit to clear theCH1_ERR_INT interrupt. + */ +#define RMT_CH1_ERR_INT_CLR (BIT(5)) +#define RMT_CH1_ERR_INT_CLR_M (RMT_CH1_ERR_INT_CLR_V << RMT_CH1_ERR_INT_CLR_S) +#define RMT_CH1_ERR_INT_CLR_V 0x00000001U +#define RMT_CH1_ERR_INT_CLR_S 5 +/** RMT_CH2_ERR_INT_CLR : WT; bitpos: [6]; default: 0; + * Set this bit to clear theCH2_ERR_INT interrupt. + */ +#define RMT_CH2_ERR_INT_CLR (BIT(6)) +#define RMT_CH2_ERR_INT_CLR_M (RMT_CH2_ERR_INT_CLR_V << RMT_CH2_ERR_INT_CLR_S) +#define RMT_CH2_ERR_INT_CLR_V 0x00000001U +#define RMT_CH2_ERR_INT_CLR_S 6 +/** RMT_CH3_ERR_INT_CLR : WT; bitpos: [7]; default: 0; + * Set this bit to clear theCH3_ERR_INT interrupt. + */ +#define RMT_CH3_ERR_INT_CLR (BIT(7)) +#define RMT_CH3_ERR_INT_CLR_M (RMT_CH3_ERR_INT_CLR_V << RMT_CH3_ERR_INT_CLR_S) +#define RMT_CH3_ERR_INT_CLR_V 0x00000001U +#define RMT_CH3_ERR_INT_CLR_S 7 +/** RMT_CH0_TX_THR_EVENT_INT_CLR : WT; bitpos: [8]; default: 0; + * Set this bit to clear theCH0_TX_THR_EVENT_INT interrupt. + */ +#define RMT_CH0_TX_THR_EVENT_INT_CLR (BIT(8)) +#define RMT_CH0_TX_THR_EVENT_INT_CLR_M (RMT_CH0_TX_THR_EVENT_INT_CLR_V << RMT_CH0_TX_THR_EVENT_INT_CLR_S) +#define RMT_CH0_TX_THR_EVENT_INT_CLR_V 0x00000001U +#define RMT_CH0_TX_THR_EVENT_INT_CLR_S 8 +/** RMT_CH1_TX_THR_EVENT_INT_CLR : WT; bitpos: [9]; default: 0; + * Set this bit to clear theCH1_TX_THR_EVENT_INT interrupt. + */ +#define RMT_CH1_TX_THR_EVENT_INT_CLR (BIT(9)) +#define RMT_CH1_TX_THR_EVENT_INT_CLR_M (RMT_CH1_TX_THR_EVENT_INT_CLR_V << RMT_CH1_TX_THR_EVENT_INT_CLR_S) +#define RMT_CH1_TX_THR_EVENT_INT_CLR_V 0x00000001U +#define RMT_CH1_TX_THR_EVENT_INT_CLR_S 9 +/** RMT_CH2_TX_THR_EVENT_INT_CLR : WT; bitpos: [10]; default: 0; + * Set this bit to clear theCH2_TX_THR_EVENT_INT interrupt. + */ +#define RMT_CH2_TX_THR_EVENT_INT_CLR (BIT(10)) +#define RMT_CH2_TX_THR_EVENT_INT_CLR_M (RMT_CH2_TX_THR_EVENT_INT_CLR_V << RMT_CH2_TX_THR_EVENT_INT_CLR_S) +#define RMT_CH2_TX_THR_EVENT_INT_CLR_V 0x00000001U +#define RMT_CH2_TX_THR_EVENT_INT_CLR_S 10 +/** RMT_CH3_TX_THR_EVENT_INT_CLR : WT; bitpos: [11]; default: 0; + * Set this bit to clear theCH3_TX_THR_EVENT_INT interrupt. + */ +#define RMT_CH3_TX_THR_EVENT_INT_CLR (BIT(11)) +#define RMT_CH3_TX_THR_EVENT_INT_CLR_M (RMT_CH3_TX_THR_EVENT_INT_CLR_V << RMT_CH3_TX_THR_EVENT_INT_CLR_S) +#define RMT_CH3_TX_THR_EVENT_INT_CLR_V 0x00000001U +#define RMT_CH3_TX_THR_EVENT_INT_CLR_S 11 +/** RMT_CH0_TX_LOOP_INT_CLR : WT; bitpos: [12]; default: 0; + * Set this bit to clear theCH0_TX_LOOP_INT interrupt. + */ +#define RMT_CH0_TX_LOOP_INT_CLR (BIT(12)) +#define RMT_CH0_TX_LOOP_INT_CLR_M (RMT_CH0_TX_LOOP_INT_CLR_V << RMT_CH0_TX_LOOP_INT_CLR_S) +#define RMT_CH0_TX_LOOP_INT_CLR_V 0x00000001U +#define RMT_CH0_TX_LOOP_INT_CLR_S 12 +/** RMT_CH1_TX_LOOP_INT_CLR : WT; bitpos: [13]; default: 0; + * Set this bit to clear theCH1_TX_LOOP_INT interrupt. + */ +#define RMT_CH1_TX_LOOP_INT_CLR (BIT(13)) +#define RMT_CH1_TX_LOOP_INT_CLR_M (RMT_CH1_TX_LOOP_INT_CLR_V << RMT_CH1_TX_LOOP_INT_CLR_S) +#define RMT_CH1_TX_LOOP_INT_CLR_V 0x00000001U +#define RMT_CH1_TX_LOOP_INT_CLR_S 13 +/** RMT_CH2_TX_LOOP_INT_CLR : WT; bitpos: [14]; default: 0; + * Set this bit to clear theCH2_TX_LOOP_INT interrupt. + */ +#define RMT_CH2_TX_LOOP_INT_CLR (BIT(14)) +#define RMT_CH2_TX_LOOP_INT_CLR_M (RMT_CH2_TX_LOOP_INT_CLR_V << RMT_CH2_TX_LOOP_INT_CLR_S) +#define RMT_CH2_TX_LOOP_INT_CLR_V 0x00000001U +#define RMT_CH2_TX_LOOP_INT_CLR_S 14 +/** RMT_CH3_TX_LOOP_INT_CLR : WT; bitpos: [15]; default: 0; + * Set this bit to clear theCH3_TX_LOOP_INT interrupt. + */ +#define RMT_CH3_TX_LOOP_INT_CLR (BIT(15)) +#define RMT_CH3_TX_LOOP_INT_CLR_M (RMT_CH3_TX_LOOP_INT_CLR_V << RMT_CH3_TX_LOOP_INT_CLR_S) +#define RMT_CH3_TX_LOOP_INT_CLR_V 0x00000001U +#define RMT_CH3_TX_LOOP_INT_CLR_S 15 +/** RMT_CH4_RX_END_INT_CLR : WT; bitpos: [16]; default: 0; + * Set this bit to clear theCH4_RX_END_INT interrupt. + */ +#define RMT_CH4_RX_END_INT_CLR (BIT(16)) +#define RMT_CH4_RX_END_INT_CLR_M (RMT_CH4_RX_END_INT_CLR_V << RMT_CH4_RX_END_INT_CLR_S) +#define RMT_CH4_RX_END_INT_CLR_V 0x00000001U +#define RMT_CH4_RX_END_INT_CLR_S 16 +/** RMT_CH5_RX_END_INT_CLR : WT; bitpos: [17]; default: 0; + * Set this bit to clear theCH5_RX_END_INT interrupt. + */ +#define RMT_CH5_RX_END_INT_CLR (BIT(17)) +#define RMT_CH5_RX_END_INT_CLR_M (RMT_CH5_RX_END_INT_CLR_V << RMT_CH5_RX_END_INT_CLR_S) +#define RMT_CH5_RX_END_INT_CLR_V 0x00000001U +#define RMT_CH5_RX_END_INT_CLR_S 17 +/** RMT_CH6_RX_END_INT_CLR : WT; bitpos: [18]; default: 0; + * Set this bit to clear theCH6_RX_END_INT interrupt. + */ +#define RMT_CH6_RX_END_INT_CLR (BIT(18)) +#define RMT_CH6_RX_END_INT_CLR_M (RMT_CH6_RX_END_INT_CLR_V << RMT_CH6_RX_END_INT_CLR_S) +#define RMT_CH6_RX_END_INT_CLR_V 0x00000001U +#define RMT_CH6_RX_END_INT_CLR_S 18 +/** RMT_CH7_RX_END_INT_CLR : WT; bitpos: [19]; default: 0; + * Set this bit to clear theCH7_RX_END_INT interrupt. + */ +#define RMT_CH7_RX_END_INT_CLR (BIT(19)) +#define RMT_CH7_RX_END_INT_CLR_M (RMT_CH7_RX_END_INT_CLR_V << RMT_CH7_RX_END_INT_CLR_S) +#define RMT_CH7_RX_END_INT_CLR_V 0x00000001U +#define RMT_CH7_RX_END_INT_CLR_S 19 +/** RMT_CH4_ERR_INT_CLR : WT; bitpos: [20]; default: 0; + * Set this bit to clear theCH4_ERR_INT interrupt. + */ +#define RMT_CH4_ERR_INT_CLR (BIT(20)) +#define RMT_CH4_ERR_INT_CLR_M (RMT_CH4_ERR_INT_CLR_V << RMT_CH4_ERR_INT_CLR_S) +#define RMT_CH4_ERR_INT_CLR_V 0x00000001U +#define RMT_CH4_ERR_INT_CLR_S 20 +/** RMT_CH5_ERR_INT_CLR : WT; bitpos: [21]; default: 0; + * Set this bit to clear theCH5_ERR_INT interrupt. + */ +#define RMT_CH5_ERR_INT_CLR (BIT(21)) +#define RMT_CH5_ERR_INT_CLR_M (RMT_CH5_ERR_INT_CLR_V << RMT_CH5_ERR_INT_CLR_S) +#define RMT_CH5_ERR_INT_CLR_V 0x00000001U +#define RMT_CH5_ERR_INT_CLR_S 21 +/** RMT_CH6_ERR_INT_CLR : WT; bitpos: [22]; default: 0; + * Set this bit to clear theCH6_ERR_INT interrupt. + */ +#define RMT_CH6_ERR_INT_CLR (BIT(22)) +#define RMT_CH6_ERR_INT_CLR_M (RMT_CH6_ERR_INT_CLR_V << RMT_CH6_ERR_INT_CLR_S) +#define RMT_CH6_ERR_INT_CLR_V 0x00000001U +#define RMT_CH6_ERR_INT_CLR_S 22 +/** RMT_CH7_ERR_INT_CLR : WT; bitpos: [23]; default: 0; + * Set this bit to clear theCH7_ERR_INT interrupt. + */ +#define RMT_CH7_ERR_INT_CLR (BIT(23)) +#define RMT_CH7_ERR_INT_CLR_M (RMT_CH7_ERR_INT_CLR_V << RMT_CH7_ERR_INT_CLR_S) +#define RMT_CH7_ERR_INT_CLR_V 0x00000001U +#define RMT_CH7_ERR_INT_CLR_S 23 +/** RMT_CH4_RX_THR_EVENT_INT_CLR : WT; bitpos: [24]; default: 0; + * Set this bit to clear theCH4_RX_THR_EVENT_INT interrupt. + */ +#define RMT_CH4_RX_THR_EVENT_INT_CLR (BIT(24)) +#define RMT_CH4_RX_THR_EVENT_INT_CLR_M (RMT_CH4_RX_THR_EVENT_INT_CLR_V << RMT_CH4_RX_THR_EVENT_INT_CLR_S) +#define RMT_CH4_RX_THR_EVENT_INT_CLR_V 0x00000001U +#define RMT_CH4_RX_THR_EVENT_INT_CLR_S 24 +/** RMT_CH5_RX_THR_EVENT_INT_CLR : WT; bitpos: [25]; default: 0; + * Set this bit to clear theCH5_RX_THR_EVENT_INT interrupt. + */ +#define RMT_CH5_RX_THR_EVENT_INT_CLR (BIT(25)) +#define RMT_CH5_RX_THR_EVENT_INT_CLR_M (RMT_CH5_RX_THR_EVENT_INT_CLR_V << RMT_CH5_RX_THR_EVENT_INT_CLR_S) +#define RMT_CH5_RX_THR_EVENT_INT_CLR_V 0x00000001U +#define RMT_CH5_RX_THR_EVENT_INT_CLR_S 25 +/** RMT_CH6_RX_THR_EVENT_INT_CLR : WT; bitpos: [26]; default: 0; + * Set this bit to clear theCH6_RX_THR_EVENT_INT interrupt. + */ +#define RMT_CH6_RX_THR_EVENT_INT_CLR (BIT(26)) +#define RMT_CH6_RX_THR_EVENT_INT_CLR_M (RMT_CH6_RX_THR_EVENT_INT_CLR_V << RMT_CH6_RX_THR_EVENT_INT_CLR_S) +#define RMT_CH6_RX_THR_EVENT_INT_CLR_V 0x00000001U +#define RMT_CH6_RX_THR_EVENT_INT_CLR_S 26 +/** RMT_CH7_RX_THR_EVENT_INT_CLR : WT; bitpos: [27]; default: 0; + * Set this bit to clear theCH7_RX_THR_EVENT_INT interrupt. + */ +#define RMT_CH7_RX_THR_EVENT_INT_CLR (BIT(27)) +#define RMT_CH7_RX_THR_EVENT_INT_CLR_M (RMT_CH7_RX_THR_EVENT_INT_CLR_V << RMT_CH7_RX_THR_EVENT_INT_CLR_S) +#define RMT_CH7_RX_THR_EVENT_INT_CLR_V 0x00000001U +#define RMT_CH7_RX_THR_EVENT_INT_CLR_S 27 +/** RMT_CH3_DMA_ACCESS_FAIL_INT_CLR : WT; bitpos: [28]; default: 0; + * Set this bit to clear the CH3_DMA_ACCESS_FAIL_INT interrupt. + */ +#define RMT_CH3_DMA_ACCESS_FAIL_INT_CLR (BIT(28)) +#define RMT_CH3_DMA_ACCESS_FAIL_INT_CLR_M (RMT_CH3_DMA_ACCESS_FAIL_INT_CLR_V << RMT_CH3_DMA_ACCESS_FAIL_INT_CLR_S) +#define RMT_CH3_DMA_ACCESS_FAIL_INT_CLR_V 0x00000001U +#define RMT_CH3_DMA_ACCESS_FAIL_INT_CLR_S 28 +/** RMT_CH7_DMA_ACCESS_FAIL_INT_CLR : WT; bitpos: [29]; default: 0; + * Set this bit to clear the CH7_DMA_ACCESS_FAIL_INT interrupt. + */ +#define RMT_CH7_DMA_ACCESS_FAIL_INT_CLR (BIT(29)) +#define RMT_CH7_DMA_ACCESS_FAIL_INT_CLR_M (RMT_CH7_DMA_ACCESS_FAIL_INT_CLR_V << RMT_CH7_DMA_ACCESS_FAIL_INT_CLR_S) +#define RMT_CH7_DMA_ACCESS_FAIL_INT_CLR_V 0x00000001U +#define RMT_CH7_DMA_ACCESS_FAIL_INT_CLR_S 29 -#define RMT_CH0CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x80) -/* RMT_CARRIER_HIGH_CH0 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */ -/*description: This register is used to configure carrier wave 's high level clock period for C -HANNEL$n..*/ -#define RMT_CARRIER_HIGH_CH0 0x0000FFFF -#define RMT_CARRIER_HIGH_CH0_M ((RMT_CARRIER_HIGH_CH0_V)<<(RMT_CARRIER_HIGH_CH0_S)) -#define RMT_CARRIER_HIGH_CH0_V 0xFFFF -#define RMT_CARRIER_HIGH_CH0_S 16 -/* RMT_CARRIER_LOW_CH0 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */ -/*description: This register is used to configure carrier wave 's low level clock period for CH -ANNEL$n..*/ -#define RMT_CARRIER_LOW_CH0 0x0000FFFF -#define RMT_CARRIER_LOW_CH0_M ((RMT_CARRIER_LOW_CH0_V)<<(RMT_CARRIER_LOW_CH0_S)) -#define RMT_CARRIER_LOW_CH0_V 0xFFFF +/** RMT_CH0CARRIER_DUTY_REG register + * Channel 0 duty cycle configuration register + */ +#define RMT_CH0CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x80) +/** RMT_CARRIER_LOW_CH0 : R/W; bitpos: [15:0]; default: 64; + * This register is used to configure carrier wave 's low level clock period for + * CHANNEL0. + */ +#define RMT_CARRIER_LOW_CH0 0x0000FFFFU +#define RMT_CARRIER_LOW_CH0_M (RMT_CARRIER_LOW_CH0_V << RMT_CARRIER_LOW_CH0_S) +#define RMT_CARRIER_LOW_CH0_V 0x0000FFFFU #define RMT_CARRIER_LOW_CH0_S 0 +/** RMT_CARRIER_HIGH_CH0 : R/W; bitpos: [31:16]; default: 64; + * This register is used to configure carrier wave 's high level clock period for + * CHANNEL0. + */ +#define RMT_CARRIER_HIGH_CH0 0x0000FFFFU +#define RMT_CARRIER_HIGH_CH0_M (RMT_CARRIER_HIGH_CH0_V << RMT_CARRIER_HIGH_CH0_S) +#define RMT_CARRIER_HIGH_CH0_V 0x0000FFFFU +#define RMT_CARRIER_HIGH_CH0_S 16 -#define RMT_CH1CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x84) -/* RMT_CARRIER_HIGH_CH1 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */ -/*description: This register is used to configure carrier wave 's high level clock period for C -HANNEL$n..*/ -#define RMT_CARRIER_HIGH_CH1 0x0000FFFF -#define RMT_CARRIER_HIGH_CH1_M ((RMT_CARRIER_HIGH_CH1_V)<<(RMT_CARRIER_HIGH_CH1_S)) -#define RMT_CARRIER_HIGH_CH1_V 0xFFFF -#define RMT_CARRIER_HIGH_CH1_S 16 -/* RMT_CARRIER_LOW_CH1 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */ -/*description: This register is used to configure carrier wave 's low level clock period for CH -ANNEL$n..*/ -#define RMT_CARRIER_LOW_CH1 0x0000FFFF -#define RMT_CARRIER_LOW_CH1_M ((RMT_CARRIER_LOW_CH1_V)<<(RMT_CARRIER_LOW_CH1_S)) -#define RMT_CARRIER_LOW_CH1_V 0xFFFF +/** RMT_CH1CARRIER_DUTY_REG register + * Channel 1 duty cycle configuration register + */ +#define RMT_CH1CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x84) +/** RMT_CARRIER_LOW_CH1 : R/W; bitpos: [15:0]; default: 64; + * This register is used to configure carrier wave 's low level clock period for + * CHANNEL1. + */ +#define RMT_CARRIER_LOW_CH1 0x0000FFFFU +#define RMT_CARRIER_LOW_CH1_M (RMT_CARRIER_LOW_CH1_V << RMT_CARRIER_LOW_CH1_S) +#define RMT_CARRIER_LOW_CH1_V 0x0000FFFFU #define RMT_CARRIER_LOW_CH1_S 0 +/** RMT_CARRIER_HIGH_CH1 : R/W; bitpos: [31:16]; default: 64; + * This register is used to configure carrier wave 's high level clock period for + * CHANNEL1. + */ +#define RMT_CARRIER_HIGH_CH1 0x0000FFFFU +#define RMT_CARRIER_HIGH_CH1_M (RMT_CARRIER_HIGH_CH1_V << RMT_CARRIER_HIGH_CH1_S) +#define RMT_CARRIER_HIGH_CH1_V 0x0000FFFFU +#define RMT_CARRIER_HIGH_CH1_S 16 -#define RMT_CH2CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x88) -/* RMT_CARRIER_HIGH_CH2 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */ -/*description: This register is used to configure carrier wave 's high level clock period for C -HANNEL$n..*/ -#define RMT_CARRIER_HIGH_CH2 0x0000FFFF -#define RMT_CARRIER_HIGH_CH2_M ((RMT_CARRIER_HIGH_CH2_V)<<(RMT_CARRIER_HIGH_CH2_S)) -#define RMT_CARRIER_HIGH_CH2_V 0xFFFF -#define RMT_CARRIER_HIGH_CH2_S 16 -/* RMT_CARRIER_LOW_CH2 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */ -/*description: This register is used to configure carrier wave 's low level clock period for CH -ANNEL$n..*/ -#define RMT_CARRIER_LOW_CH2 0x0000FFFF -#define RMT_CARRIER_LOW_CH2_M ((RMT_CARRIER_LOW_CH2_V)<<(RMT_CARRIER_LOW_CH2_S)) -#define RMT_CARRIER_LOW_CH2_V 0xFFFF +/** RMT_CH2CARRIER_DUTY_REG register + * Channel 2 duty cycle configuration register + */ +#define RMT_CH2CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x88) +/** RMT_CARRIER_LOW_CH2 : R/W; bitpos: [15:0]; default: 64; + * This register is used to configure carrier wave 's low level clock period for + * CHANNEL2. + */ +#define RMT_CARRIER_LOW_CH2 0x0000FFFFU +#define RMT_CARRIER_LOW_CH2_M (RMT_CARRIER_LOW_CH2_V << RMT_CARRIER_LOW_CH2_S) +#define RMT_CARRIER_LOW_CH2_V 0x0000FFFFU #define RMT_CARRIER_LOW_CH2_S 0 +/** RMT_CARRIER_HIGH_CH2 : R/W; bitpos: [31:16]; default: 64; + * This register is used to configure carrier wave 's high level clock period for + * CHANNEL2. + */ +#define RMT_CARRIER_HIGH_CH2 0x0000FFFFU +#define RMT_CARRIER_HIGH_CH2_M (RMT_CARRIER_HIGH_CH2_V << RMT_CARRIER_HIGH_CH2_S) +#define RMT_CARRIER_HIGH_CH2_V 0x0000FFFFU +#define RMT_CARRIER_HIGH_CH2_S 16 -#define RMT_CH3CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x8C) -/* RMT_CARRIER_HIGH_CH3 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */ -/*description: This register is used to configure carrier wave 's high level clock period for C -HANNEL$n..*/ -#define RMT_CARRIER_HIGH_CH3 0x0000FFFF -#define RMT_CARRIER_HIGH_CH3_M ((RMT_CARRIER_HIGH_CH3_V)<<(RMT_CARRIER_HIGH_CH3_S)) -#define RMT_CARRIER_HIGH_CH3_V 0xFFFF -#define RMT_CARRIER_HIGH_CH3_S 16 -/* RMT_CARRIER_LOW_CH3 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */ -/*description: This register is used to configure carrier wave 's low level clock period for CH -ANNEL$n..*/ -#define RMT_CARRIER_LOW_CH3 0x0000FFFF -#define RMT_CARRIER_LOW_CH3_M ((RMT_CARRIER_LOW_CH3_V)<<(RMT_CARRIER_LOW_CH3_S)) -#define RMT_CARRIER_LOW_CH3_V 0xFFFF +/** RMT_CH3CARRIER_DUTY_REG register + * Channel 3 duty cycle configuration register + */ +#define RMT_CH3CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x8c) +/** RMT_CARRIER_LOW_CH3 : R/W; bitpos: [15:0]; default: 64; + * This register is used to configure carrier wave 's low level clock period for + * CHANNEL3. + */ +#define RMT_CARRIER_LOW_CH3 0x0000FFFFU +#define RMT_CARRIER_LOW_CH3_M (RMT_CARRIER_LOW_CH3_V << RMT_CARRIER_LOW_CH3_S) +#define RMT_CARRIER_LOW_CH3_V 0x0000FFFFU #define RMT_CARRIER_LOW_CH3_S 0 +/** RMT_CARRIER_HIGH_CH3 : R/W; bitpos: [31:16]; default: 64; + * This register is used to configure carrier wave 's high level clock period for + * CHANNEL3. + */ +#define RMT_CARRIER_HIGH_CH3 0x0000FFFFU +#define RMT_CARRIER_HIGH_CH3_M (RMT_CARRIER_HIGH_CH3_V << RMT_CARRIER_HIGH_CH3_S) +#define RMT_CARRIER_HIGH_CH3_V 0x0000FFFFU +#define RMT_CARRIER_HIGH_CH3_S 16 -#define RMT_CH4_RX_CARRIER_RM_REG (DR_REG_RMT_BASE + 0x90) -/* RMT_CARRIER_HIGH_THRES_CH4 : R/W ;bitpos:[31:16] ;default: 16'h0 ; */ -/*description: The high level period in a carrier modulation mode is (REG_RMT_REG_CARRIER_HIGH_ -THRES_CH$m + 1) for channel $m..*/ -#define RMT_CARRIER_HIGH_THRES_CH4 0x0000FFFF -#define RMT_CARRIER_HIGH_THRES_CH4_M ((RMT_CARRIER_HIGH_THRES_CH4_V)<<(RMT_CARRIER_HIGH_THRES_CH4_S)) -#define RMT_CARRIER_HIGH_THRES_CH4_V 0xFFFF -#define RMT_CARRIER_HIGH_THRES_CH4_S 16 -/* RMT_CARRIER_LOW_THRES_CH4 : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: The low level period in a carrier modulation mode is (REG_RMT_REG_CARRIER_LOW_TH -RES_CH$m + 1) for channel $m..*/ -#define RMT_CARRIER_LOW_THRES_CH4 0x0000FFFF -#define RMT_CARRIER_LOW_THRES_CH4_M ((RMT_CARRIER_LOW_THRES_CH4_V)<<(RMT_CARRIER_LOW_THRES_CH4_S)) -#define RMT_CARRIER_LOW_THRES_CH4_V 0xFFFF +/** RMT_CH4_RX_CARRIER_RM_REG register + * Channel 4 carrier remove register + */ +#define RMT_CH4_RX_CARRIER_RM_REG (DR_REG_RMT_BASE + 0x90) +/** RMT_CARRIER_LOW_THRES_CH4 : R/W; bitpos: [15:0]; default: 0; + * The low level period in a carrier modulation mode is + * (REG_RMT_REG_CARRIER_LOW_THRES_CH4 + 1) for channel 4. + */ +#define RMT_CARRIER_LOW_THRES_CH4 0x0000FFFFU +#define RMT_CARRIER_LOW_THRES_CH4_M (RMT_CARRIER_LOW_THRES_CH4_V << RMT_CARRIER_LOW_THRES_CH4_S) +#define RMT_CARRIER_LOW_THRES_CH4_V 0x0000FFFFU #define RMT_CARRIER_LOW_THRES_CH4_S 0 +/** RMT_CARRIER_HIGH_THRES_CH4 : R/W; bitpos: [31:16]; default: 0; + * The high level period in a carrier modulation mode is + * (REG_RMT_REG_CARRIER_HIGH_THRES_CH4 + 1) for channel 4. + */ +#define RMT_CARRIER_HIGH_THRES_CH4 0x0000FFFFU +#define RMT_CARRIER_HIGH_THRES_CH4_M (RMT_CARRIER_HIGH_THRES_CH4_V << RMT_CARRIER_HIGH_THRES_CH4_S) +#define RMT_CARRIER_HIGH_THRES_CH4_V 0x0000FFFFU +#define RMT_CARRIER_HIGH_THRES_CH4_S 16 -#define RMT_CH5_RX_CARRIER_RM_REG (DR_REG_RMT_BASE + 0x94) -/* RMT_CARRIER_HIGH_THRES_CH5 : R/W ;bitpos:[31:16] ;default: 16'h0 ; */ -/*description: The high level period in a carrier modulation mode is (REG_RMT_REG_CARRIER_HIGH_ -THRES_CH$m + 1) for channel $m..*/ -#define RMT_CARRIER_HIGH_THRES_CH5 0x0000FFFF -#define RMT_CARRIER_HIGH_THRES_CH5_M ((RMT_CARRIER_HIGH_THRES_CH5_V)<<(RMT_CARRIER_HIGH_THRES_CH5_S)) -#define RMT_CARRIER_HIGH_THRES_CH5_V 0xFFFF -#define RMT_CARRIER_HIGH_THRES_CH5_S 16 -/* RMT_CARRIER_LOW_THRES_CH5 : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: The low level period in a carrier modulation mode is (REG_RMT_REG_CARRIER_LOW_TH -RES_CH$m + 1) for channel $m..*/ -#define RMT_CARRIER_LOW_THRES_CH5 0x0000FFFF -#define RMT_CARRIER_LOW_THRES_CH5_M ((RMT_CARRIER_LOW_THRES_CH5_V)<<(RMT_CARRIER_LOW_THRES_CH5_S)) -#define RMT_CARRIER_LOW_THRES_CH5_V 0xFFFF +/** RMT_CH5_RX_CARRIER_RM_REG register + * Channel 5 carrier remove register + */ +#define RMT_CH5_RX_CARRIER_RM_REG (DR_REG_RMT_BASE + 0x94) +/** RMT_CARRIER_LOW_THRES_CH5 : R/W; bitpos: [15:0]; default: 0; + * The low level period in a carrier modulation mode is + * (REG_RMT_REG_CARRIER_LOW_THRES_CH5 + 1) for channel 5. + */ +#define RMT_CARRIER_LOW_THRES_CH5 0x0000FFFFU +#define RMT_CARRIER_LOW_THRES_CH5_M (RMT_CARRIER_LOW_THRES_CH5_V << RMT_CARRIER_LOW_THRES_CH5_S) +#define RMT_CARRIER_LOW_THRES_CH5_V 0x0000FFFFU #define RMT_CARRIER_LOW_THRES_CH5_S 0 +/** RMT_CARRIER_HIGH_THRES_CH5 : R/W; bitpos: [31:16]; default: 0; + * The high level period in a carrier modulation mode is + * (REG_RMT_REG_CARRIER_HIGH_THRES_CH5 + 1) for channel 5. + */ +#define RMT_CARRIER_HIGH_THRES_CH5 0x0000FFFFU +#define RMT_CARRIER_HIGH_THRES_CH5_M (RMT_CARRIER_HIGH_THRES_CH5_V << RMT_CARRIER_HIGH_THRES_CH5_S) +#define RMT_CARRIER_HIGH_THRES_CH5_V 0x0000FFFFU +#define RMT_CARRIER_HIGH_THRES_CH5_S 16 -#define RMT_CH6_RX_CARRIER_RM_REG (DR_REG_RMT_BASE + 0x98) -/* RMT_CARRIER_HIGH_THRES_CH6 : R/W ;bitpos:[31:16] ;default: 16'h0 ; */ -/*description: The high level period in a carrier modulation mode is (REG_RMT_REG_CARRIER_HIGH_ -THRES_CH$m + 1) for channel $m..*/ -#define RMT_CARRIER_HIGH_THRES_CH6 0x0000FFFF -#define RMT_CARRIER_HIGH_THRES_CH6_M ((RMT_CARRIER_HIGH_THRES_CH6_V)<<(RMT_CARRIER_HIGH_THRES_CH6_S)) -#define RMT_CARRIER_HIGH_THRES_CH6_V 0xFFFF -#define RMT_CARRIER_HIGH_THRES_CH6_S 16 -/* RMT_CARRIER_LOW_THRES_CH6 : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: The low level period in a carrier modulation mode is (REG_RMT_REG_CARRIER_LOW_TH -RES_CH$m + 1) for channel $m..*/ -#define RMT_CARRIER_LOW_THRES_CH6 0x0000FFFF -#define RMT_CARRIER_LOW_THRES_CH6_M ((RMT_CARRIER_LOW_THRES_CH6_V)<<(RMT_CARRIER_LOW_THRES_CH6_S)) -#define RMT_CARRIER_LOW_THRES_CH6_V 0xFFFF +/** RMT_CH6_RX_CARRIER_RM_REG register + * Channel 6 carrier remove register + */ +#define RMT_CH6_RX_CARRIER_RM_REG (DR_REG_RMT_BASE + 0x98) +/** RMT_CARRIER_LOW_THRES_CH6 : R/W; bitpos: [15:0]; default: 0; + * The low level period in a carrier modulation mode is + * (REG_RMT_REG_CARRIER_LOW_THRES_CH6 + 1) for channel 6. + */ +#define RMT_CARRIER_LOW_THRES_CH6 0x0000FFFFU +#define RMT_CARRIER_LOW_THRES_CH6_M (RMT_CARRIER_LOW_THRES_CH6_V << RMT_CARRIER_LOW_THRES_CH6_S) +#define RMT_CARRIER_LOW_THRES_CH6_V 0x0000FFFFU #define RMT_CARRIER_LOW_THRES_CH6_S 0 +/** RMT_CARRIER_HIGH_THRES_CH6 : R/W; bitpos: [31:16]; default: 0; + * The high level period in a carrier modulation mode is + * (REG_RMT_REG_CARRIER_HIGH_THRES_CH6 + 1) for channel 6. + */ +#define RMT_CARRIER_HIGH_THRES_CH6 0x0000FFFFU +#define RMT_CARRIER_HIGH_THRES_CH6_M (RMT_CARRIER_HIGH_THRES_CH6_V << RMT_CARRIER_HIGH_THRES_CH6_S) +#define RMT_CARRIER_HIGH_THRES_CH6_V 0x0000FFFFU +#define RMT_CARRIER_HIGH_THRES_CH6_S 16 -#define RMT_CH7_RX_CARRIER_RM_REG (DR_REG_RMT_BASE + 0x9C) -/* RMT_CARRIER_HIGH_THRES_CH7 : R/W ;bitpos:[31:16] ;default: 16'h0 ; */ -/*description: The high level period in a carrier modulation mode is (REG_RMT_REG_CARRIER_HIGH_ -THRES_CH$m + 1) for channel $m..*/ -#define RMT_CARRIER_HIGH_THRES_CH7 0x0000FFFF -#define RMT_CARRIER_HIGH_THRES_CH7_M ((RMT_CARRIER_HIGH_THRES_CH7_V)<<(RMT_CARRIER_HIGH_THRES_CH7_S)) -#define RMT_CARRIER_HIGH_THRES_CH7_V 0xFFFF -#define RMT_CARRIER_HIGH_THRES_CH7_S 16 -/* RMT_CARRIER_LOW_THRES_CH7 : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ -/*description: The low level period in a carrier modulation mode is (REG_RMT_REG_CARRIER_LOW_TH -RES_CH$m + 1) for channel $m..*/ -#define RMT_CARRIER_LOW_THRES_CH7 0x0000FFFF -#define RMT_CARRIER_LOW_THRES_CH7_M ((RMT_CARRIER_LOW_THRES_CH7_V)<<(RMT_CARRIER_LOW_THRES_CH7_S)) -#define RMT_CARRIER_LOW_THRES_CH7_V 0xFFFF +/** RMT_CH7_RX_CARRIER_RM_REG register + * Channel 7 carrier remove register + */ +#define RMT_CH7_RX_CARRIER_RM_REG (DR_REG_RMT_BASE + 0x9c) +/** RMT_CARRIER_LOW_THRES_CH7 : R/W; bitpos: [15:0]; default: 0; + * The low level period in a carrier modulation mode is + * (REG_RMT_REG_CARRIER_LOW_THRES_CH7 + 1) for channel 7. + */ +#define RMT_CARRIER_LOW_THRES_CH7 0x0000FFFFU +#define RMT_CARRIER_LOW_THRES_CH7_M (RMT_CARRIER_LOW_THRES_CH7_V << RMT_CARRIER_LOW_THRES_CH7_S) +#define RMT_CARRIER_LOW_THRES_CH7_V 0x0000FFFFU #define RMT_CARRIER_LOW_THRES_CH7_S 0 +/** RMT_CARRIER_HIGH_THRES_CH7 : R/W; bitpos: [31:16]; default: 0; + * The high level period in a carrier modulation mode is + * (REG_RMT_REG_CARRIER_HIGH_THRES_CH7 + 1) for channel 7. + */ +#define RMT_CARRIER_HIGH_THRES_CH7 0x0000FFFFU +#define RMT_CARRIER_HIGH_THRES_CH7_M (RMT_CARRIER_HIGH_THRES_CH7_V << RMT_CARRIER_HIGH_THRES_CH7_S) +#define RMT_CARRIER_HIGH_THRES_CH7_V 0x0000FFFFU +#define RMT_CARRIER_HIGH_THRES_CH7_S 16 -#define RMT_CH0_TX_LIM_REG (DR_REG_RMT_BASE + 0xA0) -/* RMT_LOOP_STOP_EN_CH0 : R/W ;bitpos:[21] ;default: 1'b0 ; */ -/*description: This bit is used to enable the loop send stop function after the loop counter co -unts to loop number for CHANNEL$n..*/ -#define RMT_LOOP_STOP_EN_CH0 (BIT(21)) -#define RMT_LOOP_STOP_EN_CH0_M (BIT(21)) -#define RMT_LOOP_STOP_EN_CH0_V 0x1 -#define RMT_LOOP_STOP_EN_CH0_S 21 -/* RMT_LOOP_COUNT_RESET_CH0 : WT ;bitpos:[20] ;default: 1'b0 ; */ -/*description: This register is used to reset the loop count when tx_conti_mode is valid..*/ -#define RMT_LOOP_COUNT_RESET_CH0 (BIT(20)) -#define RMT_LOOP_COUNT_RESET_CH0_M (BIT(20)) -#define RMT_LOOP_COUNT_RESET_CH0_V 0x1 -#define RMT_LOOP_COUNT_RESET_CH0_S 20 -/* RMT_TX_LOOP_CNT_EN_CH0 : R/W ;bitpos:[19] ;default: 1'b0 ; */ -/*description: This register is the enabled bit for loop count..*/ -#define RMT_TX_LOOP_CNT_EN_CH0 (BIT(19)) -#define RMT_TX_LOOP_CNT_EN_CH0_M (BIT(19)) -#define RMT_TX_LOOP_CNT_EN_CH0_V 0x1 -#define RMT_TX_LOOP_CNT_EN_CH0_S 19 -/* RMT_TX_LOOP_NUM_CH0 : R/W ;bitpos:[18:9] ;default: 10'b0 ; */ -/*description: This register is used to configure the maximum loop count when tx_conti_mode is -valid..*/ -#define RMT_TX_LOOP_NUM_CH0 0x000003FF -#define RMT_TX_LOOP_NUM_CH0_M ((RMT_TX_LOOP_NUM_CH0_V)<<(RMT_TX_LOOP_NUM_CH0_S)) -#define RMT_TX_LOOP_NUM_CH0_V 0x3FF -#define RMT_TX_LOOP_NUM_CH0_S 9 -/* RMT_TX_LIM_CH0 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */ -/*description: This register is used to configure the maximum entries that CHANNEL$n can send o -ut..*/ -#define RMT_TX_LIM_CH0 0x000001FF -#define RMT_TX_LIM_CH0_M ((RMT_TX_LIM_CH0_V)<<(RMT_TX_LIM_CH0_S)) -#define RMT_TX_LIM_CH0_V 0x1FF +/** RMT_CH0_TX_LIM_REG register + * Channel 0 Tx event configuration register + */ +#define RMT_CH0_TX_LIM_REG (DR_REG_RMT_BASE + 0xa0) +/** RMT_TX_LIM_CH0 : R/W; bitpos: [8:0]; default: 128; + * This register is used to configure the maximum entries that CHANNEL0 can send out. + */ +#define RMT_TX_LIM_CH0 0x000001FFU +#define RMT_TX_LIM_CH0_M (RMT_TX_LIM_CH0_V << RMT_TX_LIM_CH0_S) +#define RMT_TX_LIM_CH0_V 0x000001FFU #define RMT_TX_LIM_CH0_S 0 +/** RMT_TX_LOOP_NUM_CH0 : R/W; bitpos: [18:9]; default: 0; + * This register is used to configure the maximum loop count when tx_conti_mode is + * valid. + */ +#define RMT_TX_LOOP_NUM_CH0 0x000003FFU +#define RMT_TX_LOOP_NUM_CH0_M (RMT_TX_LOOP_NUM_CH0_V << RMT_TX_LOOP_NUM_CH0_S) +#define RMT_TX_LOOP_NUM_CH0_V 0x000003FFU +#define RMT_TX_LOOP_NUM_CH0_S 9 +/** RMT_TX_LOOP_CNT_EN_CH0 : R/W; bitpos: [19]; default: 0; + * This register is the enabled bit for loop count. + */ +#define RMT_TX_LOOP_CNT_EN_CH0 (BIT(19)) +#define RMT_TX_LOOP_CNT_EN_CH0_M (RMT_TX_LOOP_CNT_EN_CH0_V << RMT_TX_LOOP_CNT_EN_CH0_S) +#define RMT_TX_LOOP_CNT_EN_CH0_V 0x00000001U +#define RMT_TX_LOOP_CNT_EN_CH0_S 19 +/** RMT_LOOP_COUNT_RESET_CH0 : WT; bitpos: [20]; default: 0; + * This register is used to reset the loop count when tx_conti_mode is valid. + */ +#define RMT_LOOP_COUNT_RESET_CH0 (BIT(20)) +#define RMT_LOOP_COUNT_RESET_CH0_M (RMT_LOOP_COUNT_RESET_CH0_V << RMT_LOOP_COUNT_RESET_CH0_S) +#define RMT_LOOP_COUNT_RESET_CH0_V 0x00000001U +#define RMT_LOOP_COUNT_RESET_CH0_S 20 +/** RMT_LOOP_STOP_EN_CH0 : R/W; bitpos: [21]; default: 0; + * This bit is used to enable the loop send stop function after the loop counter + * counts to loop number for CHANNEL0. + */ +#define RMT_LOOP_STOP_EN_CH0 (BIT(21)) +#define RMT_LOOP_STOP_EN_CH0_M (RMT_LOOP_STOP_EN_CH0_V << RMT_LOOP_STOP_EN_CH0_S) +#define RMT_LOOP_STOP_EN_CH0_V 0x00000001U +#define RMT_LOOP_STOP_EN_CH0_S 21 -#define RMT_CH1_TX_LIM_REG (DR_REG_RMT_BASE + 0xA4) -/* RMT_LOOP_STOP_EN_CH1 : R/W ;bitpos:[21] ;default: 1'b0 ; */ -/*description: This bit is used to enable the loop send stop function after the loop counter co -unts to loop number for CHANNEL$n..*/ -#define RMT_LOOP_STOP_EN_CH1 (BIT(21)) -#define RMT_LOOP_STOP_EN_CH1_M (BIT(21)) -#define RMT_LOOP_STOP_EN_CH1_V 0x1 -#define RMT_LOOP_STOP_EN_CH1_S 21 -/* RMT_LOOP_COUNT_RESET_CH1 : WT ;bitpos:[20] ;default: 1'b0 ; */ -/*description: This register is used to reset the loop count when tx_conti_mode is valid..*/ -#define RMT_LOOP_COUNT_RESET_CH1 (BIT(20)) -#define RMT_LOOP_COUNT_RESET_CH1_M (BIT(20)) -#define RMT_LOOP_COUNT_RESET_CH1_V 0x1 -#define RMT_LOOP_COUNT_RESET_CH1_S 20 -/* RMT_TX_LOOP_CNT_EN_CH1 : R/W ;bitpos:[19] ;default: 1'b0 ; */ -/*description: This register is the enabled bit for loop count..*/ -#define RMT_TX_LOOP_CNT_EN_CH1 (BIT(19)) -#define RMT_TX_LOOP_CNT_EN_CH1_M (BIT(19)) -#define RMT_TX_LOOP_CNT_EN_CH1_V 0x1 -#define RMT_TX_LOOP_CNT_EN_CH1_S 19 -/* RMT_TX_LOOP_NUM_CH1 : R/W ;bitpos:[18:9] ;default: 10'b0 ; */ -/*description: This register is used to configure the maximum loop count when tx_conti_mode is -valid..*/ -#define RMT_TX_LOOP_NUM_CH1 0x000003FF -#define RMT_TX_LOOP_NUM_CH1_M ((RMT_TX_LOOP_NUM_CH1_V)<<(RMT_TX_LOOP_NUM_CH1_S)) -#define RMT_TX_LOOP_NUM_CH1_V 0x3FF -#define RMT_TX_LOOP_NUM_CH1_S 9 -/* RMT_TX_LIM_CH1 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */ -/*description: This register is used to configure the maximum entries that CHANNEL$n can send o -ut..*/ -#define RMT_TX_LIM_CH1 0x000001FF -#define RMT_TX_LIM_CH1_M ((RMT_TX_LIM_CH1_V)<<(RMT_TX_LIM_CH1_S)) -#define RMT_TX_LIM_CH1_V 0x1FF +/** RMT_CH1_TX_LIM_REG register + * Channel 1 Tx event configuration register + */ +#define RMT_CH1_TX_LIM_REG (DR_REG_RMT_BASE + 0xa4) +/** RMT_TX_LIM_CH1 : R/W; bitpos: [8:0]; default: 128; + * This register is used to configure the maximum entries that CHANNEL1 can send out. + */ +#define RMT_TX_LIM_CH1 0x000001FFU +#define RMT_TX_LIM_CH1_M (RMT_TX_LIM_CH1_V << RMT_TX_LIM_CH1_S) +#define RMT_TX_LIM_CH1_V 0x000001FFU #define RMT_TX_LIM_CH1_S 0 +/** RMT_TX_LOOP_NUM_CH1 : R/W; bitpos: [18:9]; default: 0; + * This register is used to configure the maximum loop count when tx_conti_mode is + * valid. + */ +#define RMT_TX_LOOP_NUM_CH1 0x000003FFU +#define RMT_TX_LOOP_NUM_CH1_M (RMT_TX_LOOP_NUM_CH1_V << RMT_TX_LOOP_NUM_CH1_S) +#define RMT_TX_LOOP_NUM_CH1_V 0x000003FFU +#define RMT_TX_LOOP_NUM_CH1_S 9 +/** RMT_TX_LOOP_CNT_EN_CH1 : R/W; bitpos: [19]; default: 0; + * This register is the enabled bit for loop count. + */ +#define RMT_TX_LOOP_CNT_EN_CH1 (BIT(19)) +#define RMT_TX_LOOP_CNT_EN_CH1_M (RMT_TX_LOOP_CNT_EN_CH1_V << RMT_TX_LOOP_CNT_EN_CH1_S) +#define RMT_TX_LOOP_CNT_EN_CH1_V 0x00000001U +#define RMT_TX_LOOP_CNT_EN_CH1_S 19 +/** RMT_LOOP_COUNT_RESET_CH1 : WT; bitpos: [20]; default: 0; + * This register is used to reset the loop count when tx_conti_mode is valid. + */ +#define RMT_LOOP_COUNT_RESET_CH1 (BIT(20)) +#define RMT_LOOP_COUNT_RESET_CH1_M (RMT_LOOP_COUNT_RESET_CH1_V << RMT_LOOP_COUNT_RESET_CH1_S) +#define RMT_LOOP_COUNT_RESET_CH1_V 0x00000001U +#define RMT_LOOP_COUNT_RESET_CH1_S 20 +/** RMT_LOOP_STOP_EN_CH1 : R/W; bitpos: [21]; default: 0; + * This bit is used to enable the loop send stop function after the loop counter + * counts to loop number for CHANNEL1. + */ +#define RMT_LOOP_STOP_EN_CH1 (BIT(21)) +#define RMT_LOOP_STOP_EN_CH1_M (RMT_LOOP_STOP_EN_CH1_V << RMT_LOOP_STOP_EN_CH1_S) +#define RMT_LOOP_STOP_EN_CH1_V 0x00000001U +#define RMT_LOOP_STOP_EN_CH1_S 21 -#define RMT_CH2_TX_LIM_REG (DR_REG_RMT_BASE + 0xA8) -/* RMT_LOOP_STOP_EN_CH2 : R/W ;bitpos:[21] ;default: 1'b0 ; */ -/*description: This bit is used to enable the loop send stop function after the loop counter co -unts to loop number for CHANNEL$n..*/ -#define RMT_LOOP_STOP_EN_CH2 (BIT(21)) -#define RMT_LOOP_STOP_EN_CH2_M (BIT(21)) -#define RMT_LOOP_STOP_EN_CH2_V 0x1 -#define RMT_LOOP_STOP_EN_CH2_S 21 -/* RMT_LOOP_COUNT_RESET_CH2 : WT ;bitpos:[20] ;default: 1'b0 ; */ -/*description: This register is used to reset the loop count when tx_conti_mode is valid..*/ -#define RMT_LOOP_COUNT_RESET_CH2 (BIT(20)) -#define RMT_LOOP_COUNT_RESET_CH2_M (BIT(20)) -#define RMT_LOOP_COUNT_RESET_CH2_V 0x1 -#define RMT_LOOP_COUNT_RESET_CH2_S 20 -/* RMT_TX_LOOP_CNT_EN_CH2 : R/W ;bitpos:[19] ;default: 1'b0 ; */ -/*description: This register is the enabled bit for loop count..*/ -#define RMT_TX_LOOP_CNT_EN_CH2 (BIT(19)) -#define RMT_TX_LOOP_CNT_EN_CH2_M (BIT(19)) -#define RMT_TX_LOOP_CNT_EN_CH2_V 0x1 -#define RMT_TX_LOOP_CNT_EN_CH2_S 19 -/* RMT_TX_LOOP_NUM_CH2 : R/W ;bitpos:[18:9] ;default: 10'b0 ; */ -/*description: This register is used to configure the maximum loop count when tx_conti_mode is -valid..*/ -#define RMT_TX_LOOP_NUM_CH2 0x000003FF -#define RMT_TX_LOOP_NUM_CH2_M ((RMT_TX_LOOP_NUM_CH2_V)<<(RMT_TX_LOOP_NUM_CH2_S)) -#define RMT_TX_LOOP_NUM_CH2_V 0x3FF -#define RMT_TX_LOOP_NUM_CH2_S 9 -/* RMT_TX_LIM_CH2 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */ -/*description: This register is used to configure the maximum entries that CHANNEL$n can send o -ut..*/ -#define RMT_TX_LIM_CH2 0x000001FF -#define RMT_TX_LIM_CH2_M ((RMT_TX_LIM_CH2_V)<<(RMT_TX_LIM_CH2_S)) -#define RMT_TX_LIM_CH2_V 0x1FF +/** RMT_CH2_TX_LIM_REG register + * Channel 2 Tx event configuration register + */ +#define RMT_CH2_TX_LIM_REG (DR_REG_RMT_BASE + 0xa8) +/** RMT_TX_LIM_CH2 : R/W; bitpos: [8:0]; default: 128; + * This register is used to configure the maximum entries that CHANNEL2 can send out. + */ +#define RMT_TX_LIM_CH2 0x000001FFU +#define RMT_TX_LIM_CH2_M (RMT_TX_LIM_CH2_V << RMT_TX_LIM_CH2_S) +#define RMT_TX_LIM_CH2_V 0x000001FFU #define RMT_TX_LIM_CH2_S 0 +/** RMT_TX_LOOP_NUM_CH2 : R/W; bitpos: [18:9]; default: 0; + * This register is used to configure the maximum loop count when tx_conti_mode is + * valid. + */ +#define RMT_TX_LOOP_NUM_CH2 0x000003FFU +#define RMT_TX_LOOP_NUM_CH2_M (RMT_TX_LOOP_NUM_CH2_V << RMT_TX_LOOP_NUM_CH2_S) +#define RMT_TX_LOOP_NUM_CH2_V 0x000003FFU +#define RMT_TX_LOOP_NUM_CH2_S 9 +/** RMT_TX_LOOP_CNT_EN_CH2 : R/W; bitpos: [19]; default: 0; + * This register is the enabled bit for loop count. + */ +#define RMT_TX_LOOP_CNT_EN_CH2 (BIT(19)) +#define RMT_TX_LOOP_CNT_EN_CH2_M (RMT_TX_LOOP_CNT_EN_CH2_V << RMT_TX_LOOP_CNT_EN_CH2_S) +#define RMT_TX_LOOP_CNT_EN_CH2_V 0x00000001U +#define RMT_TX_LOOP_CNT_EN_CH2_S 19 +/** RMT_LOOP_COUNT_RESET_CH2 : WT; bitpos: [20]; default: 0; + * This register is used to reset the loop count when tx_conti_mode is valid. + */ +#define RMT_LOOP_COUNT_RESET_CH2 (BIT(20)) +#define RMT_LOOP_COUNT_RESET_CH2_M (RMT_LOOP_COUNT_RESET_CH2_V << RMT_LOOP_COUNT_RESET_CH2_S) +#define RMT_LOOP_COUNT_RESET_CH2_V 0x00000001U +#define RMT_LOOP_COUNT_RESET_CH2_S 20 +/** RMT_LOOP_STOP_EN_CH2 : R/W; bitpos: [21]; default: 0; + * This bit is used to enable the loop send stop function after the loop counter + * counts to loop number for CHANNEL2. + */ +#define RMT_LOOP_STOP_EN_CH2 (BIT(21)) +#define RMT_LOOP_STOP_EN_CH2_M (RMT_LOOP_STOP_EN_CH2_V << RMT_LOOP_STOP_EN_CH2_S) +#define RMT_LOOP_STOP_EN_CH2_V 0x00000001U +#define RMT_LOOP_STOP_EN_CH2_S 21 -#define RMT_CH3_TX_LIM_REG (DR_REG_RMT_BASE + 0xAC) -/* RMT_LOOP_STOP_EN_CH3 : R/W ;bitpos:[21] ;default: 1'b0 ; */ -/*description: This bit is used to enable the loop send stop function after the loop counter co -unts to loop number for CHANNEL$n..*/ -#define RMT_LOOP_STOP_EN_CH3 (BIT(21)) -#define RMT_LOOP_STOP_EN_CH3_M (BIT(21)) -#define RMT_LOOP_STOP_EN_CH3_V 0x1 -#define RMT_LOOP_STOP_EN_CH3_S 21 -/* RMT_LOOP_COUNT_RESET_CH3 : WT ;bitpos:[20] ;default: 1'b0 ; */ -/*description: This register is used to reset the loop count when tx_conti_mode is valid..*/ -#define RMT_LOOP_COUNT_RESET_CH3 (BIT(20)) -#define RMT_LOOP_COUNT_RESET_CH3_M (BIT(20)) -#define RMT_LOOP_COUNT_RESET_CH3_V 0x1 -#define RMT_LOOP_COUNT_RESET_CH3_S 20 -/* RMT_TX_LOOP_CNT_EN_CH3 : R/W ;bitpos:[19] ;default: 1'b0 ; */ -/*description: This register is the enabled bit for loop count..*/ -#define RMT_TX_LOOP_CNT_EN_CH3 (BIT(19)) -#define RMT_TX_LOOP_CNT_EN_CH3_M (BIT(19)) -#define RMT_TX_LOOP_CNT_EN_CH3_V 0x1 -#define RMT_TX_LOOP_CNT_EN_CH3_S 19 -/* RMT_TX_LOOP_NUM_CH3 : R/W ;bitpos:[18:9] ;default: 10'b0 ; */ -/*description: This register is used to configure the maximum loop count when tx_conti_mode is -valid..*/ -#define RMT_TX_LOOP_NUM_CH3 0x000003FF -#define RMT_TX_LOOP_NUM_CH3_M ((RMT_TX_LOOP_NUM_CH3_V)<<(RMT_TX_LOOP_NUM_CH3_S)) -#define RMT_TX_LOOP_NUM_CH3_V 0x3FF -#define RMT_TX_LOOP_NUM_CH3_S 9 -/* RMT_TX_LIM_CH3 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */ -/*description: This register is used to configure the maximum entries that CHANNEL$n can send o -ut..*/ -#define RMT_TX_LIM_CH3 0x000001FF -#define RMT_TX_LIM_CH3_M ((RMT_TX_LIM_CH3_V)<<(RMT_TX_LIM_CH3_S)) -#define RMT_TX_LIM_CH3_V 0x1FF +/** RMT_CH3_TX_LIM_REG register + * Channel 3 Tx event configuration register + */ +#define RMT_CH3_TX_LIM_REG (DR_REG_RMT_BASE + 0xac) +/** RMT_TX_LIM_CH3 : R/W; bitpos: [8:0]; default: 128; + * This register is used to configure the maximum entries that CHANNEL3 can send out. + */ +#define RMT_TX_LIM_CH3 0x000001FFU +#define RMT_TX_LIM_CH3_M (RMT_TX_LIM_CH3_V << RMT_TX_LIM_CH3_S) +#define RMT_TX_LIM_CH3_V 0x000001FFU #define RMT_TX_LIM_CH3_S 0 +/** RMT_TX_LOOP_NUM_CH3 : R/W; bitpos: [18:9]; default: 0; + * This register is used to configure the maximum loop count when tx_conti_mode is + * valid. + */ +#define RMT_TX_LOOP_NUM_CH3 0x000003FFU +#define RMT_TX_LOOP_NUM_CH3_M (RMT_TX_LOOP_NUM_CH3_V << RMT_TX_LOOP_NUM_CH3_S) +#define RMT_TX_LOOP_NUM_CH3_V 0x000003FFU +#define RMT_TX_LOOP_NUM_CH3_S 9 +/** RMT_TX_LOOP_CNT_EN_CH3 : R/W; bitpos: [19]; default: 0; + * This register is the enabled bit for loop count. + */ +#define RMT_TX_LOOP_CNT_EN_CH3 (BIT(19)) +#define RMT_TX_LOOP_CNT_EN_CH3_M (RMT_TX_LOOP_CNT_EN_CH3_V << RMT_TX_LOOP_CNT_EN_CH3_S) +#define RMT_TX_LOOP_CNT_EN_CH3_V 0x00000001U +#define RMT_TX_LOOP_CNT_EN_CH3_S 19 +/** RMT_LOOP_COUNT_RESET_CH3 : WT; bitpos: [20]; default: 0; + * This register is used to reset the loop count when tx_conti_mode is valid. + */ +#define RMT_LOOP_COUNT_RESET_CH3 (BIT(20)) +#define RMT_LOOP_COUNT_RESET_CH3_M (RMT_LOOP_COUNT_RESET_CH3_V << RMT_LOOP_COUNT_RESET_CH3_S) +#define RMT_LOOP_COUNT_RESET_CH3_V 0x00000001U +#define RMT_LOOP_COUNT_RESET_CH3_S 20 +/** RMT_LOOP_STOP_EN_CH3 : R/W; bitpos: [21]; default: 0; + * This bit is used to enable the loop send stop function after the loop counter + * counts to loop number for CHANNEL3. + */ +#define RMT_LOOP_STOP_EN_CH3 (BIT(21)) +#define RMT_LOOP_STOP_EN_CH3_M (RMT_LOOP_STOP_EN_CH3_V << RMT_LOOP_STOP_EN_CH3_S) +#define RMT_LOOP_STOP_EN_CH3_V 0x00000001U +#define RMT_LOOP_STOP_EN_CH3_S 21 -#define RMT_CH4_RX_LIM_REG (DR_REG_RMT_BASE + 0xB0) -/* RMT_RX_LIM_CH4 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */ -/*description: This register is used to configure the maximum entries that CHANNEL$m can receiv -e..*/ -#define RMT_RX_LIM_CH4 0x000001FF -#define RMT_RX_LIM_CH4_M ((RMT_RX_LIM_CH4_V)<<(RMT_RX_LIM_CH4_S)) -#define RMT_RX_LIM_CH4_V 0x1FF -#define RMT_RX_LIM_CH4_S 0 +/** RMT_CH4_RX_LIM_REG register + * Channel 4 Rx event configuration register + */ +#define RMT_CH4_RX_LIM_REG (DR_REG_RMT_BASE + 0xb0) +/** RMT_CH4_RX_LIM_REG : R/W; bitpos: [8:0]; default: 128; + * This register is used to configure the maximum entries that CHANNEL4 can receive. + */ +#define RMT_CH4_RX_LIM_REG 0x000001FFU +#define RMT_CH4_RX_LIM_REG_M (RMT_CH4_RX_LIM_REG_V << RMT_CH4_RX_LIM_REG_S) +#define RMT_CH4_RX_LIM_REG_V 0x000001FFU +#define RMT_CH4_RX_LIM_REG_S 0 -#define RMT_CH5_RX_LIM_REG (DR_REG_RMT_BASE + 0xB4) -/* RMT_RX_LIM_CH5 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */ -/*description: This register is used to configure the maximum entries that CHANNEL$m can receiv -e..*/ -#define RMT_RX_LIM_CH5 0x000001FF -#define RMT_RX_LIM_CH5_M ((RMT_RX_LIM_CH5_V)<<(RMT_RX_LIM_CH5_S)) -#define RMT_RX_LIM_CH5_V 0x1FF -#define RMT_RX_LIM_CH5_S 0 +/** RMT_CH5_RX_LIM_REG register + * Channel 5 Rx event configuration register + */ +#define RMT_CH5_RX_LIM_REG (DR_REG_RMT_BASE + 0xb4) +/** RMT_CH5_RX_LIM_REG : R/W; bitpos: [8:0]; default: 128; + * This register is used to configure the maximum entries that CHANNEL5 can receive. + */ +#define RMT_CH5_RX_LIM_REG 0x000001FFU +#define RMT_CH5_RX_LIM_REG_M (RMT_CH5_RX_LIM_REG_V << RMT_CH5_RX_LIM_REG_S) +#define RMT_CH5_RX_LIM_REG_V 0x000001FFU +#define RMT_CH5_RX_LIM_REG_S 0 -#define RMT_CH6_RX_LIM_REG (DR_REG_RMT_BASE + 0xB8) -/* RMT_RX_LIM_CH6 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */ -/*description: This register is used to configure the maximum entries that CHANNEL$m can receiv -e..*/ -#define RMT_RX_LIM_CH6 0x000001FF -#define RMT_RX_LIM_CH6_M ((RMT_RX_LIM_CH6_V)<<(RMT_RX_LIM_CH6_S)) -#define RMT_RX_LIM_CH6_V 0x1FF -#define RMT_RX_LIM_CH6_S 0 +/** RMT_CH6_RX_LIM_REG register + * Channel 6 Rx event configuration register + */ +#define RMT_CH6_RX_LIM_REG (DR_REG_RMT_BASE + 0xb8) +/** RMT_CH6_RX_LIM_REG : R/W; bitpos: [8:0]; default: 128; + * This register is used to configure the maximum entries that CHANNEL6 can receive. + */ +#define RMT_CH6_RX_LIM_REG 0x000001FFU +#define RMT_CH6_RX_LIM_REG_M (RMT_CH6_RX_LIM_REG_V << RMT_CH6_RX_LIM_REG_S) +#define RMT_CH6_RX_LIM_REG_V 0x000001FFU +#define RMT_CH6_RX_LIM_REG_S 0 -#define RMT_CH7_RX_LIM_REG (DR_REG_RMT_BASE + 0xBC) -/* RMT_RX_LIM_CH7 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */ -/*description: This register is used to configure the maximum entries that CHANNEL$m can receiv -e..*/ -#define RMT_RX_LIM_CH7 0x000001FF -#define RMT_RX_LIM_CH7_M ((RMT_RX_LIM_CH7_V)<<(RMT_RX_LIM_CH7_S)) -#define RMT_RX_LIM_CH7_V 0x1FF -#define RMT_RX_LIM_CH7_S 0 +/** RMT_CH7_RX_LIM_REG register + * Channel 7 Rx event configuration register + */ +#define RMT_CH7_RX_LIM_REG (DR_REG_RMT_BASE + 0xbc) +/** RMT_CH7_RX_LIM_REG : R/W; bitpos: [8:0]; default: 128; + * This register is used to configure the maximum entries that CHANNEL7 can receive. + */ +#define RMT_CH7_RX_LIM_REG 0x000001FFU +#define RMT_CH7_RX_LIM_REG_M (RMT_CH7_RX_LIM_REG_V << RMT_CH7_RX_LIM_REG_S) +#define RMT_CH7_RX_LIM_REG_V 0x000001FFU +#define RMT_CH7_RX_LIM_REG_S 0 -#define RMT_SYS_CONF_REG (DR_REG_RMT_BASE + 0xC0) -/* RMT_CLK_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */ -/*description: RMT register clock gate enable signal. 1: Power up the drive clock of registers. - 0: Power down the drive clock of registers.*/ -#define RMT_CLK_EN (BIT(31)) -#define RMT_CLK_EN_M (BIT(31)) -#define RMT_CLK_EN_V 0x1 -#define RMT_CLK_EN_S 31 -/* RMT_SCLK_ACTIVE : R/W ;bitpos:[26] ;default: 1'h1 ; */ -/*description: rmt_sclk switch.*/ -#define RMT_SCLK_ACTIVE (BIT(26)) -#define RMT_SCLK_ACTIVE_M (BIT(26)) -#define RMT_SCLK_ACTIVE_V 0x1 -#define RMT_SCLK_ACTIVE_S 26 -/* RMT_SCLK_SEL : R/W ;bitpos:[25:24] ;default: 2'h1 ; */ -/*description: choose the clock source of rmt_sclk. 1:CLK_80Mhz;2:CLK_8MHz; 2:XTAL .*/ -#define RMT_SCLK_SEL 0x00000003 -#define RMT_SCLK_SEL_M ((RMT_SCLK_SEL_V)<<(RMT_SCLK_SEL_S)) -#define RMT_SCLK_SEL_V 0x3 -#define RMT_SCLK_SEL_S 24 -/* RMT_SCLK_DIV_B : R/W ;bitpos:[23:18] ;default: 6'h0 ; */ -/*description: the denominator of the fractional part of the fractional divisor.*/ -#define RMT_SCLK_DIV_B 0x0000003F -#define RMT_SCLK_DIV_B_M ((RMT_SCLK_DIV_B_V)<<(RMT_SCLK_DIV_B_S)) -#define RMT_SCLK_DIV_B_V 0x3F -#define RMT_SCLK_DIV_B_S 18 -/* RMT_SCLK_DIV_A : R/W ;bitpos:[17:12] ;default: 6'h0 ; */ -/*description: the numerator of the fractional part of the fractional divisor.*/ -#define RMT_SCLK_DIV_A 0x0000003F -#define RMT_SCLK_DIV_A_M ((RMT_SCLK_DIV_A_V)<<(RMT_SCLK_DIV_A_S)) -#define RMT_SCLK_DIV_A_V 0x3F -#define RMT_SCLK_DIV_A_S 12 -/* RMT_SCLK_DIV_NUM : R/W ;bitpos:[11:4] ;default: 8'h1 ; */ -/*description: the integral part of the fractional divisor.*/ -#define RMT_SCLK_DIV_NUM 0x000000FF -#define RMT_SCLK_DIV_NUM_M ((RMT_SCLK_DIV_NUM_V)<<(RMT_SCLK_DIV_NUM_S)) -#define RMT_SCLK_DIV_NUM_V 0xFF -#define RMT_SCLK_DIV_NUM_S 4 -/* RMT_MEM_FORCE_PU : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: 1: Disable RMT memory light sleep power down function. 0: Power down RMT memory -when RMT is in light sleep mode..*/ -#define RMT_MEM_FORCE_PU (BIT(3)) -#define RMT_MEM_FORCE_PU_M (BIT(3)) -#define RMT_MEM_FORCE_PU_V 0x1 -#define RMT_MEM_FORCE_PU_S 3 -/* RMT_MEM_FORCE_PD : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: Set this bit to power down RMT memory..*/ -#define RMT_MEM_FORCE_PD (BIT(2)) -#define RMT_MEM_FORCE_PD_M (BIT(2)) -#define RMT_MEM_FORCE_PD_V 0x1 -#define RMT_MEM_FORCE_PD_S 2 -/* RMT_MEM_CLK_FORCE_ON : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: Set this bit to enable the clock for RMT memory..*/ -#define RMT_MEM_CLK_FORCE_ON (BIT(1)) -#define RMT_MEM_CLK_FORCE_ON_M (BIT(1)) -#define RMT_MEM_CLK_FORCE_ON_V 0x1 -#define RMT_MEM_CLK_FORCE_ON_S 1 -/* RMT_APB_FIFO_MASK : R/W ;bitpos:[0] ;default: 1'h0 ; */ -/*description: 1'h1: access memory directly. 1'h0: access memory by FIFO..*/ +/** RMT_SYS_CONF_REG register + * RMT apb configuration register + */ +#define RMT_SYS_CONF_REG (DR_REG_RMT_BASE + 0xc0) +/** RMT_APB_FIFO_MASK : R/W; bitpos: [0]; default: 0; + * 1'h1: access memory directly. 1'h0: access memory by FIFO. + */ #define RMT_APB_FIFO_MASK (BIT(0)) -#define RMT_APB_FIFO_MASK_M (BIT(0)) -#define RMT_APB_FIFO_MASK_V 0x1 +#define RMT_APB_FIFO_MASK_M (RMT_APB_FIFO_MASK_V << RMT_APB_FIFO_MASK_S) +#define RMT_APB_FIFO_MASK_V 0x00000001U #define RMT_APB_FIFO_MASK_S 0 +/** RMT_MEM_CLK_FORCE_ON : R/W; bitpos: [1]; default: 0; + * Set this bit to enable the clock for RMT memory. + */ +#define RMT_MEM_CLK_FORCE_ON (BIT(1)) +#define RMT_MEM_CLK_FORCE_ON_M (RMT_MEM_CLK_FORCE_ON_V << RMT_MEM_CLK_FORCE_ON_S) +#define RMT_MEM_CLK_FORCE_ON_V 0x00000001U +#define RMT_MEM_CLK_FORCE_ON_S 1 +/** RMT_MEM_FORCE_PD : R/W; bitpos: [2]; default: 0; + * Set this bit to power down RMT memory. + */ +#define RMT_MEM_FORCE_PD (BIT(2)) +#define RMT_MEM_FORCE_PD_M (RMT_MEM_FORCE_PD_V << RMT_MEM_FORCE_PD_S) +#define RMT_MEM_FORCE_PD_V 0x00000001U +#define RMT_MEM_FORCE_PD_S 2 +/** RMT_MEM_FORCE_PU : R/W; bitpos: [3]; default: 0; + * 1: Disable RMT memory light sleep power down function. 0: Power down RMT memory + * when RMT is in light sleep mode. + */ +#define RMT_MEM_FORCE_PU (BIT(3)) +#define RMT_MEM_FORCE_PU_M (RMT_MEM_FORCE_PU_V << RMT_MEM_FORCE_PU_S) +#define RMT_MEM_FORCE_PU_V 0x00000001U +#define RMT_MEM_FORCE_PU_S 3 +/** RMT_SCLK_DIV_NUM : R/W; bitpos: [11:4]; default: 1; + * the integral part of the fractional divisor + */ +#define RMT_SCLK_DIV_NUM 0x000000FFU +#define RMT_SCLK_DIV_NUM_M (RMT_SCLK_DIV_NUM_V << RMT_SCLK_DIV_NUM_S) +#define RMT_SCLK_DIV_NUM_V 0x000000FFU +#define RMT_SCLK_DIV_NUM_S 4 +/** RMT_SCLK_DIV_A : R/W; bitpos: [17:12]; default: 0; + * the numerator of the fractional part of the fractional divisor + */ +#define RMT_SCLK_DIV_A 0x0000003FU +#define RMT_SCLK_DIV_A_M (RMT_SCLK_DIV_A_V << RMT_SCLK_DIV_A_S) +#define RMT_SCLK_DIV_A_V 0x0000003FU +#define RMT_SCLK_DIV_A_S 12 +/** RMT_SCLK_DIV_B : R/W; bitpos: [23:18]; default: 0; + * the denominator of the fractional part of the fractional divisor + */ +#define RMT_SCLK_DIV_B 0x0000003FU +#define RMT_SCLK_DIV_B_M (RMT_SCLK_DIV_B_V << RMT_SCLK_DIV_B_S) +#define RMT_SCLK_DIV_B_V 0x0000003FU +#define RMT_SCLK_DIV_B_S 18 +/** RMT_SCLK_SEL : R/W; bitpos: [25:24]; default: 1; + * choose the clock source of rmt_sclk. 1:CLK_80Mhz;2:CLK_8MHz; 2:XTAL + */ +#define RMT_SCLK_SEL 0x00000003U +#define RMT_SCLK_SEL_M (RMT_SCLK_SEL_V << RMT_SCLK_SEL_S) +#define RMT_SCLK_SEL_V 0x00000003U +#define RMT_SCLK_SEL_S 24 +/** RMT_SCLK_ACTIVE : R/W; bitpos: [26]; default: 1; + * rmt_sclk switch + */ +#define RMT_SCLK_ACTIVE (BIT(26)) +#define RMT_SCLK_ACTIVE_M (RMT_SCLK_ACTIVE_V << RMT_SCLK_ACTIVE_S) +#define RMT_SCLK_ACTIVE_V 0x00000001U +#define RMT_SCLK_ACTIVE_S 26 +/** RMT_CLK_EN : R/W; bitpos: [31]; default: 0; + * RMT register clock gate enable signal. 1: Power up the drive clock of registers. 0: + * Power down the drive clock of registers + */ +#define RMT_CLK_EN (BIT(31)) +#define RMT_CLK_EN_M (RMT_CLK_EN_V << RMT_CLK_EN_S) +#define RMT_CLK_EN_V 0x00000001U +#define RMT_CLK_EN_S 31 -#define RMT_TX_SIM_REG (DR_REG_RMT_BASE + 0xC4) -/* RMT_TX_SIM_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */ -/*description: This register is used to enable multiple of channels to start sending data synch -ronously..*/ -#define RMT_TX_SIM_EN (BIT(4)) -#define RMT_TX_SIM_EN_M (BIT(4)) -#define RMT_TX_SIM_EN_V 0x1 -#define RMT_TX_SIM_EN_S 4 -/* RMT_TX_SIM_CH3 : R/W ;bitpos:[3] ;default: 1'b0 ; */ -/*description: Set this bit to enable CHANNEL$n to start sending data synchronously with other -enabled channels..*/ -#define RMT_TX_SIM_CH3 (BIT(3)) -#define RMT_TX_SIM_CH3_M (BIT(3)) -#define RMT_TX_SIM_CH3_V 0x1 -#define RMT_TX_SIM_CH3_S 3 -/* RMT_TX_SIM_CH2 : R/W ;bitpos:[2] ;default: 1'b0 ; */ -/*description: Set this bit to enable CHANNEL$n to start sending data synchronously with other -enabled channels..*/ -#define RMT_TX_SIM_CH2 (BIT(2)) -#define RMT_TX_SIM_CH2_M (BIT(2)) -#define RMT_TX_SIM_CH2_V 0x1 -#define RMT_TX_SIM_CH2_S 2 -/* RMT_TX_SIM_CH1 : R/W ;bitpos:[1] ;default: 1'b0 ; */ -/*description: Set this bit to enable CHANNEL$n to start sending data synchronously with other -enabled channels..*/ -#define RMT_TX_SIM_CH1 (BIT(1)) -#define RMT_TX_SIM_CH1_M (BIT(1)) -#define RMT_TX_SIM_CH1_V 0x1 -#define RMT_TX_SIM_CH1_S 1 -/* RMT_TX_SIM_CH0 : R/W ;bitpos:[0] ;default: 1'b0 ; */ -/*description: Set this bit to enable CHANNEL$n to start sending data synchronously with other -enabled channels..*/ +/** RMT_TX_SIM_REG register + * RMT TX synchronous register + */ +#define RMT_TX_SIM_REG (DR_REG_RMT_BASE + 0xc4) +/** RMT_TX_SIM_CH0 : R/W; bitpos: [0]; default: 0; + * Set this bit to enable CHANNEL0 to start sending data synchronously with other + * enabled channels. + */ #define RMT_TX_SIM_CH0 (BIT(0)) -#define RMT_TX_SIM_CH0_M (BIT(0)) -#define RMT_TX_SIM_CH0_V 0x1 +#define RMT_TX_SIM_CH0_M (RMT_TX_SIM_CH0_V << RMT_TX_SIM_CH0_S) +#define RMT_TX_SIM_CH0_V 0x00000001U #define RMT_TX_SIM_CH0_S 0 +/** RMT_TX_SIM_CH1 : R/W; bitpos: [1]; default: 0; + * Set this bit to enable CHANNEL1 to start sending data synchronously with other + * enabled channels. + */ +#define RMT_TX_SIM_CH1 (BIT(1)) +#define RMT_TX_SIM_CH1_M (RMT_TX_SIM_CH1_V << RMT_TX_SIM_CH1_S) +#define RMT_TX_SIM_CH1_V 0x00000001U +#define RMT_TX_SIM_CH1_S 1 +/** RMT_TX_SIM_CH2 : R/W; bitpos: [2]; default: 0; + * Set this bit to enable CHANNEL2 to start sending data synchronously with other + * enabled channels. + */ +#define RMT_TX_SIM_CH2 (BIT(2)) +#define RMT_TX_SIM_CH2_M (RMT_TX_SIM_CH2_V << RMT_TX_SIM_CH2_S) +#define RMT_TX_SIM_CH2_V 0x00000001U +#define RMT_TX_SIM_CH2_S 2 +/** RMT_TX_SIM_CH3 : R/W; bitpos: [3]; default: 0; + * Set this bit to enable CHANNEL3 to start sending data synchronously with other + * enabled channels. + */ +#define RMT_TX_SIM_CH3 (BIT(3)) +#define RMT_TX_SIM_CH3_M (RMT_TX_SIM_CH3_V << RMT_TX_SIM_CH3_S) +#define RMT_TX_SIM_CH3_V 0x00000001U +#define RMT_TX_SIM_CH3_S 3 +/** RMT_TX_SIM_EN : R/W; bitpos: [4]; default: 0; + * This register is used to enable multiple of channels to start sending data + * synchronously. + */ +#define RMT_TX_SIM_EN (BIT(4)) +#define RMT_TX_SIM_EN_M (RMT_TX_SIM_EN_V << RMT_TX_SIM_EN_S) +#define RMT_TX_SIM_EN_V 0x00000001U +#define RMT_TX_SIM_EN_S 4 -#define RMT_REF_CNT_RST_REG (DR_REG_RMT_BASE + 0xC8) -/* RMT_REF_CNT_RST_CH7 : WT ;bitpos:[7] ;default: 1'b0 ; */ -/*description: This register is used to reset the clock divider of CHANNEL$m..*/ -#define RMT_REF_CNT_RST_CH7 (BIT(7)) -#define RMT_REF_CNT_RST_CH7_M (BIT(7)) -#define RMT_REF_CNT_RST_CH7_V 0x1 -#define RMT_REF_CNT_RST_CH7_S 7 -/* RMT_REF_CNT_RST_CH6 : WT ;bitpos:[6] ;default: 1'b0 ; */ -/*description: This register is used to reset the clock divider of CHANNEL$m..*/ -#define RMT_REF_CNT_RST_CH6 (BIT(6)) -#define RMT_REF_CNT_RST_CH6_M (BIT(6)) -#define RMT_REF_CNT_RST_CH6_V 0x1 -#define RMT_REF_CNT_RST_CH6_S 6 -/* RMT_REF_CNT_RST_CH5 : WT ;bitpos:[5] ;default: 1'b0 ; */ -/*description: This register is used to reset the clock divider of CHANNEL$m..*/ -#define RMT_REF_CNT_RST_CH5 (BIT(5)) -#define RMT_REF_CNT_RST_CH5_M (BIT(5)) -#define RMT_REF_CNT_RST_CH5_V 0x1 -#define RMT_REF_CNT_RST_CH5_S 5 -/* RMT_REF_CNT_RST_CH4 : WT ;bitpos:[4] ;default: 1'b0 ; */ -/*description: This register is used to reset the clock divider of CHANNEL$m..*/ -#define RMT_REF_CNT_RST_CH4 (BIT(4)) -#define RMT_REF_CNT_RST_CH4_M (BIT(4)) -#define RMT_REF_CNT_RST_CH4_V 0x1 -#define RMT_REF_CNT_RST_CH4_S 4 -/* RMT_REF_CNT_RST_CH3 : WT ;bitpos:[3] ;default: 1'b0 ; */ -/*description: This register is used to reset the clock divider of CHANNEL$n..*/ -#define RMT_REF_CNT_RST_CH3 (BIT(3)) -#define RMT_REF_CNT_RST_CH3_M (BIT(3)) -#define RMT_REF_CNT_RST_CH3_V 0x1 -#define RMT_REF_CNT_RST_CH3_S 3 -/* RMT_REF_CNT_RST_CH2 : WT ;bitpos:[2] ;default: 1'b0 ; */ -/*description: This register is used to reset the clock divider of CHANNEL$n..*/ -#define RMT_REF_CNT_RST_CH2 (BIT(2)) -#define RMT_REF_CNT_RST_CH2_M (BIT(2)) -#define RMT_REF_CNT_RST_CH2_V 0x1 -#define RMT_REF_CNT_RST_CH2_S 2 -/* RMT_REF_CNT_RST_CH1 : WT ;bitpos:[1] ;default: 1'b0 ; */ -/*description: This register is used to reset the clock divider of CHANNEL$n..*/ -#define RMT_REF_CNT_RST_CH1 (BIT(1)) -#define RMT_REF_CNT_RST_CH1_M (BIT(1)) -#define RMT_REF_CNT_RST_CH1_V 0x1 -#define RMT_REF_CNT_RST_CH1_S 1 -/* RMT_REF_CNT_RST_CH0 : WT ;bitpos:[0] ;default: 1'b0 ; */ -/*description: This register is used to reset the clock divider of CHANNEL$n..*/ +/** RMT_REF_CNT_RST_REG register + * RMT clock divider reset register + */ +#define RMT_REF_CNT_RST_REG (DR_REG_RMT_BASE + 0xc8) +/** RMT_REF_CNT_RST_CH0 : WT; bitpos: [0]; default: 0; + * This register is used to reset the clock divider of CHANNEL0. + */ #define RMT_REF_CNT_RST_CH0 (BIT(0)) -#define RMT_REF_CNT_RST_CH0_M (BIT(0)) -#define RMT_REF_CNT_RST_CH0_V 0x1 +#define RMT_REF_CNT_RST_CH0_M (RMT_REF_CNT_RST_CH0_V << RMT_REF_CNT_RST_CH0_S) +#define RMT_REF_CNT_RST_CH0_V 0x00000001U #define RMT_REF_CNT_RST_CH0_S 0 +/** RMT_REF_CNT_RST_CH1 : WT; bitpos: [1]; default: 0; + * This register is used to reset the clock divider of CHANNEL1. + */ +#define RMT_REF_CNT_RST_CH1 (BIT(1)) +#define RMT_REF_CNT_RST_CH1_M (RMT_REF_CNT_RST_CH1_V << RMT_REF_CNT_RST_CH1_S) +#define RMT_REF_CNT_RST_CH1_V 0x00000001U +#define RMT_REF_CNT_RST_CH1_S 1 +/** RMT_REF_CNT_RST_CH2 : WT; bitpos: [2]; default: 0; + * This register is used to reset the clock divider of CHANNEL2. + */ +#define RMT_REF_CNT_RST_CH2 (BIT(2)) +#define RMT_REF_CNT_RST_CH2_M (RMT_REF_CNT_RST_CH2_V << RMT_REF_CNT_RST_CH2_S) +#define RMT_REF_CNT_RST_CH2_V 0x00000001U +#define RMT_REF_CNT_RST_CH2_S 2 +/** RMT_REF_CNT_RST_CH3 : WT; bitpos: [3]; default: 0; + * This register is used to reset the clock divider of CHANNEL3. + */ +#define RMT_REF_CNT_RST_CH3 (BIT(3)) +#define RMT_REF_CNT_RST_CH3_M (RMT_REF_CNT_RST_CH3_V << RMT_REF_CNT_RST_CH3_S) +#define RMT_REF_CNT_RST_CH3_V 0x00000001U +#define RMT_REF_CNT_RST_CH3_S 3 +/** RMT_REF_CNT_RST_CH4 : WT; bitpos: [4]; default: 0; + * This register is used to reset the clock divider of CHANNEL4. + */ +#define RMT_REF_CNT_RST_CH4 (BIT(4)) +#define RMT_REF_CNT_RST_CH4_M (RMT_REF_CNT_RST_CH4_V << RMT_REF_CNT_RST_CH4_S) +#define RMT_REF_CNT_RST_CH4_V 0x00000001U +#define RMT_REF_CNT_RST_CH4_S 4 +/** RMT_REF_CNT_RST_CH5 : WT; bitpos: [5]; default: 0; + * This register is used to reset the clock divider of CHANNEL5. + */ +#define RMT_REF_CNT_RST_CH5 (BIT(5)) +#define RMT_REF_CNT_RST_CH5_M (RMT_REF_CNT_RST_CH5_V << RMT_REF_CNT_RST_CH5_S) +#define RMT_REF_CNT_RST_CH5_V 0x00000001U +#define RMT_REF_CNT_RST_CH5_S 5 +/** RMT_REF_CNT_RST_CH6 : WT; bitpos: [6]; default: 0; + * This register is used to reset the clock divider of CHANNEL6. + */ +#define RMT_REF_CNT_RST_CH6 (BIT(6)) +#define RMT_REF_CNT_RST_CH6_M (RMT_REF_CNT_RST_CH6_V << RMT_REF_CNT_RST_CH6_S) +#define RMT_REF_CNT_RST_CH6_V 0x00000001U +#define RMT_REF_CNT_RST_CH6_S 6 +/** RMT_REF_CNT_RST_CH7 : WT; bitpos: [7]; default: 0; + * This register is used to reset the clock divider of CHANNEL7. + */ +#define RMT_REF_CNT_RST_CH7 (BIT(7)) +#define RMT_REF_CNT_RST_CH7_M (RMT_REF_CNT_RST_CH7_V << RMT_REF_CNT_RST_CH7_S) +#define RMT_REF_CNT_RST_CH7_V 0x00000001U +#define RMT_REF_CNT_RST_CH7_S 7 -#define RMT_DATE_REG (DR_REG_RMT_BASE + 0xCC) -/* RMT_DATE : R/W ;bitpos:[27:0] ;default: 28'h2101181 ; */ -/*description: This is the version register..*/ -#define RMT_DATE 0x0FFFFFFF -#define RMT_DATE_M ((RMT_DATE_V)<<(RMT_DATE_S)) -#define RMT_DATE_V 0xFFFFFFF +/** RMT_DATE_REG register + * RMT version register + */ +#define RMT_DATE_REG (DR_REG_RMT_BASE + 0xcc) +/** RMT_DATE : R/W; bitpos: [27:0]; default: 34607489; + * This is the version register. + */ +#define RMT_DATE 0x0FFFFFFFU +#define RMT_DATE_M (RMT_DATE_V << RMT_DATE_S) +#define RMT_DATE_V 0x0FFFFFFFU #define RMT_DATE_S 0 - #ifdef __cplusplus } #endif - - - -#endif /*_SOC_RMT_REG_H_ */ diff --git a/components/soc/esp32s3/include/soc/rmt_struct.h b/components/soc/esp32s3/include/soc/rmt_struct.h index 428b87df85..bfdcf33546 100644 --- a/components/soc/esp32s3/include/soc/rmt_struct.h +++ b/components/soc/esp32s3/include/soc/rmt_struct.h @@ -1,330 +1,1094 @@ -// Copyright 2017-2021 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -#ifndef _SOC_RMT_STRUCT_H_ -#define _SOC_RMT_STRUCT_H_ - +/** Copyright 2021 Espressif Systems (Shanghai) PTE LTD + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#pragma once #include #ifdef __cplusplus extern "C" { #endif -typedef volatile struct { - uint32_t data_ch[8]; - union { - struct { - uint32_t tx_start : 1; /*Set this bit to start sending data on CHANNEL$n.*/ - uint32_t mem_rd_rst : 1; /*Set this bit to reset read ram address for CHANNEL$n by accessing transmitter.*/ - uint32_t mem_rst : 1; /*Set this bit to reset W/R ram address for CHANNEL$n by accessing apb fifo.*/ - uint32_t tx_conti_mode : 1; /*Set this bit to restart transmission from the first data to the last data in CHANNEL$n.*/ - uint32_t mem_tx_wrap_en : 1; /*This is the channel $n enable bit for wraparound mode: it will resume sending at the start when the data to be sent is more than its memory size.*/ - uint32_t idle_out_lv : 1; /*This bit configures the level of output signal in CHANNEL$n when the latter is in IDLE state.*/ - uint32_t idle_out_en : 1; /*This is the output enable-control bit for CHANNEL$n in IDLE state.*/ - uint32_t tx_stop : 1; /*Set this bit to stop the transmitter of CHANNEL$n sending data out.*/ - uint32_t div_cnt : 8; /*This register is used to configure the divider for clock of CHANNEL$n.*/ - uint32_t mem_size : 4; /*This register is used to configure the maximum size of memory allocated to CHANNEL$n.*/ - uint32_t carrier_eff_en : 1; /*1: Add carrier modulation on the output signal only at the send data state for CHANNEL$n. 0: Add carrier modulation on the output signal at all state for CHANNEL$n. Only valid when RMT_CARRIER_EN_CH$n is 1.*/ - uint32_t carrier_en : 1; /*This is the carrier modulation enable-control bit for CHANNEL$n. 1: Add carrier modulation in the output signal. 0: No carrier modulation in sig_out.*/ - uint32_t carrier_out_lv : 1; /*This bit is used to configure the position of carrier wave for CHANNEL$n.; ; 1'h0: add carrier wave on low level.; ; 1'h1: add carrier wave on high level.*/ - uint32_t afifo_rst : 1; /*Reserved*/ - uint32_t conf_update : 1; /*synchronization bit for CHANNEL$n*/ - uint32_t reserved25 : 7; /*Reserved*/ - }; - uint32_t val; - } tx_conf[4]; +/** Group: FIFO R/W registers */ +/** Type of chndata register + * The read and write data register for CHANNELn by apb fifo access. + */ +typedef union { struct { - union { - struct { - uint32_t div_cnt : 8; /*This register is used to configure the divider for clock of CHANNEL$m.*/ - uint32_t idle_thres : 15; /*When no edge is detected on the input signal and continuous clock cycles is longer than this register value, received process is finished.*/ - uint32_t reserved23 : 1; /*Reserved*/ - uint32_t mem_size : 4; /*This register is used to configure the maximum size of memory allocated to CHANNEL$m.*/ - uint32_t carrier_en : 1; /*This is the carrier modulation enable-control bit for CHANNEL$m. 1: Add carrier modulation in the output signal. 0: No carrier modulation in sig_out.*/ - uint32_t carrier_out_lv : 1; /*This bit is used to configure the position of carrier wave for CHANNEL$m.; ; 1'h0: add carrier wave on low level.; ; 1'h1: add carrier wave on high level.*/ - uint32_t reserved30 : 2; /*Reserved*/ - }; - uint32_t val; - } conf0; - union { - struct { - uint32_t rx_en : 1; /*Set this bit to enable receiver to receive data on CHANNEL$m.*/ - uint32_t mem_wr_rst : 1; /*Set this bit to reset write ram address for CHANNEL$m by accessing receiver.*/ - uint32_t mem_rst : 1; /*Set this bit to reset W/R ram address for CHANNEL$m by accessing apb fifo.*/ - uint32_t mem_owner : 1; /*This register marks the ownership of CHANNEL$m's ram block.; ; 1'h1: Receiver is using the ram. ; ; 1'h0: APB bus is using the ram.*/ - uint32_t rx_filter_en : 1; /*This is the receive filter's enable bit for CHANNEL$m.*/ - uint32_t rx_filter_thres : 8; /*Ignores the input pulse when its width is smaller than this register value in APB clock periods (in receive mode).*/ - uint32_t mem_rx_wrap_en : 1; /*This is the channel $m enable bit for wraparound mode: it will resume receiving at the start when the data to be received is more than its memory size.*/ - uint32_t afifo_rst : 1; /*Reserved*/ - uint32_t conf_update : 1; /*synchronization bit for CHANNEL$m*/ - uint32_t reserved16 : 16; /*Reserved*/ - }; - uint32_t val; - } conf1; - } rx_conf[4]; + /** chndata : RO; bitpos: [31:0]; default: 0; + * Read and write data for channel n via APB FIFO. + */ + uint32_t chndata: 32; + }; + uint32_t val; +} rmt_chndata_reg_t; + +/** Type of chmdata register + * The read and write data register for CHANNEL$n by apb fifo access. + */ +typedef union { + struct { + /** chmdata : RO; bitpos: [31:0]; default: 0; + * Read and write data for channel $n via APB FIFO. + */ + uint32_t chmdata: 32; + }; + uint32_t val; +} rmt_chmdata_reg_t; + + +/** Group: Configuration registers */ +/** Type of chnconf0 register + * Channel n configure register 0 + */ +typedef union { + struct { + /** tx_start_n : WT; bitpos: [0]; default: 0; + * Set this bit to start sending data on CHANNELn. + */ + uint32_t tx_start_n: 1; + /** mem_rd_rst_n : WT; bitpos: [1]; default: 0; + * Set this bit to reset read ram address for CHANNELn by accessing transmitter. + */ + uint32_t mem_rd_rst_n: 1; + /** apb_mem_rst_n : WT; bitpos: [2]; default: 0; + * Set this bit to reset W/R ram address for CHANNELn by accessing apb fifo. + */ + uint32_t apb_mem_rst_n: 1; + /** tx_conti_mode_n : R/W; bitpos: [3]; default: 0; + * Set this bit to restart transmission from the first data to the last data in + * CHANNELn. + */ + uint32_t tx_conti_mode_n: 1; + /** mem_tx_wrap_en_n : R/W; bitpos: [4]; default: 0; + * This is the channel n enable bit for wraparound mode: it will resume sending at the + * start when the data to be sent is more than its memory size. + */ + uint32_t mem_tx_wrap_en_n: 1; + /** idle_out_lv_n : R/W; bitpos: [5]; default: 0; + * This bit configures the level of output signal in CHANNELn when the latter is in + * IDLE state. + */ + uint32_t idle_out_lv_n: 1; + /** idle_out_en_n : R/W; bitpos: [6]; default: 0; + * This is the output enable-control bit for CHANNELn in IDLE state. + */ + uint32_t idle_out_en_n: 1; + /** tx_stop_n : R/W/SC; bitpos: [7]; default: 0; + * Set this bit to stop the transmitter of CHANNELn sending data out. + */ + uint32_t tx_stop_n: 1; + /** div_cnt_n : R/W; bitpos: [15:8]; default: 2; + * This register is used to configure the divider for clock of CHANNELn. + */ + uint32_t div_cnt_n: 8; + /** mem_size_n : R/W; bitpos: [19:16]; default: 1; + * This register is used to configure the maximum size of memory allocated to CHANNELn. + */ + uint32_t mem_size_n: 4; + /** carrier_eff_en_n : R/W; bitpos: [20]; default: 1; + * 1: Add carrier modulation on the output signal only at the send data state for + * CHANNELn. 0: Add carrier modulation on the output signal at all state for CHANNELn. + * Only valid when RMT_CARRIER_EN_CHn is 1. + */ + uint32_t carrier_eff_en_n: 1; + /** carrier_en_n : R/W; bitpos: [21]; default: 1; + * This is the carrier modulation enable-control bit for CHANNELn. 1: Add carrier + * modulation in the output signal. 0: No carrier modulation in sig_out. + */ + uint32_t carrier_en_n: 1; + /** carrier_out_lv_n : R/W; bitpos: [22]; default: 1; + * This bit is used to configure the position of carrier wave for CHANNELn. + * + * 1'h0: add carrier wave on low level. + * + * 1'h1: add carrier wave on high level. + */ + uint32_t carrier_out_lv_n: 1; + /** afifo_rst_n : WT; bitpos: [23]; default: 0; + * Reserved + */ + uint32_t afifo_rst_n: 1; + /** conf_update_n : WT; bitpos: [24]; default: 0; + * synchronization bit for CHANNELn + */ + uint32_t conf_update_n: 1; + uint32_t reserved_25: 7; + }; + uint32_t val; +} rmt_chnconf0_reg_t; + +typedef struct { + /** Type of chmconf0 register + * Channel m configure register 0 + */ union { struct { - uint32_t mem_raddr_ex : 10; /*This register records the memory address offset when transmitter of CHANNEL$n is using the RAM.*/ - uint32_t reserved10 : 1; /*Reserved*/ - uint32_t mem_waddr : 10; /*This register records the memory address offset when writes RAM over APB bus.*/ - uint32_t reserved21 : 1; /*Reserved*/ - uint32_t state : 3; /*This register records the FSM status of CHANNEL$n.*/ - uint32_t mem_empty : 1; /*This status bit will be set when the data to be set is more than memory size and the wraparound mode is disabled.*/ - uint32_t mem_wr_err : 1; /*This status bit will be set if the offset address out of memory size when writes via APB bus.*/ - uint32_t reserved27 : 5; /*Reserved*/ + /** div_cnt_m : R/W; bitpos: [7:0]; default: 2; + * This register is used to configure the divider for clock of CHANNELm. + */ + uint32_t div_cnt_m: 8; + /** idle_thres_m : R/W; bitpos: [22:8]; default: 32767; + * When no edge is detected on the input signal and continuous clock cycles is longer + * than this register value, received process is finished. + */ + uint32_t idle_thres_m: 15; + uint32_t reserved_23: 1; + /** mem_size_m : R/W; bitpos: [27:24]; default: 1; + * This register is used to configure the maximum size of memory allocated to CHANNELm. + */ + uint32_t mem_size_m: 4; + /** carrier_en_m : R/W; bitpos: [28]; default: 1; + * This is the carrier modulation enable-control bit for CHANNELm. 1: Add carrier + * modulation in the output signal. 0: No carrier modulation in sig_out. + */ + uint32_t carrier_en_m: 1; + /** carrier_out_lv_m : R/W; bitpos: [29]; default: 1; + * This bit is used to configure the position of carrier wave for CHANNELm. + * + * 1'h0: add carrier wave on low level. + * + * 1'h1: add carrier wave on high level. + */ + uint32_t carrier_out_lv_m: 1; + uint32_t reserved_30: 2; }; uint32_t val; - } tx_status[4]; + } conf0; + + /** Type of chmconf1 register + * Channel m configure register 1 + */ union { struct { - uint32_t mem_waddr_ex : 10; /*This register records the memory address offset when receiver of CHANNEL$m is using the RAM.*/ - uint32_t reserved10 : 1; /*Reserved*/ - uint32_t mem_raddr : 10; /*This register records the memory address offset when reads RAM over APB bus.*/ - uint32_t reserved21 : 1; /*Reserved*/ - uint32_t state : 3; /*This register records the FSM status of CHANNEL$m.*/ - uint32_t mem_owner_err : 1; /*This status bit will be set when the ownership of memory block is wrong.*/ - uint32_t mem_full : 1; /*This status bit will be set if the receiver receives more data than the memory size.*/ - uint32_t mem_rd_err : 1; /*This status bit will be set if the offset address out of memory size when reads via APB bus.*/ - uint32_t reserved28 : 4; /*Reserved*/ + /** rx_en_m : R/W; bitpos: [0]; default: 0; + * Set this bit to enable receiver to receive data on CHANNELm. + */ + uint32_t rx_en_m: 1; + /** mem_wr_rst_m : WT; bitpos: [1]; default: 0; + * Set this bit to reset write ram address for CHANNELm by accessing receiver. + */ + uint32_t mem_wr_rst_m: 1; + /** apb_mem_rst_m : WT; bitpos: [2]; default: 0; + * Set this bit to reset W/R ram address for CHANNELm by accessing apb fifo. + */ + uint32_t apb_mem_rst_m: 1; + /** mem_owner_m : R/W/SC; bitpos: [3]; default: 1; + * This register marks the ownership of CHANNELm's ram block. + * + * 1'h1: Receiver is using the ram. + * + * 1'h0: APB bus is using the ram. + */ + uint32_t mem_owner_m: 1; + /** rx_filter_en_m : R/W; bitpos: [4]; default: 0; + * This is the receive filter's enable bit for CHANNELm. + */ + uint32_t rx_filter_en_m: 1; + /** rx_filter_thres_m : R/W; bitpos: [12:5]; default: 15; + * Ignores the input pulse when its width is smaller than this register value in APB + * clock periods (in receive mode). + */ + uint32_t rx_filter_thres_m: 8; + /** mem_rx_wrap_en_m : R/W; bitpos: [13]; default: 0; + * This is the channel m enable bit for wraparound mode: it will resume receiving at + * the start when the data to be received is more than its memory size. + */ + uint32_t mem_rx_wrap_en_m: 1; + /** afifo_rst_m : WT; bitpos: [14]; default: 0; + * Reserved + */ + uint32_t afifo_rst_m: 1; + /** conf_update_m : WT; bitpos: [15]; default: 0; + * synchronization bit for CHANNELm + */ + uint32_t conf_update_m: 1; + uint32_t reserved_16: 16; }; uint32_t val; - } rx_status[4]; - union { - struct { - uint32_t ch0_tx_end : 1; /*The interrupt raw bit for CHANNEL$n. Triggered when transmission done.*/ - uint32_t ch1_tx_end : 1; /*The interrupt raw bit for CHANNEL$n. Triggered when transmission done.*/ - uint32_t ch2_tx_end : 1; /*The interrupt raw bit for CHANNEL$n. Triggered when transmission done.*/ - uint32_t ch3_tx_end : 1; /*The interrupt raw bit for CHANNEL$n. Triggered when transmission done.*/ - uint32_t ch0_err : 1; /*The interrupt raw bit for CHANNEL$n. Triggered when error occurs.*/ - uint32_t ch1_err : 1; /*The interrupt raw bit for CHANNEL$n. Triggered when error occurs.*/ - uint32_t ch2_err : 1; /*The interrupt raw bit for CHANNEL$n. Triggered when error occurs.*/ - uint32_t ch3_err : 1; /*The interrupt raw bit for CHANNEL$n. Triggered when error occurs.*/ - uint32_t ch0_tx_thr_event : 1; /*The interrupt raw bit for CHANNEL$n. Triggered when transmitter sent more data than configured value.*/ - uint32_t ch1_tx_thr_event : 1; /*The interrupt raw bit for CHANNEL$n. Triggered when transmitter sent more data than configured value.*/ - uint32_t ch2_tx_thr_event : 1; /*The interrupt raw bit for CHANNEL$n. Triggered when transmitter sent more data than configured value.*/ - uint32_t ch3_tx_thr_event : 1; /*The interrupt raw bit for CHANNEL$n. Triggered when transmitter sent more data than configured value.*/ - uint32_t ch0_tx_loop : 1; /*The interrupt raw bit for CHANNEL$n. Triggered when the loop count reaches the configured threshold value.*/ - uint32_t ch1_tx_loop : 1; /*The interrupt raw bit for CHANNEL$n. Triggered when the loop count reaches the configured threshold value.*/ - uint32_t ch2_tx_loop : 1; /*The interrupt raw bit for CHANNEL$n. Triggered when the loop count reaches the configured threshold value.*/ - uint32_t ch3_tx_loop : 1; /*The interrupt raw bit for CHANNEL$n. Triggered when the loop count reaches the configured threshold value.*/ - uint32_t ch4_rx_end : 1; /*The interrupt raw bit for CHANNEL$m. Triggered when reception done.*/ - uint32_t ch5_rx_end : 1; /*The interrupt raw bit for CHANNEL$m. Triggered when reception done.*/ - uint32_t ch6_rx_end : 1; /*The interrupt raw bit for CHANNEL$m. Triggered when reception done.*/ - uint32_t ch7_rx_end : 1; /*The interrupt raw bit for CHANNEL$m. Triggered when reception done.*/ - uint32_t ch4_err : 1; /*The interrupt raw bit for CHANNEL$m. Triggered when error occurs.*/ - uint32_t ch5_err : 1; /*The interrupt raw bit for CHANNEL$m. Triggered when error occurs.*/ - uint32_t ch6_err : 1; /*The interrupt raw bit for CHANNEL$m. Triggered when error occurs.*/ - uint32_t ch7_err : 1; /*The interrupt raw bit for CHANNEL$m. Triggered when error occurs.*/ - uint32_t ch4_rx_thr_event : 1; /*The interrupt raw bit for CHANNEL$m. Triggered when receiver receive more data than configured value.*/ - uint32_t ch5_rx_thr_event : 1; /*The interrupt raw bit for CHANNEL$m. Triggered when receiver receive more data than configured value.*/ - uint32_t ch6_rx_thr_event : 1; /*The interrupt raw bit for CHANNEL$m. Triggered when receiver receive more data than configured value.*/ - uint32_t ch7_rx_thr_event : 1; /*The interrupt raw bit for CHANNEL$m. Triggered when receiver receive more data than configured value.*/ - uint32_t ch3_dma_access_fail : 1; /*The interrupt raw bit for CHANNEL$n. Triggered when dma accessing CHANNEL$n fails.*/ - uint32_t ch7_dma_access_fail : 1; /*The interrupt raw bit for CHANNEL$m. Triggered when dma accessing CHANNEL$m fails.*/ - uint32_t reserved30 : 2; /*Reserved*/ - }; - uint32_t val; - } int_raw; - union { - struct { - uint32_t ch0_tx_end : 1; /*The masked interrupt status bit for CH$n_TX_END_INT.*/ - uint32_t ch1_tx_end : 1; /*The masked interrupt status bit for CH$n_TX_END_INT.*/ - uint32_t ch2_tx_end : 1; /*The masked interrupt status bit for CH$n_TX_END_INT.*/ - uint32_t ch3_tx_end : 1; /*The masked interrupt status bit for CH$n_TX_END_INT.*/ - uint32_t ch0_err : 1; /*The masked interrupt status bit for CH$n_ERR_INT.*/ - uint32_t ch1_err : 1; /*The masked interrupt status bit for CH$n_ERR_INT.*/ - uint32_t ch2_err : 1; /*The masked interrupt status bit for CH$n_ERR_INT.*/ - uint32_t ch3_err : 1; /*The masked interrupt status bit for CH$n_ERR_INT.*/ - uint32_t ch0_tx_thr_event : 1; /*The masked interrupt status bit for CH$n_TX_THR_EVENT_INT.*/ - uint32_t ch1_tx_thr_event : 1; /*The masked interrupt status bit for CH$n_TX_THR_EVENT_INT.*/ - uint32_t ch2_tx_thr_event : 1; /*The masked interrupt status bit for CH$n_TX_THR_EVENT_INT.*/ - uint32_t ch3_tx_thr_event : 1; /*The masked interrupt status bit for CH$n_TX_THR_EVENT_INT.*/ - uint32_t ch0_tx_loop : 1; /*The masked interrupt status bit for CH$n_TX_LOOP_INT.*/ - uint32_t ch1_tx_loop : 1; /*The masked interrupt status bit for CH$n_TX_LOOP_INT.*/ - uint32_t ch2_tx_loop : 1; /*The masked interrupt status bit for CH$n_TX_LOOP_INT.*/ - uint32_t ch3_tx_loop : 1; /*The masked interrupt status bit for CH$n_TX_LOOP_INT.*/ - uint32_t ch4_rx_end : 1; /*The masked interrupt status bit for CH$m_RX_END_INT.*/ - uint32_t ch5_rx_end : 1; /*The masked interrupt status bit for CH$m_RX_END_INT.*/ - uint32_t ch6_rx_end : 1; /*The masked interrupt status bit for CH$m_RX_END_INT.*/ - uint32_t ch7_rx_end : 1; /*The masked interrupt status bit for CH$m_RX_END_INT.*/ - uint32_t ch4_err : 1; /*The masked interrupt status bit for CH$m_ERR_INT.*/ - uint32_t ch5_err : 1; /*The masked interrupt status bit for CH$m_ERR_INT.*/ - uint32_t ch6_err : 1; /*The masked interrupt status bit for CH$m_ERR_INT.*/ - uint32_t ch7_err : 1; /*The masked interrupt status bit for CH$m_ERR_INT.*/ - uint32_t ch4_rx_thr_event : 1; /*The masked interrupt status bit for CH$m_RX_THR_EVENT_INT.*/ - uint32_t ch5_rx_thr_event : 1; /*The masked interrupt status bit for CH$m_RX_THR_EVENT_INT.*/ - uint32_t ch6_rx_thr_event : 1; /*The masked interrupt status bit for CH$m_RX_THR_EVENT_INT.*/ - uint32_t ch7_rx_thr_event : 1; /*The masked interrupt status bit for CH$m_RX_THR_EVENT_INT.*/ - uint32_t ch3_dma_access_fail : 1; /*The masked interrupt status bit for CH$n_DMA_ACCESS_FAIL_INT.*/ - uint32_t ch7_dma_access_fail : 1; /*The masked interrupt status bit for CH$m_DMA_ACCESS_FAIL_INT.*/ - uint32_t reserved30 : 2; /*Reserved*/ - }; - uint32_t val; - } int_st; - union { - struct { - uint32_t ch0_tx_end : 1; /*The interrupt enable bit for CH$n_TX_END_INT.*/ - uint32_t ch1_tx_end : 1; /*The interrupt enable bit for CH$n_TX_END_INT.*/ - uint32_t ch2_tx_end : 1; /*The interrupt enable bit for CH$n_TX_END_INT.*/ - uint32_t ch3_tx_end : 1; /*The interrupt enable bit for CH$n_TX_END_INT.*/ - uint32_t ch0_err : 1; /*The interrupt enable bit for CH$n_ERR_INT.*/ - uint32_t ch1_err : 1; /*The interrupt enable bit for CH$n_ERR_INT.*/ - uint32_t ch2_err : 1; /*The interrupt enable bit for CH$n_ERR_INT.*/ - uint32_t ch3_err : 1; /*The interrupt enable bit for CH$n_ERR_INT.*/ - uint32_t ch0_tx_thr_event : 1; /*The interrupt enable bit for CH$n_TX_THR_EVENT_INT.*/ - uint32_t ch1_tx_thr_event : 1; /*The interrupt enable bit for CH$n_TX_THR_EVENT_INT.*/ - uint32_t ch2_tx_thr_event : 1; /*The interrupt enable bit for CH$n_TX_THR_EVENT_INT.*/ - uint32_t ch3_tx_thr_event : 1; /*The interrupt enable bit for CH$n_TX_THR_EVENT_INT.*/ - uint32_t ch0_tx_loop : 1; /*The interrupt enable bit for CH$n_TX_LOOP_INT.*/ - uint32_t ch1_tx_loop : 1; /*The interrupt enable bit for CH$n_TX_LOOP_INT.*/ - uint32_t ch2_tx_loop : 1; /*The interrupt enable bit for CH$n_TX_LOOP_INT.*/ - uint32_t ch3_tx_loop : 1; /*The interrupt enable bit for CH$n_TX_LOOP_INT.*/ - uint32_t ch4_rx_end : 1; /*The interrupt enable bit for CH$m_RX_END_INT.*/ - uint32_t ch5_rx_end : 1; /*The interrupt enable bit for CH$m_RX_END_INT.*/ - uint32_t ch6_rx_end : 1; /*The interrupt enable bit for CH$m_RX_END_INT.*/ - uint32_t ch7_rx_end : 1; /*The interrupt enable bit for CH$m_RX_END_INT.*/ - uint32_t ch4_err : 1; /*The interrupt enable bit for CH$m_ERR_INT.*/ - uint32_t ch5_err : 1; /*The interrupt enable bit for CH$m_ERR_INT.*/ - uint32_t ch6_err : 1; /*The interrupt enable bit for CH$m_ERR_INT.*/ - uint32_t ch7_err : 1; /*The interrupt enable bit for CH$m_ERR_INT.*/ - uint32_t ch4_rx_thr_event : 1; /*The interrupt enable bit for CH$m_RX_THR_EVENT_INT.*/ - uint32_t ch5_rx_thr_event : 1; /*The interrupt enable bit for CH$m_RX_THR_EVENT_INT.*/ - uint32_t ch6_rx_thr_event : 1; /*The interrupt enable bit for CH$m_RX_THR_EVENT_INT.*/ - uint32_t ch7_rx_thr_event : 1; /*The interrupt enable bit for CH$m_RX_THR_EVENT_INT.*/ - uint32_t ch3_dma_access_fail : 1; /*The interrupt enable bit for CH$n_DMA_ACCESS_FAIL_INT.*/ - uint32_t ch7_dma_access_fail : 1; /*The interrupt enable bit for CH$m_DMA_ACCESS_FAIL_INT.*/ - uint32_t reserved30 : 2; /*Reserved*/ - }; - uint32_t val; - } int_ena; - union { - struct { - uint32_t ch0_tx_end : 1; /*Set this bit to clear theCH$n_TX_END_INT interrupt.*/ - uint32_t ch1_tx_end : 1; /*Set this bit to clear theCH$n_TX_END_INT interrupt.*/ - uint32_t ch2_tx_end : 1; /*Set this bit to clear theCH$n_TX_END_INT interrupt.*/ - uint32_t ch3_tx_end : 1; /*Set this bit to clear theCH$n_TX_END_INT interrupt.*/ - uint32_t ch0_err : 1; /*Set this bit to clear theCH$n_ERR_INT interrupt.*/ - uint32_t ch1_err : 1; /*Set this bit to clear theCH$n_ERR_INT interrupt.*/ - uint32_t ch2_err : 1; /*Set this bit to clear theCH$n_ERR_INT interrupt.*/ - uint32_t ch3_err : 1; /*Set this bit to clear theCH$n_ERR_INT interrupt.*/ - uint32_t ch0_tx_thr_event : 1; /*Set this bit to clear theCH$n_TX_THR_EVENT_INT interrupt.*/ - uint32_t ch1_tx_thr_event : 1; /*Set this bit to clear theCH$n_TX_THR_EVENT_INT interrupt.*/ - uint32_t ch2_tx_thr_event : 1; /*Set this bit to clear theCH$n_TX_THR_EVENT_INT interrupt.*/ - uint32_t ch3_tx_thr_event : 1; /*Set this bit to clear theCH$n_TX_THR_EVENT_INT interrupt.*/ - uint32_t ch0_tx_loop : 1; /*Set this bit to clear theCH$n_TX_LOOP_INT interrupt.*/ - uint32_t ch1_tx_loop : 1; /*Set this bit to clear theCH$n_TX_LOOP_INT interrupt.*/ - uint32_t ch2_tx_loop : 1; /*Set this bit to clear theCH$n_TX_LOOP_INT interrupt.*/ - uint32_t ch3_tx_loop : 1; /*Set this bit to clear theCH$n_TX_LOOP_INT interrupt.*/ - uint32_t ch4_rx_end : 1; /*Set this bit to clear theCH$m_RX_END_INT interrupt.*/ - uint32_t ch5_rx_end : 1; /*Set this bit to clear theCH$m_RX_END_INT interrupt.*/ - uint32_t ch6_rx_end : 1; /*Set this bit to clear theCH$m_RX_END_INT interrupt.*/ - uint32_t ch7_rx_end : 1; /*Set this bit to clear theCH$m_RX_END_INT interrupt.*/ - uint32_t ch4_err : 1; /*Set this bit to clear theCH$m_ERR_INT interrupt.*/ - uint32_t ch5_err : 1; /*Set this bit to clear theCH$m_ERR_INT interrupt.*/ - uint32_t ch6_err : 1; /*Set this bit to clear theCH$m_ERR_INT interrupt.*/ - uint32_t ch7_err : 1; /*Set this bit to clear theCH$m_ERR_INT interrupt.*/ - uint32_t ch4_rx_thr_event : 1; /*Set this bit to clear theCH$m_RX_THR_EVENT_INT interrupt.*/ - uint32_t ch5_rx_thr_event : 1; /*Set this bit to clear theCH$m_RX_THR_EVENT_INT interrupt.*/ - uint32_t ch6_rx_thr_event : 1; /*Set this bit to clear theCH$m_RX_THR_EVENT_INT interrupt.*/ - uint32_t ch7_rx_thr_event : 1; /*Set this bit to clear theCH$m_RX_THR_EVENT_INT interrupt.*/ - uint32_t ch3_dma_access_fail : 1; /*Set this bit to clear the CH$n_DMA_ACCESS_FAIL_INT interrupt.*/ - uint32_t ch7_dma_access_fail : 1; /*Set this bit to clear the CH$m_DMA_ACCESS_FAIL_INT interrupt.*/ - uint32_t reserved30 : 2; /*Reserved*/ - }; - uint32_t val; - } int_clr; - union { - struct { - uint32_t low : 16; /*This register is used to configure carrier wave 's low level clock period for CHANNEL$n.*/ - uint32_t high : 16; /*This register is used to configure carrier wave 's high level clock period for CHANNEL$n.*/ - }; - uint32_t val; - } tx_carrier[4]; - union { - struct { - uint32_t low_thres : 16; /*The low level period in a carrier modulation mode is (REG_RMT_REG_CARRIER_LOW_THRES_CH$m + 1) for channel $m.*/ - uint32_t high_thres : 16; /*The high level period in a carrier modulation mode is (REG_RMT_REG_CARRIER_HIGH_THRES_CH$m + 1) for channel $m.*/ - }; - uint32_t val; - } rx_carrier[4]; - union { - struct { - uint32_t limit : 9; /*This register is used to configure the maximum entries that CHANNEL$n can send out.*/ - uint32_t tx_loop_num : 10; /*This register is used to configure the maximum loop count when tx_conti_mode is valid.*/ - uint32_t tx_loop_cnt_en : 1; /*This register is the enabled bit for loop count.*/ - uint32_t loop_count_reset : 1; /*This register is used to reset the loop count when tx_conti_mode is valid.*/ - uint32_t loop_stop_en : 1; /*This bit is used to enable the loop send stop function after the loop counter counts to loop number for CHANNEL$n.*/ - uint32_t reserved22 : 10; /*Reserved*/ - }; - uint32_t val; - } tx_lim[4]; - union { - struct { - uint32_t rx_lim : 9; /*This register is used to configure the maximum entries that CHANNEL$m can receive.*/ - uint32_t reserved9 : 23; /*Reserved*/ - }; - uint32_t val; - } rx_lim[4]; - union { - struct { - uint32_t fifo_mask : 1; /*1'h1: access memory directly. 1'h0: access memory by FIFO.*/ - uint32_t mem_clk_force_on : 1; /*Set this bit to enable the clock for RMT memory.*/ - uint32_t mem_force_pd : 1; /*Set this bit to power down RMT memory.*/ - uint32_t mem_force_pu : 1; /*1: Disable RMT memory light sleep power down function. 0: Power down RMT memory when RMT is in light sleep mode.*/ - uint32_t sclk_div_num : 8; /*the integral part of the fractional divisor*/ - uint32_t sclk_div_a : 6; /*the numerator of the fractional part of the fractional divisor*/ - uint32_t sclk_div_b : 6; /*the denominator of the fractional part of the fractional divisor*/ - uint32_t sclk_sel : 2; /*choose the clock source of rmt_sclk. 1:CLK_80Mhz;2:CLK_8MHz; 2:XTAL */ - uint32_t sclk_active : 1; /*rmt_sclk switch*/ - uint32_t reserved27 : 4; /*Reserved*/ - uint32_t clk_en : 1; /*RMT register clock gate enable signal. 1: Power up the drive clock of registers. 0: Power down the drive clock of registers*/ - }; - uint32_t val; - } sys_conf; - union { - struct { - uint32_t ch0 : 1; /*Set this bit to enable CHANNEL$n to start sending data synchronously with other enabled channels.*/ - uint32_t ch1 : 1; /*Set this bit to enable CHANNEL$n to start sending data synchronously with other enabled channels.*/ - uint32_t ch2 : 1; /*Set this bit to enable CHANNEL$n to start sending data synchronously with other enabled channels.*/ - uint32_t ch3 : 1; /*Set this bit to enable CHANNEL$n to start sending data synchronously with other enabled channels.*/ - uint32_t en : 1; /*This register is used to enable multiple of channels to start sending data synchronously.*/ - uint32_t reserved5 : 27; /*Reserved*/ - }; - uint32_t val; - } tx_sim; - union { - struct { - uint32_t ch0 : 1; /*This register is used to reset the clock divider of CHANNEL$n.*/ - uint32_t ch1 : 1; /*This register is used to reset the clock divider of CHANNEL$n.*/ - uint32_t ch2 : 1; /*This register is used to reset the clock divider of CHANNEL$n.*/ - uint32_t ch3 : 1; /*This register is used to reset the clock divider of CHANNEL$n.*/ - uint32_t ch4 : 1; /*This register is used to reset the clock divider of CHANNEL$m.*/ - uint32_t ch5 : 1; /*This register is used to reset the clock divider of CHANNEL$m.*/ - uint32_t ch6 : 1; /*This register is used to reset the clock divider of CHANNEL$m.*/ - uint32_t ch7 : 1; /*This register is used to reset the clock divider of CHANNEL$m.*/ - uint32_t reserved8 : 24; /*Reserved*/ - }; - uint32_t val; - } ref_cnt_rst; - union { - struct { - uint32_t date : 28; /*This is the version register.*/ - uint32_t reserved28 : 4; /*Reserved*/ - }; - uint32_t val; - } date; + } conf1; +} rmt_chmconf_reg_t; + +/** Type of chm_rx_carrier_rm register + * Channel m carrier remove register + */ +typedef union { + struct { + /** carrier_low_thres_chm : R/W; bitpos: [15:0]; default: 0; + * The low level period in a carrier modulation mode is + * (REG_RMT_REG_CARRIER_LOW_THRES_CHm + 1) for channel m. + */ + uint32_t carrier_low_thres_chm: 16; + /** carrier_high_thres_chm : R/W; bitpos: [31:16]; default: 0; + * The high level period in a carrier modulation mode is + * (REG_RMT_REG_CARRIER_HIGH_THRES_CHm + 1) for channel m. + */ + uint32_t carrier_high_thres_chm: 16; + }; + uint32_t val; +} rmt_chm_rx_carrier_rm_reg_t; + +/** Type of sys_conf register + * RMT apb configuration register + */ +typedef union { + struct { + /** apb_fifo_mask : R/W; bitpos: [0]; default: 0; + * 1'h1: access memory directly. 1'h0: access memory by FIFO. + */ + uint32_t apb_fifo_mask: 1; + /** mem_clk_force_on : R/W; bitpos: [1]; default: 0; + * Set this bit to enable the clock for RMT memory. + */ + uint32_t mem_clk_force_on: 1; + /** mem_force_pd : R/W; bitpos: [2]; default: 0; + * Set this bit to power down RMT memory. + */ + uint32_t mem_force_pd: 1; + /** mem_force_pu : R/W; bitpos: [3]; default: 0; + * 1: Disable RMT memory light sleep power down function. 0: Power down RMT memory + * when RMT is in light sleep mode. + */ + uint32_t mem_force_pu: 1; + /** sclk_div_num : R/W; bitpos: [11:4]; default: 1; + * the integral part of the fractional divisor + */ + uint32_t sclk_div_num: 8; + /** sclk_div_a : R/W; bitpos: [17:12]; default: 0; + * the numerator of the fractional part of the fractional divisor + */ + uint32_t sclk_div_a: 6; + /** sclk_div_b : R/W; bitpos: [23:18]; default: 0; + * the denominator of the fractional part of the fractional divisor + */ + uint32_t sclk_div_b: 6; + /** sclk_sel : R/W; bitpos: [25:24]; default: 1; + * choose the clock source of rmt_sclk. 1:CLK_80Mhz;2:CLK_8MHz; 2:XTAL + */ + uint32_t sclk_sel: 2; + /** sclk_active : R/W; bitpos: [26]; default: 1; + * rmt_sclk switch + */ + uint32_t sclk_active: 1; + uint32_t reserved_27: 4; + /** clk_en : R/W; bitpos: [31]; default: 0; + * RMT register clock gate enable signal. 1: Power up the drive clock of registers. 0: + * Power down the drive clock of registers + */ + uint32_t clk_en: 1; + }; + uint32_t val; +} rmt_sys_conf_reg_t; + +/** Type of ref_cnt_rst register + * RMT clock divider reset register + */ +typedef union { + struct { + /** ref_cnt_rst_ch0 : WT; bitpos: [0]; default: 0; + * This register is used to reset the clock divider of CHANNEL0. + */ + uint32_t ref_cnt_rst_ch0: 1; + /** ref_cnt_rst_ch1 : WT; bitpos: [1]; default: 0; + * This register is used to reset the clock divider of CHANNEL1. + */ + uint32_t ref_cnt_rst_ch1: 1; + /** ref_cnt_rst_ch2 : WT; bitpos: [2]; default: 0; + * This register is used to reset the clock divider of CHANNEL2. + */ + uint32_t ref_cnt_rst_ch2: 1; + /** ref_cnt_rst_ch3 : WT; bitpos: [3]; default: 0; + * This register is used to reset the clock divider of CHANNEL3. + */ + uint32_t ref_cnt_rst_ch3: 1; + /** ref_cnt_rst_ch4 : WT; bitpos: [4]; default: 0; + * This register is used to reset the clock divider of CHANNEL4. + */ + uint32_t ref_cnt_rst_ch4: 1; + /** ref_cnt_rst_ch5 : WT; bitpos: [5]; default: 0; + * This register is used to reset the clock divider of CHANNEL5. + */ + uint32_t ref_cnt_rst_ch5: 1; + /** ref_cnt_rst_ch6 : WT; bitpos: [6]; default: 0; + * This register is used to reset the clock divider of CHANNEL6. + */ + uint32_t ref_cnt_rst_ch6: 1; + /** ref_cnt_rst_ch7 : WT; bitpos: [7]; default: 0; + * This register is used to reset the clock divider of CHANNEL7. + */ + uint32_t ref_cnt_rst_ch7: 1; + uint32_t reserved_8: 24; + }; + uint32_t val; +} rmt_ref_cnt_rst_reg_t; + + +/** Group: Status registers */ +/** Type of chnstatus register + * Channel n status register + */ +typedef union { + struct { + /** mem_raddr_ex_n : RO; bitpos: [9:0]; default: 0; + * This register records the memory address offset when transmitter of CHANNELn is + * using the RAM. + */ + uint32_t mem_raddr_ex_n: 10; + uint32_t reserved_10: 1; + /** apb_mem_waddr_n : RO; bitpos: [20:11]; default: 0; + * This register records the memory address offset when writes RAM over APB bus. + */ + uint32_t apb_mem_waddr_n: 10; + uint32_t reserved_21: 1; + /** state_n : RO; bitpos: [24:22]; default: 0; + * This register records the FSM status of CHANNELn. + */ + uint32_t state_n: 3; + /** mem_empty_n : RO; bitpos: [25]; default: 0; + * This status bit will be set when the data to be set is more than memory size and + * the wraparound mode is disabled. + */ + uint32_t mem_empty_n: 1; + /** apb_mem_wr_err_n : RO; bitpos: [26]; default: 0; + * This status bit will be set if the offset address out of memory size when writes + * via APB bus. + */ + uint32_t apb_mem_wr_err_n: 1; + uint32_t reserved_27: 5; + }; + uint32_t val; +} rmt_chnstatus_reg_t; + +/** Type of chmstatus register + * Channel m status register + */ +typedef union { + struct { + /** mem_waddr_ex_m : RO; bitpos: [9:0]; default: 192; + * This register records the memory address offset when receiver of CHANNELm is using + * the RAM. + */ + uint32_t mem_waddr_ex_m: 10; + uint32_t reserved_10: 1; + /** apb_mem_raddr_m : RO; bitpos: [20:11]; default: 192; + * This register records the memory address offset when reads RAM over APB bus. + */ + uint32_t apb_mem_raddr_m: 10; + uint32_t reserved_21: 1; + /** state_m : RO; bitpos: [24:22]; default: 0; + * This register records the FSM status of CHANNELm. + */ + uint32_t state_m: 3; + /** mem_owner_err_m : RO; bitpos: [25]; default: 0; + * This status bit will be set when the ownership of memory block is wrong. + */ + uint32_t mem_owner_err_m: 1; + /** mem_full_m : RO; bitpos: [26]; default: 0; + * This status bit will be set if the receiver receives more data than the memory size. + */ + uint32_t mem_full_m: 1; + /** apb_mem_rd_err_m : RO; bitpos: [27]; default: 0; + * This status bit will be set if the offset address out of memory size when reads via + * APB bus. + */ + uint32_t apb_mem_rd_err_m: 1; + uint32_t reserved_28: 4; + }; + uint32_t val; +} rmt_chmstatus_reg_t; + + +/** Group: Interrupt registers */ +/** Type of int_raw register + * Raw interrupt status + */ +typedef union { + struct { + /** ch0_tx_end_int_raw : R/WTC/SS; bitpos: [0]; default: 0; + * The interrupt raw bit for CHANNEL0. Triggered when transmission done. + */ + uint32_t ch0_tx_end_int_raw: 1; + /** ch1_tx_end_int_raw : R/WTC/SS; bitpos: [1]; default: 0; + * The interrupt raw bit for CHANNEL1. Triggered when transmission done. + */ + uint32_t ch1_tx_end_int_raw: 1; + /** ch2_tx_end_int_raw : R/WTC/SS; bitpos: [2]; default: 0; + * The interrupt raw bit for CHANNEL2. Triggered when transmission done. + */ + uint32_t ch2_tx_end_int_raw: 1; + /** ch3_tx_end_int_raw : R/WTC/SS; bitpos: [3]; default: 0; + * The interrupt raw bit for CHANNEL3. Triggered when transmission done. + */ + uint32_t ch3_tx_end_int_raw: 1; + /** ch0_err_int_raw : R/WTC/SS; bitpos: [4]; default: 0; + * The interrupt raw bit for CHANNEL0. Triggered when error occurs. + */ + uint32_t ch0_err_int_raw: 1; + /** ch1_err_int_raw : R/WTC/SS; bitpos: [5]; default: 0; + * The interrupt raw bit for CHANNEL1. Triggered when error occurs. + */ + uint32_t ch1_err_int_raw: 1; + /** ch2_err_int_raw : R/WTC/SS; bitpos: [6]; default: 0; + * The interrupt raw bit for CHANNEL2. Triggered when error occurs. + */ + uint32_t ch2_err_int_raw: 1; + /** ch3_err_int_raw : R/WTC/SS; bitpos: [7]; default: 0; + * The interrupt raw bit for CHANNEL3. Triggered when error occurs. + */ + uint32_t ch3_err_int_raw: 1; + /** ch0_tx_thr_event_int_raw : R/WTC/SS; bitpos: [8]; default: 0; + * The interrupt raw bit for CHANNEL0. Triggered when transmitter sent more data than + * configured value. + */ + uint32_t ch0_tx_thr_event_int_raw: 1; + /** ch1_tx_thr_event_int_raw : R/WTC/SS; bitpos: [9]; default: 0; + * The interrupt raw bit for CHANNEL1. Triggered when transmitter sent more data than + * configured value. + */ + uint32_t ch1_tx_thr_event_int_raw: 1; + /** ch2_tx_thr_event_int_raw : R/WTC/SS; bitpos: [10]; default: 0; + * The interrupt raw bit for CHANNEL2. Triggered when transmitter sent more data than + * configured value. + */ + uint32_t ch2_tx_thr_event_int_raw: 1; + /** ch3_tx_thr_event_int_raw : R/WTC/SS; bitpos: [11]; default: 0; + * The interrupt raw bit for CHANNEL3. Triggered when transmitter sent more data than + * configured value. + */ + uint32_t ch3_tx_thr_event_int_raw: 1; + /** ch0_tx_loop_int_raw : R/WTC/SS; bitpos: [12]; default: 0; + * The interrupt raw bit for CHANNEL0. Triggered when the loop count reaches the + * configured threshold value. + */ + uint32_t ch0_tx_loop_int_raw: 1; + /** ch1_tx_loop_int_raw : R/WTC/SS; bitpos: [13]; default: 0; + * The interrupt raw bit for CHANNEL1. Triggered when the loop count reaches the + * configured threshold value. + */ + uint32_t ch1_tx_loop_int_raw: 1; + /** ch2_tx_loop_int_raw : R/WTC/SS; bitpos: [14]; default: 0; + * The interrupt raw bit for CHANNEL2. Triggered when the loop count reaches the + * configured threshold value. + */ + uint32_t ch2_tx_loop_int_raw: 1; + /** ch3_tx_loop_int_raw : R/WTC/SS; bitpos: [15]; default: 0; + * The interrupt raw bit for CHANNEL3. Triggered when the loop count reaches the + * configured threshold value. + */ + uint32_t ch3_tx_loop_int_raw: 1; + /** ch4_rx_end_int_raw : R/WTC/SS; bitpos: [16]; default: 0; + * The interrupt raw bit for CHANNEL4. Triggered when reception done. + */ + uint32_t ch4_rx_end_int_raw: 1; + /** ch5_rx_end_int_raw : R/WTC/SS; bitpos: [17]; default: 0; + * The interrupt raw bit for CHANNEL5. Triggered when reception done. + */ + uint32_t ch5_rx_end_int_raw: 1; + /** ch6_rx_end_int_raw : R/WTC/SS; bitpos: [18]; default: 0; + * The interrupt raw bit for CHANNEL6. Triggered when reception done. + */ + uint32_t ch6_rx_end_int_raw: 1; + /** ch7_rx_end_int_raw : R/WTC/SS; bitpos: [19]; default: 0; + * The interrupt raw bit for CHANNEL7. Triggered when reception done. + */ + uint32_t ch7_rx_end_int_raw: 1; + /** ch4_err_int_raw : R/WTC/SS; bitpos: [20]; default: 0; + * The interrupt raw bit for CHANNEL4. Triggered when error occurs. + */ + uint32_t ch4_err_int_raw: 1; + /** ch5_err_int_raw : R/WTC/SS; bitpos: [21]; default: 0; + * The interrupt raw bit for CHANNEL5. Triggered when error occurs. + */ + uint32_t ch5_err_int_raw: 1; + /** ch6_err_int_raw : R/WTC/SS; bitpos: [22]; default: 0; + * The interrupt raw bit for CHANNEL6. Triggered when error occurs. + */ + uint32_t ch6_err_int_raw: 1; + /** ch7_err_int_raw : R/WTC/SS; bitpos: [23]; default: 0; + * The interrupt raw bit for CHANNEL7. Triggered when error occurs. + */ + uint32_t ch7_err_int_raw: 1; + /** ch4_rx_thr_event_int_raw : R/WTC/SS; bitpos: [24]; default: 0; + * The interrupt raw bit for CHANNEL4. Triggered when receiver receive more data than + * configured value. + */ + uint32_t ch4_rx_thr_event_int_raw: 1; + /** ch5_rx_thr_event_int_raw : R/WTC/SS; bitpos: [25]; default: 0; + * The interrupt raw bit for CHANNEL5. Triggered when receiver receive more data than + * configured value. + */ + uint32_t ch5_rx_thr_event_int_raw: 1; + /** ch6_rx_thr_event_int_raw : R/WTC/SS; bitpos: [26]; default: 0; + * The interrupt raw bit for CHANNEL6. Triggered when receiver receive more data than + * configured value. + */ + uint32_t ch6_rx_thr_event_int_raw: 1; + /** ch7_rx_thr_event_int_raw : R/WTC/SS; bitpos: [27]; default: 0; + * The interrupt raw bit for CHANNEL7. Triggered when receiver receive more data than + * configured value. + */ + uint32_t ch7_rx_thr_event_int_raw: 1; + /** ch3_dma_access_fail_int_raw : R/WTC/SS; bitpos: [28]; default: 0; + * The interrupt raw bit for CHANNEL3. Triggered when dma accessing CHANNEL3 fails. + */ + uint32_t ch3_dma_access_fail_int_raw: 1; + /** ch7_dma_access_fail_int_raw : R/WTC/SS; bitpos: [29]; default: 0; + * The interrupt raw bit for CHANNEL7. Triggered when dma accessing CHANNEL7 fails. + */ + uint32_t ch7_dma_access_fail_int_raw: 1; + uint32_t reserved_30: 2; + }; + uint32_t val; +} rmt_int_raw_reg_t; + +/** Type of int_st register + * Masked interrupt status + */ +typedef union { + struct { + /** ch0_tx_end_int_st : RO; bitpos: [0]; default: 0; + * The masked interrupt status bit for CH0_TX_END_INT. + */ + uint32_t ch0_tx_end_int_st: 1; + /** ch1_tx_end_int_st : RO; bitpos: [1]; default: 0; + * The masked interrupt status bit for CH1_TX_END_INT. + */ + uint32_t ch1_tx_end_int_st: 1; + /** ch2_tx_end_int_st : RO; bitpos: [2]; default: 0; + * The masked interrupt status bit for CH2_TX_END_INT. + */ + uint32_t ch2_tx_end_int_st: 1; + /** ch3_tx_end_int_st : RO; bitpos: [3]; default: 0; + * The masked interrupt status bit for CH3_TX_END_INT. + */ + uint32_t ch3_tx_end_int_st: 1; + /** ch0_err_int_st : RO; bitpos: [4]; default: 0; + * The masked interrupt status bit for CH0_ERR_INT. + */ + uint32_t ch0_err_int_st: 1; + /** ch1_err_int_st : RO; bitpos: [5]; default: 0; + * The masked interrupt status bit for CH1_ERR_INT. + */ + uint32_t ch1_err_int_st: 1; + /** ch2_err_int_st : RO; bitpos: [6]; default: 0; + * The masked interrupt status bit for CH2_ERR_INT. + */ + uint32_t ch2_err_int_st: 1; + /** ch3_err_int_st : RO; bitpos: [7]; default: 0; + * The masked interrupt status bit for CH3_ERR_INT. + */ + uint32_t ch3_err_int_st: 1; + /** ch0_tx_thr_event_int_st : RO; bitpos: [8]; default: 0; + * The masked interrupt status bit for CH0_TX_THR_EVENT_INT. + */ + uint32_t ch0_tx_thr_event_int_st: 1; + /** ch1_tx_thr_event_int_st : RO; bitpos: [9]; default: 0; + * The masked interrupt status bit for CH1_TX_THR_EVENT_INT. + */ + uint32_t ch1_tx_thr_event_int_st: 1; + /** ch2_tx_thr_event_int_st : RO; bitpos: [10]; default: 0; + * The masked interrupt status bit for CH2_TX_THR_EVENT_INT. + */ + uint32_t ch2_tx_thr_event_int_st: 1; + /** ch3_tx_thr_event_int_st : RO; bitpos: [11]; default: 0; + * The masked interrupt status bit for CH3_TX_THR_EVENT_INT. + */ + uint32_t ch3_tx_thr_event_int_st: 1; + /** ch0_tx_loop_int_st : RO; bitpos: [12]; default: 0; + * The masked interrupt status bit for CH0_TX_LOOP_INT. + */ + uint32_t ch0_tx_loop_int_st: 1; + /** ch1_tx_loop_int_st : RO; bitpos: [13]; default: 0; + * The masked interrupt status bit for CH1_TX_LOOP_INT. + */ + uint32_t ch1_tx_loop_int_st: 1; + /** ch2_tx_loop_int_st : RO; bitpos: [14]; default: 0; + * The masked interrupt status bit for CH2_TX_LOOP_INT. + */ + uint32_t ch2_tx_loop_int_st: 1; + /** ch3_tx_loop_int_st : RO; bitpos: [15]; default: 0; + * The masked interrupt status bit for CH3_TX_LOOP_INT. + */ + uint32_t ch3_tx_loop_int_st: 1; + /** ch4_rx_end_int_st : RO; bitpos: [16]; default: 0; + * The masked interrupt status bit for CH4_RX_END_INT. + */ + uint32_t ch4_rx_end_int_st: 1; + /** ch5_rx_end_int_st : RO; bitpos: [17]; default: 0; + * The masked interrupt status bit for CH5_RX_END_INT. + */ + uint32_t ch5_rx_end_int_st: 1; + /** ch6_rx_end_int_st : RO; bitpos: [18]; default: 0; + * The masked interrupt status bit for CH6_RX_END_INT. + */ + uint32_t ch6_rx_end_int_st: 1; + /** ch7_rx_end_int_st : RO; bitpos: [19]; default: 0; + * The masked interrupt status bit for CH7_RX_END_INT. + */ + uint32_t ch7_rx_end_int_st: 1; + /** ch4_err_int_st : RO; bitpos: [20]; default: 0; + * The masked interrupt status bit for CH4_ERR_INT. + */ + uint32_t ch4_err_int_st: 1; + /** ch5_err_int_st : RO; bitpos: [21]; default: 0; + * The masked interrupt status bit for CH5_ERR_INT. + */ + uint32_t ch5_err_int_st: 1; + /** ch6_err_int_st : RO; bitpos: [22]; default: 0; + * The masked interrupt status bit for CH6_ERR_INT. + */ + uint32_t ch6_err_int_st: 1; + /** ch7_err_int_st : RO; bitpos: [23]; default: 0; + * The masked interrupt status bit for CH7_ERR_INT. + */ + uint32_t ch7_err_int_st: 1; + /** ch4_rx_thr_event_int_st : RO; bitpos: [24]; default: 0; + * The masked interrupt status bit for CH4_RX_THR_EVENT_INT. + */ + uint32_t ch4_rx_thr_event_int_st: 1; + /** ch5_rx_thr_event_int_st : RO; bitpos: [25]; default: 0; + * The masked interrupt status bit for CH5_RX_THR_EVENT_INT. + */ + uint32_t ch5_rx_thr_event_int_st: 1; + /** ch6_rx_thr_event_int_st : RO; bitpos: [26]; default: 0; + * The masked interrupt status bit for CH6_RX_THR_EVENT_INT. + */ + uint32_t ch6_rx_thr_event_int_st: 1; + /** ch7_rx_thr_event_int_st : RO; bitpos: [27]; default: 0; + * The masked interrupt status bit for CH7_RX_THR_EVENT_INT. + */ + uint32_t ch7_rx_thr_event_int_st: 1; + /** ch3_dma_access_fail_int_st : RO; bitpos: [28]; default: 0; + * The masked interrupt status bit for CH3_DMA_ACCESS_FAIL_INT. + */ + uint32_t ch3_dma_access_fail_int_st: 1; + /** ch7_dma_access_fail_int_st : RO; bitpos: [29]; default: 0; + * The masked interrupt status bit for CH7_DMA_ACCESS_FAIL_INT. + */ + uint32_t ch7_dma_access_fail_int_st: 1; + uint32_t reserved_30: 2; + }; + uint32_t val; +} rmt_int_st_reg_t; + +/** Type of int_ena register + * Interrupt enable bits + */ +typedef union { + struct { + /** ch0_tx_end_int_ena : R/W; bitpos: [0]; default: 0; + * The interrupt enable bit for CH0_TX_END_INT. + */ + uint32_t ch0_tx_end_int_ena: 1; + /** ch1_tx_end_int_ena : R/W; bitpos: [1]; default: 0; + * The interrupt enable bit for CH1_TX_END_INT. + */ + uint32_t ch1_tx_end_int_ena: 1; + /** ch2_tx_end_int_ena : R/W; bitpos: [2]; default: 0; + * The interrupt enable bit for CH2_TX_END_INT. + */ + uint32_t ch2_tx_end_int_ena: 1; + /** ch3_tx_end_int_ena : R/W; bitpos: [3]; default: 0; + * The interrupt enable bit for CH3_TX_END_INT. + */ + uint32_t ch3_tx_end_int_ena: 1; + /** ch0_err_int_ena : R/W; bitpos: [4]; default: 0; + * The interrupt enable bit for CH0_ERR_INT. + */ + uint32_t ch0_err_int_ena: 1; + /** ch1_err_int_ena : R/W; bitpos: [5]; default: 0; + * The interrupt enable bit for CH1_ERR_INT. + */ + uint32_t ch1_err_int_ena: 1; + /** ch2_err_int_ena : R/W; bitpos: [6]; default: 0; + * The interrupt enable bit for CH2_ERR_INT. + */ + uint32_t ch2_err_int_ena: 1; + /** ch3_err_int_ena : R/W; bitpos: [7]; default: 0; + * The interrupt enable bit for CH3_ERR_INT. + */ + uint32_t ch3_err_int_ena: 1; + /** ch0_tx_thr_event_int_ena : R/W; bitpos: [8]; default: 0; + * The interrupt enable bit for CH0_TX_THR_EVENT_INT. + */ + uint32_t ch0_tx_thr_event_int_ena: 1; + /** ch1_tx_thr_event_int_ena : R/W; bitpos: [9]; default: 0; + * The interrupt enable bit for CH1_TX_THR_EVENT_INT. + */ + uint32_t ch1_tx_thr_event_int_ena: 1; + /** ch2_tx_thr_event_int_ena : R/W; bitpos: [10]; default: 0; + * The interrupt enable bit for CH2_TX_THR_EVENT_INT. + */ + uint32_t ch2_tx_thr_event_int_ena: 1; + /** ch3_tx_thr_event_int_ena : R/W; bitpos: [11]; default: 0; + * The interrupt enable bit for CH3_TX_THR_EVENT_INT. + */ + uint32_t ch3_tx_thr_event_int_ena: 1; + /** ch0_tx_loop_int_ena : R/W; bitpos: [12]; default: 0; + * The interrupt enable bit for CH0_TX_LOOP_INT. + */ + uint32_t ch0_tx_loop_int_ena: 1; + /** ch1_tx_loop_int_ena : R/W; bitpos: [13]; default: 0; + * The interrupt enable bit for CH1_TX_LOOP_INT. + */ + uint32_t ch1_tx_loop_int_ena: 1; + /** ch2_tx_loop_int_ena : R/W; bitpos: [14]; default: 0; + * The interrupt enable bit for CH2_TX_LOOP_INT. + */ + uint32_t ch2_tx_loop_int_ena: 1; + /** ch3_tx_loop_int_ena : R/W; bitpos: [15]; default: 0; + * The interrupt enable bit for CH3_TX_LOOP_INT. + */ + uint32_t ch3_tx_loop_int_ena: 1; + /** ch4_rx_end_int_ena : R/W; bitpos: [16]; default: 0; + * The interrupt enable bit for CH4_RX_END_INT. + */ + uint32_t ch4_rx_end_int_ena: 1; + /** ch5_rx_end_int_ena : R/W; bitpos: [17]; default: 0; + * The interrupt enable bit for CH5_RX_END_INT. + */ + uint32_t ch5_rx_end_int_ena: 1; + /** ch6_rx_end_int_ena : R/W; bitpos: [18]; default: 0; + * The interrupt enable bit for CH6_RX_END_INT. + */ + uint32_t ch6_rx_end_int_ena: 1; + /** ch7_rx_end_int_ena : R/W; bitpos: [19]; default: 0; + * The interrupt enable bit for CH7_RX_END_INT. + */ + uint32_t ch7_rx_end_int_ena: 1; + /** ch4_err_int_ena : R/W; bitpos: [20]; default: 0; + * The interrupt enable bit for CH4_ERR_INT. + */ + uint32_t ch4_err_int_ena: 1; + /** ch5_err_int_ena : R/W; bitpos: [21]; default: 0; + * The interrupt enable bit for CH5_ERR_INT. + */ + uint32_t ch5_err_int_ena: 1; + /** ch6_err_int_ena : R/W; bitpos: [22]; default: 0; + * The interrupt enable bit for CH6_ERR_INT. + */ + uint32_t ch6_err_int_ena: 1; + /** ch7_err_int_ena : R/W; bitpos: [23]; default: 0; + * The interrupt enable bit for CH7_ERR_INT. + */ + uint32_t ch7_err_int_ena: 1; + /** ch4_rx_thr_event_int_ena : R/W; bitpos: [24]; default: 0; + * The interrupt enable bit for CH4_RX_THR_EVENT_INT. + */ + uint32_t ch4_rx_thr_event_int_ena: 1; + /** ch5_rx_thr_event_int_ena : R/W; bitpos: [25]; default: 0; + * The interrupt enable bit for CH5_RX_THR_EVENT_INT. + */ + uint32_t ch5_rx_thr_event_int_ena: 1; + /** ch6_rx_thr_event_int_ena : R/W; bitpos: [26]; default: 0; + * The interrupt enable bit for CH6_RX_THR_EVENT_INT. + */ + uint32_t ch6_rx_thr_event_int_ena: 1; + /** ch7_rx_thr_event_int_ena : R/W; bitpos: [27]; default: 0; + * The interrupt enable bit for CH7_RX_THR_EVENT_INT. + */ + uint32_t ch7_rx_thr_event_int_ena: 1; + /** ch3_dma_access_fail_int_ena : R/W; bitpos: [28]; default: 0; + * The interrupt enable bit for CH3_DMA_ACCESS_FAIL_INT. + */ + uint32_t ch3_dma_access_fail_int_ena: 1; + /** ch7_dma_access_fail_int_ena : R/W; bitpos: [29]; default: 0; + * The interrupt enable bit for CH7_DMA_ACCESS_FAIL_INT. + */ + uint32_t ch7_dma_access_fail_int_ena: 1; + uint32_t reserved_30: 2; + }; + uint32_t val; +} rmt_int_ena_reg_t; + +/** Type of int_clr register + * Interrupt clear bits + */ +typedef union { + struct { + /** ch0_tx_end_int_clr : WT; bitpos: [0]; default: 0; + * Set this bit to clear theCH0_TX_END_INT interrupt. + */ + uint32_t ch0_tx_end_int_clr: 1; + /** ch1_tx_end_int_clr : WT; bitpos: [1]; default: 0; + * Set this bit to clear theCH1_TX_END_INT interrupt. + */ + uint32_t ch1_tx_end_int_clr: 1; + /** ch2_tx_end_int_clr : WT; bitpos: [2]; default: 0; + * Set this bit to clear theCH2_TX_END_INT interrupt. + */ + uint32_t ch2_tx_end_int_clr: 1; + /** ch3_tx_end_int_clr : WT; bitpos: [3]; default: 0; + * Set this bit to clear theCH3_TX_END_INT interrupt. + */ + uint32_t ch3_tx_end_int_clr: 1; + /** ch0_err_int_clr : WT; bitpos: [4]; default: 0; + * Set this bit to clear theCH0_ERR_INT interrupt. + */ + uint32_t ch0_err_int_clr: 1; + /** ch1_err_int_clr : WT; bitpos: [5]; default: 0; + * Set this bit to clear theCH1_ERR_INT interrupt. + */ + uint32_t ch1_err_int_clr: 1; + /** ch2_err_int_clr : WT; bitpos: [6]; default: 0; + * Set this bit to clear theCH2_ERR_INT interrupt. + */ + uint32_t ch2_err_int_clr: 1; + /** ch3_err_int_clr : WT; bitpos: [7]; default: 0; + * Set this bit to clear theCH3_ERR_INT interrupt. + */ + uint32_t ch3_err_int_clr: 1; + /** ch0_tx_thr_event_int_clr : WT; bitpos: [8]; default: 0; + * Set this bit to clear theCH0_TX_THR_EVENT_INT interrupt. + */ + uint32_t ch0_tx_thr_event_int_clr: 1; + /** ch1_tx_thr_event_int_clr : WT; bitpos: [9]; default: 0; + * Set this bit to clear theCH1_TX_THR_EVENT_INT interrupt. + */ + uint32_t ch1_tx_thr_event_int_clr: 1; + /** ch2_tx_thr_event_int_clr : WT; bitpos: [10]; default: 0; + * Set this bit to clear theCH2_TX_THR_EVENT_INT interrupt. + */ + uint32_t ch2_tx_thr_event_int_clr: 1; + /** ch3_tx_thr_event_int_clr : WT; bitpos: [11]; default: 0; + * Set this bit to clear theCH3_TX_THR_EVENT_INT interrupt. + */ + uint32_t ch3_tx_thr_event_int_clr: 1; + /** ch0_tx_loop_int_clr : WT; bitpos: [12]; default: 0; + * Set this bit to clear theCH0_TX_LOOP_INT interrupt. + */ + uint32_t ch0_tx_loop_int_clr: 1; + /** ch1_tx_loop_int_clr : WT; bitpos: [13]; default: 0; + * Set this bit to clear theCH1_TX_LOOP_INT interrupt. + */ + uint32_t ch1_tx_loop_int_clr: 1; + /** ch2_tx_loop_int_clr : WT; bitpos: [14]; default: 0; + * Set this bit to clear theCH2_TX_LOOP_INT interrupt. + */ + uint32_t ch2_tx_loop_int_clr: 1; + /** ch3_tx_loop_int_clr : WT; bitpos: [15]; default: 0; + * Set this bit to clear theCH3_TX_LOOP_INT interrupt. + */ + uint32_t ch3_tx_loop_int_clr: 1; + /** ch4_rx_end_int_clr : WT; bitpos: [16]; default: 0; + * Set this bit to clear theCH4_RX_END_INT interrupt. + */ + uint32_t ch4_rx_end_int_clr: 1; + /** ch5_rx_end_int_clr : WT; bitpos: [17]; default: 0; + * Set this bit to clear theCH5_RX_END_INT interrupt. + */ + uint32_t ch5_rx_end_int_clr: 1; + /** ch6_rx_end_int_clr : WT; bitpos: [18]; default: 0; + * Set this bit to clear theCH6_RX_END_INT interrupt. + */ + uint32_t ch6_rx_end_int_clr: 1; + /** ch7_rx_end_int_clr : WT; bitpos: [19]; default: 0; + * Set this bit to clear theCH7_RX_END_INT interrupt. + */ + uint32_t ch7_rx_end_int_clr: 1; + /** ch4_err_int_clr : WT; bitpos: [20]; default: 0; + * Set this bit to clear theCH4_ERR_INT interrupt. + */ + uint32_t ch4_err_int_clr: 1; + /** ch5_err_int_clr : WT; bitpos: [21]; default: 0; + * Set this bit to clear theCH5_ERR_INT interrupt. + */ + uint32_t ch5_err_int_clr: 1; + /** ch6_err_int_clr : WT; bitpos: [22]; default: 0; + * Set this bit to clear theCH6_ERR_INT interrupt. + */ + uint32_t ch6_err_int_clr: 1; + /** ch7_err_int_clr : WT; bitpos: [23]; default: 0; + * Set this bit to clear theCH7_ERR_INT interrupt. + */ + uint32_t ch7_err_int_clr: 1; + /** ch4_rx_thr_event_int_clr : WT; bitpos: [24]; default: 0; + * Set this bit to clear theCH4_RX_THR_EVENT_INT interrupt. + */ + uint32_t ch4_rx_thr_event_int_clr: 1; + /** ch5_rx_thr_event_int_clr : WT; bitpos: [25]; default: 0; + * Set this bit to clear theCH5_RX_THR_EVENT_INT interrupt. + */ + uint32_t ch5_rx_thr_event_int_clr: 1; + /** ch6_rx_thr_event_int_clr : WT; bitpos: [26]; default: 0; + * Set this bit to clear theCH6_RX_THR_EVENT_INT interrupt. + */ + uint32_t ch6_rx_thr_event_int_clr: 1; + /** ch7_rx_thr_event_int_clr : WT; bitpos: [27]; default: 0; + * Set this bit to clear theCH7_RX_THR_EVENT_INT interrupt. + */ + uint32_t ch7_rx_thr_event_int_clr: 1; + /** ch3_dma_access_fail_int_clr : WT; bitpos: [28]; default: 0; + * Set this bit to clear the CH3_DMA_ACCESS_FAIL_INT interrupt. + */ + uint32_t ch3_dma_access_fail_int_clr: 1; + /** ch7_dma_access_fail_int_clr : WT; bitpos: [29]; default: 0; + * Set this bit to clear the CH7_DMA_ACCESS_FAIL_INT interrupt. + */ + uint32_t ch7_dma_access_fail_int_clr: 1; + uint32_t reserved_30: 2; + }; + uint32_t val; +} rmt_int_clr_reg_t; + + +/** Group: Carrier wave duty cycle registers */ +/** Type of chncarrier_duty register + * Channel n duty cycle configuration register + */ +typedef union { + struct { + /** carrier_low_chn : R/W; bitpos: [15:0]; default: 64; + * This register is used to configure carrier wave 's low level clock period for + * CHANNELn. + */ + uint32_t carrier_low_chn: 16; + /** carrier_high_chn : R/W; bitpos: [31:16]; default: 64; + * This register is used to configure carrier wave 's high level clock period for + * CHANNELn. + */ + uint32_t carrier_high_chn: 16; + }; + uint32_t val; +} rmt_chncarrier_duty_reg_t; + + +/** Group: Tx event configuration registers */ +/** Type of chn_tx_lim register + * Channel n Tx event configuration register + */ +typedef union { + struct { + /** tx_lim_chn : R/W; bitpos: [8:0]; default: 128; + * This register is used to configure the maximum entries that CHANNELn can send out. + */ + uint32_t tx_lim_chn: 9; + /** tx_loop_num_chn : R/W; bitpos: [18:9]; default: 0; + * This register is used to configure the maximum loop count when tx_conti_mode is + * valid. + */ + uint32_t tx_loop_num_chn: 10; + /** tx_loop_cnt_en_chn : R/W; bitpos: [19]; default: 0; + * This register is the enabled bit for loop count. + */ + uint32_t tx_loop_cnt_en_chn: 1; + /** loop_count_reset_chn : WT; bitpos: [20]; default: 0; + * This register is used to reset the loop count when tx_conti_mode is valid. + */ + uint32_t loop_count_reset_chn: 1; + /** loop_stop_en_chn : R/W; bitpos: [21]; default: 0; + * This bit is used to enable the loop send stop function after the loop counter + * counts to loop number for CHANNELn. + */ + uint32_t loop_stop_en_chn: 1; + uint32_t reserved_22: 10; + }; + uint32_t val; +} rmt_chn_tx_lim_reg_t; + +/** Type of tx_sim register + * RMT TX synchronous register + */ +typedef union { + struct { + /** tx_sim_ch0 : R/W; bitpos: [0]; default: 0; + * Set this bit to enable CHANNEL0 to start sending data synchronously with other + * enabled channels. + */ + uint32_t tx_sim_ch0: 1; + /** tx_sim_ch1 : R/W; bitpos: [1]; default: 0; + * Set this bit to enable CHANNEL1 to start sending data synchronously with other + * enabled channels. + */ + uint32_t tx_sim_ch1: 1; + /** tx_sim_ch2 : R/W; bitpos: [2]; default: 0; + * Set this bit to enable CHANNEL2 to start sending data synchronously with other + * enabled channels. + */ + uint32_t tx_sim_ch2: 1; + /** tx_sim_ch3 : R/W; bitpos: [3]; default: 0; + * Set this bit to enable CHANNEL3 to start sending data synchronously with other + * enabled channels. + */ + uint32_t tx_sim_ch3: 1; + /** tx_sim_en : R/W; bitpos: [4]; default: 0; + * This register is used to enable multiple of channels to start sending data + * synchronously. + */ + uint32_t tx_sim_en: 1; + uint32_t reserved_5: 27; + }; + uint32_t val; +} rmt_tx_sim_reg_t; + + +/** Group: Rx event configuration registers */ +/** Type of chm_rx_lim register + * Channel m Rx event configuration register + */ +typedef union { + struct { + /** chm_rx_lim_reg : R/W; bitpos: [8:0]; default: 128; + * This register is used to configure the maximum entries that CHANNELm can receive. + */ + uint32_t chm_rx_lim_reg: 9; + uint32_t reserved_9: 23; + }; + uint32_t val; +} rmt_chm_rx_lim_reg_t; + + +/** Group: Version register */ +/** Type of date register + * RMT version register + */ +typedef union { + struct { + /** date : R/W; bitpos: [27:0]; default: 34607489; + * This is the version register. + */ + uint32_t date: 28; + uint32_t reserved_28: 4; + }; + uint32_t val; +} rmt_date_reg_t; + + +typedef struct { + volatile rmt_chndata_reg_t chndata[4]; + volatile rmt_chmdata_reg_t chmdata[4]; + volatile rmt_chnconf0_reg_t chnconf0[4]; + volatile rmt_chmconf_reg_t chmconf[4]; + volatile rmt_chnstatus_reg_t chnstatus[4]; + volatile rmt_chmstatus_reg_t chmstatus[4]; + volatile rmt_int_raw_reg_t int_raw; + volatile rmt_int_st_reg_t int_st; + volatile rmt_int_ena_reg_t int_ena; + volatile rmt_int_clr_reg_t int_clr; + volatile rmt_chncarrier_duty_reg_t chncarrier_duty[4]; + volatile rmt_chm_rx_carrier_rm_reg_t chm_rx_carrier_rm[4]; + volatile rmt_chn_tx_lim_reg_t chn_tx_lim[4]; + volatile rmt_chm_rx_lim_reg_t chm_rx_lim[4]; + volatile rmt_sys_conf_reg_t sys_conf; + volatile rmt_tx_sim_reg_t tx_sim; + volatile rmt_ref_cnt_rst_reg_t ref_cnt_rst; + volatile rmt_date_reg_t date; } rmt_dev_t; +#ifndef __cplusplus +_Static_assert(sizeof(rmt_dev_t) == 0xd0, "Invalid size of rmt_dev_t structure"); +#endif + typedef struct { union { struct { @@ -337,22 +1101,22 @@ typedef struct { }; } rmt_item32_t; -extern rmt_dev_t RMT; - -typedef volatile struct { +typedef struct { struct { union { - rmt_item32_t data32[48]; + volatile rmt_item32_t data32[48]; }; } chan[8]; } rmt_mem_t; +#ifndef __cplusplus +_Static_assert(sizeof(rmt_item32_t) == 0x04, "Invalid size of rmt_item32_t structure"); +_Static_assert(sizeof(rmt_mem_t) == 0x04 * 8 * 48, "Invalid size of rmt_mem_t structure"); +#endif + +extern rmt_dev_t RMT; extern rmt_mem_t RMTMEM; #ifdef __cplusplus } #endif - - - -#endif /*_SOC_RMT_STRUCT_H_ */