From 08d38349e4da3ed61eb005876539023dc7bab363 Mon Sep 17 00:00:00 2001 From: armando Date: Mon, 1 Sep 2025 16:24:47 +0800 Subject: [PATCH 1/2] change(dsi): add dpi_type configs --- .../hal/esp32p4/include/hal/mipi_dsi_brg_ll.h | 28 ++++++++++++++++++- 1 file changed, 27 insertions(+), 1 deletion(-) diff --git a/components/hal/esp32p4/include/hal/mipi_dsi_brg_ll.h b/components/hal/esp32p4/include/hal/mipi_dsi_brg_ll.h index 78979e8453..3d086af34b 100644 --- a/components/hal/esp32p4/include/hal/mipi_dsi_brg_ll.h +++ b/components/hal/esp32p4/include/hal/mipi_dsi_brg_ll.h @@ -1,5 +1,5 @@ /* - * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD + * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD * * SPDX-License-Identifier: Apache-2.0 */ @@ -12,6 +12,7 @@ #include "soc/mipi_dsi_bridge_struct.h" #include "hal/mipi_dsi_types.h" #include "hal/lcd_types.h" +#include "hal/config.h" #define MIPI_DSI_LL_GET_BRG(bus_id) (bus_id == 0 ? &MIPI_DSI_BRIDGE : NULL) #define MIPI_DSI_LL_EVENT_UNDERRUN (1 << 0) @@ -173,6 +174,30 @@ static inline void mipi_dsi_brg_ll_credit_reset(dsi_brg_dev_t *dev) * @param color_coding Color coding value * @param sub_config Sub configuration */ +#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300 +static inline void mipi_dsi_brg_ll_set_pixel_format(dsi_brg_dev_t *dev, lcd_color_format_t color_coding, uint32_t sub_config) +{ + switch (color_coding) { + case LCD_COLOR_FMT_RGB565: + dev->pixel_type.raw_type = 2; + dev->pixel_type.dpi_type = 2; + break; + case LCD_COLOR_FMT_RGB666: + dev->pixel_type.raw_type = 1; + dev->pixel_type.dpi_type = 1; + break; + case LCD_COLOR_FMT_RGB888: + dev->pixel_type.raw_type = 0; + dev->pixel_type.dpi_type = 0; + break; + default: + // MIPI DSI host can only accept RGB data, no YUV data + HAL_ASSERT(false); + break; + } + dev->pixel_type.dpi_config = sub_config; +} +#else static inline void mipi_dsi_brg_ll_set_pixel_format(dsi_brg_dev_t *dev, lcd_color_format_t color_coding, uint32_t sub_config) { switch (color_coding) { @@ -192,6 +217,7 @@ static inline void mipi_dsi_brg_ll_set_pixel_format(dsi_brg_dev_t *dev, lcd_colo } dev->pixel_type.dpi_config = sub_config; } +#endif /** * @brief Set the color space for input color data From 406c54ebfb593c36b76eb18e4aca8fcf6ab0b594 Mon Sep 17 00:00:00 2001 From: armando Date: Mon, 1 Sep 2025 16:25:36 +0800 Subject: [PATCH 2/2] feat(csi): support csi on p4 rev3 --- .../hw_ver3/soc/mipi_csi_bridge_eco5_struct.h | 452 ---- .../hw_ver3/soc/mipi_csi_bridge_struct.h | 90 +- .../hw_ver3/soc/mipi_csi_host_eco5_struct.h | 1883 ----------------- 3 files changed, 85 insertions(+), 2340 deletions(-) delete mode 100644 components/soc/esp32p4/register/hw_ver3/soc/mipi_csi_bridge_eco5_struct.h delete mode 100644 components/soc/esp32p4/register/hw_ver3/soc/mipi_csi_host_eco5_struct.h diff --git a/components/soc/esp32p4/register/hw_ver3/soc/mipi_csi_bridge_eco5_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/mipi_csi_bridge_eco5_struct.h deleted file mode 100644 index c94e6559ab..0000000000 --- a/components/soc/esp32p4/register/hw_ver3/soc/mipi_csi_bridge_eco5_struct.h +++ /dev/null @@ -1,452 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#ifdef __cplusplus -extern "C" { -#endif - -/** Group: csi bridge regbank clock gating control register. */ -/** Type of clk_en register - * csi bridge register mapping unit clock gating. - */ -typedef union { - struct { - /** clk_en : R/W; bitpos: [0]; default: 0; - * 0: enable clock gating. 1: disable clock gating, clock always on. - */ - uint32_t clk_en:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} csi_brg_clk_en_reg_t; - - -/** Group: csi bridge control registers. */ -/** Type of csi_en register - * csi bridge enable. - */ -typedef union { - struct { - /** csi_brg_en : R/W; bitpos: [0]; default: 0; - * 0: disable csi bridge. 1: enable csi bridge. - */ - uint32_t csi_brg_en:1; - /** csi_brg_rst : R/W; bitpos: [1]; default: 0; - * 0: release csi bridge reset. 1: enable csi bridge reset. - */ - uint32_t csi_brg_rst:1; - uint32_t reserved_2:30; - }; - uint32_t val; -} csi_brg_csi_en_reg_t; - -/** Type of buf_flow_ctl register - * csi bridge buffer control. - */ -typedef union { - struct { - /** csi_buf_afull_thrd : R/W; bitpos: [13:0]; default: 2040; - * buffer almost full threshold. - */ - uint32_t csi_buf_afull_thrd:14; - uint32_t reserved_14:2; - /** csi_buf_depth : RO; bitpos: [29:16]; default: 0; - * buffer data count. - */ - uint32_t csi_buf_depth:14; - uint32_t reserved_30:2; - }; - uint32_t val; -} csi_brg_buf_flow_ctl_reg_t; - - -/** Group: csi bridge dma control registers. */ -/** Type of dma_req_cfg register - * dma request configuration. - */ -typedef union { - struct { - /** dma_burst_len : R/W; bitpos: [11:0]; default: 128; - * DMA burst length. - */ - uint32_t dma_burst_len:12; - /** dma_cfg_upd_by_blk : R/W; bitpos: [12]; default: 0; - * 1: reg_dma_burst_len & reg_dma_burst_len will be updated by dma block finish. 0: - * updated by frame. - */ - uint32_t dma_cfg_upd_by_blk:1; - uint32_t reserved_13:3; - /** dma_force_rd_status : R/W; bitpos: [16]; default: 0; - * 1: mask dma request when reading frame info. 0: disable mask. - */ - uint32_t dma_force_rd_status:1; - /** csi_dma_flow_controller : R/W; bitpos: [17]; default: 1; - * 0: dma as flow controller. 1: csi_bridge as flow controller - */ - uint32_t csi_dma_flow_controller:1; - uint32_t reserved_18:14; - }; - uint32_t val; -} csi_brg_dma_req_cfg_reg_t; - -/** Type of dma_req_interval register - * DMA interval configuration. - */ -typedef union { - struct { - /** dma_req_interval : R/W; bitpos: [15:0]; default: 1; - * 16'b1: 1 cycle. 16'b11: 2 cycle. ... ... 16'hFFFF: 16 cycle. - */ - uint32_t dma_req_interval:16; - uint32_t reserved_16:16; - }; - uint32_t val; -} csi_brg_dma_req_interval_reg_t; - -/** Type of dmablk_size register - * DMA block size configuration. - */ -typedef union { - struct { - /** dmablk_size : R/W; bitpos: [12:0]; default: 8191; - * the number of reg_dma_burst_len in a block - */ - uint32_t dmablk_size:13; - uint32_t reserved_13:19; - }; - uint32_t val; -} csi_brg_dmablk_size_reg_t; - - -/** Group: csi bridge frame format configuration registers. */ -/** Type of data_type_cfg register - * pixel data type configuration. - */ -typedef union { - struct { - /** data_type_min : R/W; bitpos: [5:0]; default: 24; - * the min value of data type used for pixel filter. - */ - uint32_t data_type_min:6; - uint32_t reserved_6:2; - /** data_type_max : R/W; bitpos: [13:8]; default: 47; - * the max value of data type used for pixel filter. - */ - uint32_t data_type_max:6; - uint32_t reserved_14:18; - }; - uint32_t val; -} csi_brg_data_type_cfg_reg_t; - -/** Type of frame_cfg register - * frame configuration. - */ -typedef union { - struct { - /** vadr_num : R/W; bitpos: [11:0]; default: 480; - * vadr of frame data. - */ - uint32_t vadr_num:12; - /** hadr_num : R/W; bitpos: [23:12]; default: 480; - * hadr of frame data. - */ - uint32_t hadr_num:12; - /** has_hsync_e : R/W; bitpos: [24]; default: 1; - * 0: frame data doesn't contain hsync. 1: frame data contains hsync. - */ - uint32_t has_hsync_e:1; - /** vadr_num_check : R/W; bitpos: [25]; default: 0; - * 0: disable vadr check. 1: enable vadr check. - */ - uint32_t vadr_num_check:1; - uint32_t reserved_26:6; - }; - uint32_t val; -} csi_brg_frame_cfg_reg_t; - -/** Type of endian_mode register - * data endianness order configuration. - */ -typedef union { - struct { - /** byte_endian_order : R/W; bitpos: [0]; default: 0; - * endianness order in bytes. 2'h0 is normal mode and 2'h3 is useful to YUV420(Legacy) - * when isp is bapassed. - */ - uint32_t byte_endian_order:1; - /** bit_endian_order : R/W; bitpos: [1]; default: 0; - * N/A - */ - uint32_t bit_endian_order:1; - uint32_t reserved_2:30; - }; - uint32_t val; -} csi_brg_endian_mode_reg_t; - - -/** Group: csi bridge interrupt registers. */ -/** Type of int_raw register - * csi bridge interrupt raw. - */ -typedef union { - struct { - /** vadr_num_gt_int_raw : R/WTC/SS; bitpos: [0]; default: 0; - * reg_vadr_num is greater than real interrupt raw. - */ - uint32_t vadr_num_gt_int_raw:1; - /** vadr_num_lt_int_raw : R/WTC/SS; bitpos: [1]; default: 0; - * reg_vadr_num is less than real interrupt raw. - */ - uint32_t vadr_num_lt_int_raw:1; - /** discard_int_raw : R/WTC/SS; bitpos: [2]; default: 0; - * an incomplete frame of data was sent interrupt raw. - */ - uint32_t discard_int_raw:1; - /** csi_buf_overrun_int_raw : R/WTC/SS; bitpos: [3]; default: 0; - * buffer overrun interrupt raw. - */ - uint32_t csi_buf_overrun_int_raw:1; - /** csi_async_fifo_ovf_int_raw : R/WTC/SS; bitpos: [4]; default: 0; - * buffer overflow interrupt raw. - */ - uint32_t csi_async_fifo_ovf_int_raw:1; - /** dma_cfg_has_updated_int_raw : R/WTC/SS; bitpos: [5]; default: 0; - * dma configuration update complete interrupt raw. - */ - uint32_t dma_cfg_has_updated_int_raw:1; - uint32_t reserved_6:26; - }; - uint32_t val; -} csi_brg_int_raw_reg_t; - -/** Type of int_clr register - * csi bridge interrupt clr. - */ -typedef union { - struct { - /** vadr_num_gt_real_int_clr : WT; bitpos: [0]; default: 0; - * reg_vadr_num is greater than real interrupt clr. - */ - uint32_t vadr_num_gt_real_int_clr:1; - /** vadr_num_lt_real_int_clr : WT; bitpos: [1]; default: 0; - * reg_vadr_num is less than real interrupt clr. - */ - uint32_t vadr_num_lt_real_int_clr:1; - /** discard_int_clr : WT; bitpos: [2]; default: 0; - * an incomplete frame of data was sent interrupt clr. - */ - uint32_t discard_int_clr:1; - /** csi_buf_overrun_int_clr : WT; bitpos: [3]; default: 0; - * buffer overrun interrupt clr. - */ - uint32_t csi_buf_overrun_int_clr:1; - /** csi_async_fifo_ovf_int_clr : WT; bitpos: [4]; default: 0; - * buffer overflow interrupt clr. - */ - uint32_t csi_async_fifo_ovf_int_clr:1; - /** dma_cfg_has_updated_int_clr : WT; bitpos: [5]; default: 0; - * dma configuration update complete interrupt clr. - */ - uint32_t dma_cfg_has_updated_int_clr:1; - uint32_t reserved_6:26; - }; - uint32_t val; -} csi_brg_int_clr_reg_t; - -/** Type of int_st register - * csi bridge interrupt st. - */ -typedef union { - struct { - /** vadr_num_gt_int_st : RO; bitpos: [0]; default: 0; - * reg_vadr_num is greater than real interrupt st. - */ - uint32_t vadr_num_gt_int_st:1; - /** vadr_num_lt_int_st : RO; bitpos: [1]; default: 0; - * reg_vadr_num is less than real interrupt st. - */ - uint32_t vadr_num_lt_int_st:1; - /** discard_int_st : RO; bitpos: [2]; default: 0; - * an incomplete frame of data was sent interrupt st. - */ - uint32_t discard_int_st:1; - /** csi_buf_overrun_int_st : RO; bitpos: [3]; default: 0; - * buffer overrun interrupt st. - */ - uint32_t csi_buf_overrun_int_st:1; - /** csi_async_fifo_ovf_int_st : RO; bitpos: [4]; default: 0; - * buffer overflow interrupt st. - */ - uint32_t csi_async_fifo_ovf_int_st:1; - /** dma_cfg_has_updated_int_st : RO; bitpos: [5]; default: 0; - * dma configuration update complete interrupt st. - */ - uint32_t dma_cfg_has_updated_int_st:1; - uint32_t reserved_6:26; - }; - uint32_t val; -} csi_brg_int_st_reg_t; - -/** Type of int_ena register - * csi bridge interrupt enable. - */ -typedef union { - struct { - /** vadr_num_gt_int_ena : R/W; bitpos: [0]; default: 0; - * reg_vadr_num is greater than real interrupt enable. - */ - uint32_t vadr_num_gt_int_ena:1; - /** vadr_num_lt_int_ena : R/W; bitpos: [1]; default: 0; - * reg_vadr_num is less than real interrupt enable. - */ - uint32_t vadr_num_lt_int_ena:1; - /** discard_int_ena : R/W; bitpos: [2]; default: 0; - * an incomplete frame of data was sent interrupt enable. - */ - uint32_t discard_int_ena:1; - /** csi_buf_overrun_int_ena : R/W; bitpos: [3]; default: 0; - * buffer overrun interrupt enable. - */ - uint32_t csi_buf_overrun_int_ena:1; - /** csi_async_fifo_ovf_int_ena : R/W; bitpos: [4]; default: 0; - * buffer overflow interrupt enable. - */ - uint32_t csi_async_fifo_ovf_int_ena:1; - /** dma_cfg_has_updated_int_ena : R/W; bitpos: [5]; default: 0; - * dma configuration update complete interrupt enable. - */ - uint32_t dma_cfg_has_updated_int_ena:1; - uint32_t reserved_6:26; - }; - uint32_t val; -} csi_brg_int_ena_reg_t; - - -/** Group: csi-host control registers from csi bridge regbank. */ -/** Type of host_ctrl register - * csi host control by csi bridge. - */ -typedef union { - struct { - /** csi_enableclk : R/W; bitpos: [0]; default: 1; - * enable clock lane module of csi phy. - */ - uint32_t csi_enableclk:1; - /** csi_cfg_clk_en : R/W; bitpos: [1]; default: 1; - * enable cfg_clk of csi host module. - */ - uint32_t csi_cfg_clk_en:1; - /** loopbk_test_en : R/W; bitpos: [2]; default: 0; - * for phy test by loopback dsi phy to csi phy. - */ - uint32_t loopbk_test_en:1; - uint32_t reserved_3:29; - }; - uint32_t val; -} csi_brg_host_ctrl_reg_t; - - -/** Group: csi host color mode control registers. */ -/** Type of host_cm_ctrl register - * CSI HOST color mode convert configuration. - */ -typedef union { - struct { - /** csi_host_cm_en : R/W; bitpos: [0]; default: 1; - * Configures whether to enable cm output - */ - uint32_t csi_host_cm_en:1; - /** csi_host_cm_bypass : R/W; bitpos: [1]; default: 1; - * Configures whether to bypass cm - */ - uint32_t csi_host_cm_bypass:1; - /** csi_host_cm_rx : R/W; bitpos: [3:2]; default: 0; - * Configures whether to bypass cm - */ - uint32_t csi_host_cm_rx:2; - /** csi_host_cm_rx_rgb_format : R/W; bitpos: [6:4]; default: 0; - * Configures whether to bypass cm - */ - uint32_t csi_host_cm_rx_rgb_format:3; - /** csi_host_cm_rx_yuv422_format : R/W; bitpos: [8:7]; default: 0; - * Configures whether to bypass cm - */ - uint32_t csi_host_cm_rx_yuv422_format:2; - /** csi_host_cm_tx : R/W; bitpos: [10:9]; default: 0; - * Configures whether to bypass cm - */ - uint32_t csi_host_cm_tx:2; - /** csi_host_cm_lane_num : R/W; bitpos: [11]; default: 1; - * Configures lane number that csi used, valid only rgb888 to rgb888. 0: 1-lane, 1: - * 2-lane - */ - uint32_t csi_host_cm_lane_num:1; - /** csi_host_cm_16bit_swap : R/W; bitpos: [12]; default: 0; - * Configures whether to swap idi32 high and low 16-bit - */ - uint32_t csi_host_cm_16bit_swap:1; - /** csi_host_cm_8bit_swap : R/W; bitpos: [13]; default: 0; - * Configures whether to swap idi32 high and low 8-bit - */ - uint32_t csi_host_cm_8bit_swap:1; - uint32_t reserved_14:18; - }; - uint32_t val; -} csi_brg_host_cm_ctrl_reg_t; - -/** Type of host_size_ctrl register - * CSI HOST color mode convert configuration. - */ -typedef union { - struct { - /** csi_host_cm_vnum : R/W; bitpos: [11:0]; default: 0; - * Configures idi32 image size in y-direction, row_num - 1, valid only when - * yuv422_to_yuv420_en = 1 - */ - uint32_t csi_host_cm_vnum:12; - /** csi_host_cm_hnum : R/W; bitpos: [23:12]; default: 0; - * Configures idi32 image size in x-direction, line_pix_num*bits_per_pix/32 - 1, valid - * only when yuv422_to_yuv420_en = 1 - */ - uint32_t csi_host_cm_hnum:12; - uint32_t reserved_24:8; - }; - uint32_t val; -} csi_brg_host_size_ctrl_reg_t; - - -typedef struct { - volatile csi_brg_clk_en_reg_t clk_en; - volatile csi_brg_csi_en_reg_t csi_en; - volatile csi_brg_dma_req_cfg_reg_t dma_req_cfg; - volatile csi_brg_buf_flow_ctl_reg_t buf_flow_ctl; - volatile csi_brg_data_type_cfg_reg_t data_type_cfg; - volatile csi_brg_frame_cfg_reg_t frame_cfg; - volatile csi_brg_endian_mode_reg_t endian_mode; - volatile csi_brg_int_raw_reg_t int_raw; - volatile csi_brg_int_clr_reg_t int_clr; - volatile csi_brg_int_st_reg_t int_st; - volatile csi_brg_int_ena_reg_t int_ena; - volatile csi_brg_dma_req_interval_reg_t dma_req_interval; - volatile csi_brg_dmablk_size_reg_t dmablk_size; - uint32_t reserved_034[3]; - volatile csi_brg_host_ctrl_reg_t host_ctrl; - uint32_t reserved_044; - volatile csi_brg_host_cm_ctrl_reg_t host_cm_ctrl; - volatile csi_brg_host_size_ctrl_reg_t host_size_ctrl; -} csi_brg_dev_t; - -extern csi_brg_dev_t MIPI_CSI_BRIDGE; - -#ifndef __cplusplus -_Static_assert(sizeof(csi_brg_dev_t) == 0x50, "Invalid size of csi_brg_dev_t structure"); -#endif - -#ifdef __cplusplus -} -#endif diff --git a/components/soc/esp32p4/register/hw_ver3/soc/mipi_csi_bridge_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/mipi_csi_bridge_struct.h index 20b393afdb..7856dd3740 100644 --- a/components/soc/esp32p4/register/hw_ver3/soc/mipi_csi_bridge_struct.h +++ b/components/soc/esp32p4/register/hw_ver3/soc/mipi_csi_bridge_struct.h @@ -36,7 +36,11 @@ typedef union { * 0: disable csi bridge. 1: enable csi bridge. */ uint32_t csi_brg_en:1; - uint32_t reserved_1:31; + /** csi_brg_rst : R/W; bitpos: [1]; default: 0; + * 0: release csi bridge reset. 1: enable csi bridge reset. + */ + uint32_t csi_brg_rst:1; + uint32_t reserved_2:30; }; uint32_t val; } csi_brg_csi_en_reg_t; @@ -81,7 +85,11 @@ typedef union { * 1: mask dma request when reading frame info. 0: disable mask. */ uint32_t dma_force_rd_status:1; - uint32_t reserved_17:15; + /** csi_dma_flow_controller : R/W; bitpos: [17]; default: 1; + * 0: dma as flow controller. 1: csi_bridge as flow controller + */ + uint32_t csi_dma_flow_controller:1; + uint32_t reserved_18:14; }; uint32_t val; } csi_brg_dma_req_cfg_reg_t; @@ -170,11 +178,11 @@ typedef union { * endianness order in bytes. 2'h0 is normal mode and 2'h3 is useful to YUV420(Legacy) * when isp is bapassed. */ - uint32_t byte_endian_order:1; //byte_swap_en + uint32_t byte_endian_order:1; /** bit_endian_order : R/W; bitpos: [1]; default: 0; * N/A */ - uint32_t bit_endian_order:1; //reserved + uint32_t bit_endian_order:1; uint32_t reserved_2:30; }; uint32_t val; @@ -343,6 +351,75 @@ typedef union { } csi_brg_host_ctrl_reg_t; +/** Group: csi host color mode control registers. */ +/** Type of host_cm_ctrl register + * CSI HOST color mode convert configuration. + */ +typedef union { + struct { + /** csi_host_cm_en : R/W; bitpos: [0]; default: 1; + * Configures whether to enable cm output + */ + uint32_t csi_host_cm_en:1; + /** csi_host_cm_bypass : R/W; bitpos: [1]; default: 1; + * Configures whether to bypass cm + */ + uint32_t csi_host_cm_bypass:1; + /** csi_host_cm_rx : R/W; bitpos: [3:2]; default: 0; + * Configures whether to bypass cm + */ + uint32_t csi_host_cm_rx:2; + /** csi_host_cm_rx_rgb_format : R/W; bitpos: [6:4]; default: 0; + * Configures whether to bypass cm + */ + uint32_t csi_host_cm_rx_rgb_format:3; + /** csi_host_cm_rx_yuv422_format : R/W; bitpos: [8:7]; default: 0; + * Configures whether to bypass cm + */ + uint32_t csi_host_cm_rx_yuv422_format:2; + /** csi_host_cm_tx : R/W; bitpos: [10:9]; default: 0; + * Configures whether to bypass cm + */ + uint32_t csi_host_cm_tx:2; + /** csi_host_cm_lane_num : R/W; bitpos: [11]; default: 1; + * Configures lane number that csi used, valid only rgb888 to rgb888. 0: 1-lane, 1: + * 2-lane + */ + uint32_t csi_host_cm_lane_num:1; + /** csi_host_cm_16bit_swap : R/W; bitpos: [12]; default: 0; + * Configures whether to swap idi32 high and low 16-bit + */ + uint32_t csi_host_cm_16bit_swap:1; + /** csi_host_cm_8bit_swap : R/W; bitpos: [13]; default: 0; + * Configures whether to swap idi32 high and low 8-bit + */ + uint32_t csi_host_cm_8bit_swap:1; + uint32_t reserved_14:18; + }; + uint32_t val; +} csi_brg_host_cm_ctrl_reg_t; + +/** Type of host_size_ctrl register + * CSI HOST color mode convert configuration. + */ +typedef union { + struct { + /** csi_host_cm_vnum : R/W; bitpos: [11:0]; default: 0; + * Configures idi32 image size in y-direction, row_num - 1, valid only when + * yuv422_to_yuv420_en = 1 + */ + uint32_t csi_host_cm_vnum:12; + /** csi_host_cm_hnum : R/W; bitpos: [23:12]; default: 0; + * Configures idi32 image size in x-direction, line_pix_num*bits_per_pix/32 - 1, valid + * only when yuv422_to_yuv420_en = 1 + */ + uint32_t csi_host_cm_hnum:12; + uint32_t reserved_24:8; + }; + uint32_t val; +} csi_brg_host_size_ctrl_reg_t; + + typedef struct csi_brg_dev_t { volatile csi_brg_clk_en_reg_t clk_en; volatile csi_brg_csi_en_reg_t csi_en; @@ -359,12 +436,15 @@ typedef struct csi_brg_dev_t { volatile csi_brg_dmablk_size_reg_t dmablk_size; uint32_t reserved_034[3]; volatile csi_brg_host_ctrl_reg_t host_ctrl; + uint32_t reserved_044; + volatile csi_brg_host_cm_ctrl_reg_t host_cm_ctrl; + volatile csi_brg_host_size_ctrl_reg_t host_size_ctrl; } csi_brg_dev_t; extern csi_brg_dev_t MIPI_CSI_BRIDGE; #ifndef __cplusplus -_Static_assert(sizeof(csi_brg_dev_t) == 0x44, "Invalid size of csi_brg_dev_t structure"); +_Static_assert(sizeof(csi_brg_dev_t) == 0x50, "Invalid size of csi_brg_dev_t structure"); #endif #ifdef __cplusplus diff --git a/components/soc/esp32p4/register/hw_ver3/soc/mipi_csi_host_eco5_struct.h b/components/soc/esp32p4/register/hw_ver3/soc/mipi_csi_host_eco5_struct.h deleted file mode 100644 index 1c4ade584f..0000000000 --- a/components/soc/esp32p4/register/hw_ver3/soc/mipi_csi_host_eco5_struct.h +++ /dev/null @@ -1,1883 +0,0 @@ -/** - * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD - * - * SPDX-License-Identifier: Apache-2.0 - */ -#pragma once - -#include -#ifdef __cplusplus -extern "C" { -#endif - -/** Group: Version Register */ -/** Type of version register - * NA - */ -typedef union { - struct { - /** version : RO; bitpos: [31:0]; default: 825569322; - * NA - */ - uint32_t version:32; - }; - uint32_t val; -} csi_host_version_reg_t; - - -/** Group: Configuration Registers */ -/** Type of n_lanes register - * NA - */ -typedef union { - struct { - /** n_lanes : R/W; bitpos: [2:0]; default: 1; - * NA - */ - uint32_t n_lanes:3; - uint32_t reserved_3:29; - }; - uint32_t val; -} csi_host_n_lanes_reg_t; - -/** Type of csi2_resetn register - * NA - */ -typedef union { - struct { - /** csi2_resetn : R/W; bitpos: [0]; default: 0; - * NA - */ - uint32_t csi2_resetn:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} csi_host_csi2_resetn_reg_t; - -/** Type of phy_shutdownz register - * NA - */ -typedef union { - struct { - /** phy_shutdownz : R/W; bitpos: [0]; default: 0; - * NA - */ - uint32_t phy_shutdownz:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} csi_host_phy_shutdownz_reg_t; - -/** Type of dphy_rstz register - * NA - */ -typedef union { - struct { - /** dphy_rstz : R/W; bitpos: [0]; default: 0; - * NA - */ - uint32_t dphy_rstz:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} csi_host_dphy_rstz_reg_t; - -/** Type of phy_rx register - * NA - */ -typedef union { - struct { - /** phy_rxulpsesc_0 : RO; bitpos: [0]; default: 0; - * NA - */ - uint32_t phy_rxulpsesc_0:1; - /** phy_rxulpsesc_1 : RO; bitpos: [1]; default: 0; - * NA - */ - uint32_t phy_rxulpsesc_1:1; - uint32_t reserved_2:14; - /** phy_rxulpsclknot : RO; bitpos: [16]; default: 1; - * NA - */ - uint32_t phy_rxulpsclknot:1; - /** phy_rxclkactivehs : RO; bitpos: [17]; default: 0; - * NA - */ - uint32_t phy_rxclkactivehs:1; - uint32_t reserved_18:14; - }; - uint32_t val; -} csi_host_phy_rx_reg_t; - -/** Type of phy_test_ctrl0 register - * NA - */ -typedef union { - struct { - /** phy_testclr : R/W; bitpos: [0]; default: 1; - * NA - */ - uint32_t phy_testclr:1; - /** phy_testclk : R/W; bitpos: [1]; default: 0; - * NA - */ - uint32_t phy_testclk:1; - uint32_t reserved_2:30; - }; - uint32_t val; -} csi_host_phy_test_ctrl0_reg_t; - -/** Type of phy_test_ctrl1 register - * NA - */ -typedef union { - struct { - /** phy_testdin : R/W; bitpos: [7:0]; default: 0; - * NA - */ - uint32_t phy_testdin:8; - /** phy_testdout : RO; bitpos: [15:8]; default: 0; - * NA - */ - uint32_t phy_testdout:8; - /** phy_testen : R/W; bitpos: [16]; default: 0; - * NA - */ - uint32_t phy_testen:1; - uint32_t reserved_17:15; - }; - uint32_t val; -} csi_host_phy_test_ctrl1_reg_t; - -/** Type of vc_extension register - * NA - */ -typedef union { - struct { - /** vcx : R/W; bitpos: [0]; default: 0; - * NA - */ - uint32_t vcx:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} csi_host_vc_extension_reg_t; - -/** Type of phy_cal register - * NA - */ -typedef union { - struct { - /** rxskewcalhs : RC; bitpos: [0]; default: 0; - * NA - */ - uint32_t rxskewcalhs:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} csi_host_phy_cal_reg_t; - -/** Type of scrambling register - * NA - */ -typedef union { - struct { - /** scramble_enable : R/W; bitpos: [0]; default: 0; - * NA - */ - uint32_t scramble_enable:1; - uint32_t reserved_1:31; - }; - uint32_t val; -} csi_host_scrambling_reg_t; - -/** Type of scrambling_seed1 register - * NA - */ -typedef union { - struct { - /** scramble_seed_lane1 : R/W; bitpos: [15:0]; default: 4104; - * NA - */ - uint32_t scramble_seed_lane1:16; - uint32_t reserved_16:16; - }; - uint32_t val; -} csi_host_scrambling_seed1_reg_t; - -/** Type of scrambling_seed2 register - * NA - */ -typedef union { - struct { - /** scramble_seed_lane2 : R/W; bitpos: [15:0]; default: 4488; - * NA - */ - uint32_t scramble_seed_lane2:16; - uint32_t reserved_16:16; - }; - uint32_t val; -} csi_host_scrambling_seed2_reg_t; - - -/** Group: Interrupt Registers */ -/** Type of int_st_main register - * NA - */ -typedef union { - struct { - /** st_status_int_phy_fatal : RC; bitpos: [0]; default: 0; - * NA - */ - uint32_t st_status_int_phy_fatal:1; - /** st_status_int_pkt_fatal : RC; bitpos: [1]; default: 0; - * NA - */ - uint32_t st_status_int_pkt_fatal:1; - /** st_status_int_bndry_frame_fatal : RC; bitpos: [2]; default: 0; - * NA - */ - uint32_t st_status_int_bndry_frame_fatal:1; - /** st_status_int_seq_frame_fatal : RC; bitpos: [3]; default: 0; - * NA - */ - uint32_t st_status_int_seq_frame_fatal:1; - /** st_status_int_crc_frame_fatal : RC; bitpos: [4]; default: 0; - * NA - */ - uint32_t st_status_int_crc_frame_fatal:1; - /** st_status_int_pld_crc_fatal : RC; bitpos: [5]; default: 0; - * NA - */ - uint32_t st_status_int_pld_crc_fatal:1; - /** st_status_int_data_id : RC; bitpos: [6]; default: 0; - * NA - */ - uint32_t st_status_int_data_id:1; - /** st_status_int_ecc_corrected : RC; bitpos: [7]; default: 0; - * NA - */ - uint32_t st_status_int_ecc_corrected:1; - uint32_t reserved_8:8; - /** st_status_int_phy : RC; bitpos: [16]; default: 0; - * NA - */ - uint32_t st_status_int_phy:1; - uint32_t reserved_17:15; - }; - uint32_t val; -} csi_host_int_st_main_reg_t; - -/** Type of int_st_phy_fatal register - * NA - */ -typedef union { - struct { - /** st_phy_errsotsynchs_0 : RC; bitpos: [0]; default: 0; - * NA - */ - uint32_t st_phy_errsotsynchs_0:1; - /** st_phy_errsotsynchs_1 : RC; bitpos: [1]; default: 0; - * NA - */ - uint32_t st_phy_errsotsynchs_1:1; - uint32_t reserved_2:30; - }; - uint32_t val; -} csi_host_int_st_phy_fatal_reg_t; - -/** Type of int_msk_phy_fatal register - * NA - */ -typedef union { - struct { - /** mask_phy_errsotsynchs_0 : R/W; bitpos: [0]; default: 0; - * NA - */ - uint32_t mask_phy_errsotsynchs_0:1; - /** mask_phy_errsotsynchs_1 : R/W; bitpos: [1]; default: 0; - * NA - */ - uint32_t mask_phy_errsotsynchs_1:1; - uint32_t reserved_2:30; - }; - uint32_t val; -} csi_host_int_msk_phy_fatal_reg_t; - -/** Type of int_force_phy_fatal register - * NA - */ -typedef union { - struct { - /** force_phy_errsotsynchs_0 : R/W; bitpos: [0]; default: 0; - * NA - */ - uint32_t force_phy_errsotsynchs_0:1; - /** force_phy_errsotsynchs_1 : R/W; bitpos: [1]; default: 0; - * NA - */ - uint32_t force_phy_errsotsynchs_1:1; - uint32_t reserved_2:30; - }; - uint32_t val; -} csi_host_int_force_phy_fatal_reg_t; - -/** Type of int_st_pkt_fatal register - * NA - */ -typedef union { - struct { - /** st_err_ecc_double : RC; bitpos: [0]; default: 0; - * NA - */ - uint32_t st_err_ecc_double:1; - /** st_shorter_payload : RC; bitpos: [1]; default: 0; - * NA - */ - uint32_t st_shorter_payload:1; - uint32_t reserved_2:30; - }; - uint32_t val; -} csi_host_int_st_pkt_fatal_reg_t; - -/** Type of int_msk_pkt_fatal register - * NA - */ -typedef union { - struct { - /** mask_err_ecc_double : R/W; bitpos: [0]; default: 0; - * NA - */ - uint32_t mask_err_ecc_double:1; - /** mask_shorter_payload : R/W; bitpos: [1]; default: 0; - * NA - */ - uint32_t mask_shorter_payload:1; - uint32_t reserved_2:30; - }; - uint32_t val; -} csi_host_int_msk_pkt_fatal_reg_t; - -/** Type of int_force_pkt_fatal register - * NA - */ -typedef union { - struct { - /** force_err_ecc_double : R/W; bitpos: [0]; default: 0; - * NA - */ - uint32_t force_err_ecc_double:1; - /** force_shorter_payload : R/W; bitpos: [1]; default: 0; - * NA - */ - uint32_t force_shorter_payload:1; - uint32_t reserved_2:30; - }; - uint32_t val; -} csi_host_int_force_pkt_fatal_reg_t; - -/** Type of int_st_phy register - * NA - */ -typedef union { - struct { - /** st_phy_errsoths_0 : RC; bitpos: [0]; default: 0; - * NA - */ - uint32_t st_phy_errsoths_0:1; - /** st_phy_errsoths_1 : RC; bitpos: [1]; default: 0; - * NA - */ - uint32_t st_phy_errsoths_1:1; - uint32_t reserved_2:14; - /** st_phy_erresc_0 : RC; bitpos: [16]; default: 0; - * NA - */ - uint32_t st_phy_erresc_0:1; - /** st_phy_erresc_1 : RC; bitpos: [17]; default: 0; - * NA - */ - uint32_t st_phy_erresc_1:1; - uint32_t reserved_18:14; - }; - uint32_t val; -} csi_host_int_st_phy_reg_t; - -/** Type of int_msk_phy register - * NA - */ -typedef union { - struct { - /** mask_phy_errsoths_0 : R/W; bitpos: [0]; default: 0; - * NA - */ - uint32_t mask_phy_errsoths_0:1; - /** mask_phy_errsoths_1 : R/W; bitpos: [1]; default: 0; - * NA - */ - uint32_t mask_phy_errsoths_1:1; - uint32_t reserved_2:14; - /** mask_phy_erresc_0 : R/W; bitpos: [16]; default: 0; - * NA - */ - uint32_t mask_phy_erresc_0:1; - /** mask_phy_erresc_1 : R/W; bitpos: [17]; default: 0; - * NA - */ - uint32_t mask_phy_erresc_1:1; - uint32_t reserved_18:14; - }; - uint32_t val; -} csi_host_int_msk_phy_reg_t; - -/** Type of int_force_phy register - * NA - */ -typedef union { - struct { - /** force_phy_errsoths_0 : R/W; bitpos: [0]; default: 0; - * NA - */ - uint32_t force_phy_errsoths_0:1; - /** force_phy_errsoths_1 : R/W; bitpos: [1]; default: 0; - * NA - */ - uint32_t force_phy_errsoths_1:1; - uint32_t reserved_2:14; - /** force_phy_erresc_0 : R/W; bitpos: [16]; default: 0; - * NA - */ - uint32_t force_phy_erresc_0:1; - /** force_phy_erresc_1 : R/W; bitpos: [17]; default: 0; - * NA - */ - uint32_t force_phy_erresc_1:1; - uint32_t reserved_18:14; - }; - uint32_t val; -} csi_host_int_force_phy_reg_t; - -/** Type of int_st_bndry_frame_fatal register - * NA - */ -typedef union { - struct { - /** st_err_f_bndry_match_vc0 : RC; bitpos: [0]; default: 0; - * NA - */ - uint32_t st_err_f_bndry_match_vc0:1; - /** st_err_f_bndry_match_vc1 : RC; bitpos: [1]; default: 0; - * NA - */ - uint32_t st_err_f_bndry_match_vc1:1; - /** st_err_f_bndry_match_vc2 : RC; bitpos: [2]; default: 0; - * NA - */ - uint32_t st_err_f_bndry_match_vc2:1; - /** st_err_f_bndry_match_vc3 : RC; bitpos: [3]; default: 0; - * NA - */ - uint32_t st_err_f_bndry_match_vc3:1; - /** st_err_f_bndry_match_vc4 : RC; bitpos: [4]; default: 0; - * NA - */ - uint32_t st_err_f_bndry_match_vc4:1; - /** st_err_f_bndry_match_vc5 : RC; bitpos: [5]; default: 0; - * NA - */ - uint32_t st_err_f_bndry_match_vc5:1; - /** st_err_f_bndry_match_vc6 : RC; bitpos: [6]; default: 0; - * NA - */ - uint32_t st_err_f_bndry_match_vc6:1; - /** st_err_f_bndry_match_vc7 : RC; bitpos: [7]; default: 0; - * NA - */ - uint32_t st_err_f_bndry_match_vc7:1; - /** st_err_f_bndry_match_vc8 : RC; bitpos: [8]; default: 0; - * NA - */ - uint32_t st_err_f_bndry_match_vc8:1; - /** st_err_f_bndry_match_vc9 : RC; bitpos: [9]; default: 0; - * NA - */ - uint32_t st_err_f_bndry_match_vc9:1; - /** st_err_f_bndry_match_vc10 : RC; bitpos: [10]; default: 0; - * NA - */ - uint32_t st_err_f_bndry_match_vc10:1; - /** st_err_f_bndry_match_vc11 : RC; bitpos: [11]; default: 0; - * NA - */ - uint32_t st_err_f_bndry_match_vc11:1; - /** st_err_f_bndry_match_vc12 : RC; bitpos: [12]; default: 0; - * NA - */ - uint32_t st_err_f_bndry_match_vc12:1; - /** st_err_f_bndry_match_vc13 : RC; bitpos: [13]; default: 0; - * NA - */ - uint32_t st_err_f_bndry_match_vc13:1; - /** st_err_f_bndry_match_vc14 : RC; bitpos: [14]; default: 0; - * NA - */ - uint32_t st_err_f_bndry_match_vc14:1; - /** st_err_f_bndry_match_vc15 : RC; bitpos: [15]; default: 0; - * NA - */ - uint32_t st_err_f_bndry_match_vc15:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} csi_host_int_st_bndry_frame_fatal_reg_t; - -/** Type of int_msk_bndry_frame_fatal register - * NA - */ -typedef union { - struct { - /** mask_err_f_bndry_match_vc0 : R/W; bitpos: [0]; default: 0; - * NA - */ - uint32_t mask_err_f_bndry_match_vc0:1; - /** mask_err_f_bndry_match_vc1 : R/W; bitpos: [1]; default: 0; - * NA - */ - uint32_t mask_err_f_bndry_match_vc1:1; - /** mask_err_f_bndry_match_vc2 : R/W; bitpos: [2]; default: 0; - * NA - */ - uint32_t mask_err_f_bndry_match_vc2:1; - /** mask_err_f_bndry_match_vc3 : R/W; bitpos: [3]; default: 0; - * NA - */ - uint32_t mask_err_f_bndry_match_vc3:1; - /** mask_err_f_bndry_match_vc4 : R/W; bitpos: [4]; default: 0; - * NA - */ - uint32_t mask_err_f_bndry_match_vc4:1; - /** mask_err_f_bndry_match_vc5 : R/W; bitpos: [5]; default: 0; - * NA - */ - uint32_t mask_err_f_bndry_match_vc5:1; - /** mask_err_f_bndry_match_vc6 : R/W; bitpos: [6]; default: 0; - * NA - */ - uint32_t mask_err_f_bndry_match_vc6:1; - /** mask_err_f_bndry_match_vc7 : R/W; bitpos: [7]; default: 0; - * NA - */ - uint32_t mask_err_f_bndry_match_vc7:1; - /** mask_err_f_bndry_match_vc8 : R/W; bitpos: [8]; default: 0; - * NA - */ - uint32_t mask_err_f_bndry_match_vc8:1; - /** mask_err_f_bndry_match_vc9 : R/W; bitpos: [9]; default: 0; - * NA - */ - uint32_t mask_err_f_bndry_match_vc9:1; - /** mask_err_f_bndry_match_vc10 : R/W; bitpos: [10]; default: 0; - * NA - */ - uint32_t mask_err_f_bndry_match_vc10:1; - /** mask_err_f_bndry_match_vc11 : R/W; bitpos: [11]; default: 0; - * NA - */ - uint32_t mask_err_f_bndry_match_vc11:1; - /** mask_err_f_bndry_match_vc12 : R/W; bitpos: [12]; default: 0; - * NA - */ - uint32_t mask_err_f_bndry_match_vc12:1; - /** mask_err_f_bndry_match_vc13 : R/W; bitpos: [13]; default: 0; - * NA - */ - uint32_t mask_err_f_bndry_match_vc13:1; - /** mask_err_f_bndry_match_vc14 : R/W; bitpos: [14]; default: 0; - * NA - */ - uint32_t mask_err_f_bndry_match_vc14:1; - /** mask_err_f_bndry_match_vc15 : R/W; bitpos: [15]; default: 0; - * NA - */ - uint32_t mask_err_f_bndry_match_vc15:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} csi_host_int_msk_bndry_frame_fatal_reg_t; - -/** Type of int_force_bndry_frame_fatal register - * NA - */ -typedef union { - struct { - /** force_err_f_bndry_match_vc0 : R/W; bitpos: [0]; default: 0; - * NA - */ - uint32_t force_err_f_bndry_match_vc0:1; - /** force_err_f_bndry_match_vc1 : R/W; bitpos: [1]; default: 0; - * NA - */ - uint32_t force_err_f_bndry_match_vc1:1; - /** force_err_f_bndry_match_vc2 : R/W; bitpos: [2]; default: 0; - * NA - */ - uint32_t force_err_f_bndry_match_vc2:1; - /** force_err_f_bndry_match_vc3 : R/W; bitpos: [3]; default: 0; - * NA - */ - uint32_t force_err_f_bndry_match_vc3:1; - /** force_err_f_bndry_match_vc4 : R/W; bitpos: [4]; default: 0; - * NA - */ - uint32_t force_err_f_bndry_match_vc4:1; - /** force_err_f_bndry_match_vc5 : R/W; bitpos: [5]; default: 0; - * NA - */ - uint32_t force_err_f_bndry_match_vc5:1; - /** force_err_f_bndry_match_vc6 : R/W; bitpos: [6]; default: 0; - * NA - */ - uint32_t force_err_f_bndry_match_vc6:1; - /** force_err_f_bndry_match_vc7 : R/W; bitpos: [7]; default: 0; - * NA - */ - uint32_t force_err_f_bndry_match_vc7:1; - /** force_err_f_bndry_match_vc8 : R/W; bitpos: [8]; default: 0; - * NA - */ - uint32_t force_err_f_bndry_match_vc8:1; - /** force_err_f_bndry_match_vc9 : R/W; bitpos: [9]; default: 0; - * NA - */ - uint32_t force_err_f_bndry_match_vc9:1; - /** force_err_f_bndry_match_vc10 : R/W; bitpos: [10]; default: 0; - * NA - */ - uint32_t force_err_f_bndry_match_vc10:1; - /** force_err_f_bndry_match_vc11 : R/W; bitpos: [11]; default: 0; - * NA - */ - uint32_t force_err_f_bndry_match_vc11:1; - /** force_err_f_bndry_match_vc12 : R/W; bitpos: [12]; default: 0; - * NA - */ - uint32_t force_err_f_bndry_match_vc12:1; - /** force_err_f_bndry_match_vc13 : R/W; bitpos: [13]; default: 0; - * NA - */ - uint32_t force_err_f_bndry_match_vc13:1; - /** force_err_f_bndry_match_vc14 : R/W; bitpos: [14]; default: 0; - * NA - */ - uint32_t force_err_f_bndry_match_vc14:1; - /** force_err_f_bndry_match_vc15 : R/W; bitpos: [15]; default: 0; - * NA - */ - uint32_t force_err_f_bndry_match_vc15:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} csi_host_int_force_bndry_frame_fatal_reg_t; - -/** Type of int_st_seq_frame_fatal register - * NA - */ -typedef union { - struct { - /** st_err_f_seq_vc0 : RC; bitpos: [0]; default: 0; - * NA - */ - uint32_t st_err_f_seq_vc0:1; - /** st_err_f_seq_vc1 : RC; bitpos: [1]; default: 0; - * NA - */ - uint32_t st_err_f_seq_vc1:1; - /** st_err_f_seq_vc2 : RC; bitpos: [2]; default: 0; - * NA - */ - uint32_t st_err_f_seq_vc2:1; - /** st_err_f_seq_vc3 : RC; bitpos: [3]; default: 0; - * NA - */ - uint32_t st_err_f_seq_vc3:1; - /** st_err_f_seq_vc4 : RC; bitpos: [4]; default: 0; - * NA - */ - uint32_t st_err_f_seq_vc4:1; - /** st_err_f_seq_vc5 : RC; bitpos: [5]; default: 0; - * NA - */ - uint32_t st_err_f_seq_vc5:1; - /** st_err_f_seq_vc6 : RC; bitpos: [6]; default: 0; - * NA - */ - uint32_t st_err_f_seq_vc6:1; - /** st_err_f_seq_vc7 : RC; bitpos: [7]; default: 0; - * NA - */ - uint32_t st_err_f_seq_vc7:1; - /** st_err_f_seq_vc8 : RC; bitpos: [8]; default: 0; - * NA - */ - uint32_t st_err_f_seq_vc8:1; - /** st_err_f_seq_vc9 : RC; bitpos: [9]; default: 0; - * NA - */ - uint32_t st_err_f_seq_vc9:1; - /** st_err_f_seq_vc10 : RC; bitpos: [10]; default: 0; - * NA - */ - uint32_t st_err_f_seq_vc10:1; - /** st_err_f_seq_vc11 : RC; bitpos: [11]; default: 0; - * NA - */ - uint32_t st_err_f_seq_vc11:1; - /** st_err_f_seq_vc12 : RC; bitpos: [12]; default: 0; - * NA - */ - uint32_t st_err_f_seq_vc12:1; - /** st_err_f_seq_vc13 : RC; bitpos: [13]; default: 0; - * NA - */ - uint32_t st_err_f_seq_vc13:1; - /** st_err_f_seq_vc14 : RC; bitpos: [14]; default: 0; - * NA - */ - uint32_t st_err_f_seq_vc14:1; - /** st_err_f_seq_vc15 : RC; bitpos: [15]; default: 0; - * NA - */ - uint32_t st_err_f_seq_vc15:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} csi_host_int_st_seq_frame_fatal_reg_t; - -/** Type of int_msk_seq_frame_fatal register - * NA - */ -typedef union { - struct { - /** mask_err_f_seq_vc0 : R/W; bitpos: [0]; default: 0; - * NA - */ - uint32_t mask_err_f_seq_vc0:1; - /** mask_err_f_seq_vc1 : R/W; bitpos: [1]; default: 0; - * NA - */ - uint32_t mask_err_f_seq_vc1:1; - /** mask_err_f_seq_vc2 : R/W; bitpos: [2]; default: 0; - * NA - */ - uint32_t mask_err_f_seq_vc2:1; - /** mask_err_f_seq_vc3 : R/W; bitpos: [3]; default: 0; - * NA - */ - uint32_t mask_err_f_seq_vc3:1; - /** mask_err_f_seq_vc4 : R/W; bitpos: [4]; default: 0; - * NA - */ - uint32_t mask_err_f_seq_vc4:1; - /** mask_err_f_seq_vc5 : R/W; bitpos: [5]; default: 0; - * NA - */ - uint32_t mask_err_f_seq_vc5:1; - /** mask_err_f_seq_vc6 : R/W; bitpos: [6]; default: 0; - * NA - */ - uint32_t mask_err_f_seq_vc6:1; - /** mask_err_f_seq_vc7 : R/W; bitpos: [7]; default: 0; - * NA - */ - uint32_t mask_err_f_seq_vc7:1; - /** mask_err_f_seq_vc8 : R/W; bitpos: [8]; default: 0; - * NA - */ - uint32_t mask_err_f_seq_vc8:1; - /** mask_err_f_seq_vc9 : R/W; bitpos: [9]; default: 0; - * NA - */ - uint32_t mask_err_f_seq_vc9:1; - /** mask_err_f_seq_vc10 : R/W; bitpos: [10]; default: 0; - * NA - */ - uint32_t mask_err_f_seq_vc10:1; - /** mask_err_f_seq_vc11 : R/W; bitpos: [11]; default: 0; - * NA - */ - uint32_t mask_err_f_seq_vc11:1; - /** mask_err_f_seq_vc12 : R/W; bitpos: [12]; default: 0; - * NA - */ - uint32_t mask_err_f_seq_vc12:1; - /** mask_err_f_seq_vc13 : R/W; bitpos: [13]; default: 0; - * NA - */ - uint32_t mask_err_f_seq_vc13:1; - /** mask_err_f_seq_vc14 : R/W; bitpos: [14]; default: 0; - * NA - */ - uint32_t mask_err_f_seq_vc14:1; - /** mask_err_f_seq_vc15 : R/W; bitpos: [15]; default: 0; - * NA - */ - uint32_t mask_err_f_seq_vc15:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} csi_host_int_msk_seq_frame_fatal_reg_t; - -/** Type of int_force_seq_frame_fatal register - * NA - */ -typedef union { - struct { - /** force_err_f_seq_vc0 : R/W; bitpos: [0]; default: 0; - * NA - */ - uint32_t force_err_f_seq_vc0:1; - /** force_err_f_seq_vc1 : R/W; bitpos: [1]; default: 0; - * NA - */ - uint32_t force_err_f_seq_vc1:1; - /** force_err_f_seq_vc2 : R/W; bitpos: [2]; default: 0; - * NA - */ - uint32_t force_err_f_seq_vc2:1; - /** force_err_f_seq_vc3 : R/W; bitpos: [3]; default: 0; - * NA - */ - uint32_t force_err_f_seq_vc3:1; - /** force_err_f_seq_vc4 : R/W; bitpos: [4]; default: 0; - * NA - */ - uint32_t force_err_f_seq_vc4:1; - /** force_err_f_seq_vc5 : R/W; bitpos: [5]; default: 0; - * NA - */ - uint32_t force_err_f_seq_vc5:1; - /** force_err_f_seq_vc6 : R/W; bitpos: [6]; default: 0; - * NA - */ - uint32_t force_err_f_seq_vc6:1; - /** force_err_f_seq_vc7 : R/W; bitpos: [7]; default: 0; - * NA - */ - uint32_t force_err_f_seq_vc7:1; - /** force_err_f_seq_vc8 : R/W; bitpos: [8]; default: 0; - * NA - */ - uint32_t force_err_f_seq_vc8:1; - /** force_err_f_seq_vc9 : R/W; bitpos: [9]; default: 0; - * NA - */ - uint32_t force_err_f_seq_vc9:1; - /** force_err_f_seq_vc10 : R/W; bitpos: [10]; default: 0; - * NA - */ - uint32_t force_err_f_seq_vc10:1; - /** force_err_f_seq_vc11 : R/W; bitpos: [11]; default: 0; - * NA - */ - uint32_t force_err_f_seq_vc11:1; - /** force_err_f_seq_vc12 : R/W; bitpos: [12]; default: 0; - * NA - */ - uint32_t force_err_f_seq_vc12:1; - /** force_err_f_seq_vc13 : R/W; bitpos: [13]; default: 0; - * NA - */ - uint32_t force_err_f_seq_vc13:1; - /** force_err_f_seq_vc14 : R/W; bitpos: [14]; default: 0; - * NA - */ - uint32_t force_err_f_seq_vc14:1; - /** force_err_f_seq_vc15 : R/W; bitpos: [15]; default: 0; - * NA - */ - uint32_t force_err_f_seq_vc15:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} csi_host_int_force_seq_frame_fatal_reg_t; - -/** Type of int_st_crc_frame_fatal register - * NA - */ -typedef union { - struct { - /** st_err_frame_data_vc0 : RC; bitpos: [0]; default: 0; - * NA - */ - uint32_t st_err_frame_data_vc0:1; - /** st_err_frame_data_vc1 : RC; bitpos: [1]; default: 0; - * NA - */ - uint32_t st_err_frame_data_vc1:1; - /** st_err_frame_data_vc2 : RC; bitpos: [2]; default: 0; - * NA - */ - uint32_t st_err_frame_data_vc2:1; - /** st_err_frame_data_vc3 : RC; bitpos: [3]; default: 0; - * NA - */ - uint32_t st_err_frame_data_vc3:1; - /** st_err_frame_data_vc4 : RC; bitpos: [4]; default: 0; - * NA - */ - uint32_t st_err_frame_data_vc4:1; - /** st_err_frame_data_vc5 : RC; bitpos: [5]; default: 0; - * NA - */ - uint32_t st_err_frame_data_vc5:1; - /** st_err_frame_data_vc6 : RC; bitpos: [6]; default: 0; - * NA - */ - uint32_t st_err_frame_data_vc6:1; - /** st_err_frame_data_vc7 : RC; bitpos: [7]; default: 0; - * NA - */ - uint32_t st_err_frame_data_vc7:1; - /** st_err_frame_data_vc8 : RC; bitpos: [8]; default: 0; - * NA - */ - uint32_t st_err_frame_data_vc8:1; - /** st_err_frame_data_vc9 : RC; bitpos: [9]; default: 0; - * NA - */ - uint32_t st_err_frame_data_vc9:1; - /** st_err_frame_data_vc10 : RC; bitpos: [10]; default: 0; - * NA - */ - uint32_t st_err_frame_data_vc10:1; - /** st_err_frame_data_vc11 : RC; bitpos: [11]; default: 0; - * NA - */ - uint32_t st_err_frame_data_vc11:1; - /** st_err_frame_data_vc12 : RC; bitpos: [12]; default: 0; - * NA - */ - uint32_t st_err_frame_data_vc12:1; - /** st_err_frame_data_vc13 : RC; bitpos: [13]; default: 0; - * NA - */ - uint32_t st_err_frame_data_vc13:1; - /** st_err_frame_data_vc14 : RC; bitpos: [14]; default: 0; - * NA - */ - uint32_t st_err_frame_data_vc14:1; - /** st_err_frame_data_vc15 : RC; bitpos: [15]; default: 0; - * NA - */ - uint32_t st_err_frame_data_vc15:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} csi_host_int_st_crc_frame_fatal_reg_t; - -/** Type of int_msk_crc_frame_fatal register - * NA - */ -typedef union { - struct { - /** mask_err_frame_data_vc0 : R/W; bitpos: [0]; default: 0; - * NA - */ - uint32_t mask_err_frame_data_vc0:1; - /** mask_err_frame_data_vc1 : R/W; bitpos: [1]; default: 0; - * NA - */ - uint32_t mask_err_frame_data_vc1:1; - /** mask_err_frame_data_vc2 : R/W; bitpos: [2]; default: 0; - * NA - */ - uint32_t mask_err_frame_data_vc2:1; - /** mask_err_frame_data_vc3 : R/W; bitpos: [3]; default: 0; - * NA - */ - uint32_t mask_err_frame_data_vc3:1; - /** mask_err_frame_data_vc4 : R/W; bitpos: [4]; default: 0; - * NA - */ - uint32_t mask_err_frame_data_vc4:1; - /** mask_err_frame_data_vc5 : R/W; bitpos: [5]; default: 0; - * NA - */ - uint32_t mask_err_frame_data_vc5:1; - /** mask_err_frame_data_vc6 : R/W; bitpos: [6]; default: 0; - * NA - */ - uint32_t mask_err_frame_data_vc6:1; - /** mask_err_frame_data_vc7 : R/W; bitpos: [7]; default: 0; - * NA - */ - uint32_t mask_err_frame_data_vc7:1; - /** mask_err_frame_data_vc8 : R/W; bitpos: [8]; default: 0; - * NA - */ - uint32_t mask_err_frame_data_vc8:1; - /** mask_err_frame_data_vc9 : R/W; bitpos: [9]; default: 0; - * NA - */ - uint32_t mask_err_frame_data_vc9:1; - /** mask_err_frame_data_vc10 : R/W; bitpos: [10]; default: 0; - * NA - */ - uint32_t mask_err_frame_data_vc10:1; - /** mask_err_frame_data_vc11 : R/W; bitpos: [11]; default: 0; - * NA - */ - uint32_t mask_err_frame_data_vc11:1; - /** mask_err_frame_data_vc12 : R/W; bitpos: [12]; default: 0; - * NA - */ - uint32_t mask_err_frame_data_vc12:1; - /** mask_err_frame_data_vc13 : R/W; bitpos: [13]; default: 0; - * NA - */ - uint32_t mask_err_frame_data_vc13:1; - /** mask_err_frame_data_vc14 : R/W; bitpos: [14]; default: 0; - * NA - */ - uint32_t mask_err_frame_data_vc14:1; - /** mask_err_frame_data_vc15 : R/W; bitpos: [15]; default: 0; - * NA - */ - uint32_t mask_err_frame_data_vc15:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} csi_host_int_msk_crc_frame_fatal_reg_t; - -/** Type of int_force_crc_frame_fatal register - * NA - */ -typedef union { - struct { - /** force_err_frame_data_vc0 : R/W; bitpos: [0]; default: 0; - * NA - */ - uint32_t force_err_frame_data_vc0:1; - /** force_err_frame_data_vc1 : R/W; bitpos: [1]; default: 0; - * NA - */ - uint32_t force_err_frame_data_vc1:1; - /** force_err_frame_data_vc2 : R/W; bitpos: [2]; default: 0; - * NA - */ - uint32_t force_err_frame_data_vc2:1; - /** force_err_frame_data_vc3 : R/W; bitpos: [3]; default: 0; - * NA - */ - uint32_t force_err_frame_data_vc3:1; - /** force_err_frame_data_vc4 : R/W; bitpos: [4]; default: 0; - * NA - */ - uint32_t force_err_frame_data_vc4:1; - /** force_err_frame_data_vc5 : R/W; bitpos: [5]; default: 0; - * NA - */ - uint32_t force_err_frame_data_vc5:1; - /** force_err_frame_data_vc6 : R/W; bitpos: [6]; default: 0; - * NA - */ - uint32_t force_err_frame_data_vc6:1; - /** force_err_frame_data_vc7 : R/W; bitpos: [7]; default: 0; - * NA - */ - uint32_t force_err_frame_data_vc7:1; - /** force_err_frame_data_vc8 : R/W; bitpos: [8]; default: 0; - * NA - */ - uint32_t force_err_frame_data_vc8:1; - /** force_err_frame_data_vc9 : R/W; bitpos: [9]; default: 0; - * NA - */ - uint32_t force_err_frame_data_vc9:1; - /** force_err_frame_data_vc10 : R/W; bitpos: [10]; default: 0; - * NA - */ - uint32_t force_err_frame_data_vc10:1; - /** force_err_frame_data_vc11 : R/W; bitpos: [11]; default: 0; - * NA - */ - uint32_t force_err_frame_data_vc11:1; - /** force_err_frame_data_vc12 : R/W; bitpos: [12]; default: 0; - * NA - */ - uint32_t force_err_frame_data_vc12:1; - /** force_err_frame_data_vc13 : R/W; bitpos: [13]; default: 0; - * NA - */ - uint32_t force_err_frame_data_vc13:1; - /** force_err_frame_data_vc14 : R/W; bitpos: [14]; default: 0; - * NA - */ - uint32_t force_err_frame_data_vc14:1; - /** force_err_frame_data_vc15 : R/W; bitpos: [15]; default: 0; - * NA - */ - uint32_t force_err_frame_data_vc15:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} csi_host_int_force_crc_frame_fatal_reg_t; - -/** Type of int_st_pld_crc_fatal register - * NA - */ -typedef union { - struct { - /** st_err_crc_vc0 : RC; bitpos: [0]; default: 0; - * NA - */ - uint32_t st_err_crc_vc0:1; - /** st_err_crc_vc1 : RC; bitpos: [1]; default: 0; - * NA - */ - uint32_t st_err_crc_vc1:1; - /** st_err_crc_vc2 : RC; bitpos: [2]; default: 0; - * NA - */ - uint32_t st_err_crc_vc2:1; - /** st_err_crc_vc3 : RC; bitpos: [3]; default: 0; - * NA - */ - uint32_t st_err_crc_vc3:1; - /** st_err_crc_vc4 : RC; bitpos: [4]; default: 0; - * NA - */ - uint32_t st_err_crc_vc4:1; - /** st_err_crc_vc5 : RC; bitpos: [5]; default: 0; - * NA - */ - uint32_t st_err_crc_vc5:1; - /** st_err_crc_vc6 : RC; bitpos: [6]; default: 0; - * NA - */ - uint32_t st_err_crc_vc6:1; - /** st_err_crc_vc7 : RC; bitpos: [7]; default: 0; - * NA - */ - uint32_t st_err_crc_vc7:1; - /** st_err_crc_vc8 : RC; bitpos: [8]; default: 0; - * NA - */ - uint32_t st_err_crc_vc8:1; - /** st_err_crc_vc9 : RC; bitpos: [9]; default: 0; - * NA - */ - uint32_t st_err_crc_vc9:1; - /** st_err_crc_vc10 : RC; bitpos: [10]; default: 0; - * NA - */ - uint32_t st_err_crc_vc10:1; - /** st_err_crc_vc11 : RC; bitpos: [11]; default: 0; - * NA - */ - uint32_t st_err_crc_vc11:1; - /** st_err_crc_vc12 : RC; bitpos: [12]; default: 0; - * NA - */ - uint32_t st_err_crc_vc12:1; - /** st_err_crc_vc13 : RC; bitpos: [13]; default: 0; - * NA - */ - uint32_t st_err_crc_vc13:1; - /** st_err_crc_vc14 : RC; bitpos: [14]; default: 0; - * NA - */ - uint32_t st_err_crc_vc14:1; - /** st_err_crc_vc15 : RC; bitpos: [15]; default: 0; - * NA - */ - uint32_t st_err_crc_vc15:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} csi_host_int_st_pld_crc_fatal_reg_t; - -/** Type of int_msk_pld_crc_fatal register - * NA - */ -typedef union { - struct { - /** mask_err_crc_vc0 : R/W; bitpos: [0]; default: 0; - * NA - */ - uint32_t mask_err_crc_vc0:1; - /** mask_err_crc_vc1 : R/W; bitpos: [1]; default: 0; - * NA - */ - uint32_t mask_err_crc_vc1:1; - /** mask_err_crc_vc2 : R/W; bitpos: [2]; default: 0; - * NA - */ - uint32_t mask_err_crc_vc2:1; - /** mask_err_crc_vc3 : R/W; bitpos: [3]; default: 0; - * NA - */ - uint32_t mask_err_crc_vc3:1; - /** mask_err_crc_vc4 : R/W; bitpos: [4]; default: 0; - * NA - */ - uint32_t mask_err_crc_vc4:1; - /** mask_err_crc_vc5 : R/W; bitpos: [5]; default: 0; - * NA - */ - uint32_t mask_err_crc_vc5:1; - /** mask_err_crc_vc6 : R/W; bitpos: [6]; default: 0; - * NA - */ - uint32_t mask_err_crc_vc6:1; - /** mask_err_crc_vc7 : R/W; bitpos: [7]; default: 0; - * NA - */ - uint32_t mask_err_crc_vc7:1; - /** mask_err_crc_vc8 : R/W; bitpos: [8]; default: 0; - * NA - */ - uint32_t mask_err_crc_vc8:1; - /** mask_err_crc_vc9 : R/W; bitpos: [9]; default: 0; - * NA - */ - uint32_t mask_err_crc_vc9:1; - /** mask_err_crc_vc10 : R/W; bitpos: [10]; default: 0; - * NA - */ - uint32_t mask_err_crc_vc10:1; - /** mask_err_crc_vc11 : R/W; bitpos: [11]; default: 0; - * NA - */ - uint32_t mask_err_crc_vc11:1; - /** mask_err_crc_vc12 : R/W; bitpos: [12]; default: 0; - * NA - */ - uint32_t mask_err_crc_vc12:1; - /** mask_err_crc_vc13 : R/W; bitpos: [13]; default: 0; - * NA - */ - uint32_t mask_err_crc_vc13:1; - /** mask_err_crc_vc14 : R/W; bitpos: [14]; default: 0; - * NA - */ - uint32_t mask_err_crc_vc14:1; - /** mask_err_crc_vc15 : R/W; bitpos: [15]; default: 0; - * NA - */ - uint32_t mask_err_crc_vc15:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} csi_host_int_msk_pld_crc_fatal_reg_t; - -/** Type of int_force_pld_crc_fatal register - * NA - */ -typedef union { - struct { - /** force_err_crc_vc0 : R/W; bitpos: [0]; default: 0; - * NA - */ - uint32_t force_err_crc_vc0:1; - /** force_err_crc_vc1 : R/W; bitpos: [1]; default: 0; - * NA - */ - uint32_t force_err_crc_vc1:1; - /** force_err_crc_vc2 : R/W; bitpos: [2]; default: 0; - * NA - */ - uint32_t force_err_crc_vc2:1; - /** force_err_crc_vc3 : R/W; bitpos: [3]; default: 0; - * NA - */ - uint32_t force_err_crc_vc3:1; - /** force_err_crc_vc4 : R/W; bitpos: [4]; default: 0; - * NA - */ - uint32_t force_err_crc_vc4:1; - /** force_err_crc_vc5 : R/W; bitpos: [5]; default: 0; - * NA - */ - uint32_t force_err_crc_vc5:1; - /** force_err_crc_vc6 : R/W; bitpos: [6]; default: 0; - * NA - */ - uint32_t force_err_crc_vc6:1; - /** force_err_crc_vc7 : R/W; bitpos: [7]; default: 0; - * NA - */ - uint32_t force_err_crc_vc7:1; - /** force_err_crc_vc8 : R/W; bitpos: [8]; default: 0; - * NA - */ - uint32_t force_err_crc_vc8:1; - /** force_err_crc_vc9 : R/W; bitpos: [9]; default: 0; - * NA - */ - uint32_t force_err_crc_vc9:1; - /** force_err_crc_vc10 : R/W; bitpos: [10]; default: 0; - * NA - */ - uint32_t force_err_crc_vc10:1; - /** force_err_crc_vc11 : R/W; bitpos: [11]; default: 0; - * NA - */ - uint32_t force_err_crc_vc11:1; - /** force_err_crc_vc12 : R/W; bitpos: [12]; default: 0; - * NA - */ - uint32_t force_err_crc_vc12:1; - /** force_err_crc_vc13 : R/W; bitpos: [13]; default: 0; - * NA - */ - uint32_t force_err_crc_vc13:1; - /** force_err_crc_vc14 : R/W; bitpos: [14]; default: 0; - * NA - */ - uint32_t force_err_crc_vc14:1; - /** force_err_crc_vc15 : R/W; bitpos: [15]; default: 0; - * NA - */ - uint32_t force_err_crc_vc15:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} csi_host_int_force_pld_crc_fatal_reg_t; - -/** Type of int_st_data_id register - * NA - */ -typedef union { - struct { - /** st_err_id_vc0 : RC; bitpos: [0]; default: 0; - * NA - */ - uint32_t st_err_id_vc0:1; - /** st_err_id_vc1 : RC; bitpos: [1]; default: 0; - * NA - */ - uint32_t st_err_id_vc1:1; - /** st_err_id_vc2 : RC; bitpos: [2]; default: 0; - * NA - */ - uint32_t st_err_id_vc2:1; - /** st_err_id_vc3 : RC; bitpos: [3]; default: 0; - * NA - */ - uint32_t st_err_id_vc3:1; - /** st_err_id_vc4 : RC; bitpos: [4]; default: 0; - * NA - */ - uint32_t st_err_id_vc4:1; - /** st_err_id_vc5 : RC; bitpos: [5]; default: 0; - * NA - */ - uint32_t st_err_id_vc5:1; - /** st_err_id_vc6 : RC; bitpos: [6]; default: 0; - * NA - */ - uint32_t st_err_id_vc6:1; - /** st_err_id_vc7 : RC; bitpos: [7]; default: 0; - * NA - */ - uint32_t st_err_id_vc7:1; - /** st_err_id_vc8 : RC; bitpos: [8]; default: 0; - * NA - */ - uint32_t st_err_id_vc8:1; - /** st_err_id_vc9 : RC; bitpos: [9]; default: 0; - * NA - */ - uint32_t st_err_id_vc9:1; - /** st_err_id_vc10 : RC; bitpos: [10]; default: 0; - * NA - */ - uint32_t st_err_id_vc10:1; - /** st_err_id_vc11 : RC; bitpos: [11]; default: 0; - * NA - */ - uint32_t st_err_id_vc11:1; - /** st_err_id_vc12 : RC; bitpos: [12]; default: 0; - * NA - */ - uint32_t st_err_id_vc12:1; - /** st_err_id_vc13 : RC; bitpos: [13]; default: 0; - * NA - */ - uint32_t st_err_id_vc13:1; - /** st_err_id_vc14 : RC; bitpos: [14]; default: 0; - * NA - */ - uint32_t st_err_id_vc14:1; - /** st_err_id_vc15 : RC; bitpos: [15]; default: 0; - * NA - */ - uint32_t st_err_id_vc15:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} csi_host_int_st_data_id_reg_t; - -/** Type of int_msk_data_id register - * NA - */ -typedef union { - struct { - /** mask_err_id_vc0 : R/W; bitpos: [0]; default: 0; - * NA - */ - uint32_t mask_err_id_vc0:1; - /** mask_err_id_vc1 : R/W; bitpos: [1]; default: 0; - * NA - */ - uint32_t mask_err_id_vc1:1; - /** mask_err_id_vc2 : R/W; bitpos: [2]; default: 0; - * NA - */ - uint32_t mask_err_id_vc2:1; - /** mask_err_id_vc3 : R/W; bitpos: [3]; default: 0; - * NA - */ - uint32_t mask_err_id_vc3:1; - /** mask_err_id_vc4 : R/W; bitpos: [4]; default: 0; - * NA - */ - uint32_t mask_err_id_vc4:1; - /** mask_err_id_vc5 : R/W; bitpos: [5]; default: 0; - * NA - */ - uint32_t mask_err_id_vc5:1; - /** mask_err_id_vc6 : R/W; bitpos: [6]; default: 0; - * NA - */ - uint32_t mask_err_id_vc6:1; - /** mask_err_id_vc7 : R/W; bitpos: [7]; default: 0; - * NA - */ - uint32_t mask_err_id_vc7:1; - /** mask_err_id_vc8 : R/W; bitpos: [8]; default: 0; - * NA - */ - uint32_t mask_err_id_vc8:1; - /** mask_err_id_vc9 : R/W; bitpos: [9]; default: 0; - * NA - */ - uint32_t mask_err_id_vc9:1; - /** mask_err_id_vc10 : R/W; bitpos: [10]; default: 0; - * NA - */ - uint32_t mask_err_id_vc10:1; - /** mask_err_id_vc11 : R/W; bitpos: [11]; default: 0; - * NA - */ - uint32_t mask_err_id_vc11:1; - /** mask_err_id_vc12 : R/W; bitpos: [12]; default: 0; - * NA - */ - uint32_t mask_err_id_vc12:1; - /** mask_err_id_vc13 : R/W; bitpos: [13]; default: 0; - * NA - */ - uint32_t mask_err_id_vc13:1; - /** mask_err_id_vc14 : R/W; bitpos: [14]; default: 0; - * NA - */ - uint32_t mask_err_id_vc14:1; - /** mask_err_id_vc15 : R/W; bitpos: [15]; default: 0; - * NA - */ - uint32_t mask_err_id_vc15:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} csi_host_int_msk_data_id_reg_t; - -/** Type of int_force_data_id register - * NA - */ -typedef union { - struct { - /** force_err_id_vc0 : R/W; bitpos: [0]; default: 0; - * NA - */ - uint32_t force_err_id_vc0:1; - /** force_err_id_vc1 : R/W; bitpos: [1]; default: 0; - * NA - */ - uint32_t force_err_id_vc1:1; - /** force_err_id_vc2 : R/W; bitpos: [2]; default: 0; - * NA - */ - uint32_t force_err_id_vc2:1; - /** force_err_id_vc3 : R/W; bitpos: [3]; default: 0; - * NA - */ - uint32_t force_err_id_vc3:1; - /** force_err_id_vc4 : R/W; bitpos: [4]; default: 0; - * NA - */ - uint32_t force_err_id_vc4:1; - /** force_err_id_vc5 : R/W; bitpos: [5]; default: 0; - * NA - */ - uint32_t force_err_id_vc5:1; - /** force_err_id_vc6 : R/W; bitpos: [6]; default: 0; - * NA - */ - uint32_t force_err_id_vc6:1; - /** force_err_id_vc7 : R/W; bitpos: [7]; default: 0; - * NA - */ - uint32_t force_err_id_vc7:1; - /** force_err_id_vc8 : R/W; bitpos: [8]; default: 0; - * NA - */ - uint32_t force_err_id_vc8:1; - /** force_err_id_vc9 : R/W; bitpos: [9]; default: 0; - * NA - */ - uint32_t force_err_id_vc9:1; - /** force_err_id_vc10 : R/W; bitpos: [10]; default: 0; - * NA - */ - uint32_t force_err_id_vc10:1; - /** force_err_id_vc11 : R/W; bitpos: [11]; default: 0; - * NA - */ - uint32_t force_err_id_vc11:1; - /** force_err_id_vc12 : R/W; bitpos: [12]; default: 0; - * NA - */ - uint32_t force_err_id_vc12:1; - /** force_err_id_vc13 : R/W; bitpos: [13]; default: 0; - * NA - */ - uint32_t force_err_id_vc13:1; - /** force_err_id_vc14 : R/W; bitpos: [14]; default: 0; - * NA - */ - uint32_t force_err_id_vc14:1; - /** force_err_id_vc15 : R/W; bitpos: [15]; default: 0; - * NA - */ - uint32_t force_err_id_vc15:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} csi_host_int_force_data_id_reg_t; - -/** Type of int_st_ecc_corrected register - * NA - */ -typedef union { - struct { - /** st_err_ecc_corrected_vc0 : RC; bitpos: [0]; default: 0; - * NA - */ - uint32_t st_err_ecc_corrected_vc0:1; - /** st_err_ecc_corrected_vc1 : RC; bitpos: [1]; default: 0; - * NA - */ - uint32_t st_err_ecc_corrected_vc1:1; - /** st_err_ecc_corrected_vc2 : RC; bitpos: [2]; default: 0; - * NA - */ - uint32_t st_err_ecc_corrected_vc2:1; - /** st_err_ecc_corrected_vc3 : RC; bitpos: [3]; default: 0; - * NA - */ - uint32_t st_err_ecc_corrected_vc3:1; - /** st_err_ecc_corrected_vc4 : RC; bitpos: [4]; default: 0; - * NA - */ - uint32_t st_err_ecc_corrected_vc4:1; - /** st_err_ecc_corrected_vc5 : RC; bitpos: [5]; default: 0; - * NA - */ - uint32_t st_err_ecc_corrected_vc5:1; - /** st_err_ecc_corrected_vc6 : RC; bitpos: [6]; default: 0; - * NA - */ - uint32_t st_err_ecc_corrected_vc6:1; - /** st_err_ecc_corrected_vc7 : RC; bitpos: [7]; default: 0; - * NA - */ - uint32_t st_err_ecc_corrected_vc7:1; - /** st_err_ecc_corrected_vc8 : RC; bitpos: [8]; default: 0; - * NA - */ - uint32_t st_err_ecc_corrected_vc8:1; - /** st_err_ecc_corrected_vc9 : RC; bitpos: [9]; default: 0; - * NA - */ - uint32_t st_err_ecc_corrected_vc9:1; - /** st_err_ecc_corrected_vc10 : RC; bitpos: [10]; default: 0; - * NA - */ - uint32_t st_err_ecc_corrected_vc10:1; - /** st_err_ecc_corrected_vc11 : RC; bitpos: [11]; default: 0; - * NA - */ - uint32_t st_err_ecc_corrected_vc11:1; - /** st_err_ecc_corrected_vc12 : RC; bitpos: [12]; default: 0; - * NA - */ - uint32_t st_err_ecc_corrected_vc12:1; - /** st_err_ecc_corrected_vc13 : RC; bitpos: [13]; default: 0; - * NA - */ - uint32_t st_err_ecc_corrected_vc13:1; - /** st_err_ecc_corrected_vc14 : RC; bitpos: [14]; default: 0; - * NA - */ - uint32_t st_err_ecc_corrected_vc14:1; - /** st_err_ecc_corrected_vc15 : RC; bitpos: [15]; default: 0; - * NA - */ - uint32_t st_err_ecc_corrected_vc15:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} csi_host_int_st_ecc_corrected_reg_t; - -/** Type of int_msk_ecc_corrected register - * NA - */ -typedef union { - struct { - /** mask_err_ecc_corrected_vc0 : R/W; bitpos: [0]; default: 0; - * NA - */ - uint32_t mask_err_ecc_corrected_vc0:1; - /** mask_err_ecc_corrected_vc1 : R/W; bitpos: [1]; default: 0; - * NA - */ - uint32_t mask_err_ecc_corrected_vc1:1; - /** mask_err_ecc_corrected_vc2 : R/W; bitpos: [2]; default: 0; - * NA - */ - uint32_t mask_err_ecc_corrected_vc2:1; - /** mask_err_ecc_corrected_vc3 : R/W; bitpos: [3]; default: 0; - * NA - */ - uint32_t mask_err_ecc_corrected_vc3:1; - /** mask_err_ecc_corrected_vc4 : R/W; bitpos: [4]; default: 0; - * NA - */ - uint32_t mask_err_ecc_corrected_vc4:1; - /** mask_err_ecc_corrected_vc5 : R/W; bitpos: [5]; default: 0; - * NA - */ - uint32_t mask_err_ecc_corrected_vc5:1; - /** mask_err_ecc_corrected_vc6 : R/W; bitpos: [6]; default: 0; - * NA - */ - uint32_t mask_err_ecc_corrected_vc6:1; - /** mask_err_ecc_corrected_vc7 : R/W; bitpos: [7]; default: 0; - * NA - */ - uint32_t mask_err_ecc_corrected_vc7:1; - /** mask_err_ecc_corrected_vc8 : R/W; bitpos: [8]; default: 0; - * NA - */ - uint32_t mask_err_ecc_corrected_vc8:1; - /** mask_err_ecc_corrected_vc9 : R/W; bitpos: [9]; default: 0; - * NA - */ - uint32_t mask_err_ecc_corrected_vc9:1; - /** mask_err_ecc_corrected_vc10 : R/W; bitpos: [10]; default: 0; - * NA - */ - uint32_t mask_err_ecc_corrected_vc10:1; - /** mask_err_ecc_corrected_vc11 : R/W; bitpos: [11]; default: 0; - * NA - */ - uint32_t mask_err_ecc_corrected_vc11:1; - /** mask_err_ecc_corrected_vc12 : R/W; bitpos: [12]; default: 0; - * NA - */ - uint32_t mask_err_ecc_corrected_vc12:1; - /** mask_err_ecc_corrected_vc13 : R/W; bitpos: [13]; default: 0; - * NA - */ - uint32_t mask_err_ecc_corrected_vc13:1; - /** mask_err_ecc_corrected_vc14 : R/W; bitpos: [14]; default: 0; - * NA - */ - uint32_t mask_err_ecc_corrected_vc14:1; - /** mask_err_ecc_corrected_vc15 : R/W; bitpos: [15]; default: 0; - * NA - */ - uint32_t mask_err_ecc_corrected_vc15:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} csi_host_int_msk_ecc_corrected_reg_t; - -/** Type of int_force_ecc_corrected register - * NA - */ -typedef union { - struct { - /** force_err_ecc_corrected_vc0 : R/W; bitpos: [0]; default: 0; - * NA - */ - uint32_t force_err_ecc_corrected_vc0:1; - /** force_err_ecc_corrected_vc1 : R/W; bitpos: [1]; default: 0; - * NA - */ - uint32_t force_err_ecc_corrected_vc1:1; - /** force_err_ecc_corrected_vc2 : R/W; bitpos: [2]; default: 0; - * NA - */ - uint32_t force_err_ecc_corrected_vc2:1; - /** force_err_ecc_corrected_vc3 : R/W; bitpos: [3]; default: 0; - * NA - */ - uint32_t force_err_ecc_corrected_vc3:1; - /** force_err_ecc_corrected_vc4 : R/W; bitpos: [4]; default: 0; - * NA - */ - uint32_t force_err_ecc_corrected_vc4:1; - /** force_err_ecc_corrected_vc5 : R/W; bitpos: [5]; default: 0; - * NA - */ - uint32_t force_err_ecc_corrected_vc5:1; - /** force_err_ecc_corrected_vc6 : R/W; bitpos: [6]; default: 0; - * NA - */ - uint32_t force_err_ecc_corrected_vc6:1; - /** force_err_ecc_corrected_vc7 : R/W; bitpos: [7]; default: 0; - * NA - */ - uint32_t force_err_ecc_corrected_vc7:1; - /** force_err_ecc_corrected_vc8 : R/W; bitpos: [8]; default: 0; - * NA - */ - uint32_t force_err_ecc_corrected_vc8:1; - /** force_err_ecc_corrected_vc9 : R/W; bitpos: [9]; default: 0; - * NA - */ - uint32_t force_err_ecc_corrected_vc9:1; - /** force_err_ecc_corrected_vc10 : R/W; bitpos: [10]; default: 0; - * NA - */ - uint32_t force_err_ecc_corrected_vc10:1; - /** force_err_ecc_corrected_vc11 : R/W; bitpos: [11]; default: 0; - * NA - */ - uint32_t force_err_ecc_corrected_vc11:1; - /** force_err_ecc_corrected_vc12 : R/W; bitpos: [12]; default: 0; - * NA - */ - uint32_t force_err_ecc_corrected_vc12:1; - /** force_err_ecc_corrected_vc13 : R/W; bitpos: [13]; default: 0; - * NA - */ - uint32_t force_err_ecc_corrected_vc13:1; - /** force_err_ecc_corrected_vc14 : R/W; bitpos: [14]; default: 0; - * NA - */ - uint32_t force_err_ecc_corrected_vc14:1; - /** force_err_ecc_corrected_vc15 : R/W; bitpos: [15]; default: 0; - * NA - */ - uint32_t force_err_ecc_corrected_vc15:1; - uint32_t reserved_16:16; - }; - uint32_t val; -} csi_host_int_force_ecc_corrected_reg_t; - - -/** Group: Status Registers */ -/** Type of phy_stopstate register - * NA - */ -typedef union { - struct { - /** phy_stopstatedata_0 : RO; bitpos: [0]; default: 0; - * NA - */ - uint32_t phy_stopstatedata_0:1; - /** phy_stopstatedata_1 : RO; bitpos: [1]; default: 0; - * NA - */ - uint32_t phy_stopstatedata_1:1; - uint32_t reserved_2:14; - /** phy_stopstateclk : RO; bitpos: [16]; default: 0; - * NA - */ - uint32_t phy_stopstateclk:1; - uint32_t reserved_17:15; - }; - uint32_t val; -} csi_host_phy_stopstate_reg_t; - - -typedef struct { - volatile csi_host_version_reg_t version; - volatile csi_host_n_lanes_reg_t n_lanes; - volatile csi_host_csi2_resetn_reg_t csi2_resetn; - volatile csi_host_int_st_main_reg_t int_st_main; - uint32_t reserved_010[12]; - volatile csi_host_phy_shutdownz_reg_t phy_shutdownz; - volatile csi_host_dphy_rstz_reg_t dphy_rstz; - volatile csi_host_phy_rx_reg_t phy_rx; - volatile csi_host_phy_stopstate_reg_t phy_stopstate; - volatile csi_host_phy_test_ctrl0_reg_t phy_test_ctrl0; - volatile csi_host_phy_test_ctrl1_reg_t phy_test_ctrl1; - uint32_t reserved_058[28]; - volatile csi_host_vc_extension_reg_t vc_extension; - volatile csi_host_phy_cal_reg_t phy_cal; - uint32_t reserved_0d0[4]; - volatile csi_host_int_st_phy_fatal_reg_t int_st_phy_fatal; - volatile csi_host_int_msk_phy_fatal_reg_t int_msk_phy_fatal; - volatile csi_host_int_force_phy_fatal_reg_t int_force_phy_fatal; - uint32_t reserved_0ec; - volatile csi_host_int_st_pkt_fatal_reg_t int_st_pkt_fatal; - volatile csi_host_int_msk_pkt_fatal_reg_t int_msk_pkt_fatal; - volatile csi_host_int_force_pkt_fatal_reg_t int_force_pkt_fatal; - uint32_t reserved_0fc[5]; - volatile csi_host_int_st_phy_reg_t int_st_phy; - volatile csi_host_int_msk_phy_reg_t int_msk_phy; - volatile csi_host_int_force_phy_reg_t int_force_phy; - uint32_t reserved_11c[89]; - volatile csi_host_int_st_bndry_frame_fatal_reg_t int_st_bndry_frame_fatal; - volatile csi_host_int_msk_bndry_frame_fatal_reg_t int_msk_bndry_frame_fatal; - volatile csi_host_int_force_bndry_frame_fatal_reg_t int_force_bndry_frame_fatal; - uint32_t reserved_28c; - volatile csi_host_int_st_seq_frame_fatal_reg_t int_st_seq_frame_fatal; - volatile csi_host_int_msk_seq_frame_fatal_reg_t int_msk_seq_frame_fatal; - volatile csi_host_int_force_seq_frame_fatal_reg_t int_force_seq_frame_fatal; - uint32_t reserved_29c; - volatile csi_host_int_st_crc_frame_fatal_reg_t int_st_crc_frame_fatal; - volatile csi_host_int_msk_crc_frame_fatal_reg_t int_msk_crc_frame_fatal; - volatile csi_host_int_force_crc_frame_fatal_reg_t int_force_crc_frame_fatal; - uint32_t reserved_2ac; - volatile csi_host_int_st_pld_crc_fatal_reg_t int_st_pld_crc_fatal; - volatile csi_host_int_msk_pld_crc_fatal_reg_t int_msk_pld_crc_fatal; - volatile csi_host_int_force_pld_crc_fatal_reg_t int_force_pld_crc_fatal; - uint32_t reserved_2bc; - volatile csi_host_int_st_data_id_reg_t int_st_data_id; - volatile csi_host_int_msk_data_id_reg_t int_msk_data_id; - volatile csi_host_int_force_data_id_reg_t int_force_data_id; - uint32_t reserved_2cc; - volatile csi_host_int_st_ecc_corrected_reg_t int_st_ecc_corrected; - volatile csi_host_int_msk_ecc_corrected_reg_t int_msk_ecc_corrected; - volatile csi_host_int_force_ecc_corrected_reg_t int_force_ecc_corrected; - uint32_t reserved_2dc[9]; - volatile csi_host_scrambling_reg_t scrambling; - volatile csi_host_scrambling_seed1_reg_t scrambling_seed1; - volatile csi_host_scrambling_seed2_reg_t scrambling_seed2; -} csi_host_dev_t; - -extern csi_host_dev_t MIPI_CSI_HOST; - -#ifndef __cplusplus -_Static_assert(sizeof(csi_host_dev_t) == 0x30c, "Invalid size of csi_host_dev_t structure"); -#endif - -#ifdef __cplusplus -} -#endif