From e97b1a8b51784ce16b8a2f75b9453f30d82d1811 Mon Sep 17 00:00:00 2001 From: Xiao Xufeng Date: Fri, 31 Jan 2025 19:17:40 +0800 Subject: [PATCH] fix(mmap): fixed cache2phys and phy2cache not patched when XIP on PSRAM --- .../esp_rom/esp32c5/ld/esp32c5.rom.spiflash.ld | 4 ++-- .../esp_rom/esp32c61/ld/esp32c61.rom.spiflash.ld | 4 ++-- components/esp_rom/esp32s3/ld/esp32s3.rom.ld | 4 ++-- components/spi_flash/flash_mmap.c | 14 ++++++++++++-- .../peripherals/spi_flash/spi_flash_idf_vs_rom.rst | 2 ++ 5 files changed, 20 insertions(+), 8 deletions(-) diff --git a/components/esp_rom/esp32c5/ld/esp32c5.rom.spiflash.ld b/components/esp_rom/esp32c5/ld/esp32c5.rom.spiflash.ld index c7c934b1e8..2e0054fc31 100644 --- a/components/esp_rom/esp32c5/ld/esp32c5.rom.spiflash.ld +++ b/components/esp_rom/esp32c5/ld/esp32c5.rom.spiflash.ld @@ -38,8 +38,8 @@ spi_flash_munmap = 0x40000228; spi_flash_mmap_dump = 0x4000022c; spi_flash_check_and_flush_cache = 0x40000230; spi_flash_mmap_get_free_pages = 0x40000234; -spi_flash_cache2phys = 0x40000238; -spi_flash_phys2cache = 0x4000023c; +PROVIDE(spi_flash_cache2phys = 0x40000238); /* patched when XIP */ +PROVIDE(spi_flash_phys2cache = 0x4000023c); /* patched when XIP */ /*************************************** diff --git a/components/esp_rom/esp32c61/ld/esp32c61.rom.spiflash.ld b/components/esp_rom/esp32c61/ld/esp32c61.rom.spiflash.ld index a36d84ab23..ed026aa09b 100644 --- a/components/esp_rom/esp32c61/ld/esp32c61.rom.spiflash.ld +++ b/components/esp_rom/esp32c61/ld/esp32c61.rom.spiflash.ld @@ -38,8 +38,8 @@ spi_flash_munmap = 0x40000228; spi_flash_mmap_dump = 0x4000022c; spi_flash_check_and_flush_cache = 0x40000230; spi_flash_mmap_get_free_pages = 0x40000234; -spi_flash_cache2phys = 0x40000238; -spi_flash_phys2cache = 0x4000023c; +PROVIDE(spi_flash_cache2phys = 0x40000238); /* patched when XIP */ +PROVIDE(spi_flash_phys2cache = 0x4000023c); /* patched when XIP */ /*************************************** diff --git a/components/esp_rom/esp32s3/ld/esp32s3.rom.ld b/components/esp_rom/esp32s3/ld/esp32s3.rom.ld index c3799fb4cf..a3871bcf38 100644 --- a/components/esp_rom/esp32s3/ld/esp32s3.rom.ld +++ b/components/esp_rom/esp32s3/ld/esp32s3.rom.ld @@ -194,8 +194,8 @@ PROVIDE( spi_flash_munmap = 0x40000bc4 ); PROVIDE( spi_flash_mmap_dump = 0x40000bd0 ); PROVIDE( spi_flash_check_and_flush_cache = 0x40000bdc ); PROVIDE( spi_flash_mmap_get_free_pages = 0x40000be8 ); -PROVIDE( spi_flash_cache2phys = 0x40000bf4 ); -PROVIDE( spi_flash_phys2cache = 0x40000c00 ); +PROVIDE( spi_flash_cache2phys = 0x40000bf4 ); /* patched when XIP */ +PROVIDE( spi_flash_phys2cache = 0x40000c00 ); /* patched when XIP */ PROVIDE( spi_flash_disable_cache = 0x40000c0c ); PROVIDE( spi_flash_restore_cache = 0x40000c18 ); PROVIDE( spi_flash_cache_enabled = 0x40000c24 ); diff --git a/components/spi_flash/flash_mmap.c b/components/spi_flash/flash_mmap.c index 2554c26863..d9476cbe30 100644 --- a/components/spi_flash/flash_mmap.c +++ b/components/spi_flash/flash_mmap.c @@ -327,8 +327,12 @@ IRAM_ATTR bool spi_flash_check_and_flush_cache(size_t start_addr, size_t length) #endif // !ESP_ROM_HAS_SPI_FLASH_MMAP || !CONFIG_SPI_FLASH_ROM_IMPL #if !ESP_ROM_HAS_SPI_FLASH_MMAP || !CONFIG_SPI_FLASH_ROM_IMPL || CONFIG_SPIRAM_FETCH_INSTRUCTIONS || CONFIG_SPIRAM_RODATA -//The ROM implementation returns physical address of the PSRAM when the .text or .rodata is in the PSRAM. -//Always patch it when SPIRAM_FETCH_INSTRUCTIONS or SPIRAM_RODATA is set. +/* ROM and patch information + * Latest: Add the mapping from psram physical address to flash when CONFIG_SPIRAM_FETCH_INSTRUCTIONS or CONFIG_SPIRAM_RODATA enabled + * V1 (Latest): added to ROM + */ +// The ROM implementation returns physical address of the PSRAM when the .text or .rodata is in the PSRAM. +// Patched when XIP from PSRAM (partially) enabled. size_t spi_flash_cache2phys(const void *cached) { if (cached == NULL) { @@ -370,6 +374,12 @@ size_t spi_flash_cache2phys(const void *cached) return paddr + offset * CONFIG_MMU_PAGE_SIZE; } +/* ROM and patch information + * Latest: Add the mapping from flash physical address to psram when CONFIG_SPIRAM_FETCH_INSTRUCTIONS or CONFIG_SPIRAM_RODATA enabled + * V1 (Latest): added to ROM + */ +// The ROM implementation takes physical address of the PSRAM when the .text or .rodata is in the PSRAM. +// Patched when XIP from PSRAM (partially) enabled. const void * spi_flash_phys2cache(size_t phys_offs, spi_flash_mmap_memory_t memory) { esp_err_t ret = ESP_FAIL; diff --git a/docs/en/api-reference/peripherals/spi_flash/spi_flash_idf_vs_rom.rst b/docs/en/api-reference/peripherals/spi_flash/spi_flash_idf_vs_rom.rst index 8fba50aeec..c87c4415a5 100644 --- a/docs/en/api-reference/peripherals/spi_flash/spi_flash_idf_vs_rom.rst +++ b/docs/en/api-reference/peripherals/spi_flash/spi_flash_idf_vs_rom.rst @@ -24,6 +24,8 @@ Feature Supported by ESP-IDF but Not in Chip-ROM - :ref:`CONFIG_SPI_FLASH_DANGEROUS_WRITE`, enabling this option checks for flash programming to certain protected regions like bootloader, partition table or application itself. - :ref:`CONFIG_SPI_FLASH_ENABLE_COUNTERS`, enabling this option to collect performance data for ESP-IDF SPI flash driver APIs. - :ref:`CONFIG_SPI_FLASH_AUTO_SUSPEND`, enabling this option to automatically suspend or resume a long flash operation when short flash operation happens. Note that this feature is an optional feature, please do read :ref:`auto-suspend-intro` for more limitations. + :ESP_ROM_HAS_SPI_FLASH_MMAP and SOC_SPIRAM_XIP_SUPPORTED and not esp32s3: - :ref:`CONFIG_SPIRAM_XIP_FROM_PSRAM`, enabling this option allows you to use external PSRAM as instruction cache and read-only data cache. Some functions in the ROM don't support this usage, and a ESP-IDF version of these functions is provided. + :esp32s3: - :ref:`CONFIG_SPIRAM_FETCH_INSTRUCTIONS` and :ref:`CONFIG_SPIRAM_RODATA`, enabling these options allows you to use external PSRAM as instruction cache and read-only data cache. Some functions in the ROM don't support this usage, and a ESP-IDF version of these functions is provided. Bugfixes Introduced in ESP-IDF but Not in Chip-ROM --------------------------------------------------