diff --git a/components/efuse/esp32h2/esp_efuse_fields.c b/components/efuse/esp32h2/esp_efuse_fields.c new file mode 100644 index 0000000000..66d1954680 --- /dev/null +++ b/components/efuse/esp32h2/esp_efuse_fields.c @@ -0,0 +1,63 @@ +/* + * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "esp_efuse.h" +#include "esp_efuse_utility.h" +#include "esp_efuse_table.h" +#include "stdlib.h" +#include "esp_types.h" +#include "esp32h2/rom/efuse.h" +#include "assert.h" +#include "esp_err.h" +#include "esp_log.h" +#include "soc/efuse_periph.h" +#include "bootloader_random.h" +#include "sys/param.h" + +static __attribute__((unused)) const char *TAG = "efuse"; + +// Contains functions that provide access to efuse fields which are often used in IDF. + +// Returns chip version from efuse +uint8_t esp_efuse_get_chip_ver(void) +{ + uint32_t chip_ver = 0; + esp_efuse_read_field_blob(ESP_EFUSE_WAFER_VERSION, &chip_ver, ESP_EFUSE_WAFER_VERSION[0]->bit_count); + return chip_ver; +} + +// Returns chip package from efuse +uint32_t esp_efuse_get_pkg_ver(void) +{ + uint32_t pkg_ver = 0; + esp_efuse_read_field_blob(ESP_EFUSE_PKG_VERSION, &pkg_ver, ESP_EFUSE_PKG_VERSION[0]->bit_count); + return pkg_ver; +} + + +esp_err_t esp_efuse_set_rom_log_scheme(esp_efuse_rom_log_scheme_t log_scheme) +{ + int cur_log_scheme = 0; + esp_efuse_read_field_blob(ESP_EFUSE_UART_PRINT_CONTROL, &cur_log_scheme, 2); + if (!cur_log_scheme) { // not burned yet + return esp_efuse_write_field_blob(ESP_EFUSE_UART_PRINT_CONTROL, &log_scheme, 2); + } else { + return ESP_ERR_INVALID_STATE; + } +} + +esp_err_t esp_efuse_disable_rom_download_mode(void) +{ + return esp_efuse_write_field_bit(ESP_EFUSE_DIS_DOWNLOAD_MODE); +} + +esp_err_t esp_efuse_enable_rom_secure_download_mode(void) +{ + if (esp_efuse_read_field_bit(ESP_EFUSE_DIS_DOWNLOAD_MODE)) { + return ESP_ERR_INVALID_STATE; + } + return esp_efuse_write_field_bit(ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD); +} diff --git a/components/efuse/esp32h2/esp_efuse_rtc_calib.c b/components/efuse/esp32h2/esp_efuse_rtc_calib.c new file mode 100644 index 0000000000..52e4167363 --- /dev/null +++ b/components/efuse/esp32h2/esp_efuse_rtc_calib.c @@ -0,0 +1,89 @@ +/* + * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include "esp_efuse.h" +#include "esp_efuse_table.h" + +int esp_efuse_rtc_calib_get_ver(void) +{ + uint32_t result = 0; + esp_efuse_read_field_blob(ESP_EFUSE_BLOCK2_VERSION, &result, 3); + return result; +} + +uint16_t esp_efuse_rtc_calib_get_init_code(int version, int atten) +{ + assert(version == 1); + const esp_efuse_desc_t** init_code_efuse; + assert(atten < 4); + if (atten == 0) { + init_code_efuse = ESP_EFUSE_ADC1_INIT_CODE_ATTEN0; + } else if (atten == 1) { + init_code_efuse = ESP_EFUSE_ADC1_INIT_CODE_ATTEN1; + } else if (atten == 2) { + init_code_efuse = ESP_EFUSE_ADC1_INIT_CODE_ATTEN2; + } else { + init_code_efuse = ESP_EFUSE_ADC1_INIT_CODE_ATTEN3; + } + + int init_code_size = esp_efuse_get_field_size(init_code_efuse); + assert(init_code_size == 10); + + uint32_t init_code = 0; + ESP_ERROR_CHECK(esp_efuse_read_field_blob(init_code_efuse, &init_code, init_code_size)); + return init_code + 1000; // version 1 logic +} + +esp_err_t esp_efuse_rtc_calib_get_cal_voltage(int version, int atten, uint32_t* out_digi, uint32_t* out_vol_mv) +{ + const esp_efuse_desc_t** cal_vol_efuse; + uint32_t calib_vol_expected_mv; + if (version != 1) { + return ESP_ERR_INVALID_ARG; + } + if (atten >= 4) { + return ESP_ERR_INVALID_ARG; + } + if (atten == 0) { + cal_vol_efuse = ESP_EFUSE_ADC1_CAL_VOL_ATTEN0; + calib_vol_expected_mv = 400; + } else if (atten == 1) { + cal_vol_efuse = ESP_EFUSE_ADC1_CAL_VOL_ATTEN1; + calib_vol_expected_mv = 550; + } else if (atten == 2) { + cal_vol_efuse = ESP_EFUSE_ADC1_CAL_VOL_ATTEN2; + calib_vol_expected_mv = 750; + } else { + cal_vol_efuse = ESP_EFUSE_ADC1_CAL_VOL_ATTEN3; + calib_vol_expected_mv = 1370; + } + + assert(cal_vol_efuse[0]->bit_count == 10); + + uint32_t cal_vol = 0; + ESP_ERROR_CHECK(esp_efuse_read_field_blob(cal_vol_efuse, &cal_vol, cal_vol_efuse[0]->bit_count)); + + *out_digi = 2000 + ((cal_vol & BIT(9))? -(cal_vol & ~BIT9): cal_vol); + *out_vol_mv = calib_vol_expected_mv; + return ESP_OK; +} + +float esp_efuse_rtc_calib_get_cal_temp(int version) +{ + assert(version == 1); + const esp_efuse_desc_t** cal_temp_efuse; + cal_temp_efuse = ESP_EFUSE_TEMP_CALIB; + int cal_temp_size = esp_efuse_get_field_size(cal_temp_efuse); + assert(cal_temp_size == 9); + + uint32_t cal_temp = 0; + esp_err_t err = esp_efuse_read_field_blob(cal_temp_efuse, &cal_temp, cal_temp_size); + assert(err == ESP_OK); + (void)err; + // BIT(8) stands for sign: 1: negtive, 0: positive + return ((cal_temp & BIT(8)) != 0)? -(uint8_t)cal_temp: (uint8_t)cal_temp; +} diff --git a/components/efuse/esp32h2/esp_efuse_table.c b/components/efuse/esp32h2/esp_efuse_table.c new file mode 100644 index 0000000000..a3933b5f09 --- /dev/null +++ b/components/efuse/esp32h2/esp_efuse_table.c @@ -0,0 +1,1128 @@ +/* + * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "sdkconfig.h" +#include "esp_efuse.h" +#include +#include "esp_efuse_table.h" + +// md5_digest_table 9e42b2f9dd879191ca75ad0cf50841a1 +// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY. +// If you want to change some fields, you need to change esp_efuse_table.csv file +// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file. +// To show efuse_table run the command 'show_efuse_table'. + +static const esp_efuse_desc_t WR_DIS[] = { + {EFUSE_BLK0, 0, 32}, // Write protection, +}; + +static const esp_efuse_desc_t WR_DIS_RD_DIS[] = { + {EFUSE_BLK0, 0, 1}, // Write protection for RD_DIS_KEY0 RD_DIS_KEY1 RD_DIS_KEY2 RD_DIS_KEY3 RD_DIS_KEY4 RD_DIS_KEY5 RD_DIS_SYS_DATA_PART2, +}; + +static const esp_efuse_desc_t WR_DIS_GROUP_1[] = { + {EFUSE_BLK0, 2, 1}, // Write protection for DIS_ICACHE DIS_DOWNLOAD_ICACHE DIS_FORCE_DOWNLOAD DIS_USB DIS_CAN SOFT_DIS_JTAG DIS_DOWNLOAD_MANUAL_ENCRYPT, +}; + +static const esp_efuse_desc_t WR_DIS_GROUP_2[] = { + {EFUSE_BLK0, 3, 1}, // Write protection for WDT_DELAY_SEL, +}; + +static const esp_efuse_desc_t WR_DIS_SPI_BOOT_CRYPT_CNT[] = { + {EFUSE_BLK0, 4, 1}, // Write protection for SPI_BOOT_CRYPT_CNT, +}; + +static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_KEY_REVOKE0[] = { + {EFUSE_BLK0, 5, 1}, // Write protection for SECURE_BOOT_KEY_REVOKE0, +}; + +static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_KEY_REVOKE1[] = { + {EFUSE_BLK0, 6, 1}, // Write protection for SECURE_BOOT_KEY_REVOKE1, +}; + +static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_KEY_REVOKE2[] = { + {EFUSE_BLK0, 7, 1}, // Write protection for SECURE_BOOT_KEY_REVOKE2, +}; + +static const esp_efuse_desc_t WR_DIS_KEY0_PURPOSE[] = { + {EFUSE_BLK0, 8, 1}, // Write protection for key_purpose. KEY0, +}; + +static const esp_efuse_desc_t WR_DIS_KEY1_PURPOSE[] = { + {EFUSE_BLK0, 9, 1}, // Write protection for key_purpose. KEY1, +}; + +static const esp_efuse_desc_t WR_DIS_KEY2_PURPOSE[] = { + {EFUSE_BLK0, 10, 1}, // Write protection for key_purpose. KEY2, +}; + +static const esp_efuse_desc_t WR_DIS_KEY3_PURPOSE[] = { + {EFUSE_BLK0, 11, 1}, // Write protection for key_purpose. KEY3, +}; + +static const esp_efuse_desc_t WR_DIS_KEY4_PURPOSE[] = { + {EFUSE_BLK0, 12, 1}, // Write protection for key_purpose. KEY4, +}; + +static const esp_efuse_desc_t WR_DIS_KEY5_PURPOSE[] = { + {EFUSE_BLK0, 13, 1}, // Write protection for key_purpose. KEY5, +}; + +static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_EN[] = { + {EFUSE_BLK0, 15, 1}, // Write protection for SECURE_BOOT_EN, +}; + +static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[] = { + {EFUSE_BLK0, 16, 1}, // Write protection for SECURE_BOOT_AGGRESSIVE_REVOKE, +}; + +static const esp_efuse_desc_t WR_DIS_GROUP_3[] = { + {EFUSE_BLK0, 18, 1}, // Write protection for FLASH_TPUW DIS_DOWNLOAD_MODE DIS_LEGACY_SPI_BOOT UART_PRINT_CHANNEL DIS_TINY_BASIC DIS_USB_DOWNLOAD_MODE ENABLE_SECURITY_DOWNLOAD UART_PRINT_CONTROL PIN_POWER_SELECTION FLASH_TYPE FORCE_SEND_RESUME SECURE_VERSION, +}; + +static const esp_efuse_desc_t WR_DIS_BLK1[] = { + {EFUSE_BLK0, 20, 1}, // Write protection for EFUSE_BLK1. MAC_SPI_8M_SYS, +}; + +static const esp_efuse_desc_t WR_DIS_SYS_DATA_PART1[] = { + {EFUSE_BLK0, 21, 1}, // Write protection for EFUSE_BLK2. SYS_DATA_PART1, +}; + +static const esp_efuse_desc_t WR_DIS_USER_DATA[] = { + {EFUSE_BLK0, 22, 1}, // Write protection for EFUSE_BLK3. USER_DATA, +}; + +static const esp_efuse_desc_t WR_DIS_KEY0[] = { + {EFUSE_BLK0, 23, 1}, // Write protection for EFUSE_BLK4. KEY0, +}; + +static const esp_efuse_desc_t WR_DIS_KEY1[] = { + {EFUSE_BLK0, 24, 1}, // Write protection for EFUSE_BLK5. KEY1, +}; + +static const esp_efuse_desc_t WR_DIS_KEY2[] = { + {EFUSE_BLK0, 25, 1}, // Write protection for EFUSE_BLK6. KEY2, +}; + +static const esp_efuse_desc_t WR_DIS_KEY3[] = { + {EFUSE_BLK0, 26, 1}, // Write protection for EFUSE_BLK7. KEY3, +}; + +static const esp_efuse_desc_t WR_DIS_KEY4[] = { + {EFUSE_BLK0, 27, 1}, // Write protection for EFUSE_BLK8. KEY4, +}; + +static const esp_efuse_desc_t WR_DIS_KEY5[] = { + {EFUSE_BLK0, 28, 1}, // Write protection for EFUSE_BLK9. KEY5, +}; + +static const esp_efuse_desc_t WR_DIS_SYS_DATA_PART2[] = { + {EFUSE_BLK0, 29, 1}, // Write protection for EFUSE_BLK10. SYS_DATA_PART2, +}; + +static const esp_efuse_desc_t RD_DIS[] = { + {EFUSE_BLK0, 32, 7}, // Read protection, +}; + +static const esp_efuse_desc_t RD_DIS_KEY0[] = { + {EFUSE_BLK0, 32, 1}, // Read protection for EFUSE_BLK4. KEY0, +}; + +static const esp_efuse_desc_t RD_DIS_KEY1[] = { + {EFUSE_BLK0, 33, 1}, // Read protection for EFUSE_BLK5. KEY1, +}; + +static const esp_efuse_desc_t RD_DIS_KEY2[] = { + {EFUSE_BLK0, 34, 1}, // Read protection for EFUSE_BLK6. KEY2, +}; + +static const esp_efuse_desc_t RD_DIS_KEY3[] = { + {EFUSE_BLK0, 35, 1}, // Read protection for EFUSE_BLK7. KEY3, +}; + +static const esp_efuse_desc_t RD_DIS_KEY4[] = { + {EFUSE_BLK0, 36, 1}, // Read protection for EFUSE_BLK8. KEY4, +}; + +static const esp_efuse_desc_t RD_DIS_KEY5[] = { + {EFUSE_BLK0, 37, 1}, // Read protection for EFUSE_BLK9. KEY5, +}; + +static const esp_efuse_desc_t RD_DIS_SYS_DATA_PART2[] = { + {EFUSE_BLK0, 38, 1}, // Read protection for EFUSE_BLK10. SYS_DATA_PART2, +}; + +static const esp_efuse_desc_t DIS_RTC_RAM_BOOT[] = { + {EFUSE_BLK0, 39, 1}, // Disable boot from RTC RAM, +}; + +static const esp_efuse_desc_t DIS_ICACHE[] = { + {EFUSE_BLK0, 40, 1}, // Disable Icache, +}; + +static const esp_efuse_desc_t DIS_USB_JTAG[] = { + {EFUSE_BLK0, 41, 1}, // Disable USB JTAG, +}; + +static const esp_efuse_desc_t DIS_DOWNLOAD_ICACHE[] = { + {EFUSE_BLK0, 42, 1}, // Disable Icache in download mode, +}; + +static const esp_efuse_desc_t DIS_USB_DEVICE[] = { + {EFUSE_BLK0, 43, 1}, // Disable USB_DEVICE, +}; + +static const esp_efuse_desc_t DIS_FORCE_DOWNLOAD[] = { + {EFUSE_BLK0, 44, 1}, // Disable force chip go to download mode function, +}; + +static const esp_efuse_desc_t DIS_USB[] = { + {EFUSE_BLK0, 45, 1}, // Disable USB function, +}; + +static const esp_efuse_desc_t DIS_CAN[] = { + {EFUSE_BLK0, 46, 1}, // Disable CAN function, +}; + +static const esp_efuse_desc_t JTAG_SEL_ENABLE[] = { + {EFUSE_BLK0, 47, 1}, // Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0., +}; + +static const esp_efuse_desc_t SOFT_DIS_JTAG[] = { + {EFUSE_BLK0, 48, 2}, // Set these bits to disable JTAG in the soft way (odd number 1 means disable). JTAG can be enabled in HMAC module., +}; + +static const esp_efuse_desc_t DIS_PAD_JTAG[] = { + {EFUSE_BLK0, 51, 1}, // Disable JTAG in the hard way. JTAG is disabled permanently., +}; + +static const esp_efuse_desc_t DIS_DOWNLOAD_MANUAL_ENCRYPT[] = { + {EFUSE_BLK0, 52, 1}, // Disable flash encryption when in download boot modes., +}; + +static const esp_efuse_desc_t USB_DREFH[] = { + {EFUSE_BLK0, 53, 2}, // Controls single-end input threshold vrefh 1.76 V to 2 V with step of 80 mV stored in eFuse., +}; + +static const esp_efuse_desc_t USB_DREFL[] = { + {EFUSE_BLK0, 55, 2}, // Controls single-end input threshold vrefl 0.8 V to 1.04 V with step of 80 mV stored in eFuse., +}; + +static const esp_efuse_desc_t USB_EXCHG_PINS[] = { + {EFUSE_BLK0, 57, 1}, // Exchange D+ D- pins, +}; + +static const esp_efuse_desc_t VDD_SPI_AS_GPIO[] = { + {EFUSE_BLK0, 58, 1}, // Set this bit to vdd spi pin function as gpio, +}; + +static const esp_efuse_desc_t BTLC_GPIO_ENABLE[] = { + {EFUSE_BLK0, 59, 2}, // Enable btlc gpio, +}; + +static const esp_efuse_desc_t POWERGLITCH_EN[] = { + {EFUSE_BLK0, 61, 1}, // Set this bit to enable power glitch function, +}; + +static const esp_efuse_desc_t POWER_GLITCH_DSENSE[] = { + {EFUSE_BLK0, 62, 2}, // Sample delay configuration of power glitch, +}; + +static const esp_efuse_desc_t WDT_DELAY_SEL[] = { + {EFUSE_BLK0, 80, 2}, // Select RTC WDT time out threshold, +}; + +static const esp_efuse_desc_t SPI_BOOT_CRYPT_CNT[] = { + {EFUSE_BLK0, 82, 3}, // SPI boot encrypt decrypt enable. odd number 1 enable. even number 1 disable, +}; + +static const esp_efuse_desc_t SECURE_BOOT_KEY_REVOKE0[] = { + {EFUSE_BLK0, 85, 1}, // Enable revoke first secure boot key, +}; + +static const esp_efuse_desc_t SECURE_BOOT_KEY_REVOKE1[] = { + {EFUSE_BLK0, 86, 1}, // Enable revoke second secure boot key, +}; + +static const esp_efuse_desc_t SECURE_BOOT_KEY_REVOKE2[] = { + {EFUSE_BLK0, 87, 1}, // Enable revoke third secure boot key, +}; + +static const esp_efuse_desc_t KEY_PURPOSE_0[] = { + {EFUSE_BLK0, 88, 4}, // Key0 purpose, +}; + +static const esp_efuse_desc_t KEY_PURPOSE_1[] = { + {EFUSE_BLK0, 92, 4}, // Key1 purpose, +}; + +static const esp_efuse_desc_t KEY_PURPOSE_2[] = { + {EFUSE_BLK0, 96, 4}, // Key2 purpose, +}; + +static const esp_efuse_desc_t KEY_PURPOSE_3[] = { + {EFUSE_BLK0, 100, 4}, // Key3 purpose, +}; + +static const esp_efuse_desc_t KEY_PURPOSE_4[] = { + {EFUSE_BLK0, 104, 4}, // Key4 purpose, +}; + +static const esp_efuse_desc_t KEY_PURPOSE_5[] = { + {EFUSE_BLK0, 108, 4}, // Key5 purpose, +}; + +static const esp_efuse_desc_t SECURE_BOOT_EN[] = { + {EFUSE_BLK0, 116, 1}, // Secure boot enable, +}; + +static const esp_efuse_desc_t SECURE_BOOT_AGGRESSIVE_REVOKE[] = { + {EFUSE_BLK0, 117, 1}, // Enable aggressive secure boot revoke, +}; + +static const esp_efuse_desc_t FLASH_TPUW[] = { + {EFUSE_BLK0, 124, 4}, // Flash wait time after power up. (unit is ms). When value is 15. the time is 30 ms, +}; + +static const esp_efuse_desc_t DIS_DOWNLOAD_MODE[] = { + {EFUSE_BLK0, 128, 1}, // Disble download mode include boot_mode[3:0] is 0 1 2 3 6 7, +}; + +static const esp_efuse_desc_t DIS_LEGACY_SPI_BOOT[] = { + {EFUSE_BLK0, 129, 1}, // Disable_Legcy_SPI_boot mode include boot_mode[3:0] is 4, +}; + +static const esp_efuse_desc_t UART_PRINT_CHANNEL[] = { + {EFUSE_BLK0, 130, 1}, // 0: UART0. 1: UART1, +}; + +static const esp_efuse_desc_t FLASH_ECC_MODE[] = { + {EFUSE_BLK0, 131, 1}, // Set this bit to set flsah ecc mode. 0:flash ecc 16to18 byte mode. 1:flash ecc 16to17 byte mode, +}; + +static const esp_efuse_desc_t DIS_USB_DOWNLOAD_MODE[] = { + {EFUSE_BLK0, 132, 1}, // Disable download through USB, +}; + +static const esp_efuse_desc_t ENABLE_SECURITY_DOWNLOAD[] = { + {EFUSE_BLK0, 133, 1}, // Enable security download mode, +}; + +static const esp_efuse_desc_t UART_PRINT_CONTROL[] = { + {EFUSE_BLK0, 134, 2}, // b00:force print. b01:control by GPIO8 - low level print. b10:control by GPIO8 - high level print. b11:force disable print., +}; + +static const esp_efuse_desc_t PIN_POWER_SELECTION[] = { + {EFUSE_BLK0, 136, 1}, // GPIO33-GPIO37 power supply selection in ROM code. 0:VDD3P3_CPU. 1:VDD_SPI., +}; + +static const esp_efuse_desc_t FLASH_TYPE[] = { + {EFUSE_BLK0, 137, 1}, // Connected Flash interface type. 0: 4 data line. 1: 8 data line, +}; + +static const esp_efuse_desc_t FLASH_PAGE_SIZE[] = { + {EFUSE_BLK0, 138, 2}, // Flash page size, +}; + +static const esp_efuse_desc_t FLASH_ECC_EN[] = { + {EFUSE_BLK0, 140, 1}, // Enable ECC for flash boot, +}; + +static const esp_efuse_desc_t FORCE_SEND_RESUME[] = { + {EFUSE_BLK0, 141, 1}, // Force ROM code to send a resume command during SPI boot, +}; + +static const esp_efuse_desc_t SECURE_VERSION[] = { + {EFUSE_BLK0, 142, 16}, // Secure version for anti-rollback, +}; + +static const esp_efuse_desc_t MAC_FACTORY[] = { + {EFUSE_BLK1, 40, 8}, // Factory MAC addr [0], + {EFUSE_BLK1, 32, 8}, // Factory MAC addr [1], + {EFUSE_BLK1, 24, 8}, // Factory MAC addr [2], + {EFUSE_BLK1, 16, 8}, // Factory MAC addr [3], + {EFUSE_BLK1, 8, 8}, // Factory MAC addr [4], + {EFUSE_BLK1, 0, 8}, // Factory MAC addr [5], +}; + +static const esp_efuse_desc_t SPI_PAD_CONFIG_CLK[] = { + {EFUSE_BLK1, 48, 6}, // SPI_PAD_configure CLK, +}; + +static const esp_efuse_desc_t SPI_PAD_CONFIG_Q_D1[] = { + {EFUSE_BLK1, 54, 6}, // SPI_PAD_configure Q(D1), +}; + +static const esp_efuse_desc_t SPI_PAD_CONFIG_D_D0[] = { + {EFUSE_BLK1, 60, 6}, // SPI_PAD_configure D(D0), +}; + +static const esp_efuse_desc_t SPI_PAD_CONFIG_CS[] = { + {EFUSE_BLK1, 66, 6}, // SPI_PAD_configure CS, +}; + +static const esp_efuse_desc_t SPI_PAD_CONFIG_HD_D3[] = { + {EFUSE_BLK1, 72, 6}, // SPI_PAD_configure HD(D3), +}; + +static const esp_efuse_desc_t SPI_PAD_CONFIG_WP_D2[] = { + {EFUSE_BLK1, 78, 6}, // SPI_PAD_configure WP(D2), +}; + +static const esp_efuse_desc_t SPI_PAD_CONFIG_DQS[] = { + {EFUSE_BLK1, 84, 6}, // SPI_PAD_configure DQS, +}; + +static const esp_efuse_desc_t SPI_PAD_CONFIG_D4[] = { + {EFUSE_BLK1, 90, 6}, // SPI_PAD_configure D4, +}; + +static const esp_efuse_desc_t SPI_PAD_CONFIG_D5[] = { + {EFUSE_BLK1, 96, 6}, // SPI_PAD_configure D5, +}; + +static const esp_efuse_desc_t SPI_PAD_CONFIG_D6[] = { + {EFUSE_BLK1, 102, 6}, // SPI_PAD_configure D6, +}; + +static const esp_efuse_desc_t SPI_PAD_CONFIG_D7[] = { + {EFUSE_BLK1, 108, 6}, // SPI_PAD_configure D7, +}; + +static const esp_efuse_desc_t WAFER_VERSION[] = { + {EFUSE_BLK1, 114, 3}, // WAFER version, +}; + +static const esp_efuse_desc_t PKG_VERSION[] = { + {EFUSE_BLK1, 117, 3}, // Package version 0:ESP32H2, +}; + +static const esp_efuse_desc_t BLOCK1_VERSION[] = { + {EFUSE_BLK1, 120, 3}, // BLOCK1 efuse version, +}; + +static const esp_efuse_desc_t OPTIONAL_UNIQUE_ID[] = { + {EFUSE_BLK2, 0, 128}, // Optional unique 128-bit ID, +}; + +static const esp_efuse_desc_t BLOCK2_VERSION[] = { + {EFUSE_BLK2, 128, 3}, // Version of BLOCK2, +}; + +static const esp_efuse_desc_t TEMP_CALIB[] = { + {EFUSE_BLK2, 131, 9}, // Temperature calibration data, +}; + +static const esp_efuse_desc_t OCODE[] = { + {EFUSE_BLK2, 140, 8}, // ADC OCode, +}; + +static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN0[] = { + {EFUSE_BLK2, 148, 10}, // ADC1 init code at atten0, +}; + +static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN1[] = { + {EFUSE_BLK2, 158, 10}, // ADC1 init code at atten1, +}; + +static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN2[] = { + {EFUSE_BLK2, 168, 10}, // ADC1 init code at atten2, +}; + +static const esp_efuse_desc_t ADC1_INIT_CODE_ATTEN3[] = { + {EFUSE_BLK2, 178, 10}, // ADC1 init code at atten3, +}; + +static const esp_efuse_desc_t ADC1_CAL_VOL_ATTEN0[] = { + {EFUSE_BLK2, 188, 10}, // ADC1 calibration voltage at atten0, +}; + +static const esp_efuse_desc_t ADC1_CAL_VOL_ATTEN1[] = { + {EFUSE_BLK2, 198, 10}, // ADC1 calibration voltage at atten1, +}; + +static const esp_efuse_desc_t ADC1_CAL_VOL_ATTEN2[] = { + {EFUSE_BLK2, 208, 10}, // ADC1 calibration voltage at atten2, +}; + +static const esp_efuse_desc_t ADC1_CAL_VOL_ATTEN3[] = { + {EFUSE_BLK2, 218, 10}, // ADC1 calibration voltage at atten3, +}; + +static const esp_efuse_desc_t USER_DATA[] = { + {EFUSE_BLK3, 0, 256}, // User data, +}; + +static const esp_efuse_desc_t KEY0[] = { + {EFUSE_BLK4, 0, 256}, // Key0 or user data, +}; + +static const esp_efuse_desc_t KEY1[] = { + {EFUSE_BLK5, 0, 256}, // Key1 or user data, +}; + +static const esp_efuse_desc_t KEY2[] = { + {EFUSE_BLK6, 0, 256}, // Key2 or user data, +}; + +static const esp_efuse_desc_t KEY3[] = { + {EFUSE_BLK7, 0, 256}, // Key3 or user data, +}; + +static const esp_efuse_desc_t KEY4[] = { + {EFUSE_BLK8, 0, 256}, // Key4 or user data, +}; + +static const esp_efuse_desc_t KEY5[] = { + {EFUSE_BLK9, 0, 256}, // Key5 or user data, +}; + +static const esp_efuse_desc_t SYS_DATA_PART2[] = { + {EFUSE_BLK10, 0, 256}, // System configuration, +}; + +static const esp_efuse_desc_t K_RTC_LDO[] = { + {EFUSE_BLK1, 135, 7}, // BLOCK1 K_RTC_LDO, +}; + +static const esp_efuse_desc_t K_DIG_LDO[] = { + {EFUSE_BLK1, 142, 7}, // BLOCK1 K_DIG_LDO, +}; + +static const esp_efuse_desc_t V_RTC_DBIAS20[] = { + {EFUSE_BLK1, 149, 8}, // BLOCK1 voltage of rtc dbias20, +}; + +static const esp_efuse_desc_t V_DIG_DBIAS20[] = { + {EFUSE_BLK1, 157, 8}, // BLOCK1 voltage of digital dbias20, +}; + +static const esp_efuse_desc_t DIG_DBIAS_HVT[] = { + {EFUSE_BLK1, 165, 5}, // BLOCK1 digital dbias when hvt, +}; + +static const esp_efuse_desc_t THRES_HVT[] = { + {EFUSE_BLK1, 170, 10}, // BLOCK1 pvt threshold when hvt, +}; + + + + + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS[] = { + &WR_DIS[0], // Write protection + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RD_DIS[] = { + &WR_DIS_RD_DIS[0], // Write protection for RD_DIS_KEY0 RD_DIS_KEY1 RD_DIS_KEY2 RD_DIS_KEY3 RD_DIS_KEY4 RD_DIS_KEY5 RD_DIS_SYS_DATA_PART2 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_1[] = { + &WR_DIS_GROUP_1[0], // Write protection for DIS_ICACHE DIS_DOWNLOAD_ICACHE DIS_FORCE_DOWNLOAD DIS_USB DIS_CAN SOFT_DIS_JTAG DIS_DOWNLOAD_MANUAL_ENCRYPT + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_2[] = { + &WR_DIS_GROUP_2[0], // Write protection for WDT_DELAY_SEL + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT[] = { + &WR_DIS_SPI_BOOT_CRYPT_CNT[0], // Write protection for SPI_BOOT_CRYPT_CNT + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE0[] = { + &WR_DIS_SECURE_BOOT_KEY_REVOKE0[0], // Write protection for SECURE_BOOT_KEY_REVOKE0 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE1[] = { + &WR_DIS_SECURE_BOOT_KEY_REVOKE1[0], // Write protection for SECURE_BOOT_KEY_REVOKE1 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE2[] = { + &WR_DIS_SECURE_BOOT_KEY_REVOKE2[0], // Write protection for SECURE_BOOT_KEY_REVOKE2 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY0_PURPOSE[] = { + &WR_DIS_KEY0_PURPOSE[0], // Write protection for key_purpose. KEY0 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY1_PURPOSE[] = { + &WR_DIS_KEY1_PURPOSE[0], // Write protection for key_purpose. KEY1 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY2_PURPOSE[] = { + &WR_DIS_KEY2_PURPOSE[0], // Write protection for key_purpose. KEY2 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY3_PURPOSE[] = { + &WR_DIS_KEY3_PURPOSE[0], // Write protection for key_purpose. KEY3 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY4_PURPOSE[] = { + &WR_DIS_KEY4_PURPOSE[0], // Write protection for key_purpose. KEY4 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY5_PURPOSE[] = { + &WR_DIS_KEY5_PURPOSE[0], // Write protection for key_purpose. KEY5 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_EN[] = { + &WR_DIS_SECURE_BOOT_EN[0], // Write protection for SECURE_BOOT_EN + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[] = { + &WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[0], // Write protection for SECURE_BOOT_AGGRESSIVE_REVOKE + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_3[] = { + &WR_DIS_GROUP_3[0], // Write protection for FLASH_TPUW DIS_DOWNLOAD_MODE DIS_LEGACY_SPI_BOOT UART_PRINT_CHANNEL DIS_TINY_BASIC DIS_USB_DOWNLOAD_MODE ENABLE_SECURITY_DOWNLOAD UART_PRINT_CONTROL PIN_POWER_SELECTION FLASH_TYPE FORCE_SEND_RESUME SECURE_VERSION + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK1[] = { + &WR_DIS_BLK1[0], // Write protection for EFUSE_BLK1. MAC_SPI_8M_SYS + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[] = { + &WR_DIS_SYS_DATA_PART1[0], // Write protection for EFUSE_BLK2. SYS_DATA_PART1 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USER_DATA[] = { + &WR_DIS_USER_DATA[0], // Write protection for EFUSE_BLK3. USER_DATA + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY0[] = { + &WR_DIS_KEY0[0], // Write protection for EFUSE_BLK4. KEY0 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY1[] = { + &WR_DIS_KEY1[0], // Write protection for EFUSE_BLK5. KEY1 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY2[] = { + &WR_DIS_KEY2[0], // Write protection for EFUSE_BLK6. KEY2 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY3[] = { + &WR_DIS_KEY3[0], // Write protection for EFUSE_BLK7. KEY3 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY4[] = { + &WR_DIS_KEY4[0], // Write protection for EFUSE_BLK8. KEY4 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY5[] = { + &WR_DIS_KEY5[0], // Write protection for EFUSE_BLK9. KEY5 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART2[] = { + &WR_DIS_SYS_DATA_PART2[0], // Write protection for EFUSE_BLK10. SYS_DATA_PART2 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_RD_DIS[] = { + &RD_DIS[0], // Read protection + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY0[] = { + &RD_DIS_KEY0[0], // Read protection for EFUSE_BLK4. KEY0 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY1[] = { + &RD_DIS_KEY1[0], // Read protection for EFUSE_BLK5. KEY1 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY2[] = { + &RD_DIS_KEY2[0], // Read protection for EFUSE_BLK6. KEY2 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY3[] = { + &RD_DIS_KEY3[0], // Read protection for EFUSE_BLK7. KEY3 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY4[] = { + &RD_DIS_KEY4[0], // Read protection for EFUSE_BLK8. KEY4 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY5[] = { + &RD_DIS_KEY5[0], // Read protection for EFUSE_BLK9. KEY5 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_SYS_DATA_PART2[] = { + &RD_DIS_SYS_DATA_PART2[0], // Read protection for EFUSE_BLK10. SYS_DATA_PART2 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DIS_RTC_RAM_BOOT[] = { + &DIS_RTC_RAM_BOOT[0], // Disable boot from RTC RAM + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DIS_ICACHE[] = { + &DIS_ICACHE[0], // Disable Icache + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_JTAG[] = { + &DIS_USB_JTAG[0], // Disable USB JTAG + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_ICACHE[] = { + &DIS_DOWNLOAD_ICACHE[0], // Disable Icache in download mode + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_DEVICE[] = { + &DIS_USB_DEVICE[0], // Disable USB_DEVICE + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DIS_FORCE_DOWNLOAD[] = { + &DIS_FORCE_DOWNLOAD[0], // Disable force chip go to download mode function + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DIS_USB[] = { + &DIS_USB[0], // Disable USB function + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DIS_CAN[] = { + &DIS_CAN[0], // Disable CAN function + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_JTAG_SEL_ENABLE[] = { + &JTAG_SEL_ENABLE[0], // Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0. + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_SOFT_DIS_JTAG[] = { + &SOFT_DIS_JTAG[0], // Set these bits to disable JTAG in the soft way (odd number 1 means disable). JTAG can be enabled in HMAC module. + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DIS_PAD_JTAG[] = { + &DIS_PAD_JTAG[0], // Disable JTAG in the hard way. JTAG is disabled permanently. + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT[] = { + &DIS_DOWNLOAD_MANUAL_ENCRYPT[0], // Disable flash encryption when in download boot modes. + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_USB_DREFH[] = { + &USB_DREFH[0], // Controls single-end input threshold vrefh 1.76 V to 2 V with step of 80 mV stored in eFuse. + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_USB_DREFL[] = { + &USB_DREFL[0], // Controls single-end input threshold vrefl 0.8 V to 1.04 V with step of 80 mV stored in eFuse. + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_USB_EXCHG_PINS[] = { + &USB_EXCHG_PINS[0], // Exchange D+ D- pins + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_AS_GPIO[] = { + &VDD_SPI_AS_GPIO[0], // Set this bit to vdd spi pin function as gpio + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_BTLC_GPIO_ENABLE[] = { + &BTLC_GPIO_ENABLE[0], // Enable btlc gpio + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_POWERGLITCH_EN[] = { + &POWERGLITCH_EN[0], // Set this bit to enable power glitch function + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_POWER_GLITCH_DSENSE[] = { + &POWER_GLITCH_DSENSE[0], // Sample delay configuration of power glitch + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WDT_DELAY_SEL[] = { + &WDT_DELAY_SEL[0], // Select RTC WDT time out threshold + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_SPI_BOOT_CRYPT_CNT[] = { + &SPI_BOOT_CRYPT_CNT[0], // SPI boot encrypt decrypt enable. odd number 1 enable. even number 1 disable + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE0[] = { + &SECURE_BOOT_KEY_REVOKE0[0], // Enable revoke first secure boot key + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE1[] = { + &SECURE_BOOT_KEY_REVOKE1[0], // Enable revoke second secure boot key + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE2[] = { + &SECURE_BOOT_KEY_REVOKE2[0], // Enable revoke third secure boot key + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_0[] = { + &KEY_PURPOSE_0[0], // Key0 purpose + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_1[] = { + &KEY_PURPOSE_1[0], // Key1 purpose + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_2[] = { + &KEY_PURPOSE_2[0], // Key2 purpose + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_3[] = { + &KEY_PURPOSE_3[0], // Key3 purpose + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_4[] = { + &KEY_PURPOSE_4[0], // Key4 purpose + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_5[] = { + &KEY_PURPOSE_5[0], // Key5 purpose + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_EN[] = { + &SECURE_BOOT_EN[0], // Secure boot enable + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE[] = { + &SECURE_BOOT_AGGRESSIVE_REVOKE[0], // Enable aggressive secure boot revoke + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_FLASH_TPUW[] = { + &FLASH_TPUW[0], // Flash wait time after power up. (unit is ms). When value is 15. the time is 30 ms + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MODE[] = { + &DIS_DOWNLOAD_MODE[0], // Disble download mode include boot_mode[3:0] is 0 1 2 3 6 7 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DIS_LEGACY_SPI_BOOT[] = { + &DIS_LEGACY_SPI_BOOT[0], // Disable_Legcy_SPI_boot mode include boot_mode[3:0] is 4 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_UART_PRINT_CHANNEL[] = { + &UART_PRINT_CHANNEL[0], // 0: UART0. 1: UART1 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_FLASH_ECC_MODE[] = { + &FLASH_ECC_MODE[0], // Set this bit to set flsah ecc mode. 0:flash ecc 16to18 byte mode. 1:flash ecc 16to17 byte mode + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_DOWNLOAD_MODE[] = { + &DIS_USB_DOWNLOAD_MODE[0], // Disable download through USB + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD[] = { + &ENABLE_SECURITY_DOWNLOAD[0], // Enable security download mode + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_UART_PRINT_CONTROL[] = { + &UART_PRINT_CONTROL[0], // b00:force print. b01:control by GPIO8 - low level print. b10:control by GPIO8 - high level print. b11:force disable print. + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_PIN_POWER_SELECTION[] = { + &PIN_POWER_SELECTION[0], // GPIO33-GPIO37 power supply selection in ROM code. 0:VDD3P3_CPU. 1:VDD_SPI. + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_FLASH_TYPE[] = { + &FLASH_TYPE[0], // Connected Flash interface type. 0: 4 data line. 1: 8 data line + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_FLASH_PAGE_SIZE[] = { + &FLASH_PAGE_SIZE[0], // Flash page size + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_FLASH_ECC_EN[] = { + &FLASH_ECC_EN[0], // Enable ECC for flash boot + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_FORCE_SEND_RESUME[] = { + &FORCE_SEND_RESUME[0], // Force ROM code to send a resume command during SPI boot + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[] = { + &SECURE_VERSION[0], // Secure version for anti-rollback + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_MAC_FACTORY[] = { + &MAC_FACTORY[0], // Factory MAC addr [0] + &MAC_FACTORY[1], // Factory MAC addr [1] + &MAC_FACTORY[2], // Factory MAC addr [2] + &MAC_FACTORY[3], // Factory MAC addr [3] + &MAC_FACTORY[4], // Factory MAC addr [4] + &MAC_FACTORY[5], // Factory MAC addr [5] + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CLK[] = { + &SPI_PAD_CONFIG_CLK[0], // SPI_PAD_configure CLK + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_Q_D1[] = { + &SPI_PAD_CONFIG_Q_D1[0], // SPI_PAD_configure Q(D1) + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D_D0[] = { + &SPI_PAD_CONFIG_D_D0[0], // SPI_PAD_configure D(D0) + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CS[] = { + &SPI_PAD_CONFIG_CS[0], // SPI_PAD_configure CS + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_HD_D3[] = { + &SPI_PAD_CONFIG_HD_D3[0], // SPI_PAD_configure HD(D3) + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_WP_D2[] = { + &SPI_PAD_CONFIG_WP_D2[0], // SPI_PAD_configure WP(D2) + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_DQS[] = { + &SPI_PAD_CONFIG_DQS[0], // SPI_PAD_configure DQS + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D4[] = { + &SPI_PAD_CONFIG_D4[0], // SPI_PAD_configure D4 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D5[] = { + &SPI_PAD_CONFIG_D5[0], // SPI_PAD_configure D5 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D6[] = { + &SPI_PAD_CONFIG_D6[0], // SPI_PAD_configure D6 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D7[] = { + &SPI_PAD_CONFIG_D7[0], // SPI_PAD_configure D7 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION[] = { + &WAFER_VERSION[0], // WAFER version + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[] = { + &PKG_VERSION[0], // Package version 0:ESP32C3 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_BLOCK1_VERSION[] = { + &BLOCK1_VERSION[0], // BLOCK1 efuse version + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[] = { + &OPTIONAL_UNIQUE_ID[0], // Optional unique 128-bit ID + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_BLOCK2_VERSION[] = { + &BLOCK2_VERSION[0], // Version of BLOCK2 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_TEMP_CALIB[] = { + &TEMP_CALIB[0], // Temperature calibration data + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_OCODE[] = { + &OCODE[0], // ADC OCode + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0[] = { + &ADC1_INIT_CODE_ATTEN0[0], // ADC1 init code at atten0 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN1[] = { + &ADC1_INIT_CODE_ATTEN1[0], // ADC1 init code at atten1 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN2[] = { + &ADC1_INIT_CODE_ATTEN2[0], // ADC1 init code at atten2 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN3[] = { + &ADC1_INIT_CODE_ATTEN3[0], // ADC1 init code at atten3 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN0[] = { + &ADC1_CAL_VOL_ATTEN0[0], // ADC1 calibration voltage at atten0 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN1[] = { + &ADC1_CAL_VOL_ATTEN1[0], // ADC1 calibration voltage at atten1 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN2[] = { + &ADC1_CAL_VOL_ATTEN2[0], // ADC1 calibration voltage at atten2 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN3[] = { + &ADC1_CAL_VOL_ATTEN3[0], // ADC1 calibration voltage at atten3 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[] = { + &USER_DATA[0], // User data + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_KEY0[] = { + &KEY0[0], // Key0 or user data + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_KEY1[] = { + &KEY1[0], // Key1 or user data + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_KEY2[] = { + &KEY2[0], // Key2 or user data + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_KEY3[] = { + &KEY3[0], // Key3 or user data + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_KEY4[] = { + &KEY4[0], // Key4 or user data + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_KEY5[] = { + &KEY5[0], // Key5 or user data + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_SYS_DATA_PART2[] = { + &SYS_DATA_PART2[0], // System configuration + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_K_RTC_LDO[] = { + &K_RTC_LDO[0], // BLOCK1 K_RTC_LDO + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_K_DIG_LDO[] = { + &K_DIG_LDO[0], // BLOCK1 K_DIG_LDO + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_V_RTC_DBIAS20[] = { + &V_RTC_DBIAS20[0], // BLOCK1 voltage of rtc dbias20 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_V_DIG_DBIAS20[] = { + &V_DIG_DBIAS20[0], // BLOCK1 voltage of digital dbias20 + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_DIG_DBIAS_HVT[] = { + &DIG_DBIAS_HVT[0], // BLOCK1 digital dbias when hvt + NULL +}; + +const esp_efuse_desc_t* ESP_EFUSE_THRES_HVT[] = { + &THRES_HVT[0], // BLOCK1 pvt threshold when hvt + NULL +}; diff --git a/components/efuse/esp32h2/esp_efuse_table.csv b/components/efuse/esp32h2/esp_efuse_table.csv new file mode 100644 index 0000000000..e56cb8a01f --- /dev/null +++ b/components/efuse/esp32h2/esp_efuse_table.csv @@ -0,0 +1,165 @@ +# field_name, | efuse_block, | bit_start, | bit_count, |comment # +# | (EFUSE_BLK0 | (0..255) | (1..-) | # +# | EFUSE_BLK1 | |MAX_BLK_LEN*| # +# | ... | | | # +# | EFUSE_BLK10)| | | # +########################################################################## +# *) The value MAX_BLK_LEN depends on CONFIG_EFUSE_MAX_BLK_LEN, will be replaced with "None" - 256. "3/4" - 192. "REPEAT" - 128. +# !!!!!!!!!!! # +# After editing this file, run the command manually "make efuse_common_table" or "idf.py efuse_common_table" +# this will generate new source files, next rebuild all the sources. +# !!!!!!!!!!! # + +# ESP32H2-TODO: IDF-3390 +# EFUSE_RD_REPEAT_DATA BLOCK # +############################## + # EFUSE_RD_WR_DIS_REG # + WR_DIS, EFUSE_BLK0, 0, 32, Write protection + WR_DIS.RD_DIS, EFUSE_BLK0, 0, 1, Write protection for RD_DIS_KEY0 RD_DIS_KEY1 RD_DIS_KEY2 RD_DIS_KEY3 RD_DIS_KEY4 RD_DIS_KEY5 RD_DIS_SYS_DATA_PART2 + WR_DIS.GROUP_1, EFUSE_BLK0, 2, 1, Write protection for DIS_ICACHE DIS_DOWNLOAD_ICACHE DIS_FORCE_DOWNLOAD DIS_USB DIS_CAN SOFT_DIS_JTAG DIS_DOWNLOAD_MANUAL_ENCRYPT + WR_DIS.GROUP_2, EFUSE_BLK0, 3, 1, Write protection for WDT_DELAY_SEL + WR_DIS.SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 4, 1, Write protection for SPI_BOOT_CRYPT_CNT + WR_DIS.SECURE_BOOT_KEY_REVOKE0,EFUSE_BLK0, 5, 1, Write protection for SECURE_BOOT_KEY_REVOKE0 + WR_DIS.SECURE_BOOT_KEY_REVOKE1,EFUSE_BLK0, 6, 1, Write protection for SECURE_BOOT_KEY_REVOKE1 + WR_DIS.SECURE_BOOT_KEY_REVOKE2,EFUSE_BLK0, 7, 1, Write protection for SECURE_BOOT_KEY_REVOKE2 + WR_DIS.KEY0_PURPOSE, EFUSE_BLK0, 8, 1, Write protection for key_purpose. KEY0 + WR_DIS.KEY1_PURPOSE, EFUSE_BLK0, 9, 1, Write protection for key_purpose. KEY1 + WR_DIS.KEY2_PURPOSE, EFUSE_BLK0, 10, 1, Write protection for key_purpose. KEY2 + WR_DIS.KEY3_PURPOSE, EFUSE_BLK0, 11, 1, Write protection for key_purpose. KEY3 + WR_DIS.KEY4_PURPOSE, EFUSE_BLK0, 12, 1, Write protection for key_purpose. KEY4 + WR_DIS.KEY5_PURPOSE, EFUSE_BLK0, 13, 1, Write protection for key_purpose. KEY5 + WR_DIS.SECURE_BOOT_EN, EFUSE_BLK0, 15, 1, Write protection for SECURE_BOOT_EN + WR_DIS.SECURE_BOOT_AGGRESSIVE_REVOKE,EFUSE_BLK0, 16, 1, Write protection for SECURE_BOOT_AGGRESSIVE_REVOKE + WR_DIS.GROUP_3, EFUSE_BLK0, 18, 1, Write protection for FLASH_TPUW DIS_DOWNLOAD_MODE DIS_LEGACY_SPI_BOOT UART_PRINT_CHANNEL DIS_TINY_BASIC DIS_USB_DOWNLOAD_MODE ENABLE_SECURITY_DOWNLOAD UART_PRINT_CONTROL PIN_POWER_SELECTION FLASH_TYPE FORCE_SEND_RESUME SECURE_VERSION + WR_DIS.BLK1, EFUSE_BLK0, 20, 1, Write protection for EFUSE_BLK1. MAC_SPI_8M_SYS + WR_DIS.SYS_DATA_PART1, EFUSE_BLK0, 21, 1, Write protection for EFUSE_BLK2. SYS_DATA_PART1 + WR_DIS.USER_DATA, EFUSE_BLK0, 22, 1, Write protection for EFUSE_BLK3. USER_DATA + WR_DIS.KEY0, EFUSE_BLK0, 23, 1, Write protection for EFUSE_BLK4. KEY0 + WR_DIS.KEY1, EFUSE_BLK0, 24, 1, Write protection for EFUSE_BLK5. KEY1 + WR_DIS.KEY2, EFUSE_BLK0, 25, 1, Write protection for EFUSE_BLK6. KEY2 + WR_DIS.KEY3, EFUSE_BLK0, 26, 1, Write protection for EFUSE_BLK7. KEY3 + WR_DIS.KEY4, EFUSE_BLK0, 27, 1, Write protection for EFUSE_BLK8. KEY4 + WR_DIS.KEY5, EFUSE_BLK0, 28, 1, Write protection for EFUSE_BLK9. KEY5 + WR_DIS.SYS_DATA_PART2, EFUSE_BLK0, 29, 1, Write protection for EFUSE_BLK10. SYS_DATA_PART2 + + # EFUSE_RD_REPEAT_DATA0_REG # + RD_DIS, EFUSE_BLK0, 32, 7, Read protection + RD_DIS.KEY0, EFUSE_BLK0, 32, 1, Read protection for EFUSE_BLK4. KEY0 + RD_DIS.KEY1, EFUSE_BLK0, 33, 1, Read protection for EFUSE_BLK5. KEY1 + RD_DIS.KEY2, EFUSE_BLK0, 34, 1, Read protection for EFUSE_BLK6. KEY2 + RD_DIS.KEY3, EFUSE_BLK0, 35, 1, Read protection for EFUSE_BLK7. KEY3 + RD_DIS.KEY4, EFUSE_BLK0, 36, 1, Read protection for EFUSE_BLK8. KEY4 + RD_DIS.KEY5, EFUSE_BLK0, 37, 1, Read protection for EFUSE_BLK9. KEY5 + RD_DIS.SYS_DATA_PART2, EFUSE_BLK0, 38, 1, Read protection for EFUSE_BLK10. SYS_DATA_PART2 + DIS_RTC_RAM_BOOT, EFUSE_BLK0, 39, 1, Disable boot from RTC RAM + DIS_ICACHE, EFUSE_BLK0, 40, 1, Disable Icache + DIS_USB_JTAG, EFUSE_BLK0, 41, 1, Disable USB JTAG + DIS_DOWNLOAD_ICACHE, EFUSE_BLK0, 42, 1, Disable Icache in download mode + DIS_USB_DEVICE, EFUSE_BLK0, 43, 1, Disable USB_DEVICE + DIS_FORCE_DOWNLOAD, EFUSE_BLK0, 44, 1, Disable force chip go to download mode function + DIS_USB, EFUSE_BLK0, 45, 1, Disable USB function + DIS_CAN, EFUSE_BLK0, 46, 1, Disable CAN function + JTAG_SEL_ENABLE, EFUSE_BLK0, 47, 1, Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0. + SOFT_DIS_JTAG, EFUSE_BLK0, 48, 2, Set these bits to disable JTAG in the soft way (odd number 1 means disable). JTAG can be enabled in HMAC module. + DIS_PAD_JTAG, EFUSE_BLK0, 51, 1, Disable JTAG in the hard way. JTAG is disabled permanently. + DIS_DOWNLOAD_MANUAL_ENCRYPT, EFUSE_BLK0, 52, 1, Disable flash encryption when in download boot modes. + USB_DREFH, EFUSE_BLK0, 53, 2, Controls single-end input threshold vrefh 1.76 V to 2 V with step of 80 mV stored in eFuse. + USB_DREFL, EFUSE_BLK0, 55, 2, Controls single-end input threshold vrefl 0.8 V to 1.04 V with step of 80 mV stored in eFuse. + USB_EXCHG_PINS, EFUSE_BLK0, 57, 1, Exchange D+ D- pins + VDD_SPI_AS_GPIO, EFUSE_BLK0, 58, 1, Set this bit to vdd spi pin function as gpio + BTLC_GPIO_ENABLE, EFUSE_BLK0, 59, 2, Enable btlc gpio + POWERGLITCH_EN, EFUSE_BLK0, 61, 1, Set this bit to enable power glitch function + POWER_GLITCH_DSENSE, EFUSE_BLK0, 62, 2, Sample delay configuration of power glitch + + # EFUSE_RD_REPEAT_DATA1_REG # + WDT_DELAY_SEL, EFUSE_BLK0, 80, 2, Select RTC WDT time out threshold + SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 82, 3, SPI boot encrypt decrypt enable. odd number 1 enable. even number 1 disable + SECURE_BOOT_KEY_REVOKE0, EFUSE_BLK0, 85, 1, Enable revoke first secure boot key + SECURE_BOOT_KEY_REVOKE1, EFUSE_BLK0, 86, 1, Enable revoke second secure boot key + SECURE_BOOT_KEY_REVOKE2, EFUSE_BLK0, 87, 1, Enable revoke third secure boot key + KEY_PURPOSE_0, EFUSE_BLK0, 88, 4, Key0 purpose + KEY_PURPOSE_1, EFUSE_BLK0, 92, 4, Key1 purpose + + # EFUSE_RD_REPEAT_DATA2_REG # + KEY_PURPOSE_2, EFUSE_BLK0, 96, 4, Key2 purpose + KEY_PURPOSE_3, EFUSE_BLK0, 100, 4, Key3 purpose + KEY_PURPOSE_4, EFUSE_BLK0, 104, 4, Key4 purpose + KEY_PURPOSE_5, EFUSE_BLK0, 108, 4, Key5 purpose + SECURE_BOOT_EN, EFUSE_BLK0, 116, 1, Secure boot enable + SECURE_BOOT_AGGRESSIVE_REVOKE, EFUSE_BLK0, 117, 1, Enable aggressive secure boot revoke + FLASH_TPUW, EFUSE_BLK0, 124, 4, Flash wait time after power up. (unit is ms). When value is 15. the time is 30 ms + + # EFUSE_RD_REPEAT_DATA3_REG # + DIS_DOWNLOAD_MODE, EFUSE_BLK0, 128, 1, Disble download mode include boot_mode[3:0] is 0 1 2 3 6 7 + DIS_LEGACY_SPI_BOOT, EFUSE_BLK0, 129, 1, Disable_Legcy_SPI_boot mode include boot_mode[3:0] is 4 + UART_PRINT_CHANNEL, EFUSE_BLK0, 130, 1, 0: UART0. 1: UART1 + FLASH_ECC_MODE, EFUSE_BLK0, 131, 1, Set this bit to set flsah ecc mode. 0:flash ecc 16to18 byte mode. 1:flash ecc 16to17 byte mode + DIS_USB_DOWNLOAD_MODE, EFUSE_BLK0, 132, 1, Disable download through USB + ENABLE_SECURITY_DOWNLOAD, EFUSE_BLK0, 133, 1, Enable security download mode + UART_PRINT_CONTROL, EFUSE_BLK0, 134, 2, b00:force print. b01:control by GPIO8 - low level print. b10:control by GPIO8 - high level print. b11:force disable print. + PIN_POWER_SELECTION, EFUSE_BLK0, 136, 1, GPIO33-GPIO37 power supply selection in ROM code. 0:VDD3P3_CPU. 1:VDD_SPI. + FLASH_TYPE, EFUSE_BLK0, 137, 1, Connected Flash interface type. 0: 4 data line. 1: 8 data line + FLASH_PAGE_SIZE, EFUSE_BLK0, 138, 2, Flash page size + FLASH_ECC_EN, EFUSE_BLK0, 140, 1, Enable ECC for flash boot + FORCE_SEND_RESUME, EFUSE_BLK0, 141, 1, Force ROM code to send a resume command during SPI boot + SECURE_VERSION, EFUSE_BLK0, 142, 16, Secure version for anti-rollback + + # EFUSE_RD_REPEAT_DATA4_REG # + + +# MAC_SPI_SYS BLOCK# +####################### + MAC_FACTORY, EFUSE_BLK1, 40, 8, Factory MAC addr [0] + , EFUSE_BLK1, 32, 8, Factory MAC addr [1] + , EFUSE_BLK1, 24, 8, Factory MAC addr [2] + , EFUSE_BLK1, 16, 8, Factory MAC addr [3] + , EFUSE_BLK1, 8, 8, Factory MAC addr [4] + , EFUSE_BLK1, 0, 8, Factory MAC addr [5] + SPI_PAD_CONFIG_CLK, EFUSE_BLK1, 48, 6, SPI_PAD_configure CLK + SPI_PAD_CONFIG_Q_D1, EFUSE_BLK1, 54, 6, SPI_PAD_configure Q(D1) + SPI_PAD_CONFIG_D_D0, EFUSE_BLK1, 60, 6, SPI_PAD_configure D(D0) + SPI_PAD_CONFIG_CS, EFUSE_BLK1, 66, 6, SPI_PAD_configure CS + SPI_PAD_CONFIG_HD_D3, EFUSE_BLK1, 72, 6, SPI_PAD_configure HD(D3) + SPI_PAD_CONFIG_WP_D2, EFUSE_BLK1, 78, 6, SPI_PAD_configure WP(D2) + SPI_PAD_CONFIG_DQS, EFUSE_BLK1, 84, 6, SPI_PAD_configure DQS + SPI_PAD_CONFIG_D4, EFUSE_BLK1, 90, 6, SPI_PAD_configure D4 + SPI_PAD_CONFIG_D5, EFUSE_BLK1, 96, 6, SPI_PAD_configure D5 + SPI_PAD_CONFIG_D6, EFUSE_BLK1, 102, 6, SPI_PAD_configure D6 + SPI_PAD_CONFIG_D7, EFUSE_BLK1, 108, 6, SPI_PAD_configure D7 + WAFER_VERSION, EFUSE_BLK1, 114, 3, WAFER version + PKG_VERSION, EFUSE_BLK1, 117, 3, Package version 0:ESP32H2 + BLOCK1_VERSION, EFUSE_BLK1, 120, 3, BLOCK1 efuse version + +# SYS_DATA_PART1 BLOCK# - System configuration +####################### + OPTIONAL_UNIQUE_ID, EFUSE_BLK2, 0, 128, Optional unique 128-bit ID + BLOCK2_VERSION, EFUSE_BLK2, 128, 3, Version of BLOCK2 + TEMP_CALIB, EFUSE_BLK2, 131, 9, Temperature calibration data + OCODE, EFUSE_BLK2, 140, 8, ADC OCode + ADC1_INIT_CODE_ATTEN0, EFUSE_BLK2, 148, 10, ADC1 init code at atten0 + ADC1_INIT_CODE_ATTEN1, EFUSE_BLK2, 158, 10, ADC1 init code at atten1 + ADC1_INIT_CODE_ATTEN2, EFUSE_BLK2, 168, 10, ADC1 init code at atten2 + ADC1_INIT_CODE_ATTEN3, EFUSE_BLK2, 178, 10, ADC1 init code at atten3 + ADC1_CAL_VOL_ATTEN0, EFUSE_BLK2, 188, 10, ADC1 calibration voltage at atten0 + ADC1_CAL_VOL_ATTEN1, EFUSE_BLK2, 198, 10, ADC1 calibration voltage at atten1 + ADC1_CAL_VOL_ATTEN2, EFUSE_BLK2, 208, 10, ADC1 calibration voltage at atten2 + ADC1_CAL_VOL_ATTEN3, EFUSE_BLK2, 218, 10, ADC1 calibration voltage at atten3 + +################ +USER_DATA, EFUSE_BLK3, 0, 256, User data +KEY0, EFUSE_BLK4, 0, 256, Key0 or user data +KEY1, EFUSE_BLK5, 0, 256, Key1 or user data +KEY2, EFUSE_BLK6, 0, 256, Key2 or user data +KEY3, EFUSE_BLK7, 0, 256, Key3 or user data +KEY4, EFUSE_BLK8, 0, 256, Key4 or user data +KEY5, EFUSE_BLK9, 0, 256, Key5 or user data +SYS_DATA_PART2, EFUSE_BLK10, 0, 256, System configuration + +# AUTO CONFIG DIG&RTC DBIAS# +################ +K_RTC_LDO, EFUSE_BLK1, 135, 7, BLOCK1 K_RTC_LDO +K_DIG_LDO, EFUSE_BLK1, 142, 7, BLOCK1 K_DIG_LDO +V_RTC_DBIAS20, EFUSE_BLK1, 149, 8, BLOCK1 voltage of rtc dbias20 +V_DIG_DBIAS20, EFUSE_BLK1, 157, 8, BLOCK1 voltage of digital dbias20 +DIG_DBIAS_HVT, EFUSE_BLK1, 165, 5, BLOCK1 digital dbias when hvt +THRES_HVT, EFUSE_BLK1, 170, 10, BLOCK1 pvt threshold when hvt diff --git a/components/efuse/esp32h2/esp_efuse_utility.c b/components/efuse/esp32h2/esp_efuse_utility.c new file mode 100644 index 0000000000..6ea6b16473 --- /dev/null +++ b/components/efuse/esp32h2/esp_efuse_utility.c @@ -0,0 +1,141 @@ +/* + * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include "sdkconfig.h" +#include "esp_log.h" +#include "assert.h" +#include "esp_efuse_utility.h" +#include "soc/efuse_periph.h" +#include "esp32h2/clk.h" +#include "esp32h2/rom/efuse.h" + +static const char *TAG = "efuse"; + +#ifdef CONFIG_EFUSE_VIRTUAL +extern uint32_t virt_blocks[EFUSE_BLK_MAX][COUNT_EFUSE_REG_PER_BLOCK]; +#endif // CONFIG_EFUSE_VIRTUAL + +/*Range addresses to read blocks*/ +const esp_efuse_range_addr_t range_read_addr_blocks[] = { + {EFUSE_RD_WR_DIS_REG, EFUSE_RD_REPEAT_DATA4_REG}, // range address of EFUSE_BLK0 REPEAT + {EFUSE_RD_MAC_SPI_SYS_0_REG, EFUSE_RD_MAC_SPI_SYS_5_REG}, // range address of EFUSE_BLK1 MAC_SPI_8M + {EFUSE_RD_SYS_PART1_DATA0_REG, EFUSE_RD_SYS_PART1_DATA7_REG}, // range address of EFUSE_BLK2 SYS_DATA + {EFUSE_RD_USR_DATA0_REG, EFUSE_RD_USR_DATA7_REG}, // range address of EFUSE_BLK3 USR_DATA + {EFUSE_RD_KEY0_DATA0_REG, EFUSE_RD_KEY0_DATA7_REG}, // range address of EFUSE_BLK4 KEY0 + {EFUSE_RD_KEY1_DATA0_REG, EFUSE_RD_KEY1_DATA7_REG}, // range address of EFUSE_BLK5 KEY1 + {EFUSE_RD_KEY2_DATA0_REG, EFUSE_RD_KEY2_DATA7_REG}, // range address of EFUSE_BLK6 KEY2 + {EFUSE_RD_KEY3_DATA0_REG, EFUSE_RD_KEY3_DATA7_REG}, // range address of EFUSE_BLK7 KEY3 + {EFUSE_RD_KEY4_DATA0_REG, EFUSE_RD_KEY4_DATA7_REG}, // range address of EFUSE_BLK8 KEY4 + {EFUSE_RD_KEY5_DATA0_REG, EFUSE_RD_KEY5_DATA7_REG}, // range address of EFUSE_BLK9 KEY5 + {EFUSE_RD_SYS_PART2_DATA0_REG, EFUSE_RD_SYS_PART2_DATA7_REG} // range address of EFUSE_BLK10 KEY6 +}; + +static uint32_t write_mass_blocks[EFUSE_BLK_MAX][COUNT_EFUSE_REG_PER_BLOCK] = { 0 }; + +/*Range addresses to write blocks (it is not real regs, it is buffer) */ +const esp_efuse_range_addr_t range_write_addr_blocks[] = { + {(uint32_t) &write_mass_blocks[EFUSE_BLK0][0], (uint32_t) &write_mass_blocks[EFUSE_BLK0][5]}, + {(uint32_t) &write_mass_blocks[EFUSE_BLK1][0], (uint32_t) &write_mass_blocks[EFUSE_BLK1][5]}, + {(uint32_t) &write_mass_blocks[EFUSE_BLK2][0], (uint32_t) &write_mass_blocks[EFUSE_BLK2][7]}, + {(uint32_t) &write_mass_blocks[EFUSE_BLK3][0], (uint32_t) &write_mass_blocks[EFUSE_BLK3][7]}, + {(uint32_t) &write_mass_blocks[EFUSE_BLK4][0], (uint32_t) &write_mass_blocks[EFUSE_BLK4][7]}, + {(uint32_t) &write_mass_blocks[EFUSE_BLK5][0], (uint32_t) &write_mass_blocks[EFUSE_BLK5][7]}, + {(uint32_t) &write_mass_blocks[EFUSE_BLK6][0], (uint32_t) &write_mass_blocks[EFUSE_BLK6][7]}, + {(uint32_t) &write_mass_blocks[EFUSE_BLK7][0], (uint32_t) &write_mass_blocks[EFUSE_BLK7][7]}, + {(uint32_t) &write_mass_blocks[EFUSE_BLK8][0], (uint32_t) &write_mass_blocks[EFUSE_BLK8][7]}, + {(uint32_t) &write_mass_blocks[EFUSE_BLK9][0], (uint32_t) &write_mass_blocks[EFUSE_BLK9][7]}, + {(uint32_t) &write_mass_blocks[EFUSE_BLK10][0], (uint32_t) &write_mass_blocks[EFUSE_BLK10][7]}, +}; + +#ifndef CONFIG_EFUSE_VIRTUAL +// Update Efuse timing configuration +static esp_err_t esp_efuse_set_timing(void) +{ + // efuse clock is fixed in ESP32-C3, so the ets_efuse_set_timing() function + // takes an argument for compatibility with older ROM functions but it's ignored. + int res = ets_efuse_set_timing(0); + assert(res == 0); + (void)res; + + REG_SET_FIELD(EFUSE_WR_TIM_CONF2_REG, EFUSE_PWR_OFF_NUM, 0x60); + + return ESP_OK; +} +#endif // ifndef CONFIG_EFUSE_VIRTUAL + +// Efuse read operation: copies data from physical efuses to efuse read registers. +void esp_efuse_utility_clear_program_registers(void) +{ + ets_efuse_read(); + ets_efuse_clear_program_registers(); +} + +// Burn values written to the efuse write registers +void esp_efuse_utility_burn_efuses(void) +{ +#ifdef CONFIG_EFUSE_VIRTUAL + ESP_LOGW(TAG, "Virtual efuses enabled: Not really burning eFuses"); + for (int num_block = EFUSE_BLK_MAX - 1; num_block >= EFUSE_BLK0; num_block--) { + int subblock = 0; + for (uint32_t addr_wr_block = range_write_addr_blocks[num_block].start; addr_wr_block <= range_write_addr_blocks[num_block].end; addr_wr_block += 4) { + virt_blocks[num_block][subblock++] |= REG_READ(addr_wr_block); + } + } +#ifdef CONFIG_EFUSE_VIRTUAL_KEEP_IN_FLASH + esp_efuse_utility_write_efuses_to_flash(); +#endif +#else + if (esp_efuse_set_timing() != ESP_OK) { + ESP_LOGE(TAG, "Efuse fields are not burnt"); + } else { + // Permanently update values written to the efuse write registers + // It is necessary to process blocks in the order from MAX-> EFUSE_BLK0, because EFUSE_BLK0 has protection bits for other blocks. + for (int num_block = EFUSE_BLK_MAX - 1; num_block >= EFUSE_BLK0; num_block--) { + for (uint32_t addr_wr_block = range_write_addr_blocks[num_block].start; addr_wr_block <= range_write_addr_blocks[num_block].end; addr_wr_block += 4) { + if (REG_READ(addr_wr_block) != 0) { + if (esp_efuse_get_coding_scheme(num_block) == EFUSE_CODING_SCHEME_RS) { + uint8_t block_rs[12]; + ets_efuse_rs_calculate((void *)range_write_addr_blocks[num_block].start, block_rs); + memcpy((void *)EFUSE_PGM_CHECK_VALUE0_REG, block_rs, sizeof(block_rs)); + } + int data_len = (range_write_addr_blocks[num_block].end - range_write_addr_blocks[num_block].start) + sizeof(uint32_t); + memcpy((void *)EFUSE_PGM_DATA0_REG, (void *)range_write_addr_blocks[num_block].start, data_len); + ets_efuse_program(num_block); + break; + } + } + } + } +#endif // CONFIG_EFUSE_VIRTUAL + esp_efuse_utility_reset(); +} + +// After esp_efuse_write.. functions EFUSE_BLKx_WDATAx_REG were filled is not coded values. +// This function reads EFUSE_BLKx_WDATAx_REG registers, and checks possible to write these data with RS coding scheme. +// The RS coding scheme does not require data changes for the encoded data. esp32s2 has special registers for this. +// They will be filled during the burn operation. +esp_err_t esp_efuse_utility_apply_new_coding_scheme() +{ + // start with EFUSE_BLK1. EFUSE_BLK0 - always uses EFUSE_CODING_SCHEME_NONE. + for (int num_block = EFUSE_BLK1; num_block < EFUSE_BLK_MAX; num_block++) { + if (esp_efuse_get_coding_scheme(num_block) == EFUSE_CODING_SCHEME_RS) { + for (uint32_t addr_wr_block = range_write_addr_blocks[num_block].start; addr_wr_block <= range_write_addr_blocks[num_block].end; addr_wr_block += 4) { + if (REG_READ(addr_wr_block)) { + int num_reg = 0; + for (uint32_t addr_rd_block = range_read_addr_blocks[num_block].start; addr_rd_block <= range_read_addr_blocks[num_block].end; addr_rd_block += 4, ++num_reg) { + if (esp_efuse_utility_read_reg(num_block, num_reg)) { + ESP_LOGE(TAG, "Bits are not empty. Write operation is forbidden."); + return ESP_ERR_CODING; + } + } + break; + } + } + } + } + return ESP_OK; +} diff --git a/components/efuse/esp32h2/include/esp_efuse.h b/components/efuse/esp32h2/include/esp_efuse.h new file mode 100644 index 0000000000..4dce9e72b0 --- /dev/null +++ b/components/efuse/esp32h2/include/esp_efuse.h @@ -0,0 +1,79 @@ +/* + * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Type of eFuse blocks ESP32H2 + */ +typedef enum { + EFUSE_BLK0 = 0, /**< Number of eFuse BLOCK0. REPEAT_DATA */ + + EFUSE_BLK1 = 1, /**< Number of eFuse BLOCK1. MAC_SPI_8M_SYS */ + + EFUSE_BLK2 = 2, /**< Number of eFuse BLOCK2. SYS_DATA_PART1 */ + EFUSE_BLK_SYS_DATA_PART1 = 2, /**< Number of eFuse BLOCK2. SYS_DATA_PART1 */ + + EFUSE_BLK3 = 3, /**< Number of eFuse BLOCK3. USER_DATA*/ + EFUSE_BLK_USER_DATA = 3, /**< Number of eFuse BLOCK3. USER_DATA*/ + + EFUSE_BLK4 = 4, /**< Number of eFuse BLOCK4. KEY0 */ + EFUSE_BLK_KEY0 = 4, /**< Number of eFuse BLOCK4. KEY0 */ + + EFUSE_BLK5 = 5, /**< Number of eFuse BLOCK5. KEY1 */ + EFUSE_BLK_KEY1 = 5, /**< Number of eFuse BLOCK5. KEY1 */ + + EFUSE_BLK6 = 6, /**< Number of eFuse BLOCK6. KEY2 */ + EFUSE_BLK_KEY2 = 6, /**< Number of eFuse BLOCK6. KEY2 */ + + EFUSE_BLK7 = 7, /**< Number of eFuse BLOCK7. KEY3 */ + EFUSE_BLK_KEY3 = 7, /**< Number of eFuse BLOCK7. KEY3 */ + + EFUSE_BLK8 = 8, /**< Number of eFuse BLOCK8. KEY4 */ + EFUSE_BLK_KEY4 = 8, /**< Number of eFuse BLOCK8. KEY4 */ + + EFUSE_BLK9 = 9, /**< Number of eFuse BLOCK9. KEY5 */ + EFUSE_BLK_KEY5 = 9, /**< Number of eFuse BLOCK9. KEY5 */ + EFUSE_BLK_KEY_MAX = 10, + + EFUSE_BLK10 = 10, /**< Number of eFuse BLOCK10. SYS_DATA_PART2 */ + EFUSE_BLK_SYS_DATA_PART2 = 10, /**< Number of eFuse BLOCK10. SYS_DATA_PART2 */ + + EFUSE_BLK_MAX +} esp_efuse_block_t; + +/** + * @brief Type of coding scheme + */ +typedef enum { + EFUSE_CODING_SCHEME_NONE = 0, /**< None */ + EFUSE_CODING_SCHEME_RS = 3, /**< Reed-Solomon coding */ +} esp_efuse_coding_scheme_t; + +/** + * @brief Type of key purpose + */ +typedef enum { + ESP_EFUSE_KEY_PURPOSE_USER = 0, /**< User purposes (software-only use) */ + ESP_EFUSE_KEY_PURPOSE_RESERVED = 1, /**< Reserved */ + ESP_EFUSE_KEY_PURPOSE_XTS_AES_128_KEY = 4, /**< XTS_AES_128_KEY (flash/PSRAM encryption) */ + ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_ALL = 5, /**< HMAC Downstream mode */ + ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_JTAG = 6, /**< JTAG soft enable key (uses HMAC Downstream mode) */ + ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_DIGITAL_SIGNATURE = 7, /**< Digital Signature peripheral key (uses HMAC Downstream mode) */ + ESP_EFUSE_KEY_PURPOSE_HMAC_UP = 8, /**< HMAC Upstream mode */ + ESP_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST0 = 9, /**< SECURE_BOOT_DIGEST0 (Secure Boot key digest) */ + ESP_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST1 = 10, /**< SECURE_BOOT_DIGEST1 (Secure Boot key digest) */ + ESP_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST2 = 11, /**< SECURE_BOOT_DIGEST2 (Secure Boot key digest) */ + ESP_EFUSE_KEY_PURPOSE_MAX, /**< MAX PURPOSE */ +} esp_efuse_purpose_t; + +#ifdef __cplusplus +} +#endif diff --git a/components/efuse/esp32h2/include/esp_efuse_rtc_calib.h b/components/efuse/esp32h2/include/esp_efuse_rtc_calib.h new file mode 100644 index 0000000000..0e059c4f3f --- /dev/null +++ b/components/efuse/esp32h2/include/esp_efuse_rtc_calib.h @@ -0,0 +1,54 @@ +/* + * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Get the RTC calibration efuse version + * + * @return Version of the stored efuse + */ +int esp_efuse_rtc_calib_get_ver(void); + +/** + * @brief Get the init code in the efuse, for the corresponding attenuation. + * + * @param version Version of the stored efuse + * @param atten Attenuation of the init code + * @return The init code stored in efuse + */ +uint16_t esp_efuse_rtc_calib_get_init_code(int version, int atten); + +/** + * @brief Get the calibration digits stored in the efuse, and the corresponding voltage. + * + * @param version Version of the stored efuse + * @param atten Attenuation to use + * @param out_digi Output buffer of the digits + * @param out_vol_mv Output of the voltage, in mV + * @return + * - ESP_ERR_INVALID_ARG: If efuse version or attenuation is invalid + * - ESP_OK: if success + */ +esp_err_t esp_efuse_rtc_calib_get_cal_voltage(int version, int atten, uint32_t* out_digi, uint32_t* out_vol_mv); + +/** + * @brief Get the temperature sensor calibration number delta_T stored in the efuse. + * + * @param version Version of the stored efuse + * + * @return The specification of temperature sensor calibration number in efuse. + */ +float esp_efuse_rtc_calib_get_cal_temp(int version); + +#ifdef __cplusplus +} +#endif diff --git a/components/efuse/esp32h2/include/esp_efuse_table.h b/components/efuse/esp32h2/include/esp_efuse_table.h new file mode 100644 index 0000000000..465d5c29f8 --- /dev/null +++ b/components/efuse/esp32h2/include/esp_efuse_table.h @@ -0,0 +1,144 @@ +/* + * SPDX-FileCopyrightText: 2017-2021 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifdef __cplusplus +extern "C" { +#endif + + +// md5_digest_table 9e42b2f9dd879191ca75ad0cf50841a1 +// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY. +// If you want to change some fields, you need to change esp_efuse_table.csv file +// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file. +// To show efuse_table run the command 'show_efuse_table'. + + +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RD_DIS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY0_PURPOSE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY1_PURPOSE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY2_PURPOSE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY3_PURPOSE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY4_PURPOSE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY5_PURPOSE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_EN[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_3[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USER_DATA[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY3[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY4[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY5[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY3[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY4[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY5[]; +extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_SYS_DATA_PART2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_RTC_RAM_BOOT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_ICACHE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_JTAG[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_ICACHE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_DEVICE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_FORCE_DOWNLOAD[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_CAN[]; +extern const esp_efuse_desc_t* ESP_EFUSE_JTAG_SEL_ENABLE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SOFT_DIS_JTAG[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_PAD_JTAG[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_USB_DREFH[]; +extern const esp_efuse_desc_t* ESP_EFUSE_USB_DREFL[]; +extern const esp_efuse_desc_t* ESP_EFUSE_USB_EXCHG_PINS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_AS_GPIO[]; +extern const esp_efuse_desc_t* ESP_EFUSE_BTLC_GPIO_ENABLE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_POWERGLITCH_EN[]; +extern const esp_efuse_desc_t* ESP_EFUSE_POWER_GLITCH_DSENSE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WDT_DELAY_SEL[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SPI_BOOT_CRYPT_CNT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_3[]; +extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_4[]; +extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_5[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_EN[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_TPUW[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MODE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_LEGACY_SPI_BOOT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_UART_PRINT_CHANNEL[]; +extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_ECC_MODE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB_DOWNLOAD_MODE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD[]; +extern const esp_efuse_desc_t* ESP_EFUSE_UART_PRINT_CONTROL[]; +extern const esp_efuse_desc_t* ESP_EFUSE_PIN_POWER_SELECTION[]; +extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_TYPE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_PAGE_SIZE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_ECC_EN[]; +extern const esp_efuse_desc_t* ESP_EFUSE_FORCE_SEND_RESUME[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[]; +extern const esp_efuse_desc_t* ESP_EFUSE_MAC_FACTORY[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CLK[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_Q_D1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D_D0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_HD_D3[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_WP_D2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_DQS[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D4[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D5[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D6[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D7[]; +extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION[]; +extern const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[]; +extern const esp_efuse_desc_t* ESP_EFUSE_BLOCK1_VERSION[]; +extern const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[]; +extern const esp_efuse_desc_t* ESP_EFUSE_BLOCK2_VERSION[]; +extern const esp_efuse_desc_t* ESP_EFUSE_TEMP_CALIB[]; +extern const esp_efuse_desc_t* ESP_EFUSE_OCODE[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_INIT_CODE_ATTEN3[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CAL_VOL_ATTEN3[]; +extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[]; +extern const esp_efuse_desc_t* ESP_EFUSE_KEY0[]; +extern const esp_efuse_desc_t* ESP_EFUSE_KEY1[]; +extern const esp_efuse_desc_t* ESP_EFUSE_KEY2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_KEY3[]; +extern const esp_efuse_desc_t* ESP_EFUSE_KEY4[]; +extern const esp_efuse_desc_t* ESP_EFUSE_KEY5[]; +extern const esp_efuse_desc_t* ESP_EFUSE_SYS_DATA_PART2[]; +extern const esp_efuse_desc_t* ESP_EFUSE_K_RTC_LDO[]; +extern const esp_efuse_desc_t* ESP_EFUSE_K_DIG_LDO[]; +extern const esp_efuse_desc_t* ESP_EFUSE_V_RTC_DBIAS20[]; +extern const esp_efuse_desc_t* ESP_EFUSE_V_DIG_DBIAS20[]; +extern const esp_efuse_desc_t* ESP_EFUSE_DIG_DBIAS_HVT[]; +extern const esp_efuse_desc_t* ESP_EFUSE_THRES_HVT[]; + +#ifdef __cplusplus +} +#endif diff --git a/components/efuse/esp32h2/private_include/esp_efuse_utility.h b/components/efuse/esp32h2/private_include/esp_efuse_utility.h new file mode 100644 index 0000000000..37573eea8f --- /dev/null +++ b/components/efuse/esp32h2/private_include/esp_efuse_utility.h @@ -0,0 +1,21 @@ +/* + * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#define COUNT_EFUSE_REG_PER_BLOCK 8 /* The number of registers per block. */ + +#define ESP_EFUSE_SECURE_VERSION_NUM_BLOCK EFUSE_BLK0 + +#define ESP_EFUSE_FIELD_CORRESPONDS_CODING_SCHEME(scheme, max_num_bit) + +#ifdef __cplusplus +} +#endif diff --git a/components/efuse/esp32h2/sources.cmake b/components/efuse/esp32h2/sources.cmake new file mode 100644 index 0000000000..9dffd72008 --- /dev/null +++ b/components/efuse/esp32h2/sources.cmake @@ -0,0 +1,4 @@ +set(EFUSE_SOC_SRCS "esp_efuse_table.c" + "esp_efuse_fields.c" + "esp_efuse_rtc_calib.c" + "esp_efuse_utility.c") diff --git a/components/esp_gdbstub/esp32h2/gdbstub_esp32h2.c b/components/esp_gdbstub/esp32h2/gdbstub_esp32h2.c new file mode 100644 index 0000000000..102cb322b5 --- /dev/null +++ b/components/esp_gdbstub/esp32h2/gdbstub_esp32h2.c @@ -0,0 +1,124 @@ +// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include "soc/uart_periph.h" +#include "soc/gpio_periph.h" +#include "soc/soc.h" +#include "soc/usb_serial_jtag_struct.h" +#include "hal/usb_serial_jtag_ll.h" +#include "esp_gdbstub_common.h" +#include "sdkconfig.h" + +#define UART_NUM CONFIG_ESP_CONSOLE_UART_NUM + +#define GDBSTUB_MEM_REGION_COUNT 9 + +#define UART_REG_FIELD_LEN 0x84 + +typedef struct { + intptr_t lower; + intptr_t upper; +} mem_bound_t; + +static const mem_bound_t mem_region_table [GDBSTUB_MEM_REGION_COUNT] = +{ + {SOC_DROM_LOW, SOC_DROM_HIGH}, + {SOC_IROM_LOW, SOC_IROM_HIGH}, + {SOC_IRAM_LOW, SOC_IRAM_HIGH}, + {SOC_DRAM_LOW, SOC_DRAM_HIGH}, + {SOC_IROM_MASK_LOW, SOC_IROM_MASK_HIGH}, + {SOC_DROM_MASK_LOW, SOC_DROM_MASK_HIGH}, + {SOC_RTC_IRAM_LOW, SOC_RTC_IRAM_HIGH}, + // RTC DRAM and RTC DATA are identical with RTC IRAM, hence we skip them + // We shouldn't read the uart registers since it will disturb the debugging via UART, + // so skip UART part of the peripheral registers. + {DR_REG_UART_BASE + UART_REG_FIELD_LEN, SOC_PERIPHERAL_HIGH}, + {SOC_DEBUG_LOW, SOC_DEBUG_HIGH}, +}; + +static inline bool check_inside_valid_region(intptr_t addr) +{ + for (size_t i = 0; i < GDBSTUB_MEM_REGION_COUNT; i++) { + if (addr >= mem_region_table[i].lower && addr < mem_region_table[i].upper) { + return true; + } + } + + return false; +} + +void esp_gdbstub_target_init() +{ +} + +#if CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG + +int esp_gdbstub_getchar() +{ + uint8_t c; + //retry the read until we succeed + while (usb_serial_jtag_ll_read_rxfifo(&c, 1)==0) ; + return c; +} + +void esp_gdbstub_putchar(int c) +{ + uint8_t cc=c; + //retry the write until we succeed + while (usb_serial_jtag_ll_write_txfifo(&cc, 1)<1) ; +} + +void esp_gdbstub_flush() +{ + usb_serial_jtag_ll_txfifo_flush(); +} + + +#else + +//assume UART gdbstub channel + +int esp_gdbstub_getchar() +{ + while (REG_GET_FIELD(UART_STATUS_REG(UART_NUM), UART_RXFIFO_CNT) == 0) { + ; + } + return REG_READ(UART_FIFO_AHB_REG(UART_NUM)); +} + +void esp_gdbstub_putchar(int c) +{ + while (REG_GET_FIELD(UART_STATUS_REG(UART_NUM), UART_TXFIFO_CNT) >= 126) { + ; + } + REG_WRITE(UART_FIFO_AHB_REG(UART_NUM), c); +} + +void esp_gdbstub_flush() +{ + //not needed for uart +} + +#endif + +int esp_gdbstub_readmem(intptr_t addr) +{ + if (!check_inside_valid_region(addr)) { + /* see esp_cpu_configure_region_protection */ + return -1; + } + uint32_t val_aligned = *(uint32_t *)(addr & (~3)); + uint32_t shift = (addr & 3) * 8; + return (val_aligned >> shift) & 0xff; +} diff --git a/components/esp_gdbstub/esp32h2/gdbstub_target_config.h b/components/esp_gdbstub/esp32h2/gdbstub_target_config.h new file mode 100644 index 0000000000..527dc5e2da --- /dev/null +++ b/components/esp_gdbstub/esp32h2/gdbstub_target_config.h @@ -0,0 +1,15 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once diff --git a/components/esp_phy/CMakeLists.txt b/components/esp_phy/CMakeLists.txt index 4d98099422..8a92c477f7 100644 --- a/components/esp_phy/CMakeLists.txt +++ b/components/esp_phy/CMakeLists.txt @@ -8,7 +8,13 @@ else() set(ldfragments "linker.lf") endif() -idf_component_register(SRCS "src/phy_init.c" +if(IDF_TARGET STREQUAL "esp32h2") + set(srcs "src/esp32h2/phy_init.c") +else() + set(srcs "src/phy_init.c") +endif() + +idf_component_register(SRCS "${srcs}" INCLUDE_DIRS "include" "${idf_target}/include" PRIV_REQUIRES nvs_flash LDFRAGMENTS "${ldfragments}") diff --git a/components/esp_phy/esp32h2/include/phy_init_data.h b/components/esp_phy/esp32h2/include/phy_init_data.h new file mode 100644 index 0000000000..c29eab08ec --- /dev/null +++ b/components/esp_phy/esp32h2/include/phy_init_data.h @@ -0,0 +1,30 @@ +// Copyright 2016-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef PHY_INIT_DATA_H +#define PHY_INIT_DATA_H /* don't use #pragma once here, we compile this file sometimes */ +#include "esp_phy_init.h" +#include "sdkconfig.h" + +#ifdef __cplusplus +extern "C" { +#endif + +// ESP32H2-TODO: IDF-3398 + +#ifdef __cplusplus +} +#endif + +#endif /* PHY_INIT_DATA_H */ diff --git a/components/esp_phy/lib b/components/esp_phy/lib index f2c0563405..5fd56f1692 160000 --- a/components/esp_phy/lib +++ b/components/esp_phy/lib @@ -1 +1 @@ -Subproject commit f2c056340505399429dbc8792e7109b7c69f5d77 +Subproject commit 5fd56f1692128209056fea699f9d118e88e176f6 diff --git a/components/esp_phy/src/esp32h2/phy_init.c b/components/esp_phy/src/esp32h2/phy_init.c new file mode 100644 index 0000000000..fdbd687fe3 --- /dev/null +++ b/components/esp_phy/src/esp32h2/phy_init.c @@ -0,0 +1,15 @@ +// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// ESP32H2-TODO: IDF-3398