From 672e70a023e7ff912e9ebb35965b2f1f80c0d296 Mon Sep 17 00:00:00 2001 From: Ivan Grokhotkov Date: Fri, 1 Jul 2022 19:50:00 +0200 Subject: [PATCH 1/9] esp_hw_support: add 26 MHz XTAL option for esp32c2 Some esp32c2 boards will be produced with a 26 MHz XTAL. This commit adds the basic Kconfig option for this type of hardware. Support for CONFIG_ESP32C2_XTAL_FREQ_26 in other areas of IDF will be implemented in subsequent commits. --- .../port/esp32c2/Kconfig.hw_support | 21 +++++++++++++++++++ 1 file changed, 21 insertions(+) create mode 100644 components/esp_hw_support/port/esp32c2/Kconfig.hw_support diff --git a/components/esp_hw_support/port/esp32c2/Kconfig.hw_support b/components/esp_hw_support/port/esp32c2/Kconfig.hw_support new file mode 100644 index 0000000000..d84edf2692 --- /dev/null +++ b/components/esp_hw_support/port/esp32c2/Kconfig.hw_support @@ -0,0 +1,21 @@ +config ESP32C2_XTAL_FREQ + int + default 40 if ESP32C2_XTAL_FREQ_40 + default 26 if ESP32C2_XTAL_FREQ_26 + +choice ESP32C2_XTAL_FREQ_SEL + prompt "Main XTAL frequency" + default ESP32C2_XTAL_FREQ_40 + help + ESP32-C2 currently supports the following XTAL frequencies: + + - 26 MHz + - 40 MHz + + This option must be set to the correct value for the given hardware. + + config ESP32C2_XTAL_FREQ_40 # TODO: IDF-5488 + bool "40 MHz" + config ESP32C2_XTAL_FREQ_26 + bool "26 MHz" +endchoice From f0f98900960a8832f36aac17ca0e4be331f44bc8 Mon Sep 17 00:00:00 2001 From: Ivan Grokhotkov Date: Fri, 1 Jul 2022 20:27:31 +0200 Subject: [PATCH 2/9] bootloader: set the initial XTAL frequency based on the Kconfig option --- components/bootloader_support/src/bootloader_clock_init.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/components/bootloader_support/src/bootloader_clock_init.c b/components/bootloader_support/src/bootloader_clock_init.c index 3f20543d3d..3a12b73eb8 100644 --- a/components/bootloader_support/src/bootloader_clock_init.c +++ b/components/bootloader_support/src/bootloader_clock_init.c @@ -45,7 +45,10 @@ __attribute__((weak)) void bootloader_clock_configure(void) #if CONFIG_IDF_TARGET_ESP32 clk_cfg.xtal_freq = CONFIG_ESP32_XTAL_FREQ; #endif - /* Except ESP32, there is no XTAL_FREQ choice */ +#if CONFIG_IDF_TARGET_ESP32C2 + clk_cfg.xtal_freq = CONFIG_ESP32C2_XTAL_FREQ; +#endif + /* For other chips, there is no XTAL_FREQ choice */ clk_cfg.cpu_freq_mhz = cpu_freq_mhz; clk_cfg.slow_clk_src = rtc_clk_slow_src_get(); if (clk_cfg.slow_clk_src == SOC_RTC_SLOW_CLK_SRC_INVALID) { From 5b54ae76d43449ddafe4b06ca359983b5218c17c Mon Sep 17 00:00:00 2001 From: Ivan Grokhotkov Date: Fri, 1 Jul 2022 19:58:23 +0200 Subject: [PATCH 3/9] esp_timer, hal: add support for non-integer systimer frequency When ESP32-C2 is paired with a 26 MHz XTAL, the systimer tick frequency becomes equal to 26 / 2.5 = 10.4 MHz. Previously we always assumed that systimer tick frequency is integer (and 1 MHz * power of two, above that!). This commit introduces a new LL macro, SYSTIMER_LL_TICKS_PER_US_DIV. It should be set in such a way that: 1. SYSTIMER_LL_TICKS_PER_US / SYSTIMER_LL_TICKS_PER_US_DIV equals the actual systimer tick frequency, 2. and SYSTIMER_LL_TICKS_PER_US is integer. For ESP32-C2 this means that SYSTIMER_LL_TICKS_PER_US = 52 and SYSTIMER_LL_TICKS_PER_US_DIV = 5. This introduced two possible issues: 1. Overflow when multiplying systimer counter by 5 - Should not be an issue, since systimer counter is 52-bit, so counter * 5 is no more than 55-bit. 2. The code needs to perform: - divide by 5: when converting from microseconds to ticks - divide by 52: when converting from ticks to microseconds The latter potentially introduces a performance issue for the esp_timer_get_time function. --- .../esp_timer/src/esp_timer_impl_systimer.c | 10 ++++--- .../hal/esp32c2/include/hal/systimer_ll.h | 7 +++++ .../hal/esp32c3/include/hal/systimer_ll.h | 19 ++++--------- .../hal/esp32h2/include/hal/systimer_ll.h | 1 + .../hal/esp32s2/include/hal/systimer_ll.h | 19 ++++--------- .../hal/esp32s3/include/hal/systimer_ll.h | 19 ++++--------- components/hal/include/hal/systimer_hal.h | 20 ++++--------- components/hal/systimer_hal.c | 28 +++++++++++++------ .../esp32c2/include/soc/Kconfig.soc_caps.in | 6 ++-- components/soc/esp32c2/include/soc/soc_caps.h | 16 +++++------ .../esp32c3/include/soc/Kconfig.soc_caps.in | 6 ++-- components/soc/esp32c3/include/soc/soc_caps.h | 16 +++++------ .../esp32h2/include/soc/Kconfig.soc_caps.in | 6 ++-- components/soc/esp32h2/include/soc/soc_caps.h | 16 +++++------ .../esp32s3/include/soc/Kconfig.soc_caps.in | 6 ++-- components/soc/esp32s3/include/soc/soc_caps.h | 16 +++++------ tools/ci/check_copyright_ignore.txt | 4 --- 17 files changed, 102 insertions(+), 113 deletions(-) diff --git a/components/esp_timer/src/esp_timer_impl_systimer.c b/components/esp_timer/src/esp_timer_impl_systimer.c index e7141830b1..a2af82c3be 100644 --- a/components/esp_timer/src/esp_timer_impl_systimer.c +++ b/components/esp_timer/src/esp_timer_impl_systimer.c @@ -64,7 +64,7 @@ uint64_t IRAM_ATTR esp_timer_impl_get_counter_reg(void) int64_t IRAM_ATTR esp_timer_impl_get_time(void) { - return systimer_hal_get_counter_value(&systimer_hal, SYSTIMER_LL_COUNTER_CLOCK) / SYSTIMER_LL_TICKS_PER_US; + return systimer_hal_get_counter_value(&systimer_hal, SYSTIMER_LL_COUNTER_CLOCK) * SYSTIMER_LL_TICKS_PER_US_DIV / SYSTIMER_LL_TICKS_PER_US; } int64_t esp_timer_get_time(void) __attribute__((alias("esp_timer_impl_get_time"))); @@ -96,7 +96,7 @@ static void IRAM_ATTR timer_alarm_isr(void *arg) void IRAM_ATTR esp_timer_impl_update_apb_freq(uint32_t apb_ticks_per_us) { -#if !SOC_SYSTIMER_FIXED_TICKS_US +#if !SOC_SYSTIMER_HAS_FIXED_TICKS_PER_US systimer_hal_on_apb_freq_update(&systimer_hal, apb_ticks_per_us); #endif } @@ -104,7 +104,9 @@ void IRAM_ATTR esp_timer_impl_update_apb_freq(uint32_t apb_ticks_per_us) void esp_timer_impl_set(uint64_t new_us) { portENTER_CRITICAL_SAFE(&s_time_update_lock); - systimer_counter_value_t new_count = { .val = new_us * SYSTIMER_LL_TICKS_PER_US }; + systimer_counter_value_t new_count = { + .val = new_us * SYSTIMER_LL_TICKS_PER_US / SYSTIMER_LL_TICKS_PER_US_DIV + }; systimer_ll_set_counter_value(systimer_hal.dev, SYSTIMER_LL_COUNTER_CLOCK, new_count.val); systimer_ll_apply_counter_value(systimer_hal.dev, SYSTIMER_LL_COUNTER_CLOCK); portEXIT_CRITICAL_SAFE(&s_time_update_lock); @@ -121,7 +123,7 @@ esp_err_t esp_timer_impl_early_init(void) { systimer_hal_init(&systimer_hal); -#if !SOC_SYSTIMER_FIXED_TICKS_US +#if !SOC_SYSTIMER_HAS_FIXED_TICKS_PER_US assert(esp_clk_xtal_freq() == (40 * 1000000) && "update the step for xtal to support other XTAL:APB frequency ratios"); systimer_hal_set_steps_per_tick(&systimer_hal, 0, 2); // for xtal diff --git a/components/hal/esp32c2/include/hal/systimer_ll.h b/components/hal/esp32c2/include/hal/systimer_ll.h index b993bf5347..36cc040840 100644 --- a/components/hal/esp32c2/include/hal/systimer_ll.h +++ b/components/hal/esp32c2/include/hal/systimer_ll.h @@ -9,13 +9,20 @@ #include #include "soc/systimer_struct.h" #include "hal/assert.h" +#include "sdkconfig.h" #define SYSTIMER_LL_COUNTER_CLOCK (0) // Counter used for "wallclock" time #define SYSTIMER_LL_COUNTER_OS_TICK (1) // Counter used for OS tick #define SYSTIMER_LL_ALARM_OS_TICK_CORE0 (0) // Alarm used for OS tick of CPU core 0 #define SYSTIMER_LL_ALARM_CLOCK (2) // Alarm used for "wallclock" time +#ifdef CONFIG_ESP32C2_XTAL_FREQ_26 +#define SYSTIMER_LL_TICKS_PER_US (52) // (26 / 2.5) = 10.4 = 52/5 systimer ticks per us +#define SYSTIMER_LL_TICKS_PER_US_DIV (5) +#else #define SYSTIMER_LL_TICKS_PER_US (16) // 16 systimer ticks == 1us +#define SYSTIMER_LL_TICKS_PER_US_DIV (1) +#endif // ESP32C2_XTAL_FREQ_* #ifdef __cplusplus extern "C" { diff --git a/components/hal/esp32c3/include/hal/systimer_ll.h b/components/hal/esp32c3/include/hal/systimer_ll.h index 3628978f68..beedfcb853 100644 --- a/components/hal/esp32c3/include/hal/systimer_ll.h +++ b/components/hal/esp32c3/include/hal/systimer_ll.h @@ -1,16 +1,8 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #pragma once #include @@ -24,6 +16,7 @@ #define SYSTIMER_LL_ALARM_CLOCK (2) // Alarm used for "wallclock" time #define SYSTIMER_LL_TICKS_PER_US (16) // 16 systimer ticks == 1us +#define SYSTIMER_LL_TICKS_PER_US_DIV (1) #ifdef __cplusplus extern "C" { diff --git a/components/hal/esp32h2/include/hal/systimer_ll.h b/components/hal/esp32h2/include/hal/systimer_ll.h index a17b5add9d..c1983eb439 100644 --- a/components/hal/esp32h2/include/hal/systimer_ll.h +++ b/components/hal/esp32h2/include/hal/systimer_ll.h @@ -16,6 +16,7 @@ #define SYSTIMER_LL_ALARM_CLOCK (2) // Alarm used for "wallclock" time #define SYSTIMER_LL_TICKS_PER_US (16) // 16 systimer ticks == 1us +#define SYSTIMER_LL_TICKS_PER_US_DIV (1) #ifdef __cplusplus extern "C" { diff --git a/components/hal/esp32s2/include/hal/systimer_ll.h b/components/hal/esp32s2/include/hal/systimer_ll.h index 6066674243..1c0d5498ad 100644 --- a/components/hal/esp32s2/include/hal/systimer_ll.h +++ b/components/hal/esp32s2/include/hal/systimer_ll.h @@ -1,16 +1,8 @@ -// Copyright 2020-2021 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #pragma once #include @@ -22,6 +14,7 @@ #define SYSTIMER_LL_ALARM_CLOCK (2) // Alarm used for "wallclock" time #define SYSTIMER_LL_TICKS_PER_US (80) // 80 systimer ticks == 1us +#define SYSTIMER_LL_TICKS_PER_US_DIV (1) #ifdef __cplusplus extern "C" { diff --git a/components/hal/esp32s3/include/hal/systimer_ll.h b/components/hal/esp32s3/include/hal/systimer_ll.h index 7f171e92e3..4f4084a5d6 100644 --- a/components/hal/esp32s3/include/hal/systimer_ll.h +++ b/components/hal/esp32s3/include/hal/systimer_ll.h @@ -1,16 +1,8 @@ -// Copyright 2021 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #pragma once #include @@ -25,6 +17,7 @@ #define SYSTIMER_LL_ALARM_CLOCK (2) // Alarm used for "wallclock" time #define SYSTIMER_LL_TICKS_PER_US (16) // 16 systimer ticks == 1us +#define SYSTIMER_LL_TICKS_PER_US_DIV (1) #ifdef __cplusplus extern "C" { diff --git a/components/hal/include/hal/systimer_hal.h b/components/hal/include/hal/systimer_hal.h index 9ac3262fa8..f3f197c551 100644 --- a/components/hal/include/hal/systimer_hal.h +++ b/components/hal/include/hal/systimer_hal.h @@ -1,16 +1,8 @@ -// Copyright 2020 Espressif Systems (Shanghai) PTE LTD -// -// Licensed under the Apache License, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. +/* + * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ #pragma once @@ -93,7 +85,7 @@ void systimer_hal_connect_alarm_counter(systimer_hal_context_t *hal, uint32_t al */ void systimer_hal_counter_can_stall_by_cpu(systimer_hal_context_t *hal, uint32_t counter_id, uint32_t cpu_id, bool can); -#if !SOC_SYSTIMER_FIXED_TICKS_US +#if !SOC_SYSTIMER_HAS_FIXED_TICKS_PER_US /** * @brief set increase steps for systimer counter on different clock source */ diff --git a/components/hal/systimer_hal.c b/components/hal/systimer_hal.c index b280c98a53..b2ad63a00d 100644 --- a/components/hal/systimer_hal.c +++ b/components/hal/systimer_hal.c @@ -47,19 +47,25 @@ uint64_t systimer_hal_get_counter_value(systimer_hal_context_t *hal, uint32_t co uint64_t systimer_hal_get_time(systimer_hal_context_t *hal, uint32_t counter_id) { - return systimer_hal_get_counter_value(hal, counter_id) / SYSTIMER_LL_TICKS_PER_US; + return systimer_hal_get_counter_value(hal, counter_id) * SYSTIMER_LL_TICKS_PER_US_DIV / SYSTIMER_LL_TICKS_PER_US; } #if SOC_SYSTIMER_ALARM_MISS_COMPENSATE void systimer_hal_set_alarm_target(systimer_hal_context_t *hal, uint32_t alarm_id, uint64_t target) { - systimer_counter_value_t alarm = { .val = target * SYSTIMER_LL_TICKS_PER_US}; + systimer_counter_value_t alarm = { + .val = target * SYSTIMER_LL_TICKS_PER_US / SYSTIMER_LL_TICKS_PER_US_DIV + }; systimer_ll_enable_alarm(hal->dev, alarm_id, false); systimer_ll_set_alarm_target(hal->dev, alarm_id, alarm.val); systimer_ll_apply_alarm_value(hal->dev, alarm_id); systimer_ll_enable_alarm(hal->dev, alarm_id, true); } -#else + +#else // SOC_SYSTIMER_ALARM_MISS_COMPENSATE + +_Static_assert(SYSTIMER_LL_TICKS_PER_US_DIV == 1, "SYSTIMER_LL_TICKS_PER_US_DIV > 1 && !SOC_SYSTIMER_ALARM_MISS_COMPENSATE hasn't been supported"); + void systimer_hal_set_alarm_target(systimer_hal_context_t *hal, uint32_t alarm_id, uint64_t timestamp) { int64_t offset = SYSTIMER_LL_TICKS_PER_US * 2; @@ -81,12 +87,12 @@ void systimer_hal_set_alarm_target(systimer_hal_context_t *hal, uint32_t alarm_i } } while (1); } -#endif +#endif // SOC_SYSTIMER_ALARM_MISS_COMPENSATE void systimer_hal_set_alarm_period(systimer_hal_context_t *hal, uint32_t alarm_id, uint32_t period) { systimer_ll_enable_alarm(hal->dev, alarm_id, false); - systimer_ll_set_alarm_period(hal->dev, alarm_id, period * SYSTIMER_LL_TICKS_PER_US); + systimer_ll_set_alarm_period(hal->dev, alarm_id, period * SYSTIMER_LL_TICKS_PER_US / SYSTIMER_LL_TICKS_PER_US_DIV); systimer_ll_apply_alarm_value(hal->dev, alarm_id); systimer_ll_enable_alarm(hal->dev, alarm_id, true); } @@ -103,7 +109,10 @@ void systimer_hal_enable_alarm_int(systimer_hal_context_t *hal, uint32_t alarm_i void systimer_hal_counter_value_advance(systimer_hal_context_t *hal, uint32_t counter_id, int64_t time_us) { - systimer_counter_value_t new_count = { .val = systimer_hal_get_counter_value(hal, counter_id) + time_us * SYSTIMER_LL_TICKS_PER_US }; + systimer_counter_value_t new_count = { + .val = systimer_hal_get_counter_value(hal, counter_id) + + time_us * SYSTIMER_LL_TICKS_PER_US / SYSTIMER_LL_TICKS_PER_US_DIV + }; systimer_ll_set_counter_value(hal->dev, counter_id, new_count.val); systimer_ll_apply_counter_value(hal->dev, counter_id); } @@ -137,7 +146,10 @@ void systimer_hal_counter_can_stall_by_cpu(systimer_hal_context_t *hal, uint32_t systimer_ll_counter_can_stall_by_cpu(hal->dev, counter_id, cpu_id, can); } -#if !SOC_SYSTIMER_FIXED_TICKS_US +#if !SOC_SYSTIMER_HAS_FIXED_TICKS_PER_US + +_Static_assert(SYSTIMER_LL_TICKS_PER_US_DIV == 1, "SYSTIMER_LL_TICKS_PER_US_DIV > 1 && !SOC_SYSTIMER_HAS_FIXED_TICKS_PER_US hasn't been supported"); + void systimer_hal_set_steps_per_tick(systimer_hal_context_t *hal, int clock_source, uint32_t steps) { /* Configure the counter: @@ -171,4 +183,4 @@ void systimer_hal_on_apb_freq_update(systimer_hal_context_t *hal, uint32_t apb_t systimer_ll_set_step_for_xtal(hal->dev, SYSTIMER_LL_TICKS_PER_US / apb_ticks_per_us); } } -#endif +#endif // !SOC_SYSTIMER_HAS_FIXED_TICKS_PER_US diff --git a/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in index 46b634275e..f5d95c6429 100644 --- a/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c2/include/soc/Kconfig.soc_caps.in @@ -411,9 +411,9 @@ config SOC_SYSTIMER_BIT_WIDTH_HI int default 20 -config SOC_SYSTIMER_FIXED_TICKS_US - int - default 16 +config SOC_SYSTIMER_HAS_FIXED_TICKS_PER_US + bool + default y config SOC_SYSTIMER_INT_LEVEL bool diff --git a/components/soc/esp32c2/include/soc/soc_caps.h b/components/soc/esp32c2/include/soc/soc_caps.h index f87a11e8bf..080debf2db 100644 --- a/components/soc/esp32c2/include/soc/soc_caps.h +++ b/components/soc/esp32c2/include/soc/soc_caps.h @@ -203,14 +203,14 @@ #define SOC_MEMSPI_SRC_FREQ_15M_SUPPORTED 1 /*-------------------------- SYSTIMER CAPS ----------------------------------*/ -#define SOC_SYSTIMER_SUPPORTED 1 -#define SOC_SYSTIMER_COUNTER_NUM (2) // Number of counter units -#define SOC_SYSTIMER_ALARM_NUM (3) // Number of alarm units -#define SOC_SYSTIMER_BIT_WIDTH_LO (32) // Bit width of systimer low part -#define SOC_SYSTIMER_BIT_WIDTH_HI (20) // Bit width of systimer high part -#define SOC_SYSTIMER_FIXED_TICKS_US (16) // Number of ticks per microsecond is fixed -#define SOC_SYSTIMER_INT_LEVEL (1) // Systimer peripheral uses level interrupt -#define SOC_SYSTIMER_ALARM_MISS_COMPENSATE (1) // Systimer peripheral can generate interrupt immediately if t(target) > t(current) +#define SOC_SYSTIMER_SUPPORTED 1 +#define SOC_SYSTIMER_COUNTER_NUM (2) // Number of counter units +#define SOC_SYSTIMER_ALARM_NUM (3) // Number of alarm units +#define SOC_SYSTIMER_BIT_WIDTH_LO (32) // Bit width of systimer low part +#define SOC_SYSTIMER_BIT_WIDTH_HI (20) // Bit width of systimer high part +#define SOC_SYSTIMER_HAS_FIXED_TICKS_PER_US (1) // Number of ticks per microsecond is fixed (16 ticks/us if 40MHz XTAL; 10.4 ticks/us if 26MHz XTAL) +#define SOC_SYSTIMER_INT_LEVEL (1) // Systimer peripheral uses level interrupt +#define SOC_SYSTIMER_ALARM_MISS_COMPENSATE (1) // Systimer peripheral can generate interrupt immediately if t(target) > t(current) /*--------------------------- TIMER GROUP CAPS ---------------------------------------*/ #define SOC_TIMER_GROUPS (1U) diff --git a/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in b/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in index 2f3a1d8fec..9ebc0348c3 100644 --- a/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32c3/include/soc/Kconfig.soc_caps.in @@ -603,9 +603,9 @@ config SOC_SYSTIMER_BIT_WIDTH_HI int default 20 -config SOC_SYSTIMER_FIXED_TICKS_US - int - default 16 +config SOC_SYSTIMER_HAS_FIXED_TICKS_PER_US + bool + default y config SOC_SYSTIMER_INT_LEVEL bool diff --git a/components/soc/esp32c3/include/soc/soc_caps.h b/components/soc/esp32c3/include/soc/soc_caps.h index d3729d35e9..e1426cfaa5 100644 --- a/components/soc/esp32c3/include/soc/soc_caps.h +++ b/components/soc/esp32c3/include/soc/soc_caps.h @@ -283,14 +283,14 @@ #define SOC_MEMSPI_SRC_FREQ_20M_SUPPORTED 1 /*-------------------------- SYSTIMER CAPS ----------------------------------*/ -#define SOC_SYSTIMER_SUPPORTED 1 -#define SOC_SYSTIMER_COUNTER_NUM (2) // Number of counter units -#define SOC_SYSTIMER_ALARM_NUM (3) // Number of alarm units -#define SOC_SYSTIMER_BIT_WIDTH_LO (32) // Bit width of systimer low part -#define SOC_SYSTIMER_BIT_WIDTH_HI (20) // Bit width of systimer high part -#define SOC_SYSTIMER_FIXED_TICKS_US (16) // Number of ticks per microsecond is fixed -#define SOC_SYSTIMER_INT_LEVEL (1) // Systimer peripheral uses level interrupt -#define SOC_SYSTIMER_ALARM_MISS_COMPENSATE (1) // Systimer peripheral can generate interrupt immediately if t(target) > t(current) +#define SOC_SYSTIMER_SUPPORTED 1 +#define SOC_SYSTIMER_COUNTER_NUM (2) // Number of counter units +#define SOC_SYSTIMER_ALARM_NUM (3) // Number of alarm units +#define SOC_SYSTIMER_BIT_WIDTH_LO (32) // Bit width of systimer low part +#define SOC_SYSTIMER_BIT_WIDTH_HI (20) // Bit width of systimer high part +#define SOC_SYSTIMER_HAS_FIXED_TICKS_PER_US (1) // Number of ticks per microsecond is fixed (16 ticks/us) +#define SOC_SYSTIMER_INT_LEVEL (1) // Systimer peripheral uses level interrupt +#define SOC_SYSTIMER_ALARM_MISS_COMPENSATE (1) // Systimer peripheral can generate interrupt immediately if t(target) > t(current) /*--------------------------- TIMER GROUP CAPS ---------------------------------------*/ #define SOC_TIMER_GROUPS (2) diff --git a/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in b/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in index 62c4b4d6b7..381faec6e2 100644 --- a/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32h2/include/soc/Kconfig.soc_caps.in @@ -579,9 +579,9 @@ config SOC_SYSTIMER_BIT_WIDTH_HI int default 20 -config SOC_SYSTIMER_FIXED_TICKS_US - int - default 16 +config SOC_SYSTIMER_HAS_FIXED_TICKS_PER_US + bool + default y config SOC_SYSTIMER_INT_LEVEL bool diff --git a/components/soc/esp32h2/include/soc/soc_caps.h b/components/soc/esp32h2/include/soc/soc_caps.h index c05afd7f9b..d32334c623 100644 --- a/components/soc/esp32h2/include/soc/soc_caps.h +++ b/components/soc/esp32h2/include/soc/soc_caps.h @@ -288,14 +288,14 @@ #define SOC_MEMSPI_SRC_FREQ_12M_SUPPORTED 1 /*-------------------------- SYSTIMER CAPS ----------------------------------*/ -#define SOC_SYSTIMER_SUPPORTED 1 -#define SOC_SYSTIMER_COUNTER_NUM (2) // Number of counter units -#define SOC_SYSTIMER_ALARM_NUM (3) // Number of alarm units -#define SOC_SYSTIMER_BIT_WIDTH_LO (32) // Bit width of systimer low part -#define SOC_SYSTIMER_BIT_WIDTH_HI (20) // Bit width of systimer high part -#define SOC_SYSTIMER_FIXED_TICKS_US (16) // Number of ticks per microsecond is fixed -#define SOC_SYSTIMER_INT_LEVEL (1) // Systimer peripheral uses level interrupt -#define SOC_SYSTIMER_ALARM_MISS_COMPENSATE (1) // Systimer peripheral can generate interrupt immediately if t(target) > t(current) +#define SOC_SYSTIMER_SUPPORTED 1 +#define SOC_SYSTIMER_COUNTER_NUM (2) // Number of counter units +#define SOC_SYSTIMER_ALARM_NUM (3) // Number of alarm units +#define SOC_SYSTIMER_BIT_WIDTH_LO (32) // Bit width of systimer low part +#define SOC_SYSTIMER_BIT_WIDTH_HI (20) // Bit width of systimer high part +#define SOC_SYSTIMER_HAS_FIXED_TICKS_PER_US (1) // Number of ticks per microsecond is fixed (16 ticks/us) +#define SOC_SYSTIMER_INT_LEVEL (1) // Systimer peripheral uses level interrupt +#define SOC_SYSTIMER_ALARM_MISS_COMPENSATE (1) // Systimer peripheral can generate interrupt immediately if t(target) > t(current) /*--------------------------- TIMER GROUP CAPS ---------------------------------------*/ #define SOC_TIMER_GROUPS (2) diff --git a/components/soc/esp32s3/include/soc/Kconfig.soc_caps.in b/components/soc/esp32s3/include/soc/Kconfig.soc_caps.in index ff51e5f55c..dd1962ef33 100644 --- a/components/soc/esp32s3/include/soc/Kconfig.soc_caps.in +++ b/components/soc/esp32s3/include/soc/Kconfig.soc_caps.in @@ -679,9 +679,9 @@ config SOC_SYSTIMER_BIT_WIDTH_HI int default 20 -config SOC_SYSTIMER_FIXED_TICKS_US - int - default 16 +config SOC_SYSTIMER_HAS_FIXED_TICKS_PER_US + bool + default y config SOC_SYSTIMER_INT_LEVEL bool diff --git a/components/soc/esp32s3/include/soc/soc_caps.h b/components/soc/esp32s3/include/soc/soc_caps.h index c4b63cf5ef..de5b71f250 100644 --- a/components/soc/esp32s3/include/soc/soc_caps.h +++ b/components/soc/esp32s3/include/soc/soc_caps.h @@ -277,14 +277,14 @@ #define SOC_SPIRAM_SUPPORTED 1 /*-------------------------- SYS TIMER CAPS ----------------------------------*/ -#define SOC_SYSTIMER_SUPPORTED 1 -#define SOC_SYSTIMER_COUNTER_NUM (2) // Number of counter units -#define SOC_SYSTIMER_ALARM_NUM (3) // Number of alarm units -#define SOC_SYSTIMER_BIT_WIDTH_LO (32) // Bit width of systimer low part -#define SOC_SYSTIMER_BIT_WIDTH_HI (20) // Bit width of systimer high part -#define SOC_SYSTIMER_FIXED_TICKS_US (16) // Number of ticks per microsecond is fixed -#define SOC_SYSTIMER_INT_LEVEL (1) // Systimer peripheral uses level -#define SOC_SYSTIMER_ALARM_MISS_COMPENSATE (1) // Systimer peripheral can generate interrupt immediately if t(target) > t(current) +#define SOC_SYSTIMER_SUPPORTED 1 +#define SOC_SYSTIMER_COUNTER_NUM (2) // Number of counter units +#define SOC_SYSTIMER_ALARM_NUM (3) // Number of alarm units +#define SOC_SYSTIMER_BIT_WIDTH_LO (32) // Bit width of systimer low part +#define SOC_SYSTIMER_BIT_WIDTH_HI (20) // Bit width of systimer high part +#define SOC_SYSTIMER_HAS_FIXED_TICKS_PER_US (1) // Number of ticks per microsecond is fixed (16 ticks/us) +#define SOC_SYSTIMER_INT_LEVEL (1) // Systimer peripheral uses level +#define SOC_SYSTIMER_ALARM_MISS_COMPENSATE (1) // Systimer peripheral can generate interrupt immediately if t(target) > t(current) /*-------------------------- TIMER GROUP CAPS --------------------------------*/ #define SOC_TIMER_GROUPS (2) diff --git a/tools/ci/check_copyright_ignore.txt b/tools/ci/check_copyright_ignore.txt index 903ca3293e..bd6000b736 100644 --- a/tools/ci/check_copyright_ignore.txt +++ b/tools/ci/check_copyright_ignore.txt @@ -758,7 +758,6 @@ components/hal/esp32c3/include/hal/rtc_cntl_ll.h components/hal/esp32c3/include/hal/sha_ll.h components/hal/esp32c3/include/hal/sigmadelta_ll.h components/hal/esp32c3/include/hal/spi_flash_encrypted_ll.h -components/hal/esp32c3/include/hal/systimer_ll.h components/hal/esp32c3/include/hal/uhci_ll.h components/hal/esp32c3/include/hal/usb_serial_jtag_ll.h components/hal/esp32c3/rtc_cntl_hal.c @@ -785,7 +784,6 @@ components/hal/esp32s2/include/hal/rtc_io_ll.h components/hal/esp32s2/include/hal/sha_ll.h components/hal/esp32s2/include/hal/sigmadelta_ll.h components/hal/esp32s2/include/hal/spi_flash_encrypted_ll.h -components/hal/esp32s2/include/hal/systimer_ll.h components/hal/esp32s2/include/hal/trace_ll.h components/hal/esp32s2/include/hal/usb_ll.h components/hal/esp32s2/touch_sensor_hal.c @@ -795,7 +793,6 @@ components/hal/esp32s3/include/hal/rwdt_ll.h components/hal/esp32s3/include/hal/sha_ll.h components/hal/esp32s3/include/hal/sigmadelta_ll.h components/hal/esp32s3/include/hal/spi_flash_encrypted_ll.h -components/hal/esp32s3/include/hal/systimer_ll.h components/hal/esp32s3/include/hal/uhci_ll.h components/hal/esp32s3/include/hal/usb_ll.h components/hal/esp32s3/include/hal/usb_serial_jtag_ll.h @@ -815,7 +812,6 @@ components/hal/include/hal/sigmadelta_hal.h components/hal/include/hal/spi_flash_encrypt_hal.h components/hal/include/hal/spi_slave_hal.h components/hal/include/hal/spi_slave_hd_hal.h -components/hal/include/hal/systimer_hal.h components/hal/include/hal/twai_types.h components/hal/include/hal/uhci_types.h components/hal/include/hal/usb_hal.h From a1d7089b5928d1b3850ff57f47fba9c117315cf8 Mon Sep 17 00:00:00 2001 From: Ivan Grokhotkov Date: Fri, 1 Jul 2022 20:20:39 +0200 Subject: [PATCH 4/9] ci: add build-only test for esp32c2 with 26 MHz XTAL option enabled --- .../test_apps/system/build_test/sdkconfig.ci.esp32c2_26mhz_xtal | 2 ++ 1 file changed, 2 insertions(+) create mode 100644 tools/test_apps/system/build_test/sdkconfig.ci.esp32c2_26mhz_xtal diff --git a/tools/test_apps/system/build_test/sdkconfig.ci.esp32c2_26mhz_xtal b/tools/test_apps/system/build_test/sdkconfig.ci.esp32c2_26mhz_xtal new file mode 100644 index 0000000000..520e2cf90a --- /dev/null +++ b/tools/test_apps/system/build_test/sdkconfig.ci.esp32c2_26mhz_xtal @@ -0,0 +1,2 @@ +CONFIG_IDF_TARGET="esp32c2" +CONFIG_ESP32C2_XTAL_FREQ_26=y From 2e37218ce5d8ce30a8b5e856fdb897a27984c019 Mon Sep 17 00:00:00 2001 From: Ivan Grokhotkov Date: Fri, 1 Jul 2022 20:51:04 +0200 Subject: [PATCH 5/9] soc, hal: remove XTAL_CLK_FREQ XTAL_CLK_FREQ now depends on the actual XTAL used, remove this macro and get the XTAL frequency from the RTC register instead. No uses of XTAL_CLK_FREQ found, other than in the UART LL. --- components/hal/esp32c2/include/hal/uart_ll.h | 3 ++- components/soc/esp32c2/include/soc/soc.h | 1 - 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/components/hal/esp32c2/include/hal/uart_ll.h b/components/hal/esp32c2/include/hal/uart_ll.h index aaea6e74ff..8d38c0e9e1 100644 --- a/components/hal/esp32c2/include/hal/uart_ll.h +++ b/components/hal/esp32c2/include/hal/uart_ll.h @@ -11,6 +11,7 @@ #pragma once #include "hal/uart_types.h" #include "soc/uart_periph.h" +#include "hal/clk_tree_ll.h" #ifdef __cplusplus extern "C" { @@ -157,7 +158,7 @@ static inline uint32_t uart_ll_get_sclk_freq(uart_dev_t *hw) case 2: return RTC_CLK_FREQ; case 3: - return XTAL_CLK_FREQ; + return clk_ll_xtal_load_freq_mhz() * MHZ; } } diff --git a/components/soc/esp32c2/include/soc/soc.h b/components/soc/esp32c2/include/soc/soc.h index 1f5f9a098f..b4ff43d342 100644 --- a/components/soc/esp32c2/include/soc/soc.h +++ b/components/soc/esp32c2/include/soc/soc.h @@ -148,7 +148,6 @@ #define APB_CLK_FREQ ( 40*1000000 ) #define REF_CLK_FREQ ( 1000000 ) #define RTC_CLK_FREQ (20*1000000) -#define XTAL_CLK_FREQ (40*1000000) #define UART_CLK_FREQ APB_CLK_FREQ #define WDT_CLK_FREQ APB_CLK_FREQ #define TIMER_CLK_FREQ (80000000>>4) //80MHz divided by 4 From ef813b23fa92f7e1e280bf3078f4ef94a8654eae Mon Sep 17 00:00:00 2001 From: songruojing Date: Mon, 4 Jul 2022 14:14:43 +0800 Subject: [PATCH 6/9] rtc: esp32c2 support 26MHz xtal in startup code and rtc_clk.c --- components/esp_hw_support/port/esp32c2/rtc_clk.c | 4 ++-- components/esp_system/port/soc/esp32c2/clk.c | 2 +- components/soc/esp32c2/include/soc/clk_tree_defs.h | 8 ++++---- 3 files changed, 7 insertions(+), 7 deletions(-) diff --git a/components/esp_hw_support/port/esp32c2/rtc_clk.c b/components/esp_hw_support/port/esp32c2/rtc_clk.c index 1173a06d07..9703099f30 100644 --- a/components/esp_hw_support/port/esp32c2/rtc_clk.c +++ b/components/esp_hw_support/port/esp32c2/rtc_clk.c @@ -297,8 +297,8 @@ rtc_xtal_freq_t rtc_clk_xtal_freq_get(void) { uint32_t xtal_freq_mhz = clk_ll_xtal_load_freq_mhz(); if (xtal_freq_mhz == 0) { - ESP_HW_LOGW(TAG, "invalid RTC_XTAL_FREQ_REG value, assume 40MHz"); - return RTC_XTAL_FREQ_40M; + ESP_HW_LOGW(TAG, "invalid RTC_XTAL_FREQ_REG value, assume %dMHz", CONFIG_ESP32C2_XTAL_FREQ); + return CONFIG_ESP32C2_XTAL_FREQ; } return (rtc_xtal_freq_t)xtal_freq_mhz; } diff --git a/components/esp_system/port/soc/esp32c2/clk.c b/components/esp_system/port/soc/esp32c2/clk.c index 29991272b2..4af09f70d2 100644 --- a/components/esp_system/port/soc/esp32c2/clk.c +++ b/components/esp_system/port/soc/esp32c2/clk.c @@ -71,7 +71,7 @@ static const char *TAG = "clk"; } rtc_init(cfg); - assert(rtc_clk_xtal_freq_get() == RTC_XTAL_FREQ_40M); + assert(rtc_clk_xtal_freq_get() == CONFIG_ESP32C2_XTAL_FREQ); bool rc_fast_d256_is_enabled = rtc_clk_8md256_enabled(); rtc_clk_8m_enable(true, rc_fast_d256_is_enabled); diff --git a/components/soc/esp32c2/include/soc/clk_tree_defs.h b/components/soc/esp32c2/include/soc/clk_tree_defs.h index 230b6251fc..d60697a759 100644 --- a/components/soc/esp32c2/include/soc/clk_tree_defs.h +++ b/components/soc/esp32c2/include/soc/clk_tree_defs.h @@ -19,7 +19,7 @@ extern "C" { * * The exact frequency of RC_FAST_CLK can be computed in runtime through calibration on the RC_FAST_D256_CLK. * - * 2) External 40MHz Crystal Clock: XTAL + * 2) External 26/40MHz Crystal Clock: XTAL * * 3) Internal 136kHz RC Oscillator: RC_SLOW (usually referrred as RTC in TRM or reg. description) * @@ -50,7 +50,7 @@ extern "C" { typedef enum { SOC_ROOT_CLK_INT_RC_FAST, /*!< Internal 17.5MHz RC oscillator */ SOC_ROOT_CLK_INT_RC_SLOW, /*!< Internal 136kHz RC oscillator */ - SOC_ROOT_CLK_EXT_XTAL, /*!< External 40MHz crystal */ + SOC_ROOT_CLK_EXT_XTAL, /*!< External 26/40MHz crystal */ SOC_ROOT_CLK_EXT_OSC_SLOW, /*!< External slow clock signal at pin0 */ } soc_root_clk_t; @@ -60,7 +60,7 @@ typedef enum { */ typedef enum { SOC_CPU_CLK_SRC_XTAL = 0, /*!< Select XTAL_CLK as CPU_CLK source */ - SOC_CPU_CLK_SRC_PLL = 1, /*!< Select PLL_CLK as CPU_CLK source (PLL_CLK is the output of 40MHz crystal oscillator frequency multiplier, 480MHz) */ + SOC_CPU_CLK_SRC_PLL = 1, /*!< Select PLL_CLK as CPU_CLK source (PLL_CLK is the output of 26/40MHz crystal oscillator frequency multiplier, 480MHz) */ SOC_CPU_CLK_SRC_RC_FAST = 2, /*!< Select RC_FAST_CLK as CPU_CLK source */ SOC_CPU_CLK_SRC_INVALID, /*!< Invalid CPU_CLK source */ } soc_cpu_clk_src_t; @@ -108,7 +108,7 @@ typedef enum { SOC_MOD_CLK_OSC_SLOW, /*!< OSC_SLOW_CLK comes from an external slow clock signal, passing a clock gating to the peripherals */ SOC_MOD_CLK_RC_FAST, /*!< RC_FAST_CLK comes from the internal 20MHz rc oscillator, passing a clock gating to the peripherals */ SOC_MOD_CLK_RC_FAST_D256, /*!< RC_FAST_D256_CLK comes from the internal 20MHz rc oscillator, divided by 256, and passing a clock gating to the peripherals */ - SOC_MOD_CLK_XTAL, /*!< XTAL_CLK comes from the external 40MHz crystal */ + SOC_MOD_CLK_XTAL, /*!< XTAL_CLK comes from the external 26/40MHz crystal */ } soc_module_clk_t; From b3d8db3ae2285ea74b0ed63b2b4b55add76b2e59 Mon Sep 17 00:00:00 2001 From: songruojing Date: Mon, 4 Jul 2022 14:17:54 +0800 Subject: [PATCH 7/9] bootloader, esp_system: esp32c2 console uart to support 26MHz xtal Gets the XTAL frequency from the RTC storage register, remove UART_CLK_FREQ_ROM macro from soc.h --- components/bootloader_support/src/bootloader_console.c | 2 +- components/esp_system/port/cpu_start.c | 5 +++-- components/soc/esp32c2/include/soc/soc.h | 1 - components/soc/esp32c3/include/soc/soc.h | 1 - components/soc/esp32h2/include/soc/soc.h | 1 - components/soc/esp32s2/include/soc/soc.h | 1 - components/soc/esp32s3/include/soc/soc.h | 1 - 7 files changed, 4 insertions(+), 8 deletions(-) diff --git a/components/bootloader_support/src/bootloader_console.c b/components/bootloader_support/src/bootloader_console.c index 83cc7893a0..85e4aa8027 100644 --- a/components/bootloader_support/src/bootloader_console.c +++ b/components/bootloader_support/src/bootloader_console.c @@ -90,7 +90,7 @@ void bootloader_console_init(void) // Set configured UART console baud rate uint32_t clock_hz = rtc_clk_apb_freq_get(); #if ESP_ROM_UART_CLK_IS_XTAL - clock_hz = UART_CLK_FREQ_ROM; // From esp32-s3 on, UART clock source is selected to XTAL in ROM + clock_hz = (uint32_t)rtc_clk_xtal_freq_get() * MHZ; // From esp32-s3 on, UART clk source is selected to XTAL in ROM #endif esp_rom_uart_set_clock_baudrate(uart_num, clock_hz, CONFIG_ESP_CONSOLE_UART_BAUDRATE); } diff --git a/components/esp_system/port/cpu_start.c b/components/esp_system/port/cpu_start.c index 1e660d5427..d0de1f862a 100644 --- a/components/esp_system/port/cpu_start.c +++ b/components/esp_system/port/cpu_start.c @@ -21,6 +21,7 @@ #include "esp_rom_efuse.h" #include "esp_rom_uart.h" #include "esp_rom_sys.h" +#include "esp_rom_caps.h" #include "sdkconfig.h" #if CONFIG_IDF_TARGET_ESP32 @@ -516,8 +517,8 @@ void IRAM_ATTR call_start_cpu0(void) #ifndef CONFIG_IDF_ENV_FPGA // TODO: on FPGA it should be possible to configure this, not currently working with APB_CLK_FREQ changed #ifdef CONFIG_ESP_CONSOLE_UART uint32_t clock_hz = esp_clk_apb_freq(); -#if CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32C2 - clock_hz = UART_CLK_FREQ_ROM; // From esp32-s3 on, UART clock source is selected to XTAL in ROM +#if ESP_ROM_UART_CLK_IS_XTAL + clock_hz = esp_clk_xtal_freq(); // From esp32-s3 on, UART clock source is selected to XTAL in ROM #endif esp_rom_uart_tx_wait_idle(CONFIG_ESP_CONSOLE_UART_NUM); esp_rom_uart_set_clock_baudrate(CONFIG_ESP_CONSOLE_UART_NUM, clock_hz, CONFIG_ESP_CONSOLE_UART_BAUDRATE); diff --git a/components/soc/esp32c2/include/soc/soc.h b/components/soc/esp32c2/include/soc/soc.h index b4ff43d342..83afaa5fab 100644 --- a/components/soc/esp32c2/include/soc/soc.h +++ b/components/soc/esp32c2/include/soc/soc.h @@ -142,7 +142,6 @@ //Periheral Clock {{ #define APB_CLK_FREQ_ROM ( 40*1000000 ) #define CPU_CLK_FREQ_ROM APB_CLK_FREQ_ROM -#define UART_CLK_FREQ_ROM ( 40*1000000) #define EFUSE_CLK_FREQ_ROM ( 20*1000000) #define CPU_CLK_FREQ APB_CLK_FREQ #define APB_CLK_FREQ ( 40*1000000 ) diff --git a/components/soc/esp32c3/include/soc/soc.h b/components/soc/esp32c3/include/soc/soc.h index 547b7fe815..a4131b79b8 100644 --- a/components/soc/esp32c3/include/soc/soc.h +++ b/components/soc/esp32c3/include/soc/soc.h @@ -135,7 +135,6 @@ //Periheral Clock {{ #define APB_CLK_FREQ_ROM ( 40*1000000 ) #define CPU_CLK_FREQ_ROM APB_CLK_FREQ_ROM -#define UART_CLK_FREQ_ROM ( 40*1000000) #define EFUSE_CLK_FREQ_ROM ( 20*1000000) #define CPU_CLK_FREQ APB_CLK_FREQ #if CONFIG_IDF_ENV_FPGA diff --git a/components/soc/esp32h2/include/soc/soc.h b/components/soc/esp32h2/include/soc/soc.h index 98c5f62c92..d83bca8e50 100644 --- a/components/soc/esp32h2/include/soc/soc.h +++ b/components/soc/esp32h2/include/soc/soc.h @@ -135,7 +135,6 @@ //Periheral Clock {{ #define APB_CLK_FREQ_ROM ( 32*1000000 ) #define CPU_CLK_FREQ_ROM APB_CLK_FREQ_ROM -#define UART_CLK_FREQ_ROM ( 32*1000000) #define EFUSE_CLK_FREQ_ROM ( 20*1000000) #define CPU_CLK_FREQ APB_CLK_FREQ #if CONFIG_IDF_ENV_FPGA diff --git a/components/soc/esp32s2/include/soc/soc.h b/components/soc/esp32s2/include/soc/soc.h index 55112b84e9..fe25297917 100644 --- a/components/soc/esp32s2/include/soc/soc.h +++ b/components/soc/esp32s2/include/soc/soc.h @@ -142,7 +142,6 @@ //Periheral Clock {{ #define APB_CLK_FREQ_ROM ( 40*1000000 ) #define CPU_CLK_FREQ_ROM APB_CLK_FREQ_ROM -#define UART_CLK_FREQ_ROM APB_CLK_FREQ_ROM #define CPU_CLK_FREQ APB_CLK_FREQ #define APB_CLK_FREQ ( 80*1000000 ) //unit: Hz #define REF_CLK_FREQ ( 1000000 ) diff --git a/components/soc/esp32s3/include/soc/soc.h b/components/soc/esp32s3/include/soc/soc.h index 0405dc4405..ab0db41ae3 100644 --- a/components/soc/esp32s3/include/soc/soc.h +++ b/components/soc/esp32s3/include/soc/soc.h @@ -152,7 +152,6 @@ //Periheral Clock {{ #define APB_CLK_FREQ_ROM (40*1000000) #define CPU_CLK_FREQ_ROM APB_CLK_FREQ_ROM -#define UART_CLK_FREQ_ROM (40*1000000) #define EFUSE_CLK_FREQ_ROM (20*1000000) #define CPU_CLK_FREQ APB_CLK_FREQ #define APB_CLK_FREQ (80*1000000) From a9c80650300f6068f3ae0cfdde48cfd5d2b03359 Mon Sep 17 00:00:00 2001 From: wuzhenghui Date: Mon, 4 Jul 2022 17:49:02 +0800 Subject: [PATCH 8/9] Kconfig: Update dependencies to avoid invalid configurations 1. Since the baud rate in the ROM cannot be changed, set the default baud rate of the 26Mhz version of esp32c2 to 74800 2. Since the systimer configuration of the 26Mhz version requires a non-integer systimer frequency configuration, and this feature is not supported in the current ROM, this option is disabled for the 26Mhz version esp32c2 --- components/esp_system/Kconfig | 1 + components/hal/Kconfig | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/components/esp_system/Kconfig b/components/esp_system/Kconfig index 50841152d2..60e5a4d724 100644 --- a/components/esp_system/Kconfig +++ b/components/esp_system/Kconfig @@ -331,6 +331,7 @@ menu "ESP System Settings" int prompt "UART console baud rate" if ESP_CONSOLE_UART_CUSTOM depends on ESP_CONSOLE_UART + default 74880 if ESP32C2_XTAL_FREQ_26 default 115200 range 1200 4000000 if !PM_ENABLE range 1200 1000000 if PM_ENABLE diff --git a/components/hal/Kconfig b/components/hal/Kconfig index 8b5678d790..4f35f73fe4 100644 --- a/components/hal/Kconfig +++ b/components/hal/Kconfig @@ -67,7 +67,7 @@ menu "Hardware Abstraction Layer (HAL) and Low Level (LL)" config HAL_SYSTIMER_USE_ROM_IMPL bool "Use ROM implementation of SysTimer HAL driver" - depends on ESP_ROM_HAS_HAL_SYSTIMER + depends on ESP_ROM_HAS_HAL_SYSTIMER && !ESP32C2_XTAL_FREQ_26 default y help Enable this flag to use HAL functions from ROM instead of ESP-IDF. From 996fb0cce81616d23dddbe4bed6bc8a2f0bef376 Mon Sep 17 00:00:00 2001 From: songruojing Date: Tue, 5 Jul 2022 16:12:33 +0800 Subject: [PATCH 9/9] G0: hal/regi2c_ctrl.h now defines all REGI2C macros to pass g0_components build test --- .../hal/platform_port/include/hal/regi2c_ctrl.h | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/components/hal/platform_port/include/hal/regi2c_ctrl.h b/components/hal/platform_port/include/hal/regi2c_ctrl.h index 29bc7fa1d3..b87fdb3108 100644 --- a/components/hal/platform_port/include/hal/regi2c_ctrl.h +++ b/components/hal/platform_port/include/hal/regi2c_ctrl.h @@ -17,5 +17,16 @@ #include "esp_private/regi2c_ctrl.h" #else #include "esp_rom_regi2c.h" - #define REGI2C_WRITE_MASK(block, reg_add, indata) esp_rom_regi2c_write_mask(block, block##_HOSTID, reg_add, reg_add##_MSB, reg_add##_LSB, indata) + + #define REGI2C_WRITE_MASK(block, reg_add, indata) \ + esp_rom_regi2c_write_mask(block, block##_HOSTID, reg_add, reg_add##_MSB, reg_add##_LSB, indata) + + #define REGI2C_WRITE(block, reg_add, indata) \ + esp_rom_regi2c_write(block, block##_HOSTID, reg_add, indata) + + #define REGI2C_READ_MASK(block, reg_add) \ + esp_rom_regi2c_read_mask(block, block##_HOSTID, reg_add, reg_add##_MSB, reg_add##_LSB) + + #define REGI2C_READ(block, reg_add) \ + esp_rom_regi2c_read(block, block##_HOSTID, reg_add) #endif