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fix(spi_flash): Fix the mpll clock source always pinned to 80M on PP4

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C.S.M
2024-07-11 13:59:42 +08:00
parent d02758f56b
commit eaccf8aedb
1 changed files with 21 additions and 1 deletions
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22
components/hal/esp32p4/include/hal/spimem_flash_ll.h
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@@ -29,6 +29,7 @@
#include "hal/misc.h" #include "hal/misc.h"
#include "hal/efuse_hal.h" #include "hal/efuse_hal.h"
#include "soc/chip_revision.h" #include "soc/chip_revision.h"
#include "hal/clk_tree_ll.h"
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
@@ -645,7 +646,26 @@ static inline void spimem_flash_ll_set_extra_dummy(spi_mem_dev_t *dev, uint32_t
*/ */
static inline uint8_t spimem_flash_ll_get_source_freq_mhz(void) static inline uint8_t spimem_flash_ll_get_source_freq_mhz(void)
{ {
return 80; // return 80;
int source_clk_mhz = 0;
switch (HP_SYS_CLKRST.peri_clk_ctrl00.reg_flash_clk_src_sel)
{
case 0:
source_clk_mhz = clk_ll_xtal_load_freq_mhz();
break;
case 1:
source_clk_mhz = CLK_LL_PLL_480M_FREQ_MHZ; // SPLL
break;
case 2:
source_clk_mhz = CLK_LL_PLL_400M_FREQ_MHZ; // CPLL
break;
default:
break;
}
uint8_t clock_val = source_clk_mhz / (HP_SYS_CLKRST.peri_clk_ctrl00.reg_flash_core_clk_div_num + 1);
return clock_val;
} }
/** /**