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Merge branch 'doc/spi_master_frequency_limit' into 'master'

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Doc/SPI Master: Added description for SPI clock and speed settings

Closes IDF-6024

See merge request espressif/esp-idf!20335
This commit is contained in:
Wan Lei
2022-10-10 19:53:53 +08:00
parent 1a95860559 31fa04c45b
commit ead10bf01a
1 changed files with 31 additions and 2 deletions
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33
docs/en/api-reference/peripherals/spi_master.rst
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@@ -98,8 +98,8 @@ Phase Description
============== ========================================================================================================= ============== =========================================================================================================
**Command** In this phase, a command (0-16 bit) is written to the bus by the Host. **Command** In this phase, a command (0-16 bit) is written to the bus by the Host.
**Address** In this phase, an address (0-{IDF_TARGET_ADDR_LEN} bit) is transmitted over the bus by the Host. **Address** In this phase, an address (0-{IDF_TARGET_ADDR_LEN} bit) is transmitted over the bus by the Host.
**Write** Host sends data to a Device. This data follows the optional command and address phases and is indistinguishable from them at the electrical level.
**Dummy** This phase is configurable and is used to meet the timing requirements. **Dummy** This phase is configurable and is used to meet the timing requirements.
**Write** Host sends data to a Device. This data follows the optional command and address phases and is indistinguishable from them at the electrical level.
**Read** Device sends data to its Host. **Read** Device sends data to its Host.
============== ========================================================================================================= ============== =========================================================================================================
@@ -461,8 +461,37 @@ Typical transaction duration for one byte of data are given below.
SPI Clock Frequency SPI Clock Frequency
^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^
The driver support setting an SPI peripheral to different clock frequencies. Actual clock frequency may not be exactly equal to the number you set, it will be re-calculated by the driver to the nearest hardware compatible number, you can call :cpp:func:`spi_device_get_actual_freq` to get the actual frequency computed by driver.
Transferring each byte takes eight times the clock period *8/fspi*. Theoretical maximum transfer speed of Write or Read phase can be calculated according to the table below:
.. only:: not SOC_SPI_SUPPORT_OCT
+--------------------------------+------------------------+
| Line Width of Write/Read phase | Speed (Bps) |
+================================+========================+
| 1-Line | *SPI Frequency / 8* |
+--------------------------------+------------------------+
| 2-Line | *SPI Frequency / 4* |
+--------------------------------+------------------------+
| 4-Line | *SPI Frequency / 2* |
+--------------------------------+------------------------+
.. only:: SOC_SPI_SUPPORT_OCT
+--------------------------------+------------------------+
| Line Width of Write/Read phase | Speed (Bps) |
+================================+========================+
| 1-Line | *SPI Frequency / 8* |
+--------------------------------+------------------------+
| 2-Line | *SPI Frequency / 4* |
+--------------------------------+------------------------+
| 4-Line | *SPI Frequency / 2* |
+--------------------------------+------------------------+
| 8-Line | *SPI Frequency* |
+--------------------------------+------------------------+
The transfer speed calculation of other phases(command, address, dummy) are similar.
.. only:: esp32 .. only:: esp32